KR101717721B1 - Image display device and driving method for thereof - Google Patents

Abstract

The present invention relates to an image display apparatus and a method of driving the same that can reduce a data read access time (read access time) between a TMIC and an EEPROM and reduce a system initialization time.
According to an embodiment of the present invention, there is provided a method of driving an image display device, the method comprising: granting a use right of an I2C channel to a first TMIC among a plurality of TMICs (Timing controller Merged ICs); Accessing the stored data of the EEPROM by the first TMIC that has obtained the I2C channel usage right; Detecting a device address of data to be accessed by the first TMIC and providing the device address to a second one of the plurality of TMICs; And accessing the same data through the I2C line by the first TMIC and the second TMIC when the device address accessed by the first TMIC and the device address of the data being accessed by the second TMIC are the same, And the plurality of TMICs are connected to one I2C interface.

Description

TECHNICAL FIELD [0001] The present invention relates to a video display device and a driving method thereof.

In particular, the present invention relates to an image display apparatus, and more particularly, to an image display apparatus capable of reducing a data read access time between a timing controller (TMIC) and an electrically erasable programmable read only memory (TMROM) And a method of driving the same.

The display device has been developed in accordance with the market demand for the large-sized and thinned, and the demand for a flat panel display device having advantages of thinning, light weight, and low power consumption is increasing.

Examples of the flat panel display device include a liquid crystal display (LCD) device, a plasma display panel, a field emission display device, a light emitting diode display device ), An organic light emitting diode display device (Organic Light Emitting Diode Display Device) and the like have been developed.

Of the flat panel display devices, liquid crystal display devices have secured a strong market and are expanding their applications because of the advantages of mass production technology, ease of driving means, low power consumption, thin thickness, high image quality and large screen realization.

The liquid crystal display device displays an image by moving a liquid crystal according to an input video signal and adjusting light transmittance for each pixel.

To this end, a liquid crystal display device includes a liquid crystal panel in which a plurality of pixels (liquid crystal cells) are arranged in a matrix form; A backlight unit for supplying light to the liquid crystal panel; And a driving circuit for driving the liquid crystal panel and the backlight.

Here, the driving circuit includes a timing controller (T-con), a gate driver (G-IC), a data driver (D-IC) and a backlight driver.

In recent years, a timing controller and a TMIC (Timing controller Merged IC) mounted on a single chip in a SoC (System on Chip) method have been applied to a timing controller and a data driver.

The components of the SoC are composed of a plurality of masters, an arbiter, a plurality of slaves, and a shared bus for data transmission between the master and slaves.

The master means a processor (CPU), a direct memory access (DMA) and a digital signal processor (DSP), and the slave is a memory such as SDRAM and SRAM and a memory such as a universal serial bus (USB) and a universal asynchronous receiver transmitter Means an input / output means.

The TMIC implemented by SoC is increasingly applied because it has the advantage of reducing the chip size and the design cost as well as improving the low power consumption and real time processing capability.

FIG. 1 is a view showing a method of transmitting and receiving data between a TMIC and an EEPROM of a liquid crystal display according to a related art. FIG. 2 is a diagram showing a time required for data transmission / reception between a TMIC and an EEPROM in a conventional liquid crystal display.

Referring to FIGS. 1 and 2, the TMIC 10 and the EEPROM 20 are electrically connected to a serial clock line (SCL) and serial data (SDA) to enable data reading and access. line.

The TMIC 10 may include a plurality of masters 11, 12 and 13 (MasterA to MasterC), and each of the plurality of masters 11 to 13 is a combination of a conventional timing controller and a data driver.

Each of the masters 11, 12 and 13 of the TMIC 10 can be connected to the EEPROM 20 in a predetermined order or in a round robin manner. Each of the masters 11, 12 and 13 of the TMIC 10 can load system data stored in the EEPROM 20 or write data into the EEPRO 20. [

The plurality of masters 11, 12 and 13 load system data stored in the EEPROM 20 to generate a control signal for controlling the driving circuits, Converted into a data signal, and supplied to the liquid crystal panel, thereby displaying the image on the liquid crystal panel.

A plurality of masters 11, 12 and 13 share one EEPROM 20. When the same EEPROM data is needed, the masters 11, 12, and 13 sequentially divide the time through the I2C protocol, .

In the I2C protocol, a plurality of masters are connected to one channel, and access / read is performed to one slave by sharing a line through a device ID.

Thus, in the prior art, two or more masters can not simultaneously access the EEPROM 20 at the same time. Therefore, as shown in FIG. 2, the first master 11 having the priority of channel access first accesses the EEPROM 20 and loads data.

After completing the access of the EEPROM 20 in the first master 11, a read done flag is generated to give the next master the access priority of the I2C channel. Thereafter, the other masters 12 and 13 acquire the access priority of the I2C channel according to the predetermined order, and sequentially access the EEPROM 20 to load the data.

If the time required for one master to access the EEPROM 20 and load the data is T (1 Mater EEPROM access time), a total number of N (master number) masters required to access the EEPROM 20 to load data The time is N * T.

As described above, as the number of masters in the TMIC 10 increases, the overall access time of the EEPROM 20 increases in proportion to the increase in the number of masters in the liquid crystal display device according to the related art, thereby increasing the system initialization time of the liquid crystal display device .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an image display device capable of reducing a data read access time between a timing controller (TMIC) and an electrically erasable programmable read only memory And to provide a driving method.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an image display apparatus and a driving method thereof that can reduce the initialization time of the system.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

According to an embodiment of the present invention, there is provided a method of driving an image display device, the method comprising: granting a use right of an I2C channel to a first TMIC among a plurality of TMICs (Timing controller Merged ICs); Accessing the stored data of the EEPROM by the first TMIC that has obtained the I2C channel usage right; Detecting a device address of data to be accessed by the first TMIC and providing the device address to a second one of the plurality of TMICs; And accessing the same data through the I2C line by the first TMIC and the second TMIC when the device address accessed by the first TMIC and the device address of the data being accessed by the second TMIC are the same, And the plurality of TMICs are connected to one I2C interface.

The method of driving an image display apparatus according to an exemplary embodiment of the present invention is a method of operating a video display device in which when a plurality of TMICs want to access data stored at the same device address of the EEPROM, And a plurality of TMICs access the same data at the same time.

In the method of driving an image display apparatus according to an embodiment of the present invention, a second master that fails to acquire the I2C channel usage right monitors an I2C line, and transmits an I2C start command generated in the first TMIC and transmitted through an I2C line And detects the device address of the data to be accessed by the first TMIC.

An image display apparatus according to an embodiment of the present invention includes a plurality of TMICs for converting image signals input from the outside and supplying image data to a liquid crystal panel; An EEPROM storing system data; And connecting the plurality of TMICs with the EEPROM, and when the device address of the EEPROM accessed by the first TMIC among the plurality of TMICs is the same as the device address of the EEPROM accessed by the second TMIC, And an I2C interface for allowing the first TMIC and the second TMIC to access data stored in the same device address of the second TMIC.

The I2C interface of the video display device according to the embodiment of the present invention may include an I2C controller for granting the I2C channel usage right to the plurality of TMICs in a predetermined order; A channel checking unit for checking a free state of an I2C channel to which the plurality of TMICs and the EEPROM are connected; A finite state machine (FSM) for setting the random time delay using a random time delay signal generated by a random number generator; A collision detector for detecting a collision of the I 2 C channel and entering a random time delay mode when collision of the I 2 C channel is detected; An address verification unit for confirming the device address of the EEPROM accessed by the first TMIC that has obtained the I2C channel usage right and providing the device ID to the second TMIC that has not acquired the I2C channel usage right; And a storage unit for storing data to be accessed in the EEPROM.

The I2C interface of the video display device according to an embodiment of the present invention may be configured such that when a plurality of TMICs want to access data stored in the same device address of the EEPROM, The same data is accessed to the plurality of TMICs at the same time.

The video display device and the driving method thereof according to the embodiment of the present invention can reduce the data access time (read access time) between the TMIC (Timing controller Merged IC) and the EEPROM (electrically erasable and programmable read only memory).

The image display apparatus and the driving method thereof according to the embodiment of the present invention can reduce the initialization time of the system.

In addition, other features and advantages of the present invention may be newly understood through embodiments of the present invention.

1 is a view showing a method of transmitting and receiving data between a TMIC and an EEPROM of a liquid crystal display according to a related art.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display (LCD), and more particularly,
3 is a view showing a video display device according to an embodiment of the present invention.
4 is a view showing a TMIC of a video display device according to an embodiment of the present invention.
5 and 6 are views showing a method of transmitting and receiving data between a TMIC and an EEPROM in an image display apparatus according to an embodiment of the present invention.
7 is a diagram illustrating an effect of reducing data transmission / reception time between a TMIC and an EEPROM through application of a video display device and a driving method according to an embodiment of the present invention.

Hereinafter, an image display apparatus and a driving method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

According to an embodiment of the present invention, there is provided an image display apparatus capable of reducing a data read access time (read access time) between a TMIC (Timing Controller Merged IC) and an EEPROM (Electrically Erasable and Programmable Read Only Memory) And a driving method thereof.

To this end, the image display apparatus according to the embodiment of the present invention includes a configuration as shown in FIG. 3 and FIG.

FIG. 3 is a view showing an image display apparatus according to an embodiment of the present invention, and FIG. 4 is a diagram showing a TMIC of an image display apparatus according to an embodiment of the present invention.

3 and 4, an image display apparatus according to an embodiment of the present invention includes a plurality of TMICs 100 (Timing controller Merged IC); A liquid crystal panel 300; A plurality of FPCs (flexible printed circuits) 300 for connecting the plurality of TMICs 100 and the liquid crystal panel 400; An electrically erasable programmable read only memory (EEPROM) 200; And an I2C interface (Inter Integrated Circuit interface) for controlling a channel between the plurality of TMICs 100 and the EEPROM 200; A gate driver (not shown) and a backlight driver (not shown).

The liquid crystal panel 400 displays an image using image data input from a plurality of TMICs 100 and includes a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm.

A plurality of pixels are formed for each region defined by the intersection of the plurality of gate lines and the plurality of data lines. The plurality of pixels may include R, G, and B sub-pixels, and each sub-pixel includes a storage capacitor Cst and a thin film transistor (TFT).

A plurality of TMICs 100 are formed by a timing controller and a data driver (Source Driver IC) on a single chip, and convert a video signal input from an external system into digital video data of a frame unit.

Then, the digital video data of the frame unit is converted into an analog video signal (data voltage) and supplied to the data lines formed on the liquid crystal panel 400. At this time, the video signal data is converted into digital image data using a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, and a clock signal CLK input from the outside.

The TMIC 100 generates a gate control signal GCS for controlling the gate driver (not shown) and the gate control signal GCS for controlling the gate driver (not shown) using the horizontal synchronizing signal Hsync, the vertical synchronizing signal Vsync and the clock signal CLK, And generates a data control signal DCS for controlling the supply of the analog video signal.

In addition, a backlight control signal (BLCS) for controlling driving of a backlight (LED, CCFL, or EEFL) is generated, and the generated backlight control signal BLCS is supplied to a backlight driver . At this time, the backlight control signal BLCS may be generated so as to be synchronized with the analog video signal supplied to the liquid crystal panel 400.

The data control signal DCS includes a source start pulse SSP, a source sampling clock SSC, a source output enable SOE, and a polarity control signal POL, Polarity) and the like.

The gate control signal GCS may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE).

The gate driver generates a scan signal (gate drive signal) for driving a TFT formed in each of the plurality of pixels based on a gate control signal (GCS) from the TMIC 100.

The generated scan signal is sequentially supplied to a plurality of gate lines formed in the liquid crystal panel 400 during one frame period, and the TFT formed in each pixel is driven by the scan signal to switch pixels.

Since the liquid crystal panel 400 does not generate self-light emission, the liquid crystal panel 400 displays an image using light supplied from the backlight unit.

The backlight unit is for irradiating light to the liquid crystal panel 400 and includes a plurality of backlights for generating light, an optical member for guiding light generated in the backlight toward the liquid crystal panel, (A light guide plate, a diffusion plate, a reflection plate, and a plurality of optical sheets).

Here, the CCFL (Cold Cathode Fluorescent Lamp), EEFL (External Electrode Fluorescent Lamp), and LED (Light Emitting Diode) can be applied as the backlight.

The on-off time, duty, and luminance of the backlight are controlled based on the backlight control signal BLCS provided from the TMIC 100 by controlling the driving of the backlight .

As one example, the backlight driver generates a driving signal (or PWM signal: pulse width modulation signal if the backlight is an LED) for controlling the brightness of the backlight based on the backlight control signal BLCS. The backlight driver controls the brightness of the backlight by using the generated PWM signal.

In the EEPROM 200, system initialization data of the liquid crystal display and data for controlling the TMIC 100 are stored. Each of the plurality of TIMCs 100 loads the system data stored in the EEPROM 200 at the time of system initialization to generate control signals for initialization and image display of the image display apparatus.

A plurality of TMICs 100 and an EEPROM 200 are connected to a serial clock line (SCL) and a serial data line (SDA) so that data can be read and accessed.

In the case of the TMIC 100 in which the timing controller and the data driver are integrated into one chip, a plurality of TMICs 100 share one EEPROM 200. Therefore, a plurality of TMICs 100 can access the same EEPROM 200 at the same time.

At this time, in case of the conventional EEPROM access method, when the plurality of TMICs 100 access the EEPROM 200 sequentially in the same read operation, the read access time increases in proportion to the number of TMICs .

In the present invention, a plurality of TMICs 100 can load system data stored in the EEPROM 200 at the same time. Therefore, it is possible to reduce the read access time of the EEPROM 200 regardless of the coefficient of the TMIC 100, thereby shortening the time for loading the system data and the system initialization time.

To this end, a plurality of TMICs 100 are connected to an I2C interface (Inter Integrated Circuit interface), and the I2C interface includes a channel check unit 110; A collision detecting unit 120; An address checking unit 130; An I2C controller 140; A finite state machine (FSM) 150; A pseudo random number generator 160; And a storage unit 170 (internal register).

Hereinafter, the configuration of the TMIC 100 of the video display device and the method of transmitting / receiving data between the TMIC 100 and the EEPROM 200 according to the embodiment of the present invention will be described with reference to FIG. 5 to FIG.

When the first TMIC accesses the data of the EEPROM 200 by using the I2C channel, the I2C interface transfers the I2C channel usage right to the second TMIC and the second TMIC when accessing the same data. So that all the TMICs 100 can access the data of the EEPROM 200 at the same time without limitation.

Acquiring an I2C channel usage right for a plurality of TMICs 100 sharing one EEPROM 200, acquiring an I2C channel usage right for a second TMIC and a third TMIC that have not acquired an I2C channel usage right except for the first TMIC, The TMIC 100 accesses the data accessed by the TMIC 100 in the same manner so that the TMIC 100 can complete the reading of the data in the EEPROM 200 at the same time.

The FSM 150 generates a start signal and supplies the start signal to the random number generating unit 160. The random number generating unit 160 generates a random time delay signal based on the start signal and supplies the generated random time delay signal to the FSM 150 .

Here, the FSM 150 sequentially changes state of the limited states by sequentially making a state transition with respect to the entire state that can be represented in the sequential digital circuit.

When the TMIC 100 connected to the EEPROM 200 through one I2C interface is reset, the FSM 150 generates a random time delay signal using the random time delay signal input from the random number generator 160, i.e., an idle time (S10).

When the random time delay is completed (S20), each of the plurality of TMICs 100 accesses the EEPROM 200 using an I2C channel, that is, if the I2C channel is in a free state using the channel check unit 110 (30). At this time, the channel check unit 110 reports to the FSM 150 whether the I2C channel is free.

If the I2C channel is in the free state, the I2C controller 140 gives the first TMIC of the plurality of TMICs the right to use the I2C channel.

The first TMIC that has acquired the right to use the I 2 C channel starts I 2 C read access and accesses data stored at a specific address of the EEPROM 200 (S 40). The data accessed from the EEPROM 200 is temporarily stored in the storage unit 170.

For example, the second TMIC and the third TMIC monitor the I2C line. The first TMIC and the third TMIC monitor an I2C start command transmitted through the I2C line, ) do.

At this time, the collision detecting unit 120 detects the collision of the I2C channel, and when collision detection of the I2C channel is detected, the collision detecting unit 120 enters the S10 procedure to perform the process after the idle time.

In this case, when the data stored in the same address of the EEPROM 200 is accessed using the I2C channel simultaneously by a plurality of TMICs, synchronization can be perfectly established between the TMICs, so that data stored in the EEPROM 200 It does not affect the read access of the memory. In addition, since the pull-up circuit is used due to the characteristics of the I2C line, a short phenomenon between the TMICs does not occur when a collision occurs.

The second TMIC and the third TMIC, which have detected the I2C start command in the I2C line, confirm the address of the EEPROM 200 accessed by the first TMIC using the address verification unit 130 (S60).

When the first TMIC and the third TMIC access the same address as the EEPROM 200 (slave) to which the third TMIC wants to read, that is, when the same address is detected, a control less read mode ), And accesses data accessed by the first TMIC through the I2C channel in the same manner (S70).

That is, when the first TMIC and the third TMIC want to access the same data accessed by the first TMIC, the second TMIC and the third TMIC wait for the end of the use of the first TMIC's I2C channel, And the first TMIC accesses the same data that accesses the data of the EEPROM 200 at the same time.

Thereafter, all the TMICs that have accessed the data of the same address from the EEPROM 200 perform a checksum on the read data after the read of the data, and then check the reliability of the read data (S50 ).

At this time, if the checksum fails as a result of checking the reliability of the data, the process goes to the step S10 and performs the process after the idle time.

As a result of checking the reliability of the data, if the checksum is successful, the second TMIC and the third TMIC, which have accessed the data stored in the EEPROM 200 together with the first TIMC, complete the data to be accessed by the third TMIC at step S80.

At this time, the TMIC that has accessed the data from the EEPROM 200 does not need to issue a read access complete flag for transferring the right to use the I2C channel from another TMIC.

Thereafter, all the TMICs transit to the infinite loop state and do not attempt to access the EEPROM 200. [

6 and 7, a plurality of TMICs access the data stored at the same address of the EEPROM 200 at the same time, as shown in FIG. 6 and FIG. 7, according to an embodiment of the present invention implemented by the above- , It is possible to shorten the data read access time between the TMIC and the EEPROM. Therefore, the system initialization time of the video display device can be reduced.

It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: TMIC 110: Channel check section
120: collision detector 130:
140: I2C controller 150: FSM
160: random number generator 170:
200: EEPROM 300: FPC
400: liquid crystal panel

Claims (10)

Assigning a use right of an I2C (Inter Integrated Circuit) channel to a first TMIC among a plurality of TMICs (Timing controller Merged ICs);
Accessing data stored in the EEPROM by the first TMIC that has acquired the usage right of the I2C channel;
Detecting a device address of data to be accessed by the first TMIC and providing the device address to a second one of the plurality of TMICs; And
When the first TMIC and the second TMIC access the same data via the I2C line when the device address accessed by the first TMIC and the device address of the data that the second TMIC wants to access are the same,
And the plurality of TMICs are connected to one I2C interface. The method according to claim 1,
Wherein the plurality of TMICs access the same data at the same time without limiting use rights of the I2C channel to the plurality of TMICs when the plurality of TMICs desire to access data stored at the same device address of the EEPROM, A method of driving a video display device. The method according to claim 1,
In the step of granting the right to use the I2C channel,
After the random time delay, the plurality of TMICs check the free state of the I2C channel, and when the free state of the I2C channel, the use right of the I2C channel is notified to any one of the plurality of TMICs Wherein the video display device is a video display device. The method of claim 3,
The second master that has not obtained the usage right of the I2C channel monitors the I2C line and detects an I2C start command generated in the first TMIC and transmitted through the I2C line to generate a device address Of the video signal. The method according to claim 1,
Further comprising detecting a collision of the I2C channel, and entering a random time delay mode when a collision of the I2C channel is detected. The method according to claim 1,
Further comprising checking a checksum for data that has been accessed, and upon completion of reading the data if the checksum is successful, the plurality of TMICs transitions to an infinite Loop state, A method of driving a video display device. A plurality of TMICs (Timing controller Merged IC) for converting image signals input from the outside and supplying the image data to the liquid crystal panel;
An EEPROM storing system data; And
When the device address of the EEPROM accessed by the first TMIC among the plurality of TMICs is the same as the device address of the EEPROM accessed by the second TMIC, the I2C (Inter Integrated Circuit) is connected to the plurality of TMICs and the EEPROM, And an I2C interface (Inter Integrated Circuit interface) for allowing the first TMIC and the second TMIC to access data stored in the same device address of the EEPROM through a line. 8. The method of claim 7,
The I <
An I < 2 > C controller for granting use rights of an I2C (Inter Integrated Circuit) channel to the plurality of TMICs in a predetermined order;
A channel checking unit for checking a free state of an I2C channel to which the plurality of TMICs and the EEPROM are connected;
A finite state machine (FSM) for setting a random time delay using a random time delay signal generated by a random number generator;
A collision detector for detecting a collision of the I 2 C channel and entering a random time delay mode when collision of the I 2 C channel is detected;
An address verification unit for confirming a device address of the EEPROM accessed by the first TMIC that has obtained the usage right of the I2C channel and providing the device ID to the second TMIC that has not obtained the usage right of the I2C channel; And
And a storage unit for storing data to be accessed in the EEPROM. 9. The method of claim 8,
Wherein the I2C interface transmits the same data to the plurality of TMICs at the same time to the plurality of TMICs without restriction of use rights of the I2C channel when the plurality of TMICs desire to access data stored at the same device address of the EEPROM To the display device. 9. The method of claim 8,
The second master that has not obtained the usage right of the I2C channel monitors the I2C line and detects an I2C start command generated in the first TMIC and transmitted through the I2C line to generate a device address Is detected.

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