KR101187572B1 - Drive control circuit of liquid display device - Google Patents

Abstract

The present invention relates to a technique for preventing a black screen from being displayed unnaturally when a normal signal is not input when a timing controller is used in combination with each source driver IC in an image display device.
To this end, the present invention includes one master TMC and at least one TMC, wherein the master TMC provides a master clock generated by an internal oscillator when the normal signal is not input to the slave TMC and uses the same. Image data according to the generated image control signal, and the slave TMC generates the image control signal by using the master clock provided from the master TMC when the normal signal is not input, and then uses the image. Output the data.

Description

DRIVE CONTROL CIRCUIT OF LIQUID DISPLAY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technology of a display device. In particular, when a timing controller is used in combination with each source driver IC, a display device can prevent an unnatural display of a black screen without a normal signal being input. It relates to a drive control circuit of.

In recent years, flat panel display devices such as liquid crystal display (LCD), PDDP, organic light emitting diode (OLED) panel and the like have been widely used.

1 is a block diagram of a display device including a display panel and a driving circuit unit according to the related art, and as shown therein, the display panel 110, the timing controller 120, and a plurality of source driver ICs ( 130A-130C) and a gate driver IC 140.

Referring to FIG. 1, the display panel 110 includes a plurality of pixels arranged in a matrix at an intersection of a plurality of data lines and a plurality of gate lines. Each transistor formed in the pixel transfers a data voltage input from the data line to the pixel driver in response to a scan signal supplied from the corresponding gate line.

The timing controller 120 controls the gate control signal and the source driver ICs 130A-130C to control the gate driver IC 140 using the vertical / horizontal synchronization signal and the clock supplied from the display panel 110 and the system. Generates a data control signal for control.

The source drivers ICs 130A to 130C convert the data into data voltages corresponding to the gray scale values in response to the data control signals supplied from the timing controller 120 and supply the data voltages to the data lines of the display panel 110.

The gate driver IC 140 sequentially supplies scan pulses (gate pulses) to the gate lines in response to a gate control signal supplied from the timing controller 120, so that horizontal lines of the display panel 110 are supplied with data. Is optionally driven.

In a state in which the normal signal is not input, the timing controller 120 provides the source driver ICs 130A-130C with data (mainly black data) generated using an internal oscillator. The state in which the normal signal is not input includes a state in which power is applied and a signal is not input (a section before inputting a normal signal after power on) or an abnormal signal in which power is applied and out of a normal operation range.

However, even when the normal signal is not input as described above, since one timing controller 120 provides data to the plurality of source driver ICs 130A-130C and drives them, as described above, the plurality of source driver ICs 130A The problem of having to synchronize the data output of -130C) does not occur.

Recently, in order to meet the demand for larger and slimmer display devices, a driving chip (TMIC) merged into a timing controller and a plurality of source driver ICs (hereinafter, referred to as 'TM IC') Is being developed.

As such, in the case of the TMC in which the timing controller is merged into a plurality of source driver ICs, the timing controller has its own oscillator and performs a timing control function and a source driving function by using a clock generated therefrom. Therefore, when a plurality of TMCs are used to drive the display panel, deviations occur between frequencies generated by the oscillators provided in each TMC.

Therefore, when the TMC outputs image data using image control signals such as a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal generated by an internal oscillator clock in a state where no normal signal is input, The problem of inconsistency occurs.

For this reason, in the conventional display field, when the vertical synchronization signal, the horizontal synchronization signal, the data enable signal or the data clock are not input in the power-on state, or when a signal is input but a signal out of the normal operating range is input, There is a defect that an unnatural black screen is displayed.

Accordingly, an object of the present invention is to synchronize the data synchronization between TMCs in a system using a TMC in which a timing controller and respective source driver ICs are merged, so that slave TMCs use a master clock supplied from a master TMC. To make it possible.

The objects of the present invention are not limited to the above-mentioned objects. Other objects and advantages of the invention will be more clearly understood by the following description.

According to the present invention for achieving the above object, when the normal signal is not input, the master TMC provides a master clock generated by the internal oscillator to the slave TMC, the slave TMC from the oscillator of the master TMC A source driver and a timing controller, each of which is configured to generate an image control signal using a provided master clock and output image data using the master clock, include a master TMC and one or more slave TMCs.

According to the present invention, in a system using a TMC in which a timing controller and each source driver IC are merged, a horizontal synchronous signal using a master clock supplied from a master TMC to a slave TMC in a state in which a signal is not supplied from the outside, By generating image control signals such as a vertical synchronization signal and a data enable signal, and outputting the image data by using them, the synchronization of data between TMCs can be matched, resulting in an unnatural black screen on the display panel. There is an effect that can be prevented from being displayed.

1 is a block diagram of a display device including a display panel and a driving circuit unit according to the related art.
2 is a block diagram of a drive control circuit of a market value according to an embodiment of the present invention.
FIG. 3 is a detailed block diagram of the master TMC and the slave TMC in FIG. 2.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a driving control circuit of a display device according to an exemplary embodiment of the present invention. As shown therein, a display panel 210, a plurality of TMCs 220A-220C, and a gate driver IC 230 are shown. Equipped.

Referring to FIG. 2, the display panel 210 includes a plurality of pixels arranged in a matrix at an intersection of a plurality of data lines and a plurality of gate lines. Each transistor formed in the pixel transfers a data voltage input from the data line to the pixel driving element in response to a scan signal supplied from the corresponding gate line.

TMC 220A-220C includes one TMC acting as a master and one or more TCM acting as slaves. In this example, the TMC 220A operates as a master and the remaining TMCs 220B and 200C operate as slaves. The output pads of the TMC 220A are electrically connected to input pads of adjacent TMC 220B, and the output pads of the TMC 220B are electrically connected to input pads of adjacent TMC ICs 220B and 200C. do. Accordingly, the master clock output from the oscillator 223A of the TMC 220A is transmitted to the TMC 220B, and then to the TMC 200C of the next stage.

The TMC 220A includes a source driver 221A, a timing controller 222A, and an oscillator 223A. The TM IC 220B includes a source driver 221B, a timing controller 222B, an oscillator 223B, and a multiplexer 224B. Similarly, the TMC 220C includes a source driver 221C, a timing controller 222C, an oscillator 223C, and a multiplexer 224C.

The source drivers 221A to 221C include a shift register, a latch, a D / A converter, a gamma voltage generator, and an output unit.

The shift register repeats the operation of storing the data of each input channel one by one in accordance with the shifted pulses, and once all of the image data of one horizontal line are stored, they are outputted to the latch portion at once. The latch unit temporarily stores the input one horizontal line amount of image data and outputs it to the digital (D) / analog (A) converter. The D / A converter selects a gamma voltage corresponding to the input data value from the gamma voltage input from the gamma voltage generator and outputs it to the output unit.

The timing controllers 222A to 222C include a command processor, a register controller, a timing processor, a synchronization signal generator, and a gate signal generator.

The command processor interfaces the input command signal and transfers the command signal to the register controller. The register controller controls operations of the multiplexers 224B, 224C, and the oscillators 223A-223C in response to the master / slave operation information provided from the command processor. The command signal may include master / slave operation information. For example, the register controller stores master / slave operation information in a register, and the information controls the operations of the multiplexers 224B, 224C, and the oscillators 223A-223C. The master / slave operation information is information for determining whether the corresponding timing processor operates as a master or as a slave. The master / slave operation information may be set as a pin option input or a register value. The sync signal generator generates a source control signal such as a vertical / horizontal sync signal, a data enable signal, and provides the same to the source drivers 221A-221C according to the control of the timing processor. The timing processor generates timing information using the clocks of the oscillators among the oscillators 223A through 223C, and controls the driving of the sync signal generator and the gate signal generator by using the timing information. The gate signal generator generates a gate control signal under the control of the timing processor and provides the gate control signal to a gate line of the display panel 210. The gate control signal includes a gate clock GCLK and a gate output enable signal GOE.

The multiplexer 224B selects a master clock input from the oscillator 223A of the TMC 220A through an input pad according to the slave information and provides the master clock to the timing controller 22B. Similarly, the multiplexer 224C selects a master clock input from the oscillator 223A of the TMC 220A through the TMC 220B and an input pad according to the slave information and provides the same to the timing controller 220C. do.

Oscillator 223B of TMC 220B and oscillator 223C of TMC 220C may be turned off according to the slave operation information.

The TMC 220A operates as a master according to the master operation information when a state in which a normal signal is not input is detected. At this time, the timing controller 222A of the TMC 220A provides the master clock generated by the oscillator 223A to the timing controller 222B corresponding to the first slave driving chip through the output pad. The timing controller 222A detects a signal input to the source driver 221A by using the master clock generated by the oscillator 223A, thereby determining whether or not a normal signal is not input.

When the state in which the normal signal is not input as described above is detected, TMC 220B operates as a slave according to the slave operation information. In this case, the multiplexer 224B of the TMC 220B selects a master clock provided from the TMC 220A and provides the master clock to the timing controller 222B.

When the state in which the normal signal is not input as described above is detected, the TMC 220C corresponding to the second slave driving chip operates as a slave according to the slave operation information. In this case, the multiplexer 224C of the TMC 220C selects a master clock provided from the TMC 220A and provides the master clock to the timing controller 222C.

There may be various paths for providing the master clock generated by the TMC 220A operating as the master to the TMC 220B and the TMC 220C operating as the slave without the normal signal being input.

For example, as illustrated in FIG. 2, the glass 211 may be transferred or may be transferred through an FPC (Flexible Printed Circuit).

As a result, according to the present exemplary embodiment, since the slave driving chips share the master clock generated by the master driving chip in a state where the normal signal is not input, the problem that the image data output from the plurality of driving chips is not synchronized is eliminated. Can be.

Although the preferred embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto, and may be implemented in various embodiments based on the basic concept of the present invention defined in the following claims. Such embodiments are also within the scope of the present invention.

210: display panel 220A-220C: TMC
221A-221C: Source Driver 222A-222C: Timing Control
223A-223C: Oscillator 224B, 224C: Multiplexer
230: gate driver IC

Claims (5)

In the driving control circuit of a display device comprising a master TMC and one or more slave TMC each of which the source driver and the timing controller are merged,
The master TMC provides a master clock generated by an internal oscillator when the normal signal is not input to the slave TMC and outputs image data according to an image control signal generated by using the master TMC.
The slave TMC generates the image control signal using the master clock provided from the master TMC when the normal signal is not input, and then outputs the image data using the master control circuit. .
The method of claim 1, wherein the master TCM
An oscillator for generating a master clock inside the master TMC;
When the normal signal is not input, the controller operates in a master mode according to master / slave operation information to generate an image control signal using a master clock generated by the oscillator, and outputs an image control signal to an internal source driver, and outputs the master clock to the master clock. And a first timing controller provided to the slave TMC side.
The method of claim 1, wherein the slave TMC is
A multiplexer for selecting a slave clock generated by an internal oscillator when a normal signal is input, and selecting and outputting a master clock provided from the master TMC when the normal signal is not input;
And a second timing controller which operates in a slave mode according to master / slave operation information when a normal signal is not input to generate an image control signal using a master clock received through the multiplexer and provide the image control signal to an internal source driver. A drive control circuit for a display device.
4. The drive control circuit according to claim 2 or 3, wherein the master / slave operation information is set to a pin option input or a register value.
The driving control circuit of claim 1, wherein the slave TMC is received through the glass or the FPC when the master TMC receives the master clock from the master TMC.

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