TWM341927U - Packaging structure - Google Patents

Packaging structure Download PDF

Info

Publication number
TWM341927U
TWM341927U TW097205767U TW97205767U TWM341927U TW M341927 U TWM341927 U TW M341927U TW 097205767 U TW097205767 U TW 097205767U TW 97205767 U TW97205767 U TW 97205767U TW M341927 U TWM341927 U TW M341927U
Authority
TW
Taiwan
Prior art keywords
substrate
pads
die
package structure
conductive strips
Prior art date
Application number
TW097205767U
Other languages
Chinese (zh)
Inventor
Ching-Shan Wang
Chin-Chih Chen
Original Assignee
Chipsip Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipsip Technology Co Ltd filed Critical Chipsip Technology Co Ltd
Priority to TW097205767U priority Critical patent/TWM341927U/en
Publication of TWM341927U publication Critical patent/TWM341927U/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

A packaging structure including a substrate, a plurality of pads, a plurality of wires, a plurality of conductive sticks, a die and a packaging material is provided. The pads are located on the substrate and disposed to two side of the substrate, respectively. The conductive sticks are located on the pads. The die is located on the substrate. The wires electrically contact the die to the pads. The packaging material overlaying the substrate, one side of each conductive stick is exposed to the outside of the packaging material.

Description

M341927M341927

且特別是一 種半導體 八、新型說明: 【新型所屬之技術領域】 本創作是有關於一種封裝結構 元件的封裝結構。 【先前技術】And especially a semiconductor. 8. New description: [New technical field] This creation is about a package structure of a package structure component. [Prior Art]

隨著科技的進步,半導體產業蓬勃發展 (例如:晶粒)的封裝技術也不斷推陳出冑,所〜導體元件 對於半導體元件作包裝,可以保護半導體元;係 並提供與外界電路連接的功能。 α政熱’ ,像 是二造:::封裝技術仍具有許多問題需要解決 因此’基於上述原因’需要—種新的封裝結構 到降低製造成本的目的 【新型内容】 本創作的目的就是提供一種封裝結構,所解決的技術 問題係為此封裝結構的侧面可連接外部電路,解決問題的 技術手段可參照以下的實施例。 依照本創作一實施例,一種封裝結構包含:一基板、 多個焊墊、多個焊線、多個導電條、一晶粒、一封裝膠體。 其中,多個焊墊,位於此基板上且分別配置於此基板之兩 側;多個導電條,分別位於多個焊墊上;至少一晶粒,位 於此基板上;多個焊線,電性連接此晶粒與多個焊墊;以 及’此封裝膠體上覆此基板,其中每一導電條的一面暴露 5 M341927 「------------: . i μ . ' I . ·,- I * f . ^ ^ i ^ • i年月日7 : 丨 於此封裝膠體外。藉此,此封裝結構的側面所暴露的導電 • 條可連接外部電路。對照先前技術的功效係為此封裝結構 無需額外的接腳來連接外部電路,有效地降低製造成本。 以下將以實施例對上述之說明以及接下來的實施方式 做詳細的描述,並對本創作提供更進一步的解釋。 【實施方式】 為了使本創作之敘述更加詳盡與完備,可參照下列之 圖示及各種實施例,圖示中相同之號碼代表相似之元件。 另一方面’眾所週知的電路元件並未描述於實施例中,以 避免造成本創作不必要的P艮制。 請參照第1A-1B圖,其中第1A圖係繪示依照本創作 實施例的一種封裝結構的立體圖,而第1B圖係繪示沿第 3A圖之A-A線的剖面圖。第1B圖中,封裝結構1〇〇可包 含一基板110、多個焊墊130、多個焊線15〇、多個導電條 120、至少一晶粒160、一封裝膠體170。其中,多個焊墊 130係位於基板11〇上且分別配置於基板11()之二側,多個 導電條120分別位於多個焊墊130上,且導電條12〇電性 連接焊墊130’晶粒160位於基板11〇上,多個焊線15〇 電性連接蟲粒160與多個焊墊130,封裝膠體17〇上覆基板 110,並包覆晶粒160及焊線150,其中導電條13〇的面220 暴露於封裝膠體170外,且導電條130的面220分別眺連 基板110兩侧的側面430。如此一來,可藉由暴露於封裝膠 體170外的面220,使晶粒160與外部電路作電性連接。 另外,導電條120可包含金屬,封裝膠體17〇可包含 M341927 環氧樹脂。 97i 7. 3 1 修正補充 年月曰 雖然未創作已以實施例揭露如上,然其並非用以限定 本創作,任何熟習此技藝者,在不脫離本創作之精神和範 圍内,當可作各種之更動與潤飾,因此本創作之保護範圍 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1A圖係繪示依照本創作實施例的一種封裝結構的 立體圖。 第1B圖係繪示沿第1A圖之A_A線的剖面圖。 【主要元件符號說明】 100 :封裝結構 110 :基板 120:導電條 130 :焊墊 15〇 :焊線 160 :晶粒 170 :封裝膠體 220 :面 43〇 :側面 7With the advancement of technology, the packaging technology of the semiconductor industry booming (for example, die) is constantly evolving. The conductor components are packaged for semiconductor components to protect the semiconductor elements; the system provides functions for connecting to external circuits. . "α政热', like the second::: packaging technology still has many problems to be solved, so 'based on the above reasons' need - a new packaging structure to reduce manufacturing costs [new content] The purpose of this creation is to provide a The package structure, the technical problem to be solved is that the side of the package structure can be connected to an external circuit, and the technical means for solving the problem can be referred to the following embodiments. According to an embodiment of the present invention, a package structure includes: a substrate, a plurality of pads, a plurality of bonding wires, a plurality of conductive stripes, a die, and an encapsulant. Wherein, a plurality of solder pads are disposed on the substrate and respectively disposed on two sides of the substrate; a plurality of conductive strips respectively located on the plurality of pads; at least one die on the substrate; a plurality of bonding wires, electrical Connecting the die and the plurality of pads; and 'this encapsulant overlying the substrate, wherein one side of each of the strips is exposed to 5 M341927 "------------: . i μ . ' I ·, - I * f . ^ ^ i ^ • i date 7: 丨 outside the package, whereby the conductive strips exposed on the sides of the package structure can be connected to external circuits. For this package structure, no additional pins are needed to connect the external circuit, which effectively reduces the manufacturing cost. The above description and the following embodiments will be described in detail with reference to the embodiments, and further explanation of the present invention is provided. [Embodiment] In order to make the description of the present invention more detailed and complete, reference is made to the following drawings and various embodiments, in which like numerals represent like elements. On the other hand, the well-known circuit elements are not described in the implementation. In the example 1A-1B, wherein FIG. 1A is a perspective view of a package structure according to the present embodiment, and FIG. 1B is a view along line 3A. A cross-sectional view of the AA line. In FIG. 1B, the package structure 1A may include a substrate 110, a plurality of pads 130, a plurality of bonding wires 15A, a plurality of conductive strips 120, at least one die 160, and a package. The plurality of soldering pads 130 are disposed on the substrate 11 and are respectively disposed on the two sides of the substrate 11 (). The plurality of conductive strips 120 are respectively disposed on the plurality of pads 130, and the conductive strips 12 are electrically connected. The pad 130 dies 160 are located on the substrate 11 , and the plurality of bonding wires 15 are electrically connected to the worm 160 and the plurality of pads 130 . The encapsulant 17 is overlying the substrate 110 and covers the die 160 and the bonding wires. 150, wherein the surface 220 of the conductive strip 13 is exposed outside the encapsulant 170, and the surface 220 of the conductive strip 130 is respectively connected to the side 430 on both sides of the substrate 110. Thus, the surface exposed by the encapsulant 170 can be exposed 220, the die 160 is electrically connected to an external circuit. In addition, the conductive strip 120 may comprise a metal, and the encapsulant 17 M341927 Epoxy resin may be included. 97i 7. 3 1 Amendment Supplementary Year 曰 Although it has not been created by the above examples, it is not intended to limit the creation of this work, and anyone who is familiar with the art does not deviate from the spirit of this creation. In the scope of the present invention, the scope of protection of the present invention is subject to the definition of the patent application scope. [FIG. 1A] FIG. FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A. [Main component symbol description] 100: package structure 110: substrate 120: conductive strip 130: pad 15: wire 160 : die 170 : encapsulant 220 : face 43 〇: side 7

Claims (1)

M341927 九、申請專利範圍: 1 · 一種封裝結構,包含: 一基板; 複數個焊塾,位於該基板上且分別配置於該基板之二 侧; 複數個導電條,分別位於該些焊墊上; 至少一晶粒,位於該基板上; 複數個焊線,電性連接該晶粒與該些焊墊;以及 * 一㈣膠體,上覆該基板,其中每—導電條的一面暴 露於該封裝膠體外。 2·如叫求項1所述之封裝結構,其中該些導電條的該 些面分別毗連該基板之二側的侧面。 3·如請求項1所述之料結構,其中該些導電條分別 電性連接該些焊墊。 月求項1所述之封裝結構,其中該封裝膠體包覆 該晶粒及該些焊線。 5.如請求们所述之料結構,其中該導電條包含金 8 M341927 6.如請求項1所述之封裝結構,其中該封裝膠體包含 環氧樹脂。M341927 IX. Patent application scope: 1 · A package structure comprising: a substrate; a plurality of soldering pads on the substrate and respectively disposed on two sides of the substrate; a plurality of conductive strips respectively located on the pads; a die on the substrate; a plurality of bonding wires electrically connecting the die and the pads; and a (four) colloid overlying the substrate, wherein one side of each of the conductive strips is exposed to the package . 2. The package structure of claim 1, wherein the faces of the plurality of conductive strips respectively adjoin the sides of the two sides of the substrate. 3. The material structure of claim 1, wherein the conductive strips are electrically connected to the pads. The package structure of claim 1, wherein the encapsulant encapsulates the die and the bonding wires. 5. The material structure as claimed in claim 1, wherein the conductive strip comprises gold 8 M341927. 6. The package structure of claim 1, wherein the encapsulant comprises an epoxy resin.
TW097205767U 2008-04-03 2008-04-03 Packaging structure TWM341927U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW097205767U TWM341927U (en) 2008-04-03 2008-04-03 Packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW097205767U TWM341927U (en) 2008-04-03 2008-04-03 Packaging structure

Publications (1)

Publication Number Publication Date
TWM341927U true TWM341927U (en) 2008-10-01

Family

ID=44334620

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097205767U TWM341927U (en) 2008-04-03 2008-04-03 Packaging structure

Country Status (1)

Country Link
TW (1) TWM341927U (en)

Similar Documents

Publication Publication Date Title
US8115299B2 (en) Semiconductor device, lead frame and method of manufacturing semiconductor device
JP3619773B2 (en) Manufacturing method of semiconductor device
US8451621B2 (en) Semiconductor component and method of manufacture
US9385072B2 (en) Method of manufacturing semiconductor device and semiconductor device
US20160056097A1 (en) Semiconductor device with inspectable solder joints
TWI621232B (en) Semiconductor device
JP2014515187A5 (en)
JP2011155203A (en) Semiconductor device
JP2014127706A5 (en) Manufacturing method of semiconductor device
CN104241233A (en) A wafer level semiconductor package and a manufacturing method thereof
CN203871315U (en) Electronic equipment
JP6909630B2 (en) Semiconductor device
JP6258538B1 (en) Semiconductor device and manufacturing method thereof
TWI429351B (en) Memory card package having a small substrate
TWM341927U (en) Packaging structure
JP6909629B2 (en) Semiconductor device
US9190355B2 (en) Multi-use substrate for integrated circuit
KR20100069001A (en) Semiconductor package
JP5587464B2 (en) Manufacturing method of semiconductor device
CN104681504A (en) Electronic equipment with first and second contact bonding pads and relevant method thereof
TW201711114A (en) Semiconductor device manufacturing method, semiconductor device and lead frame capable of suppressing unnecessary deformation of a lead
CN106531709B (en) The manufacturing method of semiconductor device
TW407442B (en) Flat chip package structure
TW201526187A (en) Chip element and chip package
TWI243463B (en) Chip on board package and method for manufacturing the same

Legal Events

Date Code Title Description
MM4K Annulment or lapse of a utility model due to non-payment of fees