M339758 八、新型說明： 【新型所屬之技術領域】 本創作係-種記憶體模組，特別係-種具有高可靠度的記憶賴組。 【先前技術】 • 按，記憶體模組於電腦及週邊的應用相當地普及，且隨著對於資 料存取完整性之高度需求，有些記憶體模組具有錯誤偵測及校正功能或 是自我測試功能，以提高記憶體模組之功效。 • 紗我國專利證號第1242號之「用於記憶體模組之自我測試及修復之 系統及方法」，主要是使用自我測試模組運行自我測試功能以識職記憶體裝置 之缺陷記舰位址，再使歸麵_應針_記㈣裝置之雜記憶體位址 的記憶體請求，及重新導向記㈣紐之無缺陷記題位址，$，缺陷記憶體 位址無法再次使用，儲存之資料數值無法進行錯誤偵測及校正，僅標記缺陷記 憶體位址，但依舊無法達到高可靠度要求；我國專利證號第烈備號之「具有 内建自我測試之記憶體模組及記顏元件」，其揭示—種具有喊自我測試之記 離憶體元件，主要是由回返電路比較輸出及輸入測試資料，並產生測試結果，控 •制器將記憶體陣列測試資料傳送給記憶體陣列，並存放測試資料於記憶體之 -中’並從記憶體中讀取該記憶體陣列之測試資料，進行測試資料比較，以產生 測試結果，惟，測試資料圖案不易建立，且無法進行記憶體陣列之缺陷記憶體 .位址標記，亦無數值資料之錯誤_及校正魏，而無法達到高可靠度要求， 另，我國專利證號第69525號之「偵測電腦系統中記憶區段干擾之方法與裝置」， 藉由微處理器在力紐上定義許多祕段，每-個記憶體區段有_對應的之權 限等級，由保護暫存器來儲存及決定記憶體區段索引值，保護暫存器依據索引 5 M339758 值來判定是否發生記憶體違規，此方法僅用來標示記憶體區段之存取權限，卻 無法提供高可靠度的數值資料。 我國專利證號第1252397號之「錯誤症狀辨識之記憶體自我診斷與修復的 方法與裝置」，主要是利用三種不同失敗圖案的辨識方法及一個症狀格式結構， •在測試記憶體的過程中去辨識該記憶體之錯誤的位址及錯誤字元，並輸出該錯 誤症狀的資訊，再根據前述資訊利用内建冗餘分析法則，找出空白的記憶體元 素去修復錯誤的記憶胞，此方法僅提供自我診斷及修復功能，惟，一旦記憶體 馨之任-記憶體區段出現永久性失效時，就會造成所有記憶體無法使用，且又缺 乏缺陷記憶齡址標記；細專卿5_9號之「錯誤改正記㈣及其操作方 法」’其揭示-種半導體記職置，主要是由記㈣_儲存資料數值及對應之 錯誤更正碼數值(Error Correction Code，ECC)，當記憶體陣列在一寫入存取 動作編，因應該寫入資料數值以產生一錯誤更正魏值，當讀取寫入的資料 數值時，錯誤更正碼數值如偵測到錯誤，會產生一錯誤指示信號，於是寫入緩 衝器會在記髓裝置_置週_，將更正㈣料數值及對蘭錯誤更正碼數 馨值回寫至記憶體陣列，完成資料數值的校正，此方法僅提供資料數值的錯誤偵 測及ϋ &旦雜、體之任—記憶體區段…見永久性失效時，就會造成所 -有δ己憶體無法使用’且又缺乏缺陷記憶體位址標記。 細補《第卿5號之「職偵_修正鎌統」，其所揭示的偵測 錯誤於記憶系統之方法，主要是使用錯誤偵测與校正(Err〇r Detecti〇n㈣M339758 VIII. New description: [New technical field] This creation is a kind of memory module, especially a kind of memory with high reliability. [Prior Art] • Press, memory modules are widely used in computers and peripheral applications, and with the high demand for data access integrity, some memory modules have error detection and correction functions or self-tests. Function to improve the efficiency of the memory module. • Yarn China Patent No. 1242, “Systems and Methods for Self-Testing and Repair of Memory Modules”, mainly using self-test modules to run self-test functions to locate faults in memory devices. Address, then the _ _ _ _ _ _ (4) device memory address request memory, and re-directed (four) New Zealand's defect-free address, $, defective memory address can not be reused, stored information The value cannot be detected and corrected by mistake. Only the address of the defective memory is marked, but the high reliability requirement cannot be achieved. The memory module and the recording component with built-in self-test are the patent number of China Patent Certificate No. , revealing a kind of memory component with a self-test, mainly by comparing the output and input test data by the return circuit, and generating test results, and the controller transmits the memory array test data to the memory array, and The test data is stored in the middle of the memory and the test data of the memory array is read from the memory, and the test data is compared to generate the test result, however, The test data pattern is not easy to establish, and the defect memory and address mark of the memory array cannot be performed, and there is no error in the numerical data _ and the correction of Wei, and the high reliability requirement cannot be achieved. In addition, China Patent No. 69525 "Method and device for detecting memory segment interference in a computer system", by means of a microprocessor defining a plurality of secret segments on the force, each memory segment has a corresponding level of authority, by the protection register To store and determine the memory segment index value, the protection scratchpad determines whether a memory violation occurs according to the index 5 M339758 value. This method is only used to indicate the access rights of the memory segment, but cannot provide high reliability. Numerical data. China Patent No. 1252397, "Method and Device for Memory Self-diagnosis and Repair of Wrong Symptom Recognition", mainly uses three different failure pattern identification methods and a symptom format structure, • in the process of testing memory Identify the wrong address and error character of the memory, and output the information of the error symptom, and then use the built-in redundancy analysis rule to find a blank memory element to repair the wrong memory cell according to the foregoing information. Only self-diagnosis and repair functions are provided. However, once the memory of the memory-permanent section has a permanent failure, all the memory will be unusable and the defect memory age mark will be lacking. "Error Correction (4) and its operation method" 'disclosed - a semiconductor record, mainly by remembering (4) _ store data values and corresponding error correction code values (ECC), when the memory array is in Write access action code, because the data value should be written to generate an error correction Wei value, when reading the written data value, the error is more If the positive code value detects an error, an error indication signal will be generated, so the write buffer will write back the memory value in the memory device, and correct the (four) material value and the correct value of the blue error correction code to the memory. Array, complete the correction of the data value, this method only provides the error detection of the data value and the amp & 杂, the body of the —— memory segment ... see permanent failure, it will cause the δ ** recall Unable to use 'and lack defective memory address tag. To supplement the "Secondary No. 5 "Occupational Reconnaissance_Revision System", the method of detecting errors in the memory system is mainly to use error detection and correction (Err〇r Detecti〇n (4)
Correct ’腫)機制’將資料數值加上錯誤_碼數值儲存至記憶體區段， 利用錯誤綱設施，進行㈣數似錯誤_碼錄之錯誤侧及錯誤校正， 此方法僅提供資值的錯誤_及校正，惟，—旦記賴之任—記憶體區段 6 M339758 出現水久性失效時’就會造成所有記憶體無法使用，且又缺乏缺陷記憶體位址 標記。 因此’在a憶體模組領域，係有必要提出—種更完善的記憶體模 組，以解決上述之限制與缺失。 【新型内容】 在此具體且詳細敘述本創作之目的，其為了克服習知技術之缺 點’遂提出-種朗的記憶體模組，其具有錯關測與校正功能以及 _自制4功i，改善自動倾舰並加人數值校正形成錯誤細與校正() 碼’而自制郝賴加人標記舰，記錄錯誤症狀及產生次數，再利用標案 管理方式以酬錯誤標記_段，保«料數值的完，故可提高系統的抗 干擾能力，進而達到高可靠度的要求。 '根據本創作所揭示的記憶體模組，係包括一記憶體陣列，一樓案管理 控制器，闕狄或輸出至少―:雜錄，且決定資料數值寫人至記憶體陣列 之-無錯誤標記的區段中，—自我測試控繼，其_檔錄理控制器且產生 φ -具有正碟字元特徵與錯誤字元特徵的自我測試圖案，及一錯誤侧及校正 、⑽c)編解碼電路與記憶體陣列、檔案管理控制器、自我測試控制器柄接， -以接收貝料數值且產生對應該資料的錯誤制與校正碼（EDAc)數值，並將資 料數值與EDAC數值儲存在記憶體陣列甲，當讀取資料數值時係先經由編解碼電 路，進行錯誤侧與校正碼確認、標記或校正後，才經由該檔錄理控制器輸 出’且編解碼電路X可減自細試贿職記紐_是^有錯紐段，若 有，則對錯誤區進行標記且輸出-自我測試結果至自我測試控制器，其再輸出 自我測試結果至檔案管理控制器以紀錄此錯誤區段。 7 M339758 本創作之目的或其他目的對於此技藝之通常知識者而言，閱讀以下實施例 之詳細内容後係顯而易知的。 先前的概述與接下來的詳細敘述都是範例，以便能進一步解釋本創作之專 利請求項。 【實施方式】 請參照第一圖，係本創作之記憶體模組結構示意圖。如圖所示， 本創作之記憶體模組10乃包括一記憶體陣列12，其係同步動態隨機存取記憶 馨體(Synchronous Dynamic Random Access Memory，SDRAM)之記憶體陣列，一檔 案管理控制器14，用以接收或輸出資料數值及負責檔案管理，且決定將資料數 值寫入至記憶體陣列12之一無錯誤標記的區段，其中檔案管理控制器μ包括一 檔案類型紀錄器141以及一區段鏈結表(Sector Chain Table，SCT)142，透過區 段鏈結表(SCT)142來紀錄記憶體陣列12所使用之區段、檔案結束區段、空白區 段、預定區段與錯誤標記區段，檔案類型紀錄器14ι則用於決定區段鏈結表142 之最後區段是否需連結至起始區段，即檔案管理控制器14係以檔案方式來管理 _所有記憶财列12之容量，依據檔案之大小自動鏈結對應區段，且當記憶體陣 列12之區段具有錯誤標記時，區段鏈絲142會_被標記之記憶體陣列區段， 並自動鏈結至下-個記㈣陣舰段，以符合難崎的正確完整，一自我測 試控制器16祕檔案管理控制器14,其中自我測試控制器16包括—自我測試圖 案早70161與-相麵接的序列產生器162，自我測試圖案單元i6i係用以產生一自 我測試圖案，且此自我測試_包括正確字元特徵及單—錯誤料、多重錯誤 字疋特徵’序列產生益162則是用以產生自我測試圖案至記憶體陣列⑽位址。 錯誤偵測及校正（Error Detection and Correction，EDAC)的編解碼電路 8 M339758 18 ’其具一錯誤偵測及校正(EDAC)編解碼器181耦接記憶體陣列12，係用以產生 對應資料數值的錯誤偵測與校正碼（EDAC)數值，一多工器182耦接EDAC編解碼 器181、自我測試圖案單元161與擋案管理控制器14 ,用以接收資料數值與自我 測試圖案，一解多工器183耦接EDAC編解碼器181與自我測試控制器16，用以接 收受標記的錯誤區段之單一或多重的錯誤字元之錯誤特徵。另有一記憶體控制 器20，其具有一序列產生器且耦接記憶體陣列12與檔案管理控制器14，用以安 排資料至記憶體陣列12的路徑。 φ 承上述之記憶體模組10，檔案管理控制器14接收數值資料，如第一圖所示 接收數值資料1與數值資料2，之後檔案管理控制器14將數值資料傳送至^^…編 解碼電路18 ’ EDAC編解碼電路18經由多工器182接收資料數值且傳送至舰〇編解 碼器181產生職此㈣數_錯誤制與校正碼⑽AG)數值，並將資料數值 與EDAC數值合併在同一寫入指定位址而儲存在記憶體陣列12中，其中記憶體控 制器20就是用以控制記憶體陣列12於寫入存取動作期間，安排資料數值、寫入 位址數值及EDAC數值至指定記憶體陣列12之路徑，且，數值資料丨與數值資料2 籲受讀取或輸出時，減經由EDAC、編解碼器18卜進行錯誤偵測與校正碼確認、標 、記或校正後，才經由檔案管理控制器14輸出，其中，舰c編解碼器181輸出數值 •資料時，尚會將錯誤_及校正⑽AC)碼移除。另，#在讀寫過程發生一位元 之資料數值錯誤時，EDAC編碼器⑻即進行數值校正，並將錯誤概、症狀傳輸 至檔錄理控制H14以記錄之，當在讀寫過程發生二位元之_數值錯誤時， EDAC編碼!|1關·行數健正，而錢將錯轉徵、錄傳至齡管理控制 器14以記錄之。 由此可知’利用EDAC編解碼電路18即可读測資料數值是否有錯誤字元，甚 9 M339758 至當資料數值是發生-位元錯誤，尚可對其進行數值校正後才輸出，故透過EDAC 編解碼電路18之设什更能確保資料數值的正確性與完整性。 且’本創作並可對記憶體p車列12進行測試，⑽試所有的空白記憶體是否有 錯誤區段，p方止數值資料儲存在記憶體陣列之錯誤區段中。射，當自我測試控 ,制器16接收槽案管理控制器14之指令後，就進行記憶體自我測試，即自我測試圖 案單兀161輸出自我測試圖案至EDAC編解碼電路ι8，^^人^編解碼器181就可根據自 我測試控·16所輸出的自我職_職記髓_12是否有錯誤區段，依照 肇序列產生器162所產生之記憶體位址進行自我測試圖案之寫入及讀取動作，直至 記憶體陣列12之所有位址冑完成為止，當£廳編解碼㈣丨有侧到錯誤區段， 則標記此錯誤區段且輸出-自我測試結果至自我測試控制器16，自我測試控制器 再輸出此自我測試結果至檔案管理控制器14之區段鍵結表142，對此錯誤區段進 行紀錄。 因此，區段鏈結表142跳過記憶體陣列之有錯誤標記區段，並自動鏈結至下 -個記憶断列區段’進而提供此資訊給用以安排資料至記顏_路徑的記 眷憶體控制器2〇，使得數值資料或是EMC值能夠儲存在記憶體陣列之無錯誤區段 •中，避開已產生錯誤之記憶體區段，提高記憶體陣列之使用效率，保存完整之 資料數值。且，檔案型態年錄器141具有線性檔案型態及循環權案型態，依照所 屬的標案名稱及類型進行記憶體陣列的使用規劃，同時可存在多個不同類型權 .案於記憶體陣列，資料數值的輸入介面可為多重介面，而不再是單一輸入及輸 出’其中’在線性檔案型態下，資料數值寫入至記憶體陣列係從起始區段至結 束區段時即停止，若是在彳《髓Μ下，倾數值寫人至結束區段並跳至起 始區段繼續寫入。 M339758 综上所述，本創作所揭示的記憶體模紅，可跳過有錯誤症狀標記的記 憶體陣列區段而完成資料數值的存取動作，提高記憶體陣列之使用效率，進而 克服習知記憶體模組因具有一、二個或三個字元的錯誤就無法使用之窘境，且 本創作又透過檔案管理方式，同時接收不同介面來源的資料數值，因此記憶體 模組的功能性可更為提高，應用性亦更為廣泛。 • 以上所述之實施例僅係為說明本創作之技術思想及特點，其目的 在使熟習此項技藝之人士能夠瞭解本創作之内容旅據以實施，當不能 •以之限定本創作之專利範圍，即大凡依本創作所揭示之精神所作之均 等變化或修飾，仍應涵蓋在本創作之專利範圍内。 【圖式簡單說明】 第一圖係本創作之記憶體模組的方塊示意圖。 【主要元件符號說明】 10記憶體模組 1以舰_ 14構案管理控制器141檔案類型紀錄器 籲142區段鏈結表 丨6自我測試控制器 161自_試_單元⑽相產生_ .18錯誤偵測及校正編解碼電路 181錯誤偵測及校正編解碼器 182多工器 183解多工器 2〇記憶體控制器Correct 'swelling mechanism' stores the data value plus the error _ code value in the memory segment, and uses the error program to perform (4) error-like _ code recording error side and error correction. This method only provides the error of the value. _ and correction, only, if the record is - memory segment 6 M339758 when the water is ineffective, 'will cause all memory to be used, and lack of defective memory address mark. Therefore, in the field of a memory module, it is necessary to propose a more complete memory model to solve the above limitations and defects. [New content] The purpose of this creation is specifically and in detail described herein, in order to overcome the shortcomings of the prior art, the proposed memory module has a fault detection and correction function and a self-made function. Improve the automatic dumping and add the numerical correction to form the error fine and correct () code' and the self-made Hao Laijia marked the ship, record the error symptoms and the number of occurrences, and then use the standard management method to compensate the error mark _ segment, protect the material After the value is completed, the anti-interference ability of the system can be improved, thereby achieving high reliability requirements. The memory module disclosed in the present invention includes a memory array, a first-floor case management controller, or a display of at least ": a chord, and determines the data value to be written to the memory array - no error In the marked section, the self-test is controlled, and the _-recording controller generates φ - a self-test pattern with positive disc character features and wrong character features, and an error side and correction, (10) c) codec The circuit is connected to the memory array, the file management controller, and the self-test controller, to receive the billet value and generate an error system and an error code (EDAc) value corresponding to the data, and store the data value and the EDAC value in the memory. Body array A, when reading the data value, the code side circuit is first confirmed, marked or corrected by the error side and the correction code, and then the output is processed via the file recording controller, and the codec circuit X can be reduced from the fine test. The bribe letter _ is ^ there is a wrong section, if there is, the error area is marked and the output - self-test results to the self-test controller, which then outputs the self-test results to the file management controller to record the error Incorrect section. 7 M339758 The purpose of this creation or other objects will become apparent to those of ordinary skill in the art in reading the details of the following embodiments. The previous overview and the following detailed description are examples to further explain the patent claims of this creation. [Embodiment] Please refer to the first figure, which is a schematic diagram of the structure of the memory module of the present invention. As shown in the figure, the memory module 10 of the present invention comprises a memory array 12, which is a synchronous dynamic random access memory (SDRAM) memory array, a file management controller. 14. The method for receiving or outputting data values and responsible for file management, and determining to write the data values to a segment of the memory array 12 without error marks, wherein the file management controller μ includes a file type recorder 141 and a A Sector Chain Table (SCT) 142 records a section, a file end section, a blank section, a predetermined section, and an error used by the memory array 12 through a section chain table (SCT) 142. The markup section, the file type recorder 14i is used to determine whether the last section of the section link table 142 needs to be linked to the start section, that is, the file management controller 14 manages all files in an archive manner. The capacity, the corresponding segment is automatically linked according to the size of the file, and when the segment of the memory array 12 has an error flag, the segment chain 142 will be marked with the memory array segment, and the automatic chain Down to the next (four) array segment to meet the correct integrity of the difficult, a self-test controller 16 secret file management controller 14, wherein the self-test controller 16 includes - self-test pattern early 70161 and - face-to-face The sequence generator 162, the self-test pattern unit i6i is used to generate a self-test pattern, and the self-test _ includes the correct character feature and the single-error material, the multiple error word feature' sequence generation benefit 162 is used to generate Self test pattern to memory array (10) address. Error Detection and Correction (EDAC) codec circuit 8 M339758 18 'Equipped with an error detection and correction (EDAC) codec 181 coupled to the memory array 12 for generating corresponding data values The error detection and correction code (EDAC) value, a multiplexer 182 is coupled to the EDAC codec 181, the self-test pattern unit 161 and the file management controller 14 for receiving data values and self-test patterns, The multiplexer 183 is coupled to the EDAC codec 181 and the self test controller 16 for receiving error characteristics of single or multiple error characters of the marked error segment. There is another memory controller 20 having a sequence generator coupled to the memory array 12 and the file management controller 14 for arranging the data to the memory array 12. φ According to the above memory module 10, the file management controller 14 receives the numerical data, and receives the numerical data 1 and the numerical data 2 as shown in the first figure, after which the file management controller 14 transmits the numerical data to the ^^... codec. The circuit 18' EDAC codec circuit 18 receives the data value via the multiplexer 182 and transmits it to the ship codec 181 to generate the (four) number_error system and the correction code (10) AG) value, and combines the data value with the EDAC value. The memory controller 20 is used to control the memory array 12 during the write access operation to arrange the data value, the write address value, and the EDAC value to the specified address. The path of the memory array 12, and when the numerical data 数值 and the numerical data 2 are subjected to reading or outputting, the error detection and correction code confirmation, labeling, recording or correction are performed after the EDAC and the codec 18 are subtracted. Outputted via the file management controller 14, wherein the error code and the correction (10) AC) code are removed when the ship c codec 181 outputs the value data. In addition, when the data value of one bit in the reading and writing process is wrong, the EDAC encoder (8) performs numerical correction, and transmits the error profile and symptoms to the file recording control H14 to record it, when the reading and writing process occurs. When the _value of the bit is wrong, the EDAC code!|1 is closed and the number of lines is positive, and the money will be transferred to the age management controller 14 for recording. It can be seen that 'UDAC codec circuit 18 can read the data value whether there is an error character, even 9 M339758 to when the data value is generated - bit error, it can be output after the value correction, so through EDAC The codec circuit 18 is more capable of ensuring the correctness and integrity of the data values. And the author can test the memory p train 12, (10) test whether all the blank memory has an error segment, and the p-square value data is stored in the error segment of the memory array. When the self-test is controlled, the controller 16 receives the instruction of the slot management controller 14, and performs a memory self-test, that is, the self-test pattern unit 161 outputs the self-test pattern to the EDAC codec circuit ι8, ^^人^ The codec 181 can write and read the self-test pattern according to the memory address generated by the sequence generator 162 according to whether the self-test control 16 outputs the self-service _12. The action is taken until all the addresses of the memory array 12 are completed. When the codec (4) has the side to the wrong section, the error section is marked and the self-test result is output to the self-test controller 16, self. The test controller then outputs the self test result to the segment key table 142 of the file management controller 14, and records the error segment. Therefore, the segment link table 142 skips the error flag segment of the memory array and automatically links to the next memory segment segment' to provide this information to the record for arranging the data to the face_path. The memory controller 2〇 enables the numerical data or the EMC value to be stored in the error-free section of the memory array, avoiding the memory segment that has generated errors, improving the efficiency of the memory array, and saving the integrity. The data value. Moreover, the file type annual record recorder 141 has a linear file type and a circular rights type, and uses the memory array according to the name and type of the standard file, and there may be multiple different types of rights. Array, the input interface of the data value can be multiple interfaces, instead of a single input and output 'where' in the linear file type, when the data value is written to the memory array from the start segment to the end segment Stop, if it is under the sputum, pour the value to the end segment and jump to the starting segment to continue writing. M339758 In summary, the memory redness disclosed in the present invention can skip the memory array segment with the wrong symptom mark and complete the access operation of the data value, thereby improving the use efficiency of the memory array, thereby overcoming the conventional knowledge. The memory module can not be used because of the error of one, two or three characters. The creation of the memory module can also receive the data values of different interface sources through the file management method. Therefore, the functionality of the memory module can be It is more improved and more applicable. The above-mentioned embodiments are only for explaining the technical ideas and characteristics of this creation, and the purpose thereof is to enable those skilled in the art to understand the content of the creation of the creation, and to implement the patents of the creation. The scope, that is, the equivalent changes or modifications made by the spirit of this creation, should still be covered by the scope of this creation. [Simple description of the diagram] The first diagram is a block diagram of the memory module of the present creation. [Main component symbol description] 10 memory module 1 with ship _ 14 configuration management controller 141 file type recorder 142 section link table 丨 6 self-test controller 161 from _ test _ unit (10) phase generation _. 18 error detection and correction codec circuit 181 error detection and correction codec 182 multiplexer 183 solution multiplexer 2 〇 memory controller