TW440765B - L2 cache testing method - Google Patents

Abstract

This invention provides a L2 cache testing method for directly testing the L2 cache of computer system through the execution of computer to check if the function of L2 cache works properly. The method includes: getting the allocation parameter and capacity size of the L2 cache; then initiating the L2 cache to make the content of cache (including a L1 cache and a L2 cache) identical to that of the memory; and finally using the cache bus related control registers to access the L2 cache to check if the function of L2 cache works correctly.

Description

440765 V. Description of the invention (1) [Scope of application of the invention] The present invention relates to a test method of a secondary cache memory / particularly a buffer storage using a computer system (Pe [ulum Π or higher) as The Cache Bus Related Control Registers (Cache Bus Related Control Reglsters) can control the status and access data of the u Cachet tag module and the data module respectively, and can directly use the operation of the computer to detect L2. Cache function is the normal test method. [Technical background of the invention] In the past, in the computer structure of Intel Pentium II or lower, a cache memory (Cache) was set between the microprocessor and the main memory (MaU Memory). The technology to improve the data access speed of the microprocessor is already well known (its hardware block diagram is shown in "Figure 1A"). And this type of cache memory (Cache) includes: The first level buffer memory 20 (li Cache) of the processor 10 (CPU) and a second level cache memory 3 (L2 Cache) located outside the microprocessor; and the Intel Pentium II level (inclusive) and above The L2 Cache 30 in the computer system is placed in the processor, and its hardware block diagram is as shown in "Figure 1B"; where the L2 Cache ( The scale of L2 Cache) 30 is much larger than that of LI Cache 20, and under normal operating conditions, 'Ll Cache 20's access speed is usually 1 times faster than L2 Cache 30' and L2 Cache 30 Is usually faster than main memory (main

C: \ PrograraFiles \ Patent \ p-0178tw.ptd Page 4 076 5 V. Description of the invention (2) " 'memory " 40 is 3 to 5 times faster' 'Therefore it has an advantage in improving the access speed of the microprocessor 10. Obvious benefits. So ’’s Cache working? It is very important for computer makers or users. 'If the cache is damaged during the manufacturing process', it may cause disorder and crash of the computer system in operation, or cause serious loss of data. Cause serious losses. If such hardware defects are not properly detected, it will not only affect the manufacturer's goodwill ’, but also cause consumers to suffer inestimable damage. However, in the current known technology, there is still no test method or test tool (such as test software) that can directly test the function of L2 Cache. [Objective and Summary of the Invention] The main object of the present invention is to provide a function that can be directly executed by a computer to perform a function test on a level 2 cache (L2 Cache) in a computer system of Pentium level II or higher. method. According to the test method disclosed in the present invention, the following steps can be completed through a computer: 1. Initialize the L2 Cache; [During this process, disable (Disable) the LI Cache and the L2 Cache to invalidate the contents of the Cache and let the The modified data in the cache and the unmodified data in the main memory (Memory) are written back to the main memory, so that the contents of Cache and Merary are consistent. ] 2. Perform data access test on the L2 Cache and output the corresponding test results; [Generate read and write commands to the L2 Cache and test the actual address space corresponding to the L2 Cache lines (Cache lines)

C: \ Program F i1es \ Patent \ p-〇178tw. Ptd page 5 " 440765 V. Description of the invention (3) Buffer bus related control register (Cache Bus

Related Control Registers) read and write the L2 Cache to verify the integrity of the L2 Cache function. ] And 3. Judge the test results and output success or error messages. According to the technology disclosed in the present invention, the user can quickly complete the L2 Cache test by performing the above steps on the computer system where the L2 Cache is to be tested, thereby providing a quick and convenient test method. . The detailed technical content and embodiments of the present invention are described as follows with reference to the drawings. [Illustration of the diagram] Qiao 1A 'is a hardware block diagram between the microprocessor, LI Cache, L2 Cache, and main memory in the computer system below Pen t um Π level. Figure 1 β is a hardware block diagram between the Pentium I level I (inclusive) computer system, ten microprocessors, LI Cache, L2 Cache, and main memory. Figure 2 shows the data storage structure inside L2 Cache. Figure 3 is a flowchart of the main test steps of the method. Fig. 4 'is a detailed flowchart of a partial test procedure of the present invention. FIG. 5 is a detailed flowchart of a partial test procedure of the present invention. Figures 6-1, 6-2 are detailed flowcharts of the partial test steps of the present invention. Please refer to "Figure 2" for the internal data storage of L2 Cache 30

440765 V. Description of the invention (4) Structure diagram 'General and Lu' L 2 C ache 3 0 includes two relatively independent tags RAM module 300 and data RAM module 301; among them, 3 modules 3 0 0 is used to store l 2 C ache 3 0 when the operation hits Hit T ag 'State (S tate), the least recently used array (Least Recently Used array); and the data module is used to The data backup of the main memory 40 is stored, that is, the data storage location. Please refer to "Figure 3". The method disclosed in the present invention can be performed by a computer by performing the following steps, which include: 1. Detect whether the environment in which the computer runs meets the requirements of the test, and if it does, proceed to the next step. ' Otherwise, it prompts the user to set the correct test environment 'and end the test; [Because the process of testing must require the current computer's operating environment to be in the real address (Rea i Address) operating mode, it is necessary to first set the current computer operating mode Perform detection so that the following test steps can be performed normally. ] 2. Obtain the configuration parameters and capacity of L2 Cache 30. [The subsequent detection process is mainly based on the data obtained here. ] 3. Initialize L2 Cache 30; [In this step, the L1 Cache 20 and L2 Cache 30 will be disabled (Disable), the contents of the Cache will be invalidated, and the changes stored in the Cache (20, 30) will be stored in the main memory. The unmodified data in the bank 40 is stored back into the main memory 40, so that the contents of the cache (20, 30) and the memory 40 are consistent. 】

C: \ Program Files \ Patent \ p-〇178tw. Ptd Page 7 440765 V. Description of the invention (5) 4. Test L2 Cache 30; [Generate read and write commands to L2 Cache 30, test L2 Cache 30 lines (Cache lines) corresponding to the actual address space, it uses the cache memory related control registers (Cache Bus Related Control Registers) to access the L2 Cache 30 data, in order to verify the positive L 2 C ache 3 0 function Integrity °] 5. Judge the test result. If the test passes, it outputs a successful message, otherwise it outputs an incorrect message; and 6, it returns to the initial state. [In this process, enable (E n a b 1 e) L1 Cache 20 and L2 Cache 30 to enable the Cache to work normally. ] Step 1 also includes (see "Figure 4"): la. Check the current computer operating mode; [Generally, there is a control named CR0 in the microprocessor 10 above 8 04 86 level A register, which controls the current state of the computer system; and in the microprocessor 10 below level 80486, a machine status word register (MSW, Machine Status Word) is provided. By detecting the logic level of the PE (Protect Enable) terminal in CR0 or MSW, the current state of the microprocessor 10 can be judged. If PE = 1, it means that it is in Protect Mode, otherwise if PE = 0 Indicates that it is in the Real Address Mode. ] 1 b · Determine whether it is a real address mode? If yes, proceed to the next step; otherwise, prompt the user to set the correct test environment, and then end the test;

C: \ Program F i1es \ Patent \ p-0178tw. Ptd p. 8 440765 5 'Description of invention (6) 1 C · Detect the type of microprocessor 1 in the computer system; and Id · Determine whether it is Pentium Π level If the above microprocessor 10? Is YES, skip to step 2, if not, end the test. [Because the method disclosed in the present invention is a hardware architecture implemented by a computer system of Pen Tium II or higher, the cache memory related control registers (Cache Bus Related Control Registers) are used to cache the L2 Cache. 30 to access data to check whether the function of L2 Cache 30 can run normally, so it is necessary to make this judgment. 】 Step 2 in it includes the following steps (see "Figure 5") '2a. Get the L2 Cache 30 capacity (Total Size); [Can be temporarily stored according to the relevant control of the "buffer storage bus" (C ache B us R e 1 ated C ο ntr ο 1 R egisters) "; and the so-called Cache Bus Related Control Registers are a group of register groups existing in the processor, and these The register group belongs to the processor MSR (Model Specific Register). Please refer to “Table 1” for related settings. ] 2b _ Get the number of memory pages (Bank) of L2 Cache 30; 2c. Get the number of associated columns (L2 way) of L2 Cache 30; and 2d · Calculate the storage capacity of each column of L2 Cache 30 (Size

Per Way). [The calculation formula is Total Size / L2 Way] As for the detailed process of testing L 2 C a c h e 3 0 described in step 4, now take

C: \ ProgramFiles \ Patent \ p-0178tw_ptd Page 9 440765 V. Description of the invention (7) Capacity 256Kbytes 'L2 Cache 30 with 32bits cache as an example' Please refer to "Section 6 — 1, 6 — 2 ", including: 4 A ♦ Set a counter I (C ache R 〇w) counter I = 0; 4B. Set a counter (Cache lines) counter J = 0; 4C * define an address Space; [that is, the L2 Cache line is converted to the actual address space in L2 Cache 30] 4 D · Fill in the test data into the aforementioned address space; [The test data is known, such as stored in Data in main memory 40. ] 4 E. Determine whether the write was successful? If yes, proceed to the next step, if not, output an error message, and then skip to step 5; 4F. Read the data in the aforementioned address space; 4 G * Determine whether the reading of the data was successful? If yes, go to the next step, if not, output an error message, then skip to step 5; 4 Η · Compare whether the data written and read are the same, if yes, go to the next step, if not, turn An error message is issued, then skip to step 5; 4 I · Set the counter of the test line (C ache 1 ines) J = j + 3 2; [Since the 'Cache line is 32 bits in this example, it is incremented by 3 2 is used to correctly read the data of the next cache line when testing the next row (R0W). ] 4 J. Determine if J > Size Per Way? If yes, go to the next step

C: \ Program Files \ Patent \ p-〇178tw. Ptd Page 10 440765 V. Description of the invention (8) Step, if not, skip to step 4C; 4k. Set the counter of the test row (Cache Row) ι = ι + ι; [Incrementally test each column] and 4L. Determine if I > L2 Way? If yes (indicating that all columns have been tested), output a normal message, and then skip to step 5, if not, skip to step 4B . Therefore, from the above technical content, we can understand that through the implementation steps disclosed in the present invention, we will be able to use a computer to directly test its internal L2 C ache 3 0 'and judge this L2 based on the results of data access. Is Cache 30 working properly? In the actual implementation stage, each of the above steps will be completed in a programmatic manner on a computer system to be tested-a test program, and this test program is stored in a computer-readable recording medium ( (E.g. CD-ROM, disk or memory) 'to run on a computer system. [Effects of the invention] 1 · Low cost: The technology provided by the present invention can be tested simply by executing the above test program directly in the computer system to be tested, without the need for other additional hardware devices. 2. Practicality: Since there is currently no testing tool for testing the L2 cache, the present invention can solve this problem. 3 _ Easy to operate: The technology provided by the present invention can be tested simply by executing the above test program directly in the computer system to be tested, without the need for complicated operations or professional skills. 4 · Can quickly detect errors: During the test, as long as the L2 Cache sends

C: \ ProgramFiles \ Patent \ p-0178tw.ptd page 11

4407 BF

V. Description of the invention (9) Any errors (such as failure to write, read, or data access errors) can be known immediately. [Illustration of Symbols]

10 · · · '•'.. · Processor 20 · · ·., * Level Cache (LI Cache) 3 0 · · 1 •. * Level 2 Cache (L2 Cache) 300 · .. .. .... Tag RAM module 301 ··· ······ Data RAM module 40 · ——_ ， * · '. Main memory (MSR) register name MSR Address (ten Hex) Description of the register i BBL_CR_D0 88 data register for reading and writing data from L2 Cache BBL_CR_D1 89 data register for reading and writing data from L2 Cache BBL_CR_D2 8A Data register | Used to read and write data from L2 Cache BBL_CR_D3 8B Data register · Used to read and write data from L2 Cache BBL_CR_ADDR 116 Address register to send data to L2 Cache The specified address BBL_CR ^ TRIG 11A trigger register, used to trigger a cache to read BBL_CR_BUSY 1 IB status register, used to indicate whether the L2 Cache command is read BBL_CR_CTL 119 control register, used to edit the L2 Cache Command BBL_CR_CTL3 HE Control Register * Used to configure L2 Cache [Table 1] C: \ Program Files \ Patent \ p-〇l78tw. Ptd page 12

Claims (1)

〇7 _ Case No. 8712Π? M… Application scope of patents — a type of secondary cache memory is included in a microprocessor-level cache memory (LI Cache) -level cache memory (L2 Cache) August - - "" . (L2 Cache) test method, a '... 于 Θ 丨 phase 1f product, JU 4 υ acne J, and a main memory (memory) pen built into the microprocessor The following steps are performed in a computer system of Tium II or higher (inclusive), which includes the following: 1 · Detect whether the environment in which the computer runs meets the requirements of the test, if it is, proceed to the next step, otherwise use it for other purposes The user sets the correct test environment, and ends the test; obtains the configuration parameters and total size of the L2 Cache; 3. initializes the L2 Cache; 4, accesses the data of the L2 Cache, do not try again, and rolls out Corresponding test results; 5. Judge the results of the test, if the test passes', then the success information is output, otherwise the wrong information is output; and 6. Restore the original state, that is, enable the "Cache and S ^ L2 Cache ° The test method for the L2 Cache described in item 1 of the scope of the patent application, wherein step 1 is performed by detecting a control register provided in the microprocessor ( CR0) or machine Device Status Word (Machine Status Word) The logical bit rate of the PE (Protect Enable) terminal ’is used to determine the current state of the computer system. If p E 2 is 1, it indicates that it is in protection mode 2 : No. 440765 ___ Case No. 87120200_Year Month Date Amendment 6. The scope of the patent application (Protect Mode), otherwise if PE = 0, it means the real address mode (Rea 1 Address Mode). 3. The test method for the second-level South-speed buffer storage 2 Cache) described in item 1 of the scope of patent application, wherein the capacity of the L2 Cache is temporarily stored according to the control related to "buffer storage buses n (Cache Bus Related Control Registers) ". ; / 4. The test method of the secondary cache (l 2 Cache) as described in item 1 of the scope of the patent application, wherein the configuration parameters of the L2 Cache include: the memory page of the L 2 C ache (B ank ) Number, the number of associated rows (L2 Way), and the storage capacity size (Size Per Way) of each row, and the Size Per Way = Total Size / L2 Way. 5. The test method of the secondary cache (L2 Cache) as described in item 1 of the scope of the patent application, wherein step 3 is to close (D i sab 1 e) the LI Cache and the L2 Cache, and enable the existence The LI Cache and the L2 Cache modify the data that has not been modified in the main memory back to the main memory, so that the LI Cache is consistent with the contents of the L2 Cache and the main memory. 6. The test method of the secondary cache (L 2 Cache) as described in item 1 of the scope of the patent application, wherein step 4 is to use a cache bus related control register (Cache Bus Related Control Registers). ) Perform data access operations on the L2 Cache, and verify whether the function of the L2 Cache is based on the access result -871202ΠΟ__Year Month and Day Amendment Six 'patent application scope is normal. 7. The test method for the secondary high-capacity buffer cache (L 2 Cache) as described in item 1 of the scope of the patent application, wherein step 4 is based on the number of memory pages (Bank) in the configuration parameters of the 12 Cache and the association The number of rows (L2 Way) and the storage capacity of each row are large * (Size Per Way), the Size Per Way = Total Size / L2 Way, to perform data access test, it also includes the following steps: 4 A · δ test counter (C ache R 〇w) counter I = 〇; 4 B · a counter test (cache 1 ines) counter j = 〇; 4C. Define an address space located in the [2 Cache; 4D. Fill in the test data into the aforementioned address space; 4E · Determine whether the writing was successful? If yes, go to next 4; otherwise, output an error message, and then skip to step 5; 4 F * Read the data in the aforementioned address space; 4G judge whether the reading of the data is successful? If yes, proceed to the next step, if not, roll out an error message, and then skip to step 5; 4 Η. Compare whether the data written and read are the same as described, if yes, proceed to the next step, if it is Otherwise, an error message is output, and then skip to step 5; ^ 4 I. Set the counter of the test line (Cacheeiines) j = j + 3 2; 4J. Determine if J > Size Per Way? If yes, go to the next step. Step, if not, skip to step 4C; 4k. Set the counter of the test row (Cache Row) 1 = 1 + 1; and 4L. Determine if I > L2 Way? If yes, output a normal message, 440765 _Case No. 8_7120200___ Car Moon Day _ Amendment __ 6. Scope of Patent Application Then skip to step 5, if not, skip to step 4B. 8. A method for testing a two-level two-speed buffer memory (L 2 C ache), which is a first-level buffer memory (LI Cache) including a microprocessor, a built-in The following steps are performed in a computer system with a primary buffer memory (L 2 C ache) external to the microprocessor and a main memory, including: 1 _initializing the L2 Cache; 2 The L2 Cache performs a data access test and outputs the corresponding test results; and 3. judges the test results and outputs success or error information. 9. The method for testing a secondary cache (L2 Cache) as described in item 8 of the scope of the patent application, wherein the step 1 is to disable (disable) the LI Cache and the L2 Cache 'and enable the LI Cache and the The data modified in the L2 Cache but not modified in the main memory is stored back to the main memory, so that the contents of the LI Cache and the L2 Cache and the main memory are kept consistent. 10. The test method for the second level cache (L2 Cache) as described in item 8 of the scope of the patent application, wherein step 2 is to use a cache bus related control register (Cache Bus Related Control Registers). ) Perform data access operation on the L2 Cache, and verify whether the function of the L2 Cache is normal according to the access result. Page