TWI342566B - Motherboard fault-finding testing method - Google Patents

Description

1342566 IX. Description of the invention: ^ [Technical field to which the invention pertains] The present invention relates to a motherboard testing technique, and more particularly to a motherboard error correction applied to a computer device having at least one memory testing method. [Prior Art] The memory system configured in the computer equipment is used to cope with the central processing unit (Cpu) to store the programs and data being executed at a high speed. Therefore, it is an important component of the computer system, and its reliability and fault tolerance. Competence has always been the subject of industry research. t目目' Industry has error detection and error correction technology (Err〇r

The Correction Code (ECC) is applied to, for example, a server, a workstation, etc., in a brain device, to test the performance of the memory configured in the computer port through the motherboard of the computer device. Moreover, the application of the above error checking and error correction technology requires the use of a memory bit error generating device to cause a memory bit error to be generated by a memory device through a reckless 6 memory bit error generating device. The motherboard performs the memory performance test operation using the error checking and error correction techniques. Please refer to FIG. 1 , which is a schematic diagram showing the configuration of the memory bit error generating device 1 applied to the memory 2 of a computer device, wherein the brother cell 2 has a plurality of chip units, and specifically, the memory is Define a memory module for double-sided pins (Dual In_line Mem〇ry

Modules; DIMMs, and the wafer unit is a Dynamic Random Access Memory (DRAM), and each of the current 110327 5 1342566: chip units have an output pin and data corresponding to the output pin 'Foot, as shown, the memory bit error generating device 1 is applied between the output pins 211a, 211b of one of the chip units 21a, 21b of the memory 2 and the data pins 2i3a, 213b to generate a double The bit memory bit is wrong, but not limited thereto, and the number of bit errors to be generated may be determined according to the number of the chip cells used by the memory bit error generating device 1 in the memory 2. . Correspondingly, the current motherboard error correction test method first inserts the memory into one of the computer device motherboards to set the Lu δ 忆 体 体 slot, and then starts the legacy computer device; then, after the computer device is started, And continuously writing a value to one of the address segments of the memory through a memory controller (MCH) 31 (shown in FIG. 1) disposed in the motherboard of the computer device; The memory bit error generating device disconnects a transmission path between the output pin of the memory unit of the memory and the data pin to generate a memory bit error block, and then reads the address bit from the memory controller through the memory controller The number of outputs is a Lu value, and when the value read from the address segment is changed from the value at the time of writing to 〇, the memory controller in the motherboard is used and the error checking and error correction technique is applied to record the value. A message about a memory error. In addition, as shown in FIG. 1, the data pins of the respective chip units of the memory device 2 disposed in the computer device are connected in parallel to the memory controller 3 through a data bus (Data Bus) 30, The data read and write operation is performed on the wafer unit of the memory 2 by the memory controller 31. However, when the transmission path between the output pins 211a and 211b of the wafer units 21a and 21b of the memory 2 and the resources 110327 6 1342566: the material pins 213a and 213b are disconnected by the memory bit error generating means. The data pins 21 3a, 213b of the wafer unit 21 a, 21 b of the memory 2 are in a floating state, that is, the value of the data pins 213a and 213b at this time depends on the error generating device by the memory bit 7C. i disconnects the output path between the output pins 2丨1 a, 2 nb and each of the δ 资料 data pins 213a, 213b, and the output pins 211 & 2111) are output to the data pins 2133, 2131) The value of the output pin 211 a, 211 b is a random number when it is disconnected, so that the value of the data pin 213a, 213b is also a random number, which may be a number # value 0 ' may also be a numerical value 1. Thus, the value J is continuously written to an address segment of the memory 2 via the memory controller 31 through the error correction test method of the motherboard, and then the memory controller 31 is from the address segment. Reading the data pin output value of each chip unit of the memory '2, at this time, the data pin of the chip unit corresponding to the memory bit error generating device j in the memory 2 corresponding to the address field The output value is still a value 丨, and the value of the data pin 213a, 213b of the chip unit 21a, 21b of the memory unit 2 in the memory 2 corresponding to the memory bit error generating device 1 may be a value. 1 or the value 〇, since the values of the data pins 21% and 213b are random numbers, when the memory bit error generating device 1 disconnects each of the output pins 211a' 211b and each of the data pins 213a, In the transmission path between 213b, when the value of the north of the data pin 213a, 21 is exactly the value 〇, the output value corresponding to the data pin ma, 213b read from the address segment is 〇, At this time, the motherboard correcting and arranging method Hyun properly destroyed, memory and recording the error-related messages; 11032771342566 and disconnected if: when 'the data pins 213a, 213b of the numerical value is exactly! When the number of outputs corresponding to the data pins 213a, 213b is ϋΪ 1, from the address segment, the value is taken from the bit ^ /, by the error correction test method of the motherboard. If both are 1, it is impossible to detect whether the memory 2 is in error or not and obtain an incorrect test result. In fact, according to the configuration of Figure 1, the double-bit memory error is generated on the 5 memory, and the memory bit error test result should record the memory device 2 position of the computer device to generate double-bit memory. Errors and other related information, and the memory error message obtained through the above-mentioned motherboard error correction test method is an uncertain factor, which greatly affects the test result. .^, 'Not on the above' How to propose a fault test that can generate correct memory - Result = Motherboard error correction test method to solve the lack of the prior art, which is the technical problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to improve the error detection test method of the motherboard of the instrument type to obtain the correct memory error test result. To achieve the above and other objects, the present invention provides a motherboard error correction test method for use in a computer device having at least one memory. ^ The clear motherboard test method includes: electrically connecting the memory to the computer device, and starting the computer device, through the motherboard of the computer device to the first address of the 4 s memory The segment continuously writes the first value, and simultaneously writes a second value to the second address segment of the memory, the _value is different from the second value; and the memory bit 110327 is generated on the memory. 1342566 The body controller simultaneously writes the first and second values to the first and second address segments of the memory, respectively, and then generates a memory bit error on the memory, and then passes through the motherboard. The memory controller reads the value outputted from the first and second address segments and compares the values written and read from the first address segment and the second address segment, respectively, and When the first and the second address segment writes are inconsistent with the read value, the 6-bit error related information is recorded, thereby disconnecting the DRAM from the memory through the memory bit error generating device. Unit output pin and data lead 'Lu foot When the transmission path is between, the value of the data pin output of the chip unit of the memory is a value of 1 or a value of 0, and one of the address segments can obtain 5 error-related information for correct test. result. The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate the other advantages and effects of the present invention from the disclosure herein. The present invention may be embodied or carried out by other specific examples of the φ, and various modifications and changes may be made without departing from the spirit and scope of the invention. . Referring to Fig. 2, there is shown a flow chart showing the operation of the error correction test method for the motherboard of the present invention. Please also refer to FIG. 1 , the method for testing the error correction of the motherboard of the present invention is applied to a computer device having at least one memory. In the present embodiment, the computer device is configured with a memory device 2 ' The memory bit error generating device i is applied to the memory 2 as shown in FIG. 1 , but not limited thereto, wherein the memory 2 110327 10 1342566 has a plurality of chip units 21a ( 21b, etc.), and Each of the chip units 2U (21b) has an output pin 211a (211b) and a data pin 213a (213b) corresponding to the output pin 211a (211b); and the computer device is equipped with a memory error check and Error correction

Correcting Code; ECC) test software operating system; in addition, the motherboard of the computer device is configured with a memory controller (Mem〇ry

Controller Hub; MCH), complex data stream (9) ataBus), and a plurality of memory slots (not shown) for plugging the memory, since the motherboard error correction test method of the present invention can be applied to conventional In the connection mode of all the memory devices of the computer device and the memory controller, the memory system of the computer device is connected to the memory controller through the data busbars in parallel, so that the memory controller The memory unit 2, 2, and the chip unit perform data reading and writing operations, so that the description and drawings are simplified, and the features and structures of the present invention are more clearly understood, and only the direct description of the present invention is shown in the drawings. The structure of the association is omitted. The specific operation steps of the error correction test method for the motherboard of the present invention will be described in detail below with reference to Fig. 1. As shown in Fig. 2, first, step Si is performed, and the memory is inserted into one of the motherboards of the computer device to set the memory slot, and then the battery is started. Wherein, the setting rule of the memory slot of the memory is that when the computer device "only inserts a single memory into the memory plug # (only a memory configured with the memory bit error generating device) When the body 2 exists): the memory slot farthest from the memory controller is used as the setting memory slot to insert the memory for generating a reasonable memory π ] 10327 1342566 configuration Since this memory configuration is well known in the art, it will not be described herein. In addition, in the embodiment, the operation of the memory error check and the error correction test software is performed after the motherboard of the computer device is started and the computer equipment system is started. Next, step S20 is performed.

In step S20, after the computer device is started, the first value of one of the first address segments of the memory is continuously written by the motherboard of the computer device, and the second address segment of the memory is continuously written. Enter the second value. Further, the first and second numbers are respectively written to the first and second address segments of the 5H memory through the memory controller disposed in the motherboard, that is, the first The value and the second value are the distinct binary digits f 'value 0 or 1). In an embodiment, the first numerical value is a value of eight / the first numerical value is a value of 1, and is 32 bits. The memory is taken as an example, that is, two: at the same time, write 0x00000000 (32-bit element = two for 〇) to the first address segment, and write 〇xffffffff to the second address segment (32-bit yuan/, all In another embodiment, the first value may be a numerical value and the second value of the second value is a numerical value, and the 32-bit memory is taken as an example, that is, respectively, to the first address. The segment write bit data is all written to 0x00000000 to the second address segment of 5H (32-bit data is all 1 in addition, the distance between the first address segment and the second address segment is not less than 4 疋 group. Then, step S30 is performed. In step S3G, a memory bit error is generated on the memory. In other words, as shown in FIG. 1, the memory bit error is generated through the hidden body bit error. The generating device 1 is applied to the wafer 110327 of the memory 2 12 丄: > 舛 / :) armor - 2 2m, 2ib output pin 2ua, 2ub and data pin ma, disconnected Φ to achieve ' The memory bit error is generated by the transmission two bows of the memory bit error generating device 1 between the legs 211a and 211b and the data pins 213a and 213b, and the memory bit error is generated in the memory 2, and the wheel center (4) corresponds. The data between the pins of the riding foot is county=time' and the memory system that generates the memory bit error J:: The memory bit error generating device is arranged in the dish! The memory proceeds to step S40. In step S40, the motherboard outputted from the first and second address segments is read by the motherboard of the computer device. In more detail, it is configured by . The memory controller in the motherboard of the Xundian device accesses the first and second address segments of the memory 2 by using the data busbars respectively, to read the first and second address segments from the first address segment The value of the data pin output of each chip unit of the memory 2. Then proceed to step S5. In step S50, the values written and read from the first address segment and the second address segment are respectively compared, and one of the first and second address segments is written. When the input and read values are inconsistent, the memory related error message is recorded. In order to more clearly understand how the error correction test method of the motherboard to which the present invention is applied is to accurately record the information related to the error (4), the first value written to the memory is the value 〇 and the second value is the value] But not limited to this) for the example step-by-step instructions. As shown in the figure i, the error generating means 1 disconnects the output pins 2lla, 2iib of the chip units 21a, 21b of the memory 2 and the respective data pins 213a, 213b. In the case of the transmission path between the data pin 213a and the value of the 110327 13 1342566 > are all numerical values, the corresponding data pin 213a is read from the first and second address segments. The output values of 213b are respectively 〇, -〇. At this time, even if the value written and read in the first address segment is 〇; if the memory 2 is not detected from the error, it may be Comparing the written and read values in the second address segment, the memory\error is detected; if the memory bit error generating device is used, the output pins 211&, 2111) and each are disconnected. When the data pin 213&, 21 is in the transmission path, the data pins 213a, 213b are all numerical values ^ ^ then read from the first and second address segments corresponding to The output values of the data pins 213a, 213b are respectively the values}, i, at this time, even if compared to the second The value written and read in the address segment is 丨, the memory 2 error is not detected from it, and the memory is detected by inconsistent with the written and read values in the first address segment. Body 2 error. That is, the memory unit of the memory 2 is disconnected when the transmission path between the output pins 211a and 211b and each of the data pins 213a and 21 is disconnected by the device. 21a, 21b data pin 2仏, 213b output value is a numerical value or a value 〇, can be obtained through the invention = machine board error correction test method from one of the address segments to obtain the correct test summary, The method for correcting the error of the motherboard of the present invention is to first record the memory slot of one of the computer device motherboards and then start the power-off month (four) preparation, and then configure the recorder in the motherboard to simultaneously The first and second address segments of the memory are successively written into the younger-and second value. Then, the memory bit 110327 14 1342566 is generated on the memory; then, the memory controller is repeatedly transmitted through the memory controller. Reading the values output from the first and second address segments, and respectively comparing the values written and read from the first address segment and the second address segment, and in the first and the When the second address segment is written and inconsistent with the read value, Recording a memory error related message, whereby the data of the chip unit of the memory is broken when the output pin and the data path of the memory chip of the memory are disconnected by a memory error bit generating device. ^= Value or value 0, can get the memory error phase information from one of the address segments to get the correct test results, greatly improving the test accuracy. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Anyone skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is listed in the range of ys &#> ^. Should apply for a patent as the latter [Simplified illustration]

Fig. 1 is a view showing a configuration of a memory bit error generating device; and Fig. 2 is a view showing a flow chart of error correction of the motherboard of the present invention. ί 铋 【 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体 体 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 '31 memory controller

SiO~S50 step

16 110327

Claims (1)

1342566, patent application paradigm: a kind of motherboard error correction test method, which is applied to the computer equipment of the I, the body, the error correction test of the motherboard;: the legal system ^ memory the memory and the computer equipment Electrically connecting the 'h brain device, through the motherboard of the computer device, continuously writes the first value to one of the address segments of the memory, and writes the second value to the memory address of the memory block. The first value and the = value are different values; - the number of memory bit errors is generated on the memory; the value output from the first __ and the second address segment is read by the motherboard of the computer device; The value of the input and the read from the first address segment and the second address is recorded, and the memory generates a related message of the bit error in the first and second address segments. Λ 2. For the error correction test method of the motherboard in the scope of patent application i, in which 'the computer equipment is equipped with a memory error check spot error, (ΕΓΓ〇Γ C〇rreCting Code1CC) test software; industry system. 3· If you please Fan Wei 2 item motherboard error correction test method, wherein the step of starting the computer device is to start the computer to set up the motherboard and enter the computer device (4) and then run the memory error check and error correction The test procedure of the test software. For example, the error correction test method of the motherboard of claim 1 is 110327 17 4. The distance between the two address segments is not less than 4 bits, and the first address segment is the same as the first group. 6. The method of claim 4, wherein the memory has a plurality of chip units, and each of the chips has an output pin and a data pin corresponding to the output pin. For example, the error correction test method for the motherboard of the fifth application patent scope is: Hai. The memory of the 7-bit error is caused by the floating state between the output pin and the data pin of the corresponding h-wheeling pin, and ^: the memory element generates a memory bit error. X. For example, the motherboard error correction test method of claim 5, wherein the data pins of each of the wafer units are connected to the motherboard through a data bus (Data Bus). In a memory controller (MCH), the memory controller of the memory is accessed by the memory controller. 8. The error correction test method for a motherboard according to claim 7, wherein the motherboard of the computer device is provided with a setting memory slot for inserting the memory, and when the computer device is only plugged in - In the case of the memory, the memory slot farthest from the memory controller is used as the setting memory slot. ~ 9. The main board error correction test method of claim 1, wherein the first value and the second value are numerical values or numerical values. 110327 18