CN101387978A - Main board error correction testing method - Google Patents
Main board error correction testing method Download PDFInfo
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- CN101387978A CN101387978A CNA2007101540469A CN200710154046A CN101387978A CN 101387978 A CN101387978 A CN 101387978A CN A2007101540469 A CNA2007101540469 A CN A2007101540469A CN 200710154046 A CN200710154046 A CN 200710154046A CN 101387978 A CN101387978 A CN 101387978A
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Abstract
The invention relates to a motherboard error correcting and testing method, which is applied to a computer with at least one memory, which comprises steps of initially electrically connecting a memory and the computer to start up the computer, then continuously writing a first numerical value to an address field of the memory through a motherboard of the computer, simultaneously continuously writing a second numerical value to a second address field of the memory, then generating memory bit errors in the memory, subsequently, reading the numerical values output by the first and the second address fields through the motherboard of the computer while respectively comparing the numerical values written or read from the first address field and the second address field, and recording the relevant information of bit errors generated by the memory when the writing values and reading values of one of the first address field and the second address field are inconsistent, thereby resolving various drawbacks in the prior art.
Description
Technical field
The present invention relates to a kind of mainboard measuring technology, more detailed it, relate to the main board error correction testing method in a kind of computer equipment that is applied to have at least one internal memory.
Background technology
The internal memory that disposes in the computer equipment is in order to cooperate CPU (central processing unit) (Central ProcessorUnit; CPU) store formula and the data of carrying out at a high speed, so as element important in the computer system, its reliability and fault-tolerant ability are the problems of industry research always.
At present, industry is with bug check and error correcting technique (Error Correcting Code; ECC) for example be applied in the computer equipment such as server, workstation, with the internal memory performance of mainboard test configurations in this computer equipment by this computer equipment.And, need be used an internal memory bit error generating apparatus when using above-mentioned bug check and error correcting technique, making an internal memory produce the memory bits mistake by this internal memory bit error generating apparatus, thus for follow-up by this mainboard and use this bug check and error correcting technique execution internal memory performance test jobs.
See also Fig. 1, show that above-mentioned internal memory bit error generating apparatus 1 is applied to the configuration schematic diagram in the internal memory 2 of a computer equipment, wherein, this internal memory 2 has the multicore blade unit, particularly, this internal memory is two-sided stitch definition memory modules (Dual In-line MemoryModules; And this chip unit is DRAM (Dynamic Random Access Memory) (Dynamic RandomAccess Memory DIMM); DRAM), and respectively this chip unit has an output pin and to data pin that should output pin, as shown in the figure, this internal memory bit error generating apparatus 1 is applied between output pin 211a, the 211b and data pin 213a, 213b of two chip unit 21a, 21b of this internal memory 2, to produce the dual-bit memory bit-errors, but, also can be determined the EMS memory error figure place of desire generation according to the quantity that this internal memory bit error generating apparatus 1 is applied to the chip unit in this internal memory 2 not as limit.Correspondingly, present main board error correction testing method starts this computer equipment after at first this internal memory being inserted into a set memory slot in this computer equipment mainboard; Then, after this computer equipment starts, by being disposed at Memory Controller Hub (the Memory Controller Hub in this computer equipment mainboard; MCH) 31 (as shown in Figure 1) write numerical value 1 continuously to an address field of this internal memory; Subsequently, disconnect the output pin of chip unit of this internal memory and the transmission path between the data pin to produce the memory bits mistake by above-mentioned internal memory bit error generating apparatus; Then, read the numerical value of exporting from this address field by this Memory Controller Hub, and become at 0 o'clock by writing fashionable numerical value 1 in the numerical value that this address field certainly reads, by the Memory Controller Hub in this mainboard and use this bug check and error correcting technique writes down the relevant information that this internal memory is made mistakes.
In addition, as shown in Figure 1, walk abreast by a data bus (Data Bus) 30 and be connected to Memory Controller Hub 31 owing to be disposed at the data pin of respectively this chip unit of the internal memory 2 in this computer equipment, carry out the reading and writing data operation with chip unit by 31 pairs of these internal memories 2 of this Memory Controller Hub.Yet, as the chip unit 21a that disconnects this internal memory 2 by above-mentioned internal memory bit error generating apparatus 1, the output pin 211a of 21b, 211b and data pin 213a, during transmission path between the 213b, the chip unit 21a of this internal memory 2, the data pin 213a of 21b, 213b is in vacant state, at this moment promptly, the numerical value of this data pin 213a and 213b depends on by this internal memory bit error generating apparatus 1 this output pin of disconnection 211a, 211b and this data pin 213a respectively, during transmission path between the 213b, this output pin 211a, 211b exports this data pin 213a to, the numerical value of 213b, because when disconnecting, this output pin 211a, the numerical value of 211b output is mess code, cause this data pin 213a, the numerical value of 213b also is mess code, numerical value 0 may be, also numerical value 1 may be.
So, then by this main board error correction testing method in advance via this Memory Controller Hub 31 after an address field of this internal memory 2 writes numerical value 1 continuously, in this address field, read the numerical value of data pin output of each chip unit of this internal memory 2 again by this Memory Controller Hub 31, at this moment, output numerical value to the data pin of the chip unit that do not dispose this internal memory bit error generating apparatus 1 in should internal memory 2 in this address field is still numerical value 1, and in this address field to the chip unit 21a of this internal memory bit error generating apparatus 1 of configuration in should internal memory 2, the data pin 213a of 21b, the numerical value of 213b output then may for numerical value 1 also or numerical value 0, because the numerical value of this data pin 213a and 213b is mess code, when disconnecting respectively this output pin 211a by this internal memory bit error generating apparatus 1,211b and this data pin 213a respectively, during transmission path between the 213b, this data pin 213a, when the numerical value of 213b just is numerical value 0, then from this address field read to should data pin 213a, the output numerical value of 213b is 0, at this moment, this main board error correction testing method can correctly write down this internal memory relevant information of makeing mistakes; And when disconnecting, when the numerical value of this data pin 213a, 213b just is numerical value 1, then the output numerical value to should data pin 213a, 213b that reads from this address field then is 1, at this moment, owing to be 1 from the numerical value that this address field writes and reads by this main board error correction testing method, then can't detect this internal memory 2 and whether make mistakes, and then obtain wrong test result.In fact, configuration mode according to Fig. 1, produce the dual-bit memory mistake on the internal memory 2, these internal memory 2 positions that memory bits error checking result should write down this computer equipment produce relevant informations such as the dual-bit memory mistake is arranged, and be a uncertain factor by the internal memory error message that above-mentioned main board error correction testing method obtains, greatly influence this test result.
In sum, how a kind of main board error correction testing method that generates proper memory error checking result is proposed, to solve the disappearance of prior art, real for desiring most ardently the technical matters of solution at present.
Summary of the invention
In view of the shortcoming of above-mentioned prior art, fundamental purpose of the present invention is to provide a kind of main board error correction testing method, to obtain proper memory error checking result, tests accuracy rate thereby promote.
For reaching above-mentioned purpose and other purposes, the invention provides the main board error correction testing method in a kind of computer equipment that is applied to have at least one internal memory.Main board error correction testing method of the present invention comprises: this internal memory and this computer equipment are electrically connected, and start this computer equipment, mainboard by this computer equipment writes first numerical value continuously to one first address field of this internal memory, one second address field to this internal memory writes second value continuously simultaneously, and this first numerical value is different numerical value with this second value; On this internal memory, produce the memory bits mistake; Mainboard by this computer equipment reads the numerical value of exporting from this first and second address field; And compare the numerical value that writes and read from this first address field and this second address field respectively, and in this first and one of them person of this second address field write with reading numerical values when inconsistent, write down the relevant information that this internal memory produces this bit-errors.
Wherein, this computer equipment is equipped with EMS memory error inspection and error correction (Error CorrectingCode; ECC) operating system of testing software, correspondingly, in main board error correction testing method of the present invention, the step that starts this computer equipment this EMS memory error of reruning after for the mainboard that starts this computer equipment and the operating system that enters this computer equipment is checked operation steps with the error correction testing software.In addition, in an embodiment, the spacing of this first address field and this second address field is not less than 4 hytes.Moreover, this internal memory has the multicore blade unit, and respectively this chip unit has an output pin and to data pin that should output pin, and the generation of this memory bits mistake makes this output pin and when being suspended state between should the data pin of output pin, and makes this internal memory produce the memory bits mistake.The internal memory that comprises this EMS memory error generation device of configuration in respectively this internal memory of this computer equipment.This computer equipment also has Memory Controller Hub (MemoryController Hub; MCH) and a plurality of using for this memory parallel respectively be connected to this Memory Controller Hub and the data bus (Data Bus) that the chip unit of this internal memory respectively carried out the reading and writing data operation by this Memory Controller Hub.
Than prior art, main board error correction testing method of the present invention is main earlier internal memory is inserted into the computer equipment mainboard a set memory slot after, after starting this computer equipment, write first and second numerical value respectively continuously to first and second address field of this internal memory simultaneously respectively by the Memory Controller Hub that disposes in this mainboard again, then, on this internal memory, produce the memory bits mistake, subsequently, read the numerical value of exporting from this first and second address field by the Memory Controller Hub in this mainboard, and compare the numerical value that writes and read from this first address field and this second address field respectively, and in this first and this second one of them address field write with reading numerical values when inconsistent, the record internal memory relevant information of makeing mistakes, thus, no matter by an internal memory bit error generating apparatus disconnect the output pin of chip unit of this internal memory and the transmission path between the data pin the time, the numerical value of the data pin output of the chip unit of this internal memory is numerical value 1 or numerical value 0, all can obtain the internal memory relevant information of makeing mistakes, to obtain correct test result by one of them address field.
Description of drawings
Fig. 1 display memory bit error generating apparatus is applied to the configuration schematic diagram in the internal memory; And
Fig. 2 shows the operating process synoptic diagram of main board error correction testing method of the present invention.
Embodiment
Below by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the described content of this instructions.The present invention also can be implemented or be used by other different instantiations, and the every details in this instructions also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
See also Fig. 2, show the operating process synoptic diagram of main board error correction testing method of the present invention.Please consult Fig. 1 Fig. 1 simultaneously, main board error correction testing method of the present invention is applied to have in the computer equipment of at least one internal memory, in present embodiment, in this computer equipment for disposing internal memory 2,2 ', and an internal memory bit error generating apparatus 1 is applied in this internal memory 2 (as shown in Figure 1), but not as limit, wherein, this internal memory 2 has multicore blade unit 21a (21b etc.), and respectively this chip unit 21a (21b) has an output pin 211a (211b) and to data pin 213a (213b) that should output pin 211a (211b); In addition, this computer equipment is for being equipped with EMS memory error inspection and error correction (Error Correcting Code; ECC) operating system of testing software; Moreover the mainboard of this computer equipment also disposes Memory Controller Hub (Memory Controller Hub; MCH), multidata bus (DataBus), and many memory banks (not shown) for this internal memory of pegging graft, because main board error correction testing method of the present invention all can be applicable in the connected mode of all internal memories of existing computer equipment and Memory Controller Hub, promptly respectively this internal memory of this computer equipment is by parallel this Memory Controller Hub that is connected to of this data bus respectively, with by this Memory Controller Hub to this internal memory 2 respectively, 2 ' chip unit carries out the reading and writing data operation, so be simplified illustration and accompanying drawing, and make feature of the present invention and structure more clear understandable, be the structure that only demonstrates in accompanying drawing with direct correlation of the present invention, all the other partly then omit.Below will cooperate Fig. 1 to describe the concrete operations step of main board error correction testing method of the present invention in detail in the lump.
As shown in Figure 2, at first carry out step S10, this internal memory is inserted into the set memory slot of mainboard of this computer equipment after, start this computer equipment.Wherein, the setting of the memory bank of this internal memory rule is for when the single internal memory of only pegging graft in respectively this memory bank of this computer equipment (only being internal memory 2 existence of disposing this internal memory bit error generating apparatus 1), will be as this set memory slot in this Memory Controller Hub memory bank farthest, with this internal memory of pegging graft, thereby for producing rational memory configurations, because this memory configurations mode is affiliated technical field common technology, does not repeat them here.In addition, in present embodiment, after starting this computer equipment and referring to start the mainboard of this computer equipment and enter the operating system of this computer equipment, this EMS memory error of reruning is checked the operation steps with the error correction testing software.Then carry out step S20.
In step S20, after this computer equipment started, the mainboard by this computer equipment write first numerical value continuously to one first address field of this internal memory, and one second address field to this internal memory writes second value continuously simultaneously.More detailed it, write first and second numerical value by the Memory Controller Hub that is disposed in this mainboard respectively to first and second address field of this internal memory.That is, this first numerical value and this second value are different binary digit (numerical value 0 or 1), in an embodiment, this first numerical value is numerical value 0, this second value is a numerical value 1, in 32, save as example, be respectively and simultaneously write 0 x 00000000 (32 bit data are 0 entirely), write 0 x ffffffff (32 bit data are 1 entirely) to this second address field to this first address field; In another embodiment, also this first numerical value is numerical value 1, this second value is a numerical value 0, in 32, save as example, be respectively and simultaneously write 0 x ffffffff (32 bit data are 1 entirely), write 0 x 00000000 (32 bit data are 0 entirely) to this second address field to this first address field.In addition, the spacing of this first address field and this second address field is not less than 4 hytes.Then carry out step S30.
In step S30, on this internal memory, produce the memory bits mistake.Particularly, as shown in Figure 1, the generation of this memory bits mistake is applied to the chip unit 21a of this internal memory 2 by an internal memory bit error generating apparatus 1, the output pin 211a of 21b, 211b and data pin 213a, the person of being achieved between the 213b, to disconnect this output pin 211a by this internal memory bit error generating apparatus 1,211b and data pin 213a, during transmission path between the 213b, and make this internal memory 2 produce the memory bits mistake, that is, make this output pin and when being suspended state between should the data pin of output pin, and this generation memory bits mistake in save as in this computer equipment configuration this recall the internal memory 2 of position mistake generation device 1.Then carry out step S40.
In step S40, the mainboard by this computer equipment reads from this first and the numerical value of second address field output.More detailed it, by the Memory Controller Hub utilization in this mainboard that is disposed at this computer equipment respectively this data bus visit first and second address field of this internal memory 2 respectively, read the numerical value of data pin output of each chip unit of this internal memory 2 with this first and second address field certainly.Then carry out step S50.
In step S50, compare the numerical value that writes and read from this first address field and this second address field respectively, and write with reading numerical values when inconsistent the relevant information that the record internal memory is made mistakes in one of them person of this first and second address field.How realizing the relevant information that the accurate recording internal memory is made mistakes for more clearly understanding application main board error correction testing method of the present invention, will be that numerical value 0, second value are that numerical value 1 (but not as limit) is that example further specifies with first numerical value that writes to this internal memory at this.As shown in Figure 1, as the chip unit 21a that disconnects this internal memory 2 by this internal memory bit error generating apparatus 1, respectively this output pin 211a of 21b, 211b and this data pin 213a respectively, during transmission path between the 213b, this data pin 213a, when the numerical value of 213b just is numerical value 0, then from this first and second address field read to should data pin 213a, the output numerical value of 213b is respectively numerical value 0,0, at this moment, even compare to write with reading numerical values in this first address field and be 0, failing therefrom to detect this internal memory 2 makes mistakes, also can be inconsistent by writing with reading numerical values in this second address field of comparison, detect this internal memory 2 and make mistakes; If disconnect respectively this output pin 211a by this internal memory bit error generating apparatus 1,211b and this data pin 213a respectively, during transmission path between the 213b, this data pin 213a, when the numerical value of 213b just is numerical value 1, then from this first and second address field read to should data pin 213a, the output numerical value of 213b then is respectively numerical value 1,1, at this moment, even compare to write with reading numerical values in this second address field and be 1, failing therefrom to detect this internal memory 2 makes mistakes, also can be inconsistent by writing with reading numerical values in this first address field of comparison, detect this internal memory 2 and make mistakes.That is, no matter disconnect respectively this output pin 211a, 211b and respectively during the transmission path between this data pin 213a, the 213b by this internal memory bit error generating apparatus 1, the numerical value of data pin 213a, the 213b of chip unit 21a, the 21b of this internal memory 2 output be numerical value 1 also or numerical value 0, all can obtain correct test result by an address field wherein by main board error correction testing method of the present invention.
In sum, after main board error correction testing method of the present invention is inserted into a set memory slot of computer equipment mainboard with internal memory earlier, start this computer equipment, afterwards, write first and second numerical value respectively continuously to first and second address field of this internal memory simultaneously respectively by the Memory Controller Hub that disposes in this mainboard again, then, on this internal memory, produce the memory bits mistake; Subsequently, at the numerical value that reads by this Memory Controller Hub from this first and second address field output, and compare the numerical value that writes and read from this first address field and this second address field respectively, and in this first and this second one of them address field write with reading numerical values when inconsistent, the record internal memory relevant information of makeing mistakes, thus, when no matter disconnecting the output pin of chip unit of this internal memory and the transmission path between the data pin by an EMS memory error position generation device, the numerical value of the data pin output of the chip unit of this internal memory is numerical value 1 or numerical value 0, all can obtain the internal memory relevant information of makeing mistakes by one of them address field, to obtain correct test result, greatly improved the test accuracy.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention, claim is listed as described later.
The main element symbol description
1 internal memory bit error generating apparatus
2,2 ' internal memory
21a, 21b chip unit
211a, 211b output pin
213a, 213b data pin
30 data buss
31 Memory Controller Hub
S10～S50 step
Claims (9)
1. a main board error correction testing method is applied to have in the computer equipment of individual at least internal memory, and this main board error correction testing method comprises:
This internal memory and this computer equipment are electrically connected, and start this computer equipment, mainboard by this computer equipment writes first numerical value continuously to one first address field of this internal memory, one second address field to this internal memory writes second value continuously simultaneously, and this first numerical value is different numerical value with this second value;
On this internal memory, produce the memory bits mistake;
Mainboard by this computer equipment reads the numerical value of exporting from this first and second address field; And
Contrast the numerical value that writes and read from this first address field and this second address field respectively, and in this first and this second address field wherein those skilled in the art person write with reading numerical values when inconsistent, write down the relevant information that this internal memory produces this bit-errors.
2. main board error correction testing method according to claim 1, wherein, this computer equipment is equipped with EMS memory error inspection and error correction (Error Correcting Code; ECC) operating system of testing software.
3. main board error correction testing method according to claim 2, wherein, the step that starts this computer equipment this EMS memory error of reruning after for the mainboard that starts this computer equipment and the operating system that enters this computer equipment is checked operation steps with the error correction testing software.
4. main board error correction testing method according to claim 1, wherein, the spacing of this first address field and this second address field is not less than 4 hytes.
5. main board error correction testing method according to claim 1, wherein, this internal memory has the multicore blade unit, and respectively this chip unit has an output pin and to data pin that should output pin.
6. main board error correction testing method according to claim 5, wherein, the generation of this memory bits mistake makes this output pin and when being suspended state between should the data pin of output pin, and makes this internal memory produce the memory bits mistake.
7. main board error correction testing method according to claim 5, wherein, the data pin of respectively this chip unit of this internal memory is connected to a Memory Controller Hub (Memory Controller Hub on this mainboard respectively by one group of data bus (Data Bus); MCH) in, the data pin of respectively this chip unit of this internal memory is carried out data access by this Memory Controller Hub.
8. main board error correction testing method according to claim 7, wherein, the mainboard of this computer equipment is provided with a set memory slot in order to this internal memory of pegging graft, when this computer equipment is only pegged graft single internal memory, and will be from this Memory Controller Hub memory bank farthest as this set memory slot.
9. main board error correction testing method according to claim 1, wherein, this first numerical value and this second value are numerical value 0 or numerical value 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101540469A CN101387978A (en) | 2007-09-13 | 2007-09-13 | Main board error correction testing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2007101540469A CN101387978A (en) | 2007-09-13 | 2007-09-13 | Main board error correction testing method |
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| CN101387978A true CN101387978A (en) | 2009-03-18 |
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| CNA2007101540469A Pending CN101387978A (en) | 2007-09-13 | 2007-09-13 | Main board error correction testing method |
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