TWI692768B - SoC CAPABLE OF CHECKING CORRECTNESS OF MEMORY DATA - Google Patents
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本發明是關於系統單晶片,尤其是關於能夠驗算記憶體資料之正確性的系統單晶片。The present invention relates to a system-on-a-chip, and particularly to a system-on-a-chip that can verify the accuracy of memory data.
系統單晶片(System on a Chip, SoC)是將電腦或其他電子系統整合到單一晶片的積體電路(IC),常用於嵌入式系統中。現代嵌入式系統通常是基於微控制器(例如:中央處理單元包含整合記憶體及/或介面電路用來與外部裝置通訊);但在較複雜的嵌入式系統中,普通微處理器(例如:中央處理單元使用外部記憶體和外部介面電路)也很常見。System on a chip (SoC) is an integrated circuit (IC) that integrates a computer or other electronic system into a single chip, and is often used in embedded systems. Modern embedded systems are usually based on microcontrollers (for example: the central processing unit contains integrated memory and/or interface circuits to communicate with external devices); but in more complex embedded systems, ordinary microprocessors (such as: It is also common for central processing units to use external memory and external interface circuits).
現今IC的整合度愈來愈高,但大尺寸動態隨機存取記憶體(DRAM)還是不適合整合至SoC,因此,SoC仍需要外部DRAM。Nowadays, the integration of ICs is getting higher and higher, but large-scale dynamic random access memory (DRAM) is still not suitable for integration into SoC. Therefore, SoC still requires external DRAM.
儘管DRAM不適合整合至SoC,但為追求高速和低成本,將SoC和DRAM整合至同一封裝是種有效的方式。上述封裝稱為多晶片模組(Multi-Chip Module, MCM),是種已知的封裝技術,此種封裝技術能夠在一個封裝內,容納兩個或兩個以上的裸晶(die)。然而,封裝過程可能造成晶片損壞,或者晶片(特別是DRAM)本身是有缺陷的,因此,封裝後的晶片仍須接受測試。Although DRAM is not suitable for integration into SoC, in order to pursue high speed and low cost, it is an effective way to integrate SoC and DRAM into the same package. The above package is called a multi-chip module (Multi-Chip Module, MCM), which is a known packaging technology. This packaging technology can accommodate two or more die in one package. However, the packaging process may cause wafer damage, or the wafer (especially DRAM) itself is defective. Therefore, the packaged wafer must still be tested.
對DRAM的測試可使用先寫後讀的程序,藉由判斷讀取內容的正確性以確認接線和反應是否正確。由於DRAM是供中央處理單元存取,因此使用中央處理單元對DRAM執行該先寫後讀的程序是種直覺的作法。使用上述作法來測試外部DRAM(未整合至SoC)雖然可行,但由於中央處理單元是逐筆地做資料比對以判斷讀取內容的正確性,因此整體測試時間會相當長,導致測試成本上升。For the test of DRAM, you can use the program that writes first and then reads. You can confirm whether the wiring and response are correct by judging the correctness of the read content. Since the DRAM is accessed by the central processing unit, it is intuitive to use the central processing unit to execute the write-before-read program on the DRAM. Although it is feasible to use the above method to test external DRAM (not integrated into SoC), because the central processing unit compares the data one by one to determine the correctness of the read content, the overall test time will be quite long, resulting in increased test costs .
本發明之一目的在於提供一種能夠驗算記憶體資料之正確性的系統單晶片,以避免先前技術的問題。An object of the present invention is to provide a system-on-a-chip capable of verifying the accuracy of memory data to avoid the problems of the prior art.
本發明之系統單晶片的一實施例包含一處理電路、一記憶體控制器、與N個直接記憶體存取(direct memory access, DMA)電路。該處理電路用來設定該N個DMA電路,其中該N個DMA電路與該處理電路的至少其中之一用來將第一預設資料寫入一記憶體的一第一儲存區塊,該N為正整數。該記憶體控制器用來依據該N個DMA電路與該處理電路的至少其中之一的控制,存取該記憶體。該N個DMA電路的每一個包含一存取控制電路與一循環冗餘校驗(Cyclic Redundancy Check, CRC)運算電路;該N個DMA電路包含一第一DMA電路,該第一DMA電路用來透過該記憶體控制器從該第一儲存區塊讀取代表該第一預設資料的第一儲存資料,並依據該第一儲存資料產生一第一CRC碼,進而提供該第一CRC碼給該處理電路。該處理電路進一步用來判斷該第一CRC碼是否符合一第一參考CRC碼,並於該第一CRC碼符合該第一參考CRC碼時,判斷該第一儲存資料是正確的,這代表該第一儲存區塊之讀寫運作是正常的。An embodiment of the system on chip of the present invention includes a processing circuit, a memory controller, and N direct memory access (DMA) circuits. The processing circuit is used to set the N DMA circuits, wherein at least one of the N DMA circuits and the processing circuit is used to write the first preset data to a first storage block of a memory, the N It is a positive integer. The memory controller is used to access the memory according to the control of at least one of the N DMA circuits and the processing circuit. Each of the N DMA circuits includes an access control circuit and a cyclic redundancy check (Cyclic Redundancy Check, CRC) operation circuit; the N DMA circuits include a first DMA circuit, and the first DMA circuit is used to Reading first storage data representing the first preset data from the first storage block through the memory controller, and generating a first CRC code according to the first storage data, and then providing the first CRC code to The processing circuit. The processing circuit is further used to determine whether the first CRC code matches a first reference CRC code, and when the first CRC code matches the first reference CRC code, determine that the first stored data is correct, which represents the The read and write operations of the first storage block are normal.
有關本發明的特徵、實作與功效,茲配合圖式作較佳實施例詳細說明如下。Regarding the features, implementation and efficacy of the present invention, the preferred embodiments in conjunction with the drawings are described in detail below.
以下說明內容的用語是參照本技術領域的習慣用語,如本說明書對部分用語有加以說明或定義,該部分用語的解釋是以本說明書的說明或定義為準。The terms used in the following description refer to the idioms in the technical field. If there are some terms or definitions in this specification, the interpretation of these terms shall be based on the descriptions or definitions in this specification.
圖1顯示本發明之系統單晶片的一實施例。圖1之系統單晶片100能夠驗算一記憶體10之資料的正確性,以得知記憶體10是否有缺陷或被損壞;上述驗算可於一生產測試作業中進行,也可於系統單晶片100的一自動的/被動的檢測作業中進行。系統單晶片100包含一處理電路110、一記憶體控制器120、以及N個直接記憶體存取(direct memory access, DMA)電路130,其中處理電路110(例如:中央處理單元)與記憶體控制器120的每一個為已知的電路,或為自行開發的電路,該N為正整數。另外,系統單晶片100與記憶體10視實施需求可包含於一多晶片模組(Multi-Chip Module, MCM)中,然此並非本發明之實施限制。再者,記憶體10為動態隨機存取記憶體(DRAM)或其它已知/自行開發的記憶體。FIG. 1 shows an embodiment of the system single chip of the present invention. The system on
請參閱圖1。處理電路110用來設定N個DMA電路130。舉例而言,處理電路110依據記憶體10的容量設定N個DMA電路130,因此,N個DMA電路130能夠同時地分別讀取記憶體10的不同儲存空間的資料,從而快速地完成讀取記憶體10的所有儲存空間的資料,以進行後續處理。進一步而言,若上述例子中,該N為三,記憶體10的容量為四個記憶庫(memory banks),處理電路110可設定該三個DMA電路130,使得每個DMA電路130分別負責讀取該四個記憶庫的其中之一的資料,並使該三個DMA電路130分別負責讀取餘下的一個記憶庫的不同儲存區塊(blocks)(每個儲存區塊存放一或多個字組( words))的資料,如此一來,整體的讀取時間可有效地縮短。值得注意的是,上述對DMA電路130的設定為已知的技術,或為自行開發的技術;另外,記憶庫與儲存區塊的定義為本領域的通常知識。另值得注意的是,即便只有一個DMA電路130負責讀取記憶體10的所有資料,本發明也能藉由後述的循環冗餘校驗(Cyclic Redundancy Check, CRC)技術來縮短測試記憶體10的時間。Please refer to Figure 1. The
請參閱圖1。N個DMA電路130的任意個及/或處理電路110視實施需求都可用來透過記憶體控制器120將資料寫入記憶體10。舉例來說,N個DMA電路130的至少其中之一及/或處理電路110用來透過記憶體控制器120將相同的預設資料寫入記憶體10的每個儲存區塊。另舉例來說,N個DMA電路130的至少其中之一及/或處理電路110用來透過記憶體控制器120將不同的預設資料(例如:第一預設資料與第二預設資料)分別寫入記憶體10的不同的儲存區塊(例如:第一儲存區塊與第二儲存區塊)。上述不同的儲存區塊依實施需求可屬於記憶體10的同一記憶庫或分屬於記憶體10的不同記憶庫。更多範例可由上述說明推衍而得。Please refer to Figure 1. Any one of the
請參閱圖1。記憶體控制器120用來依據N個DMA電路130與處理電路110的至少其中之一的控制,存取記憶體10;上述控制包含邏輯位址至實體位址的轉換等已知的控制,其細節在此省略。N個DMA電路130的每一個包含一存取控制電路210(例如:一讀取控制電路或一讀寫控制電路)與一CRC運算電路220如圖2所示;存取控制電路210與CRC運算電路220的每一個單獨而言為已知的電路,或為自行開發的電路。藉由處理電路110的設定,N個DMA電路130中至少一DMA電路130的存取控制電路210可用來讀取已寫入記憶體10中代表前述預設資料的儲存資料,該至少一DMA電路130的CRC運算電路220可用來依據該儲存資料執行一CRC運算,以產生至少一CRC碼,該至少一DMA電路130再提供該至少一CRC碼給處理電路110,處理電路110會比對該至少一CRC碼與至少一參考CRC碼,以判斷兩者是否相符,從而處理電路110可依據上述比對的結果來判斷該儲存資料是否正確,並得知記憶體10是否有問題。上述CRC運算為已知的CRC運算,或為自行開發的CRC運算的變體;由於CRC碼的大小通常僅為數個位元組(bytes),因此處理電路110可以快速地完成CRC碼的比對,從而縮短測試記憶體10的時間。Please refer to Figure 1. The
基於前述,複數個實作範例分述如下:
(一)第一實作範例:N個DMA電路130與處理電路110的至少其中之一(例如:處理電路110)將第一預設資料寫入記憶體10的一第一儲存區塊,且N個DMA電路130包含一第一DMA電路,該第一DMA電路透過記憶體控制器120從該第一儲存區塊讀取代表該第一預設資料的第一儲存資料,並依據該第一儲存資料產生一第一CRC碼,進而提供該第一CRC碼給處理電路110,接著,處理電路110判斷該第一CRC碼是否符合一第一參考CRC碼,並於該第一CRC碼符合該第一參考CRC碼時,判斷該第一儲存資料是正確的,這代表對該第一儲存區塊的寫讀操作是正常的。
(二)第二實作範例:基於該第一實作範例,N個DMA電路130與處理電路110的至少其中之一(例如:處理電路110)另將該第一預設資料寫入記憶體10的一第二儲存區塊,該第一DMA電路透過記憶體控制器120從該第二儲存區塊讀取代表該第一預設資料的第二儲存資料,並依據該第二儲存資料產生一第二CRC碼,進而提供該第二CRC碼給處理電路110,接著,處理電路110判斷該第二CRC碼是否符合該第一參考CRC碼,並於該第二CRC碼符合該第一參考CRC碼時,判斷該第二儲存資料是正確的,這代表對該第二儲存區塊的寫讀操作是正常的。
(三)第三實作範例:基於該第一實作範例,N個DMA電路130與處理電路110的至少其中之一(例如:處理電路110)另將第二預設資料寫入記憶體10的一第二儲存區塊,該第二預設資料不同於該第一預設資料,該第一DMA電路透過記憶體控制器120從該第二儲存區塊讀取代表該第二預設資料的第二儲存資料,並依據該第二儲存資料產生一第二CRC碼,進而提供該第二CRC碼給處理電路110,接著,處理電路110判斷該第二CRC碼是否符合一第二參考CRC碼,並於該第二CRC碼符合該第二參考CRC碼時,判斷該第二儲存資料是正確的,這代表對該第二儲存區塊的寫讀操作是正常的。
(四)第四實作範例中:基於該第一實作範例,N個DMA電路130與處理電路110的至少其中之一(例如:處理電路110)另將該第一預設資料寫入記憶體10的一第二儲存區塊, N個DMA電路130包含一第二DMA電路,該第二DMA電路透過記憶體控制器120從該第二儲存區塊讀取代表該第一預設資料的第二儲存資料,並依據該第二儲存資料產生一第二CRC碼,進而提供該第二CRC碼給處理電路110,接著,處理電路110判斷該第二CRC碼是否符合一第二參考CRC碼,並於該第二CRC碼符合該第二參考CRC碼時,判斷該第二儲存資料是正確的,這代表對該第二儲存區塊的寫讀操作是正常的。
(五)第五實作範例:基於該第一實作範例,N個DMA電路130與處理電路110的至少其中之一(例如:處理電路110)另將第二預設資料寫入記憶體10的一第二儲存區塊,該第二預設資料不同於該第一預設資料,N個DMA電路130包含一第二DMA電路,該第二DMA電路透過記憶體控制器120從該第二儲存區塊讀取代表該第二預設資料的第二儲存資料,並依據該第二儲存資料產生一第二CRC碼,進而提供該第二CRC碼給處理電路110,接著,處理電路110判斷該第二CRC碼是否符合一第二參考CRC碼,並於該第二CRC碼符合該第二參考CRC碼時,判斷該第二儲存資料是正確的,這代表對該第二儲存區塊的寫讀操作是正常的。
更多的實作範例可依上述範例推衍而得。
Based on the foregoing, the multiple implementation examples are described as follows:
(1) First implementation example: at least one of the
值得注意的是,前述第四與第五實作範例中,該第一DMA電路與該第二DMA電路可於同一時段(period)分別地讀取該第一儲存區塊的儲存資料與該第二儲存區塊的儲存資料,以實現記憶體資料讀取的多工作業,其中該第一儲存區塊與該第二儲存區塊視實施需求可屬於記憶體10的同一記憶庫或分屬於記憶體10的不同記憶庫,且該第一儲存區塊與該第二儲存區塊的位址不同;舉例來說,該第一/第二儲存區塊屬於一第一/第二記憶庫,該第一/第二記憶庫的每個儲存區塊均被寫入該第一/第二預設資料以供測試。另值得注意的是,前述各個實作範例中,由於該第一/第二預設資料為已知資料,因此該已知資料的CRC碼可被事先求出並儲存於系統單晶片100的一儲存電路(例如:暫存器(register))中,以作為該第一/第二參考CRC碼,簡言之,該第一參考CRC碼及/或該第二參考CRC碼可為系統單晶片100中的預存資料;若該第一及/或第二預設資料的CRC碼未被事先儲存,處理電路110可將該第一CRC碼作為該第一參考CRC碼(用來與代表該第一預設資料的每筆儲存資料的CRC碼相比對)及/或將該第二CRC碼作為該第二參考CRC碼(用來與代表該第二預設資料的每筆儲存資料的CRC碼相比對)。It is worth noting that in the foregoing fourth and fifth implementation examples, the first DMA circuit and the second DMA circuit can separately read the stored data of the first storage block and the first DMA circuit at the same period (period) Two storage blocks store data to achieve multi-tasking of memory data reading, wherein the first storage block and the second storage block may belong to the same memory bank of the
請注意,在實施為可能的前提下,本技術領域具有通常知識者可選擇性地實施前述任一實施例/實作範例中部分或全部技術特徵,或選擇性地實施前述複數個實施例/實作範例中部分或全部技術特徵的組合,藉此增加本發明實施時的彈性。Please note that under the premise that the implementation is possible, those with ordinary knowledge in the art can selectively implement some or all of the technical features in any of the foregoing embodiments/implementation examples, or selectively implement the foregoing multiple embodiments/ Implement a combination of some or all of the technical features in the example, thereby increasing the flexibility in implementing the present invention.
綜上所述,本發明能夠驗算一記憶體之資料的正確性,以得知該記憶體是否有缺陷或被損壞;另外,本發明以一或多個DMA電路讀取該記憶體之儲存資料以產生CRC碼給處理電路進行比對,藉此有效地節省測試該記憶體的時間,從而節省測試成本。In summary, the present invention can verify the accuracy of data in a memory to know whether the memory is defective or damaged; in addition, the present invention uses one or more DMA circuits to read the stored data of the memory The processing circuit is compared with the generated CRC code, thereby effectively saving the time for testing the memory, thereby saving the testing cost.
雖然本發明之實施例如上所述,然而該些實施例並非用來限定本發明,本技術領域具有通常知識者可依據本發明之明示或隱含之內容對本發明之技術特徵施以變化,凡此種種變化均可能屬於本發明所尋求之專利保護範疇,換言之,本發明之專利保護範圍須視本說明書之申請專利範圍所界定者為準。Although the embodiments of the present invention are as described above, these embodiments are not intended to limit the present invention. Those with ordinary knowledge in the technical field may change the technical features of the present invention according to the express or implied content of the present invention. Such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope defined by the patent application in this specification.
10:記憶體 100:系統單晶片 110:處理電路 120:記憶體控制器 130:DMA(直接記憶體存取)電路 210:存取控制電路 220:CRC(循環冗餘校驗)運算電路10: Memory 100: system on chip 110: Processing circuit 120: memory controller 130: DMA (direct memory access) circuit 210: Access control circuit 220: CRC (Cyclic Redundancy Check) operation circuit
[圖1]顯示本發明之系統單晶片的一實施例;以及 [圖2]顯示圖1之每個DMA電路的一實施例。 [Figure 1] An embodiment of the system single chip of the present invention is shown; and [FIG. 2] An embodiment of each DMA circuit of FIG. 1 is shown.
10:記憶體 10: Memory
100:系統單晶片 100: system on chip
110:處理電路 110: Processing circuit
120:記憶體控制器 120: memory controller
130:DMA(直接記憶體存取)電路 130: DMA (direct memory access) circuit
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US8250251B2 (en) * | 1999-05-21 | 2012-08-21 | Broadcom Corporation | Flexible DMA descriptor support |
US8326938B1 (en) * | 2006-12-01 | 2012-12-04 | Marvell International Ltd. | Packet buffer apparatus and method |
US8718087B1 (en) * | 2006-10-24 | 2014-05-06 | Marvell International Ltd. | Processing architecture for passive optical network |
US9178713B1 (en) * | 2006-11-28 | 2015-11-03 | Marvell International Ltd. | Optical line termination in a passive optical network |
US10019389B2 (en) * | 2013-08-29 | 2018-07-10 | Quixant Plc | Memory controller and memory access method |
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US8250251B2 (en) * | 1999-05-21 | 2012-08-21 | Broadcom Corporation | Flexible DMA descriptor support |
US8718087B1 (en) * | 2006-10-24 | 2014-05-06 | Marvell International Ltd. | Processing architecture for passive optical network |
US9178713B1 (en) * | 2006-11-28 | 2015-11-03 | Marvell International Ltd. | Optical line termination in a passive optical network |
US8326938B1 (en) * | 2006-12-01 | 2012-12-04 | Marvell International Ltd. | Packet buffer apparatus and method |
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