TWI692768B - SoC CAPABLE OF CHECKING CORRECTNESS OF MEMORY DATA - Google Patents

Abstract

Disclosed is a system on a chip (SoC) capable of checking the correctness of memory data. The SoC includes a processing circuit, a memory controller, and N direct memory access (DMA) circuit(s). The processing circuit configures the N DMA circuit(s), and at least one of the processing circuit and the N DMA circuit(s) writes first predetermined data into a first storage block of a memory. The memory controller accesses the memory according to the control of at least one of the processing circuit and the N DMA circuit(s). Each of the N DMA circuit(s) includes a read/write control circuit and a Cyclic Redundancy Check (CRC) calculating circuit. The N DMA circuit(s) include(s) a first DMA circuit configured to read first storage data representing the first predetermined data from the first storage block through the memory controller, generate a first CRC code according to the first storage data, and provide the first CRC code for the processing circuit. Accordingly, the processing circuit determines whether the first CRC code is equivalent to a first reference CRC code and thereby determines whether the first storage data are correct.

Description

System single chip capable of verifying correctness of memory data

The present invention relates to a system-on-a-chip, and particularly to a system-on-a-chip that can verify the accuracy of memory data.

System on a chip (SoC) is an integrated circuit (IC) that integrates a computer or other electronic system into a single chip, and is often used in embedded systems. Modern embedded systems are usually based on microcontrollers (for example: the central processing unit contains integrated memory and/or interface circuits to communicate with external devices); but in more complex embedded systems, ordinary microprocessors (such as: It is also common for central processing units to use external memory and external interface circuits).

Nowadays, the integration of ICs is getting higher and higher, but large-scale dynamic random access memory (DRAM) is still not suitable for integration into SoC. Therefore, SoC still requires external DRAM.

Although DRAM is not suitable for integration into SoC, in order to pursue high speed and low cost, it is an effective way to integrate SoC and DRAM into the same package. The above package is called a multi-chip module (Multi-Chip Module, MCM), which is a known packaging technology. This packaging technology can accommodate two or more die in one package. However, the packaging process may cause wafer damage, or the wafer (especially DRAM) itself is defective. Therefore, the packaged wafer must still be tested.

For the test of DRAM, you can use the program that writes first and then reads. You can confirm whether the wiring and response are correct by judging the correctness of the read content. Since the DRAM is accessed by the central processing unit, it is intuitive to use the central processing unit to execute the write-before-read program on the DRAM. Although it is feasible to use the above method to test external DRAM (not integrated into SoC), because the central processing unit compares the data one by one to determine the correctness of the read content, the overall test time will be quite long, resulting in increased test costs .

An object of the present invention is to provide a system-on-a-chip capable of verifying the accuracy of memory data to avoid the problems of the prior art.

An embodiment of the system on chip of the present invention includes a processing circuit, a memory controller, and N direct memory access (DMA) circuits. The processing circuit is used to set the N DMA circuits, wherein at least one of the N DMA circuits and the processing circuit is used to write the first preset data to a first storage block of a memory, the N It is a positive integer. The memory controller is used to access the memory according to the control of at least one of the N DMA circuits and the processing circuit. Each of the N DMA circuits includes an access control circuit and a cyclic redundancy check (Cyclic Redundancy Check, CRC) operation circuit; the N DMA circuits include a first DMA circuit, and the first DMA circuit is used to Reading first storage data representing the first preset data from the first storage block through the memory controller, and generating a first CRC code according to the first storage data, and then providing the first CRC code to The processing circuit. The processing circuit is further used to determine whether the first CRC code matches a first reference CRC code, and when the first CRC code matches the first reference CRC code, determine that the first stored data is correct, which represents the The read and write operations of the first storage block are normal.

Regarding the features, implementation and efficacy of the present invention, the preferred embodiments in conjunction with the drawings are described in detail below.

The terms used in the following description refer to the idioms in the technical field. If there are some terms or definitions in this specification, the interpretation of these terms shall be based on the descriptions or definitions in this specification.

FIG. 1 shows an embodiment of the system single chip of the present invention. The system on chip 100 of FIG. 1 can verify the correctness of the data of a memory 10 to know whether the memory 10 is defective or damaged; the above verification can be performed in a production test operation or on the system on chip 100 Of an automatic/passive inspection operation. The system on chip 100 includes a processing circuit 110, a memory controller 120, and N direct memory access (DMA) circuits 130, in which the processing circuit 110 (eg, central processing unit) and memory control Each of the devices 120 is a known circuit or a self-developed circuit, and N is a positive integer. In addition, the system single chip 100 and the memory 10 may be included in a multi-chip module (Multi-Chip Module, MCM) depending on implementation requirements, but this is not an implementation limitation of the present invention. Furthermore, the memory 10 is a dynamic random access memory (DRAM) or other known/self-developed memory.

Please refer to Figure 1. The processing circuit 110 is used to set N DMA circuits 130. For example, the processing circuit 110 sets N DMA circuits 130 according to the capacity of the memory 10, therefore, the N DMA circuits 130 can simultaneously read data in different storage spaces of the memory 10, thereby quickly completing reading memory Data of all storage spaces of the body 10 for subsequent processing. Further, if in the above example, the N is three and the capacity of the memory 10 is four memory banks, the processing circuit 110 may set the three DMA circuits 130 so that each DMA circuit 130 is responsible for reading Take the data from one of the four memory banks, and make the three DMA circuits 130 responsible for reading the different memory blocks of the remaining memory bank (each memory block stores one or more words) Group (words) data, so that the overall reading time can be effectively shortened. It is worth noting that the above setting of the DMA circuit 130 is a known technology or a self-developed technology; in addition, the definitions of memory banks and storage blocks are common knowledge in the field. It is also worth noting that even if there is only one DMA circuit 130 responsible for reading all the data of the memory 10, the present invention can also shorten the test memory 10 by the Cyclic Redundancy Check (CRC) technology described later time.

Please refer to Figure 1. Any one of the N DMA circuits 130 and/or the processing circuit 110 can be used to write data into the memory 10 through the memory controller 120 according to implementation requirements. For example, at least one of the N DMA circuits 130 and/or the processing circuit 110 is used to write the same preset data to each storage block of the memory 10 through the memory controller 120. For another example, at least one of the N DMA circuits 130 and/or the processing circuit 110 is used to store different preset data (eg, first preset data and second preset data) through the memory controller 120 Write to different storage blocks of the memory 10 (for example, the first storage block and the second storage block). The above-mentioned different storage blocks may belong to the same memory bank of the memory 10 or belong to different memory banks of the memory 10 according to implementation requirements. More examples can be derived from the above description.

Please refer to Figure 1. The memory controller 120 is used to access the memory 10 according to the control of at least one of the N DMA circuits 130 and the processing circuit 110; the above control includes known controls such as conversion of logical addresses to physical addresses, etc. Details are omitted here. Each of the N DMA circuits 130 includes an access control circuit 210 (for example: a read control circuit or a read-write control circuit) and a CRC operation circuit 220 as shown in FIG. 2; the access control circuit 210 and the CRC operation Each of the circuits 220 is a known circuit individually or a self-developed circuit. By the setting of the processing circuit 110, the access control circuit 210 of at least one of the DMA circuits 130 in the N DMA circuits 130 can be used to read stored data representing the preset data written in the memory 10, the at least one DMA circuit The CRC operation circuit 220 of 130 can be used to perform a CRC operation according to the stored data to generate at least one CRC code. The at least one DMA circuit 130 then provides the at least one CRC code to the processing circuit 110. The processing circuit 110 compares A CRC code and at least one reference CRC code are used to determine whether they match, so that the processing circuit 110 can determine whether the stored data is correct according to the result of the above comparison, and know whether the memory 10 has a problem. The above CRC operation is a known CRC operation or a variant of the CRC operation developed by ourselves; since the size of the CRC code is usually only a few bytes (bytes), the processing circuit 110 can quickly complete the comparison of the CRC codes , Thereby shortening the time for testing the memory 10.

Based on the foregoing, the multiple implementation examples are described as follows: (1) First implementation example: at least one of the N DMA circuits 130 and the processing circuit 110 (for example: the processing circuit 110) writes the first preset data to a first storage block of the memory 10, and The N DMA circuits 130 include a first DMA circuit that reads first stored data representing the first preset data from the first storage block through the memory controller 120 and based on the first A first CRC code is generated from the stored data, and then the first CRC code is provided to the processing circuit 110. Then, the processing circuit 110 determines whether the first CRC code matches a first reference CRC code, and the first CRC code matches the When first referring to the CRC code, it is judged that the first stored data is correct, which means that the write and read operations to the first storage block are normal. (2) Second implementation example: Based on the first implementation example, at least one of the N DMA circuits 130 and the processing circuit 110 (for example: the processing circuit 110) also writes the first preset data into the memory A second storage block of 10, the first DMA circuit reads the second stored data representing the first preset data from the second storage block through the memory controller 120, and generates according to the second stored data A second CRC code, and then provide the second CRC code to the processing circuit 110, and then, the processing circuit 110 determines whether the second CRC code matches the first reference CRC code, and the second CRC code matches the first reference When the CRC code is judged, the second storage data is judged to be correct, which means that the write and read operations to the second storage block are normal. (3) Third implementation example: Based on the first implementation example, at least one of the N DMA circuits 130 and the processing circuit 110 (eg, the processing circuit 110) also writes the second preset data to the memory 10 A second storage block, the second preset data is different from the first preset data, the first DMA circuit reads from the second storage block through the memory controller 120 to represent the second preset data The second stored data, and generates a second CRC code according to the second stored data, and then provides the second CRC code to the processing circuit 110, and then, the processing circuit 110 determines whether the second CRC code matches a second reference CRC Code, and when the second CRC code matches the second reference CRC code, it is determined that the second stored data is correct, which means that the write and read operations to the second storage block are normal. (4) In the fourth implementation example: based on the first implementation example, at least one of the N DMA circuits 130 and the processing circuit 110 (for example: the processing circuit 110) also writes the first preset data into memory A second storage block of the body 10, the N DMA circuits 130 include a second DMA circuit, the second DMA circuit reads the second storage block representing the first preset data from the second storage block through the memory controller 120 Second stored data, and generating a second CRC code according to the second stored data, and then providing the second CRC code to the processing circuit 110, and then, the processing circuit 110 determines whether the second CRC code matches a second reference CRC code , And when the second CRC code matches the second reference CRC code, it is determined that the second stored data is correct, which means that the write and read operations to the second storage block are normal. (5) Fifth implementation example: Based on the first implementation example, at least one of the N DMA circuits 130 and the processing circuit 110 (eg, the processing circuit 110) also writes the second preset data into the memory 10 A second storage block of the second preset data is different from the first preset data, N DMA circuits 130 include a second DMA circuit, the second DMA circuit through the memory controller 120 from the second The storage block reads the second stored data representing the second preset data, and generates a second CRC code according to the second stored data, and then provides the second CRC code to the processing circuit 110, and then, the processing circuit 110 determines Whether the second CRC code matches a second reference CRC code, and when the second CRC code matches the second reference CRC code, it is determined that the second stored data is correct, which represents the Write and read operations are normal. More implementation examples can be derived from the above examples.

It is worth noting that in the foregoing fourth and fifth implementation examples, the first DMA circuit and the second DMA circuit can separately read the stored data of the first storage block and the first DMA circuit at the same period (period) Two storage blocks store data to achieve multi-tasking of memory data reading, wherein the first storage block and the second storage block may belong to the same memory bank of the memory 10 or be part of the memory depending on the implementation requirements Different memory banks of the body 10, and the addresses of the first storage block and the second storage block are different; for example, the first/second storage block belongs to a first/second memory bank, the Each storage block of the first/second memory bank is written with the first/second preset data for testing. It is also worth noting that in each of the aforementioned implementation examples, since the first/second preset data is known data, the CRC code of the known data can be obtained in advance and stored in a system chip 100 The storage circuit (for example: register) is used as the first/second reference CRC code. In short, the first reference CRC code and/or the second reference CRC code may be a system on chip 100 pre-stored data; if the CRC code of the first and/or second preset data is not stored in advance, the processing circuit 110 may use the first CRC code as the first reference CRC code (used to represent the first Compare the CRC code of each stored data of a preset data and/or use the second CRC code as the second reference CRC code (used to compare with the CRC of each stored data representing the second preset data Code comparison).

Please note that under the premise that the implementation is possible, those with ordinary knowledge in the art can selectively implement some or all of the technical features in any of the foregoing embodiments/implementation examples, or selectively implement the foregoing multiple embodiments/ Implement a combination of some or all of the technical features in the example, thereby increasing the flexibility in implementing the present invention.

In summary, the present invention can verify the accuracy of data in a memory to know whether the memory is defective or damaged; in addition, the present invention uses one or more DMA circuits to read the stored data of the memory The processing circuit is compared with the generated CRC code, thereby effectively saving the time for testing the memory, thereby saving the testing cost.

Although the embodiments of the present invention are as described above, these embodiments are not intended to limit the present invention. Those with ordinary knowledge in the technical field may change the technical features of the present invention according to the express or implied content of the present invention. Such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope defined by the patent application in this specification.

10: Memory 100: system on chip 110: Processing circuit 120: memory controller 130: DMA (direct memory access) circuit 210: Access control circuit 220: CRC (Cyclic Redundancy Check) operation circuit

[Figure 1] An embodiment of the system single chip of the present invention is shown; and [FIG. 2] An embodiment of each DMA circuit of FIG. 1 is shown.

10: Memory

100: system on chip

110: Processing circuit

120: memory controller

130: DMA (direct memory access) circuit

Claims (10)

A system-on-a-chip that can verify the accuracy of memory data, including: A processing circuit for setting N direct memory access (DMA) circuits, wherein at least one of the N DMA circuits and the processing circuit is used to write the first preset data into a memory A first storage block of the volume, where N is a positive integer; A memory controller for accessing the memory according to the control of at least one of the N DMA circuits and the processing circuit; and The N DMA circuits, each of the N DMA circuits includes an access control circuit and a cyclic redundancy check (Cyclic Redundancy Check, CRC) operation circuit, the N DMA circuits include a first DMA circuit, the The first DMA circuit is used to read the first stored data representing the first preset data from the first storage block through the memory controller, and generate a first CRC code according to the first stored data, and then provide The first CRC code is given to the processing circuit, The processing circuit is further used to determine whether the first CRC code matches a first reference CRC code, and determine that the first stored data is correct when the first CRC code matches the first reference CRC code. The system on chip as described in item 1 of the patent application scope, wherein at least one of the N DMA circuits and the processing circuit is used to write the first preset data to a second storage block of the memory , The first DMA circuit is used to read the second stored data representing the first preset data from the second storage block through the memory controller, and generate a second CRC code according to the second stored data, Furthermore, the second CRC code is provided to the processing circuit, and the processing circuit is further used to determine whether the second CRC code matches the first reference CRC code, and when the second CRC code matches the first reference CRC code, determine The second stored data is correct. The system on chip as described in item 1 of the patent application scope, wherein at least one of the N DMA circuits and the processing circuit is used to write the first preset data to a second storage block of the memory The N DMA circuits further include a second DMA circuit for reading second stored data representing the first preset data from the second storage block through the memory controller, and Generate a second CRC code according to the second stored data, and then provide the second CRC code to the processing circuit, the processing circuit is further used to determine whether the second CRC code matches the first reference CRC code, and the When the two CRC codes match the first reference CRC code, it is judged that the second stored data is correct. The system on chip as described in item 3 of the patent application scope, wherein the first DMA circuit and the second DMA circuit respectively read the first stored data and the second stored data at the same time. The system single chip as described in item 2, 3 or 4 of the patent application scope, wherein the first storage block and the second storage block belong to the same memory bank (memory bank) of the memory or separately Different memory banks belonging to the memory; the first reference CRC code is pre-stored data in the system single chip, or the processing circuit uses the first CRC code as the first reference CRC code. The system on chip as described in item 1 of the patent application scope, wherein at least one of the N DMA circuits and the processing circuit is used to write the second preset data to a second storage block of the memory, The second preset data is different from the first preset data, the first DMA circuit is used to read the second stored data representing the second preset data from the second storage block through the memory controller, And generate a second CRC code according to the second stored data, and then provide the second CRC code to the processing circuit, the processing circuit is further used to determine whether the second CRC code conforms to a second reference CRC code, and When the second CRC code matches the second reference CRC code, it is determined that the second stored data is correct. The system on chip as described in item 1 of the patent application scope, wherein at least one of the N DMA circuits and the processing circuit is used to write the second preset data to a second storage block of the memory, The second preset data is different from the first preset data, the N DMA circuits further include a second DMA circuit, the second DMA circuit is used to read from the second storage block through the memory controller Representing the second stored data of the second preset data, and generating a second CRC code according to the second stored data, and then providing the second CRC code to the processing circuit, the processing circuit is further used to determine the second CRC Whether the code matches a second reference CRC code, and when the second CRC code matches the second reference CRC code, it is determined that the second stored data is correct. The system on chip as described in item 7 of the patent application scope, wherein the first DMA circuit and the second DMA circuit respectively read the first stored data and the second stored data at the same time. The system single chip as described in item 6, item 7, or item 8 of the patent application scope, wherein the first storage block and the second storage block belong to the same memory bank of the memory or belong to the memory respectively Different memory banks; the first reference CRC code and/or the second reference CRC code are pre-stored data in the system single chip, or the processing circuit uses the first CRC code as the first reference CRC code and/or Or use the second CRC code as the second reference CRC code. The system on chip as described in item 1 of the patent application scope, wherein the system on chip and the memory are contained in a multi-chip module (Multi-Chip Module, MCM).

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