M324824 八、新型說明：. 【新型所屬之技術領域】 a月參閱第四圖’本創作係有關於一種數位彩色影 像監控裝置，尤指一種以FPGA為基底，並採用具管線 功能的快速SRAM為視訊記憶體，利用FPGA完全以硬體 電路的快速運作，有效地增加影像處理速度的數位彩 色影像監控裝置。 【先前技術】 請參考第五圖，近年來，電腦產業迅速發展，在 數位彩色影像監控裝置方面，傳統均採用根據特定應 用而制定規格積體電路（Appi ication Specif ic Integrated Circuit，ASIC)來處理影像資料，以及 利用一般的同步動態隨機存取記憶體（Synchronous Dynamic Random Access Memory，SDRAM)作為視訊記 憶體。 【新型内容】 習知數位彩色影像監控裝置，其係採用ASIC晶 片，但功能固定，無法擴充，速度較慢，一般採用為 視訊記憶體的SDRAM速度也較慢，導致所獲致影像的 晝質不佳。 本創作提供一種以可程式邏輯陣列（F i e 1 d Programmable Gate Array，FPGA)為基底的偶數分 5 M324824 割數位彩色影像監控裝置，採用FPGA晶片，容量大且 提供了處理時脈的時脈延遲鎖定迴路元件（Clock Delay Locked Loop，CLKDLL)，獲得精準的時脈，採 用同步隨機存取記憶體（Synchronous Random Access Memory，SRAM)高速晶片為視訊記憶體（Video RAM)，具管線（Pipeiine)功能，減少匯流排延遲，提 升存取速度，該監控裝置包括有多數個類比轉數位轉 換器、一可程式邏輯陣列晶片、一同步隨機存取記憶 體晶片、一數位轉類比晶片、一視頻圖像陳列顯示 器，該FPGA的内部結構，包括有多數個前置處理器、 一排程與資料收集器、前後各一個先入先出緩衝器 (First In First Out，FIFO) 、一 SRAM 控制器、一 SRAM控制器與FIFO之間的介面控制器、一後端處理器 與一視頻圖像陳列（Video Graphics Array，VGA) 時脈產生器，該前置處理器中包括有一高速時脈檢出 有效資料模組、一篩選並檢出視訊影像資料模組、— 自每一條水平掃描線的影像資料中檢出所需要的像素M324824 VIII. New description:. [New technical field] A month refers to the fourth picture. 'This creation department is about a digital color image monitoring device, especially an FPGA-based and fast SRAM with pipeline function. Video memory, digital color image monitoring device that effectively increases the image processing speed by using the FPGA to operate quickly with hardware circuits. [Prior Art] Please refer to the fifth figure. In recent years, the computer industry has developed rapidly. In the field of digital color image monitoring devices, traditionally, the Appi ication Specific Integrated Circuit (ASIC) is used to process according to specific applications. Image data, and the use of a general synchronous dynamic random access memory (SDRAM) as video memory. [New content] The conventional digital color image monitoring device adopts ASIC chip, but its function is fixed, it cannot be expanded, and the speed is slow. Generally, the SDRAM speed of the video memory is also slow, resulting in the image quality of the obtained image. good. This creation provides an even-numbered 5 M324824 cut-number digital image monitoring device based on a programmable logic array (FPGA). The FPGA chip has a large capacity and provides clock delay for processing the clock. The Clock Delay Locked Loop (CLKDLL) is used to obtain accurate clocks. The Synchronous Random Access Memory (SRAM) high-speed chip is used as video memory and has Pipeiine function. To reduce bus delay and improve access speed, the monitoring device includes a plurality of analog-to-digital converters, a programmable logic array chip, a synchronous random access memory chip, a digital to analog wafer, and a video image. Display display, the internal structure of the FPGA, including a plurality of pre-processors, a schedule and data collector, a first in first out buffer (FIFO), an SRAM controller, an SRAM Interface controller between controller and FIFO, a backend processor and a video image display (Video Graphics Array VGA) clock generator, the pre-processor includes a high-speed clock detection valid data module, a screening and detecting video image data module, - a detection device in the image data of each horizontal scanning line Required pixel
(pixel)模組、一 YCbCr444 轉換成 RGB (3 位元組 RGB 資料）模組、一 RGB(3位元組RGB資料）轉成rgb(4 位元組RGB資料）模組’該高速時脈檢出有效資料模 組中採取一創新的作法，可將工作時脈速度提升，該 多數個前置處理器與排程及資料搜集器之間，用一資 料緩衝器與一資料有效旗標，建立一資料傳遞的協 M324824 疋’有效取得多個通道的資料，該sra_f⑽之間的 介面控制器中’處理#料讀寫的順序，採取—有優先 項序的5買寫策略’在SRAM與前後端的FIFO之間進行讀 寫動作。 、 本創作所提供監控裝置，制FpGU片^全以硬 體電路的快速運作，和具f線魏㈣速娜晶片為 視訊記憶體，將速度提升，設計-速度較快，影像畫 貝車父佳的數位彩色影像監控裝置。 【實施方式】 ❼閱第圖' 第二圖、第三圖、第四圖及第六 圖’ 士創作係提供一種以舰晶片為基底，並採用高 速具b線功此的SRAM晶片為視訊記憶體的偶數分割， 數位衫色影像監控裝置’該監控裝置包括有多數個類 比轉數位轉換器10、一可程式邏輯陣列晶“〇、一同 步隨機存取記憶體晶片14、一數位轉類比晶片u、一 :頻圖像陳列顯示㈣’該可程式邏輯陣列晶片懈 t的時脈延遲鎖定迴路元件，安置在多數個前置處理 盗11中、同步隨機存取記憶體控制器15中、同步隨機 存取記憶體控制H與先人先出緩衝器之間的介面 器二該可程式邏輯陣列晶片4〇包括有多數個前置 ::心、-排程與資料收集器12、一前端先入先出 緩衝器13、一同步隨機存取記憶體控制器15、一同步 隨機存取記憶體控制器與先入先出緩衝器之間的介面 M324824 、一後端先入先出緩衝器17、-後端處理器 内-視頻圖像陳列時序產生器19，該前置處理㈣ 包括有—高速時脈檢出有效資料模組 師邊並檢出視訊影像資料模組21、—自每一條 水平掃描線的影像㈣檢出有效㈣模組22、一將” YCbCr444#^^ RGBO^^^ RGB ## )#^23_ 1RGB(3/立元、组職資料）轉換成_4位元組· ，斗）模、、且24 ’ A回速時脈檢出有效資料模組別中， 用士一高速時脈60同時檢測類比轉數位轉換器1〇輸出的 日守脈61 ’以及與其同步輸出的資料62，若發現此一同 /時脈的^緣發生’則將正緣前的有效資料，致能輸 出至下一筛選並檢出視訊影像資料模組2卜該篩選並 檢出視訊影像資料模組21中，自每—圖框阶繼） 中’僅檢出所需要的水平掃描線，該自每一條水平掃 掐線的影像貧料檢出有效資料模組22中，是自每一條 水平掃描線的影像資料中，僅檢出所需要的像素/ (Pixel)，致能輸出，該YCbCr444轉換成RGB〇位元 組RGB貝料）模組23中，則將資料自YCbCr444轉換成 RGB(3位元組RGB資料），該RGB(3位元組RGB資 料）轉換成RGB(4位元組RGB資料）模組24中，則將 貝料自RGB(3位元組RGB資料）轉換成RGB(4位元組 RGB貝料）’該多數個前置處理器丨丨與排程及資料搜 集為12之間的資料傳遞機制協定如下··在每一前置處 M324824 理器11中均名1罢：欠a丨 3卜二，f 一貝料緩衝器3〇及-資料有效旗標 月J处理斋11將最新抿達的景彡傻眘料宜入-欠j·丨 衝器30時，同時逹的“象貝科寫入貧料緩 為一即時有#31 、有效貝料’當排程及資料搜集器㈣定此一 器11送出資料時，前置處理器η即將資料與 ^有效旗標同時送出，送㈣時，前置處理 清除資料有效旅俨Ή 將 下一曰4少、私1，表不此一資料已經輸出過，當(pixel) module, a YCbCr444 converted to RGB (3-bit RGB data) module, an RGB (3-byte RGB data) into rgb (4-bit RGB data) module 'this high-speed clock An innovative approach to detecting valid data modules can increase the speed of the working clock. A data buffer and a data valid flag are used between the majority of the pre-processors and the schedule and data collectors. Establish a data transfer association M324824 疋 'effectively obtain data of multiple channels, the interface between the sra_f (10) interface processor 'processing # material read and write, take - the priority order of 5 buy and write strategy' in SRAM and Read and write operations between the front and back FIFOs. The monitoring device provided by this creation, the FpGU film ^ is fully operated by the hardware circuit, and the f-line Wei (four) speed Na wafer is the video memory, the speed is increased, the design-speed is faster, the image painting is the car father. A good digital color image monitoring device. [Embodiment] Referring to the figure 'Second, Third, Fourth and Sixth', the Department of Creation provides a SRAM chip based on the ship wafer and using high-speed b-line function as video memory. The even-numbered segmentation of the body, the digital color image monitoring device includes a plurality of analog-to-digital converters 10, a programmable logic array crystal, a synchronous random access memory chip 14, and a digital to analog wafer. u, one: frequency image display display (four) 'the programmable logic array chip idle t clock delay locked loop component, placed in a plurality of pre-processing stolen 11, synchronous random access memory controller 15, synchronization The interface between the random access memory control H and the first-in first-out buffer, the programmable logic array chip 4 includes a plurality of preambles: a heart, a scheduling and data collector 12, and a front end first First out buffer 13, a synchronous random access memory controller 15, an interface between the synchronous random access memory controller and the first in first out buffer M324824, a back first in first out buffer 17, and then End processing The internal-video image display timing generator 19, the pre-processing (4) includes a high-speed clock detection effective data module side and detecting the video image data module 21, - images from each horizontal scanning line (4) Check out the valid (four) module 22, one will "YCbCr444#^^ RGBO^^^ RGB ##) #^23_ 1RGB (3 / Li Yuan, group job data) into _4 byte group, bucket), And 24' A return speed clock detection valid data module, use Shishi high-speed clock 60 to simultaneously detect the analog-to-digital converter 1〇 output of the shoumai pulse 61 ' and the data 62 synchronized with it, if It is found that the occurrence of the same/clock is generated, and the valid data before the positive edge is output to the next screening and the video image data module 2 is detected and the video image data module 21 is detected. , from each frame-by-frame, in the 'detection only the required horizontal scanning line, which is from the image-poor detection effective data module 22 of each horizontal broom line, is from each horizontal scanning line In the image data, only the required pixels / (Pixel) are detected, the output is enabled, and the YCbCr444 is converted into RGB clamps. In the group 23, the data is converted from YCbCr444 to RGB (3-byte RGB data), and the RGB (3-byte RGB data) is converted into RGB (4-byte RGB data) module. In 24, the bead material is converted from RGB (3-byte RGB data) to RGB (4-byte RGB material). The majority of the pre-processors are scheduled and the data is collected between 12 The data transfer mechanism is as follows: · At each predecessor, M324824 is named 1 in the processor 11: owing a 丨 3 卜 2, f a bunker buffer 3 〇 and - data valid flag month J processing fast 11 The latest 抿 的 彡 彡 彡 慎 慎 慎 慎 - - - 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠 欠(4) When this device 11 sends the data, the pre-processor η will send the data and the ^ valid flag at the same time, and when sent (4), the pre-processing clears the data and the effective travel will be the next 4 less, private 1 No such information has been exported, when
搜隼：12:料抵達時，再重複前述動作’排程及資料 ㈣資财效旗標後，將制旗標是 f山土右疋’則加上通道識別位元，與資料同時 ^機先f緩衝器13’若否’則略過，利用上 ”王及貧料搜集器12需花兩個時脈週期的時 得-個通道的資料，可以有效取得多數個通 料’該同步隨機存取記憶體控制器似理同步 :=Γ:咖4的管線作業’負責對同步隨機存取 存取命令’該同步隨機存取記憶體控制 二…入先出緩衝器之間的介面控制器^ 6，處理資料 3ΓΓ序’說明如下··第一優先自同步隨機存取記 ί體14中讀取一條水平掃描線的影像資料，存入後端 -先出緩衝益17’第二優先則測試前端先入先出緩 衝器13的幾乎將空（Alm〇stEmpty)旗標，若有資料則 立即讀出資料與通道識職元，再根據此識別位元， 夺不同k道的貝料寫入該通道在同步隨機存取記憶體 9 M324824Search: 12: When the material arrives, repeat the above action 'schedule and data (4) after the financial efficiency flag, the flag will be f mountain soil right 疋 ' plus the channel identification bit, and the data at the same time First f buffer 13 'if no ' is skipped, using the "Wang and poor material collector 12 takes two clock cycles of the time - channel information, can effectively obtain a majority of the material 'this random random Access memory controller sympathetic synchronization: = Γ: the pipeline operation of the coffee 4 'responsible for the synchronous random access access command' The synchronous random access memory controls the interface controller between the first-in first-out buffer ^ 6, processing data 3 order 'description' as follows · · first priority self-synchronous random access memory ί body 14 read a horizontal scan line of image data, stored in the back-first-out buffer first 17' second priority The Alm〇stEmpty flag of the first-in first-out buffer 13 of the test front end is tested, and if there is data, the data and the channel identification element are immediately read, and according to the identification bit, the bet of different k-channels is written. The channel is in synchronous random access memory 9 M324824
圖像陳列顯不器IB，該視頻圖像陳列時序產生器丨9負 責產生VGA時序。 、 【圖式簡單說明】 第一圖係本創作之整體詳細架構圖。 第二圖係本創作之每一通道的前置處理器内部結構 第三圖係本創作之多數個前置處理器與排程及資料 搜集器之間資料傳遞的協定機制圖。 第四圖係本創作之簡單架構圖。 第五圖係習知多分割數位彩色影像監控架構圖。 第八圖係本創作之每一通道前置處理器中的高 出有效資料模組中採用方法的脈衝時序說明圖。 【主要元件符號說明】 第一圖 10類比轉數位晶片 12排程及資料搜集器 14同步隨機存取記憶體 11前置處理器 13前端先入先出緩衝器 15同步隨機存取記憶體控制器 M324824 16同步隨機存取記憶體控制器與先入先出緩衝器之間 的介面控制器 18後端處理器 1A數位轉類比晶片 17後端先入先出緩衝器 19視頻圖像陳列時序產生器 1B視頻圖像陳列顯示器 - 第二圖 20南速時脈檢出有效資料模組 21篩選並檢出影像資料模組 22自每一條水平掃描線的影像資料檢出有效資料模組 23 YCbCr444轉成RGB(3位元組職資料）模組 24 RGB(3位元組RGB資料）The image display display device IB is responsible for generating the VGA timing. [Simplified description of the drawings] The first picture is the overall detailed architecture of the creation. The second figure is the internal structure of the pre-processor of each channel of the creation. The third picture is the agreement mechanism diagram of the data transfer between the majority of the pre-processors of the creation and the scheduling and data collector. The fourth picture is a simple architecture diagram of the creation. The fifth figure is a conventional multi-segment digital color image monitoring architecture diagram. The eighth figure is a pulse timing diagram of the method used in the high-efficiency data module in each channel pre-processor of the present creation. [Main component symbol description] The first figure 10 analog-to-digital wafer 12 scheduling and data collector 14 synchronous random access memory 11 pre-processor 13 front-end first-in first-out buffer 15 synchronous random access memory controller M324824 16 Synchronous random access memory controller and first-in first-out buffer interface controller 18 back-end processor 1A digital to analog wafer 17 back-end first-in first-out buffer 19 video image display timing generator 1B video Like the display display - the second picture 20 south speed clock detection effective data module 21 screens and detects the image data module 22 from each horizontal scan line image data detection effective data module 23 YCbCr444 into RGB (3 Bytes job data) module 24 RGB (3-byte RGB data)
貝竹）轉成RGB(4位元組RGB資 料）模組 M 第三圖 30資料緩衝器 31資料有效旗標 第四圖 4 0可程式邏輯陣列 第五圖〔習知〕 50根據特定應用而制定規格積體電路 51同步動態隨機存取記憶體、 M324824 * 第六圖 60高速時脈 61類比轉數位轉換器輸出與資料同步時脈 62類比轉數位轉換器輸出資料Beizhu) into RGB (4-byte RGB data) module M third Figure 30 data buffer 31 data valid flag fourth Figure 4 0 programmable logic array fifth figure [known] 50 according to specific applications Developed specification integrated circuit 51 synchronous dynamic random access memory, M324824 * Sixth figure 60 high-speed clock 61 analog-to-digital converter output and data synchronization clock 62 analog-to-digital converter output data
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