TWM324288U - Producing the wiring board - Google Patents

Producing the wiring board Download PDF

Info

Publication number
TWM324288U
TWM324288U TW096209933U TW96209933U TWM324288U TW M324288 U TWM324288 U TW M324288U TW 096209933 U TW096209933 U TW 096209933U TW 96209933 U TW96209933 U TW 96209933U TW M324288 U TWM324288 U TW M324288U
Authority
TW
Taiwan
Prior art keywords
layer
plating layer
thickness
electronic component
substrate
Prior art date
Application number
TW096209933U
Other languages
Chinese (zh)
Inventor
Masaharu Ishisaka
Original Assignee
Mitsui Mining & Smelting Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui Mining & Smelting Co filed Critical Mitsui Mining & Smelting Co
Publication of TWM324288U publication Critical patent/TWM324288U/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body

Description

M324288 八、新型說明: 【新型所屬之技術領域】 * 本創作是關於安裝電子零件用之電子零件安裝用基板 .及電子零件安裝用基板之製造方法,尤其是關於如晶片尺 •寸封裝(Chip Size Package,以下簡稱為CSP)、珠狀閘極 矩陣(Ball Grid Array,以下簡稱為_、#_珠狀閘極矩 陣U-Ball Grid Array,以下簡稱為# 一BGA)、倒裝片 (Flip Chip,以下簡稱卩〇、四角形扁平封裝((3仙(1 Flatpack Package,以下簡稱QFP)等,其尺寸略與所安裝 之電子零件相等之電子零件安裝用基板(以下簡稱為「電 子零件安裝用基板」)及電子零件安裝用基板之製造方法。 【先前技術】 隨者電子裝置產業之發達’用以安裝積體電路(ic)、大 規模積體電路⑽)等之電子零件之印刷電路基板之需要 有急遽地增加,且有電子機器之小型化、輕量化及高機能 #化之要求;而關於該等電子零件之安裝方法,最近是有採 用使用TAB帶子、Τ-BGA帶子、及ASIC帶子等之安裝方式。 尤其是,隨著電子機器之輕薄短小化’將外部連接端子配 置在其大小略對應於所要安裝之電子零件之大小之基板 =略全面上之’例如csp、BGA十脱等之使用頻度變高, 藉由以更南挽度安褒電子零件之同時,提高電子零件 靠性。 、2為該电子令件安装用基板之電子零件安裝用薄膜承 載V之衣k方法如下。首先,例如對聚亞胺薄膜等之絕緣 326\總檔\91\91114598VTF968021 M324288 缚黏貼銅箱,力兮4々斤 配線圖案以外之部將形成該光阻之 接著,將除去光阻::=rf所曝光過的光阻。 阻來形成電路圖案。 ”予以蝕刻除去,再除去光M324288 8. New description: [New technical field] * This is a manufacturing method for mounting electronic components for electronic components and a method for manufacturing electronic component mounting substrates, especially for wafer size and inch packaging (Chip) Size Package, hereinafter referred to as CSP), Ball Grid Array (hereinafter referred to as _, #_ Bead Gate Matrix U-Ball Grid Array, hereinafter referred to as #BGA), Flip Sheet (Flip) Chip, hereinafter referred to as 卩〇, 四 扁平 扁平 ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子"Substrate") and a method of manufacturing an electronic component mounting substrate. [Prior Art] A printed circuit board for electronic components such as an integrated circuit (ic) or a large-scale integrated circuit (10) is developed in the electronic device industry. There is a need to increase rapidly, and there are requirements for miniaturization, light weight, and high performance of electronic devices; and how to install such electronic components, recently There are mounting methods using TAB tapes, Τ-BGA tapes, and ASIC tapes. In particular, with the lightness and thinness of electronic devices, the external connection terminals are arranged to have a size slightly corresponding to the size of the electronic components to be mounted. The substrate = slightly more comprehensively, for example, the frequency of use of csp, BGA, etc. becomes higher, and the electronic component is improved while the electronic component is mounted in a more southerly degree. 2 is the substrate for mounting the electronic component. The method for mounting the electronic component mounting film V is as follows. First, for example, the insulating 326 of the polyimide film, the total file of the \91\91114598 VTF968021 M324288, and the copper box, the force other than the wiring pattern of the 4 jin. Subsequent to the formation of the photoresist, the photoresist resisted by the photoresist::=rf is removed. The circuit pattern is formed by blocking.

如,形成有配線圖案之電子零件安I 上’在内部導線、外部導線、焊球端子等之端子^外之 部分塗敷焊阻作為電路 ^卜, 分之端子部形成電制。阻之後’在露出部 ,此’用金屬線接合法’在與電子零件等連接之端子部 ’:鎳::鍍金層。又,為了可確保得到足夠的接合強 ==為層之厚度形成為°」〜1微米,而鏟金 【新型3微米以確保充分的接合強度。 (新型所欲解決之問題) 在該電子零件安裝用基板中,為削減成本起見, 、王月專化鑛至層’但如果使鑛金層厚度減少至U微米 广下日守艮Ρ會發生無法得到足夠的金屬線接合強度的問 題0 本創作係L於上h,其目的在於提供_種雖然儘量減少 ,至層之厚度’但能夠癌保金屬線接合強度之電子零件安 裝用基板以及電子零件安裝用基板之製造方法者。 (解決問題之手段) 解決前述問題之本創作m為,在具備有絕緣基 材,形成在該絕緣基材之一方面上所形成之配線圖案,及 326\$g^\91\91li4$98\TF968021 7 M324288 覆蓋該配線圖案之端子部除外之表面之焊阻層,在前述端 子部之表面,有疊層鍍鎳層及鍍金層之電子零件安裝用基 板中,其特徵為,前述鍍鎳層之厚度在3微米以上而維卡 硬度為350以上者。 在該第—態樣中,可以加大金屬線接合強度,雖把鍍金 層厚度減少至例如〇. 5微米以下,但仍然可得到足夠的金 屬線接合強度。 本創作之第二態樣為,在第—態樣中,前述鍍鎳層之表 面粗糖度Rz為1〜3微米為其特徵之電子零件安裝用基板 者0 在該第二態樣中’可以加大金屬線接合強度,雖把鐘金 層厚度減少至例如0.5微米以下,但仍然可得到足夠的金 屬線接合強度。 本創作之第三態樣為,在第—態樣中,前述鍍金層之厚 又在ϋ微米以下為其特徵之電子零件安裝用基板者。 在該第三態樣中’可以把鍍金層厚度減少到0.5微米以 下,可降低成本。 ,創: 乍之第四態樣為’在第二態樣中,前述鍍金層之厚 "^切下為其特徵之電子零件安裝用基板者。 在該第四態樣中,可以把 下,可降低成本。 又、—J〇·5微米以 本創作之第五態樣A,立楚 ^ 中,前述_之二 件安裝用基板者。 I 卡以下為其特徵之電子零 326\總檔\91 \91114598\TF968021 8 M324288 在該第五態樣中,可以把鍍金層厚度減少到〇 3微米以 下,可降低成本。 • 本創作之第六態樣為,在具備有絕緣基材,形成在該絕 ··緣基材之一方面上所形成之配線圖案,及覆蓋該配線圖案 ^之端子部除外之表面之焊阻層,在前述端子部之表面,有 疊層鍍鎳層及鍍金層之電子零件安裝用基板之製造方法 中,其特徵為,具備有將前述鍍鎳層形成為其厚度在3微 米以上而維卡硬度為35〇以上之製程,及在其上面形成前 述鍍金層之製程之電子零件安裝用基板之製造方法者。 在該第六態樣中,可以加大金屬線接合強度,雖把鍍金 層厚度減至例如〇 · 5微米以下,但仍然可得到足夠的金 屬線接合強度。 ’ 本創作之第七態樣為,具備有在第六態樣中,在形成前 述鍍鎳層後,處理其表面使其表面粗糙度Rz為1〜3微米之 過程為其特徵之電子零件安裝用基板之製造方法者。 籲在該第七態樣中,可以加大金屬線接合強度,雖把鍍金 層厚度減少至例如〇· 5微米以下,但仍然可得到足夠 屬線接合強度。 本創作之第八悲樣為,在第六態樣中,可把前述鐘金層 之厚度形成為〇· 5微米以下為其特徵之電子零件安裝用基 板之製造方法者。 、土 在該第八態樣中,可以把鍍金層厚度減少到〇·5微米以 下而可降低成本。 本創作之第九態樣為,在第七態樣中,可把前述鍍金層 326\總槽\91\91114598\TF968021 0 M324288 之厚度形成為0.5微米以下為其特徵之電子零件用基 板之製造方法者。 .在該第九態樣中’可以把鍍金層厚度減少到以微米以 / 下而可降低成本。 '本創作之第十態樣為,在第六至九態樣中之任一能樣 中,可把前述鍍金層之厚度形成為〇3微米以下為其特徵 之電子零件安裝用基板之製造方法者。 在該第十態樣中,可以把鍍金層厚度減少到u微米以 下而可降低成本。 【實施方式】 兹將有關本創作之一實施形態之電子零件安裝用基板 及其製造方法說明如下。在圖i及圖2中分別顯示本創作之 =零件安裝用基板及以其製造方法所製造之電子零件 安裝用基板之一例之概略平面及橫剖面。 、如圖1所示’電子零件安裝用基板1G是複數個連續地形 魯成在^狀之絕緣薄膜!上。該絕緣薄膜i之寬度方向兩側保 持一定間隔設有矛多送用之鏈輪孔2,通常是在移送之同時 安裝電子零件,安裝電子零件後,按每一個電子零件安裝 用基板10切斷之。在圖!中,在絕緣薄膜以寬度方向設有 兩個電子零件安裝用基板1〇。 該電子零件安裝用基板1〇為’在與所安裝之電子零件之 J略對應之大小之絕緣基材丨丨之全面,設有配線圖案 U、裝置側連接端子13及外部連接端子“。又,設有複數 個用以連接該配線圖案12及電子零件之開縫15。該開縫“ 326\總檔\91\91114598\TF968021 M324288 是用金屬線接合法電性連接所絲之電子零件與配線圖 案12者;而其形狀及配置圖案並無特別的限定。 - 除该裒置側連接端子13及外部連接端子丨4以外之配線 •圖案12是由嬋阻層16所覆蓋,對應於外部連接端子14之烊 .阻層16有形成端子孔17。換言之,外部連接端子“成為焊 T墊,藉由焊球而與外部連接。當然,未設有端子孔,用 焊球以外之手段來與外部連接之型式之電子零件安裝用 ; 基板也可以。 鲁^,未由焊阻層16所覆蓋之裝置側連接端子13及外部連 接Μ子14為,在形成配線圖案12之全體之導電體箔Μ上設 有鍍鎳層22及鍍金層23。鍍鎳層22及鍍金層23之構成為, 適合於以金屬線接合法實行接合之端子;在本實施形態 中,至少需要設在裝置側連接端子13。再者,不實行金屬 線接合之端子,例如外部連接端子14可以設其他電鍍層。 關於絕緣薄膜1 (絕緣基材1 1 ),可使用具有可撓性的同 #時具有耐化學藥品及耐熱性的材料。關於該種絕緣薄膜i 之材料可舉聚酯、聚醯胺及聚亞胺等為例。尤其是具有聯 二苯骨架之全芳香族聚亞胺(例如,商品名··由必烈克斯; •宇部興產公司製品)為宜。又,絕緣薄膜丨之厚度一般為25 〜125微米,而以25〜75微米為宜。 又在、、、巴、、彖薄膜1表面之配線圖案12,裝置侧連接端子13 及外部連接端子14,通常是以銅或鋁所成之導電體箔上設 圖案而幵> 成之。該導電體箔可直接疊層於絕緣薄膜1上, 或藉由黏接劑而以熱壓接等方法形成也可以。導電體箔之 326\總檔\91\91114598\TF968021 n M324288 !度為例如6〜7°微米,而以8〜35微米為宜。關於導電, 佶用為且’尤其疋考置姓刻特性,操作性等時,以 使用電解鋼為佳。 才以 又、,不是在絕緣薄膜1上設導電體箔,而是對導 上’塗敷聚亞胺先驅體’燒成而構成 成 絕緣薄膜!也可以。 妝厚胰所成之 、又,設在絕緣薄膜1上的導電體箱是用攝影刻印 j配線圖案12、裝置侧連接端子13及外部連接端子…換 石之’經光罩曝光及沖洗而在塗敷光阻材料之結果所形 之光阻材料塗敷層上形成圖案,然後,形成有圖案之光阻 材料塗敷層作為遮蔽,使用㈣液予以化學溶解(即敍刻 處理)而除去,再用鹹液等溶解除去光阻而在導電體: 形成圖案。 ' 、在如此形成有圖案之導電體箔上塗敷抗焊材料塗敷 液’依預定之圖案形成焊阻層丨6。 • 關於形成焊阻層16之材料即例如使用光焊阻材料。關於 光焊阻材料即負片型或正片型均可;只要是其具備有一般 性的光阻之性質,及保護導電體箔之性質者則可。例如, .對丙烯酸酯樹脂、尤其是對環氧丙烯酸酯樹脂等之感光性 樹脂添加光聚合作用開始劑等者。關於環氧丙烯酸酯樹脂 則可舉二苯酚A型環氧丙烯酸酯樹脂、漆用酚醛型環氧丙 烯酸酯樹脂、二苯酚A型環氧偏丙烯酸酯樹脂、漆用酚醛 型環氧偏丙烯酸酯樹脂等為例。又,關於焊阻層16,可使 用藉網版印刷技術而只塗敷在必要區域並熱硬化之一般 326\總檔\91\91114598\TF968021 12 M324288 性太干阻材料塗敷液者。 如上述設有配線圖案1 2、裝置側連接端子1 3、外部連接 •端子14及焊阻層16的絕緣薄膜i之相反之一面(背面),設 有暫時固定所要安裝之電子零件用之黏接劑層19及保護 •用薄膜20。關於該種黏接劑層19應使用熱硬化性且具有彈 性的黏接劑來形成為宜,直接塗敷在背面來形成則可,或 使用黏接帶來形成也可以。又,黏接劑層19是不必設在安 叙電子零件之區域全體部分,只設在局部性區域也可以。 _ 炫就豐層在該電子零件安裝用基板10之配線圖案12之 I置側連接端子13及外部連接端子14之鍍鎳層22及鍍金 層2 3說明如下。 在本創作中,鍍鎳層22及鍍金層23是使用與以往相同之 電鍍液而形成,·其電鍍法、電鍍條件等並無特別的規定。 換言之,使用無電解電鍍法或電解電鍍法均可;藉由調整 電鍍液組成、施加電壓、電流密度、電鍍溫度等而可形成 鲁所希望之厚度。 又,錢金層23疋只用黃金構成也可以,或含有黃金為主 要金屬的黃金合金金屬也可以。又,鍍鎳層22是只用鎳構 成也可以,或含有鎳為主要金屬的鎳合金金屬也可以。可 與鎳共同形成該層之金屬是例如Sn —Ni、C〇—…等。但在任 何情形中,形成該層之主要金屬是在形成該層金屬之合計 中含有量在50重量%以上,而以90重量%以上為宜。 關於能夠形成鍍鎳層22的鍍鎳浴為例如氨基磺酸鎳浴 等。又,關於能夠形成鍍金層23的鍍金浴為例如氰基黃金 326\|®^\91\91114598\TF968021 η M324288 浴等。 本創作中,以形成為底層之鍍鎳層22的厚度及硬度為重 要鑛鎳層22的厚度為3微米以上,硬度為維卡硬度mo 以上。此乃用以充分確保金屬線接合強度的關係。在此, 硬度是例如改變電鍍液中之光澤劑之濃度而可調整之。 又,作為底層的鍍鎳層22是在形成電鍍層後予以表面處 理,使表面粗糙度Rz在丨〜3微米之範圍内為宜。大於該範 圍,則在實行金屬線接合強度時,超音波難以傳達至底層 之鍍鎳層22的關係而降低接合強度,又,小於該範圍時, 則與鍍金層的密接強度降低而降低接合強度,均發生不良 的結果。又,表面處理方法並無特別的限定,例如,可用 鹽酸等之酸處理來調整之。 又,鍍金層23之厚度並無特別的限定,但形成上述之鍍 鎳層22之結果,雖然在〇. 5微米以下,甚至在〇. 3微米以下 時也可以得到足夠的接合強度。在此,接合強度是通常使 用之接合用金屬線之抗切斷強度之8§以上為宜,然而,形 成上述之鍍鎳層的結果,雖然鍍金層23的厚度為〇.2微米 之薄,但可得到超過其上之接合強度。再者,如果增加鍍 金層23的厚度時’可以得到更強的接合強度。 圖3中顯示對上述之電子零件安裝用基板1〇安裝電子零 件之狀態之一例。如圖3所示,在絕緣薄膜丨之背面所安裝 的電子零件之IC30與形成在絕緣薄膜丨之表面之裝置侧連 接端子13是藉由接合用金屬線31而連接,包含接合金屬線 31之開縫15及裝置側連接端子13是以封裝樹脂33成形 326\總檔\91 \91114598\TF968021 14 M324288 之。藉此,可以確保1C3〇與裝置側連接端子13之導電電路。 (實施例) - 玆根據實施例及比較例,將本創作詳加說明如下。 ·- 設在絕緣基材11上之導電體箔21上,設其硬度、厚度、 -表面粗糙度各不同之鍍鎳層22,在其上面設厚度〇2微^ 之鍍金層23。鍍鎳層之硬度為,在實施例中設定成4〇〇, 350 ’在比較例中則設定成3〇〇。又,厚度為,在實施例中 則设疋成4微米、3微米,而在比較例中則設定成2微米。 •再者,表面粗糙度RZ各設定成〇. 5微米、丨微米、2微米、3 微米、4微米。 …、 鍍鎳層22之硬度是以光澤劑之濃度來調整。又,表面粗 糙度Rz是以30%鹽酸之處理時間來調整。 又,電鍍層之厚度是根據螢光X線式厚度測定方法(jis Η 8 5 01 )來測定之。 以上述之方法形成之鍍金層23上,用金屬線接合法接合 _直径25//m0之黃金金屬線41。金屬線接合是使用麥克勞一 瑞士(Micro - Swiss)公司製之裝置,而在超音波輸出 1· 26W、施加時間22msec、加重80g、平台溫度攝氏16〇度 ―之條件下實行之。 & 又’接合強度為如圖4所示,將接合於鍍金層23之黃金 金屬線41之另一端固定在固定基板42,拉上掛在黃金H 線41之鉤43 ’以測定與鍍金層23之接合部剥離,或黃金金 屬線41切斷時之加重。 ' 其結果如表1所示。又,在強度8g以上則表示黃金金屬 326\總檔\91\91114598VTF968021 15 M324288 線41之切斷’在其以下則表示與鏟金層23之接合部之剝離 [表1 ] 鍍鎳層之 維卡硬度 ΐϊι鎳層之 厚度 (微米) _____攀鎳層之表面粗糙度Rz(微米) 0. 5 1 2 3 4 400 (實施例) 4 (實施例) 5 10 10 9 6 3 (實施例) 5 9 9 8 6 2 (比較例) 3 5 5 4 4 350 (實施例) 4 (實施例) 5 10 10 9 6 3 (實施例) 5 9 9 8 6 2 (比較例) 3 5 5 4 4 300 (比較例) 4 3 5 5 5 4 3 3 4 4 4 3 2 2 2 2 2 2 其結果,了解如果鍍鎳層為維卡硬度350以上,厚度在3 春微米以上時,雖然鍍金層厚度為〇· 2微米之薄,但可得到 足約的接合強度。又,鐘鎳層表面粗糖度^是1〜3為適 合;同時了解在0· 5或4微米時則會降低接合強度。再者, 也了解雖在如上述之表面粗經度中,如果增加錢金層之厚 度時,可提高接合強度,可以確保足夠實用的強度者。 (創作效果) 如上述,調節形成在配線圖案之端子部之鍍鎳層之厚 度、硬度、表面粗糙度之結果,能夠提高金屬線接合強度 的關係,雖把鍍金層厚度減少至以往之〇· 7〜1· 3微米以 326、總檔\91\91114598\TF968021 16For example, the electronic component on which the wiring pattern is formed is applied to the portion of the terminal of the inner lead, the outer lead, the solder ball terminal, etc. as a circuit, and the terminal portion is electrically formed. After the resistance, in the exposed portion, the metal wire bonding method is used to connect the terminal portion of the electronic component or the like: a nickel: gold plating layer. In addition, in order to ensure sufficient joint strength == the thickness of the layer is formed to be "1" to 1 micron, and the new metal is 3 micrometers to ensure sufficient joint strength. (New problem to be solved) In the electronic component mounting substrate, in order to reduce costs, Wang Yue specializes in mineralization to the layer 'but if the thickness of the gold layer is reduced to U micron The problem of the inability to obtain sufficient wire bonding strength is achieved. The purpose of this invention is to provide an electronic component mounting substrate that can reduce the thickness of the layer to the thickness of the layer. A method of manufacturing a substrate for mounting an electronic component. (Means for Solving the Problem) The present invention for solving the above problems is a wiring pattern formed by forming an insulating substrate and forming one of the insulating substrates, and 326\$g^\91\91li4$98\ TF968021 7 M324288 A solder resist layer covering the surface except the terminal portion of the wiring pattern, and a substrate for mounting an electronic component having a nickel plating layer and a gold plating layer on the surface of the terminal portion, characterized in that the nickel plating layer is provided The thickness is 3 micrometers or more and the Vicat hardness is 350 or more. In this first aspect, the bonding strength of the metal wire can be increased, and although the thickness of the gold plating layer is reduced to, for example, 〇. 5 μm or less, sufficient metal wire bonding strength can still be obtained. In the second aspect of the present invention, in the first aspect, the surface of the nickel-plated layer having a roughness Rz of 1 to 3 μm is characterized by an electronic component mounting substrate 0 in the second aspect. Increasing the bonding strength of the metal wire, although the thickness of the gold layer is reduced to, for example, 0.5 μm or less, sufficient wire bonding strength can still be obtained. The third aspect of the present invention is a substrate for mounting an electronic component characterized by a thickness of the gold plating layer of less than ϋ micron in the first aspect. In this third aspect, the thickness of the gold plating layer can be reduced to less than 0.5 μm, which can reduce the cost. , 创: The fourth aspect of 乍 is 'in the second aspect, the thickness of the gold-plated layer is " ^ cut off the substrate for electronic component mounting. In this fourth aspect, it is possible to reduce the cost. Also, -J〇·5 micron is the fifth aspect of the creation A, and the second one is the substrate for mounting. The following is the characteristic of the I card. The electronic zero 326\total file\91 \91114598\TF968021 8 M324288 In this fifth aspect, the thickness of the gold plating layer can be reduced to less than 微米 3 microns, which can reduce the cost. • The sixth aspect of the present invention is a wiring pattern formed by forming an insulating substrate and forming one of the insulating/finishing substrates, and a surface of the surface except the terminal portion covering the wiring pattern In the method for producing an electronic component mounting substrate having a laminated nickel plating layer and a gold plating layer on the surface of the terminal portion, the method further includes forming the nickel plating layer to have a thickness of 3 μm or more. A method of manufacturing a substrate for mounting electronic parts having a Vicat hardness of 35 Å or more and a process of forming the gold plating layer thereon. In the sixth aspect, the bonding strength of the metal wire can be increased, and although the thickness of the gold plating layer is reduced to, for example, 〇 5 μm or less, sufficient metal wire bonding strength can be obtained. The seventh aspect of the present invention is that there is a process for mounting an electronic component characterized by a process of treating the surface thereof to have a surface roughness Rz of 1 to 3 μm after forming the nickel plating layer in the sixth aspect. The method of manufacturing the substrate. It is claimed that in the seventh aspect, the bonding strength of the metal wire can be increased, and although the thickness of the gold plating layer is reduced to, for example, 〇·5 μm or less, sufficient line bonding strength can still be obtained. The eighth sadness of the present invention is that in the sixth aspect, the thickness of the gold layer can be formed into a method for manufacturing an electronic component mounting substrate characterized by less than 5 μm. In the eighth aspect, the thickness of the gold plating layer can be reduced to less than 〇5 μm to reduce the cost. The ninth aspect of the present invention is that, in the seventh aspect, the thickness of the gold plating layer 326\total groove \91\91114598\TF968021 0 M324288 can be formed into a substrate for electronic parts characterized by 0.5 micron or less. Method. In the ninth aspect, the thickness of the gold plating layer can be reduced to be at or below the micron to reduce the cost. The tenth aspect of the present invention is a method for manufacturing an electronic component mounting substrate in which the thickness of the gold plating layer is 〇3 μm or less in any of the sixth to ninth aspects. By. In the tenth aspect, the thickness of the gold plating layer can be reduced to less than u micron to reduce the cost. [Embodiment] An electronic component mounting substrate and a method of manufacturing the same according to an embodiment of the present invention will be described below. In Fig. i and Fig. 2, a schematic plan view and a cross section of an example of the substrate for mounting the component and the substrate for mounting the electronic component manufactured by the method of manufacturing the same are shown. As shown in Fig. 1, the electronic component mounting substrate 1G is a plurality of continuous topography Lu Cheng in the shape of an insulating film! on. The sprocket hole 2 for spear-feeding is provided at a certain interval between the two sides of the insulating film i in the width direction. Usually, electronic components are mounted at the same time as the transfer, and after mounting the electronic components, the substrate 10 for each electronic component is cut. It. In the picture! In the insulating film, two electronic component mounting substrates 1 are provided in the width direction. The electronic component mounting substrate 1A is provided with a wiring pattern U, a device-side connection terminal 13, and an external connection terminal "integrated with an insulating substrate 大小 corresponding to the size of the mounted electronic component J." , a plurality of slits 15 for connecting the wiring pattern 12 and the electronic components are provided. The slit “326” is a metal file bonding method for electrically connecting the electronic components of the wire with the metal wire bonding method. The wiring pattern 12 is not particularly limited in shape and arrangement pattern. - Wirings other than the mounting side connection terminal 13 and the external connection terminal • 4 • The pattern 12 is covered by the resist layer 16 and corresponds to the external connection terminal 14. The resist layer 16 has a terminal hole 17 formed therein. In other words, the external connection terminal "is a solder T pad and is connected to the outside by solder balls. Of course, the terminal is not provided, and the electronic component of the type that is connected to the outside by means other than solder balls is used; the substrate may be used. The device-side connection terminal 13 and the external connection die 14 which are not covered by the solder resist layer 16 are provided with a nickel-plated layer 22 and a gold-plated layer 23 on the conductor foil of the entire wiring pattern 12. The nickel layer 22 and the gold plating layer 23 are configured to be suitable for bonding by a wire bonding method. In the present embodiment, at least the device side connection terminal 13 is required. Further, the terminal for wire bonding is not performed. For example, a different plating layer may be provided for the external connection terminal 14. As for the insulating film 1 (insulating substrate 1 1 ), a material having chemical resistance and heat resistance when it is flexible may be used. The material may, for example, be a polyester, a polyamine or a polyimine, etc., in particular, a wholly aromatic polyimine having a biphenyl skeleton (for example, a trade name of Benelux; • Ube Industries Co., Ltd. ) is appropriate. Again, The thickness of the insulating film 一般 is generally 25 to 125 μm, and is preferably 25 to 75 μm. The wiring pattern 12 on the surface of the film 1, the surface of the film, the device side connection terminal 13 and the external connection terminal 14 are usually It is formed by patterning a conductor foil made of copper or aluminum. The conductor foil can be directly laminated on the insulating film 1, or formed by thermocompression bonding or the like by an adhesive. Yes. Conductor foil 326\total file\91\91114598\TF968021 n M324288 The degree is, for example, 6~7° micron, and 8~35 micron is suitable. Regarding the conduction, it is used and 'specially In the case of engraving characteristics, operability, etc., it is preferable to use electrolytic steel. In addition, instead of providing a conductive foil on the insulating film 1, a conductive film coated with a 'polyimide precursor' is formed. Insulating film! It is also possible. The conductive box provided on the insulating film 1 is formed by photo-printing j wiring pattern 12, device-side connecting terminal 13 and external connecting terminal... The mask is exposed and rinsed to coat the photoresist material as a result of applying the photoresist material Forming a pattern thereon, and then forming a patterned photoresist layer as a mask, removing it by chemical dissolution (ie, etch treatment) using a liquid, and then removing the photoresist by using a salt solution or the like to dissolve the photoresist in the conductor: forming a pattern The coating of the solder resist coating liquid on the patterned conductor foil is formed by forming a solder resist layer 6 in a predetermined pattern. • For the material forming the solder resist layer 16, for example, a solder resist material is used. The solder resist material may be either a negative type or a positive type; as long as it has a general photoresist property and protects the properties of the conductor foil, for example, an acrylate resin, especially an epoxy resin. A photosensitive resin such as an acrylate resin is added with a photopolymerization initiator, etc. Examples of the epoxy acrylate resin include a diphenol A type epoxy acrylate resin, a phenolic epoxy acrylate resin for a lacquer, and a diphenol type A. An epoxy acrylate resin, a phenolic epoxy acrylate resin, and the like are exemplified. Further, as for the solder resist layer 16, it is possible to use a screen printing technique to coat only the necessary area and heat-harden the general 326\total file\91\91114598\TF968021 12 M324288. As described above, the opposite side (back surface) of the insulating film i provided with the wiring pattern 1 2, the device side connection terminal 13 , the external connection terminal 14 and the solder resist layer 16 is provided with a temporary fixing for the electronic component to be mounted. The adhesive layer 19 and the protective film 20 are used. It is preferable that the adhesive layer 19 is formed by using a thermosetting and elastic adhesive, and it may be formed by directly coating the back surface or by using a bonding tape. Further, the adhesive layer 19 is not necessarily provided in the entire portion of the area in which the electronic component is mounted, and may be provided only in a partial region. The nickel-plated layer 22 and the gold-plated layer 23 of the I-side connection terminal 13 and the external connection terminal 14 of the wiring pattern 12 of the electronic component mounting substrate 10 are described below. In the present invention, the nickel plating layer 22 and the gold plating layer 23 are formed using the same plating solution as in the related art, and the plating method, plating conditions, and the like are not particularly limited. In other words, either electroless plating or electrolytic plating can be used; the desired thickness can be formed by adjusting the composition of the plating solution, the applied voltage, the current density, the plating temperature, and the like. In addition, the gold layer of the gold layer can be composed of only gold, or a gold alloy metal containing gold as the main metal. Further, the nickel plating layer 22 may be formed of only nickel or a nickel alloy metal containing nickel as a main metal. The metal which can form the layer together with nickel is, for example, Sn-Ni, C〇-...etc. However, in any case, the main metal forming the layer is contained in an amount of 50% by weight or more in total of the metal forming the layer, and preferably 90% by weight or more. The nickel plating bath capable of forming the nickel plating layer 22 is, for example, a nickel sulfamate bath or the like. Further, the gold plating bath capable of forming the gold plating layer 23 is, for example, a cyano gold 326\|®^\91\91114598\TF968021 η M324288 bath or the like. In the present invention, the thickness and hardness of the nickel-plated layer 22 formed as the underlayer are such that the thickness of the important ore-bearing layer 22 is 3 μm or more, and the hardness is Vika hardness mo or more. This is to fully ensure the relationship of the wire bonding strength. Here, the hardness can be adjusted, for example, by changing the concentration of the brightening agent in the plating solution. Further, the nickel plating layer 22 as the underlayer is surface-treated after the plating layer is formed, and the surface roughness Rz is preferably in the range of 丨 3 μm. When it is larger than this range, when the wire bonding strength is applied, the ultrasonic wave is hard to be transmitted to the nickel plating layer 22 of the underlayer to lower the bonding strength, and when it is less than the range, the adhesion strength to the gold plating layer is lowered to lower the bonding strength. Both have bad results. Further, the surface treatment method is not particularly limited, and for example, it can be adjusted by an acid treatment such as hydrochloric acid. Further, the thickness of the gold plating layer 23 is not particularly limited, but as a result of forming the above-described nickel plating layer 22, sufficient bonding strength can be obtained even at 微米. 5 μm or less, even at 微米.3 μm or less. Here, the bonding strength is preferably 8 § or more of the cutting strength of the bonding wire to be used, but as a result of forming the above-described nickel plating layer, although the thickness of the gold plating layer 23 is 〇. 2 μm, However, it is possible to obtain a joint strength exceeding the above. Further, if the thickness of the gold plating layer 23 is increased, a stronger bonding strength can be obtained. Fig. 3 shows an example of a state in which an electronic component is mounted on the electronic component mounting substrate 1 described above. As shown in FIG. 3, the IC 30 of the electronic component mounted on the back surface of the insulating film crucible and the device side connecting terminal 13 formed on the surface of the insulating film crucible are connected by the bonding metal wire 31, and include the bonding metal wire 31. The slit 15 and the device side connection terminal 13 are formed by encapsulating resin 33 326\total file \91 \91114598\TF968021 14 M324288. Thereby, the conductive circuit of the 1C3 〇 and the device side connection terminal 13 can be ensured. (Embodiment) - This writing will be described in detail below based on examples and comparative examples. The conductive foil 25 provided on the insulating base material 11 is provided with a nickel plating layer 22 having different hardness, thickness, and surface roughness, and a gold plating layer 23 having a thickness of 〇2 μm is provided thereon. The hardness of the nickel plating layer was set to 4 〇〇 in the examples, and 350 ' was set to 3 在 in the comparative example. Further, the thickness was set to 4 μm and 3 μm in the examples, and was set to 2 μm in the comparative example. • Further, the surface roughness RZ is set to be 5 μm, 丨 micron, 2 μm, 3 μm, and 4 μm. ..., the hardness of the nickel plating layer 22 is adjusted by the concentration of the gloss agent. Further, the surface roughness Rz was adjusted by the treatment time of 30% hydrochloric acid. Further, the thickness of the plating layer was measured in accordance with the fluorescent X-ray thickness measuring method (jis Η 8 5 01 ). On the gold plating layer 23 formed by the above method, the gold metal wire 41 having a diameter of 25/m0 was joined by wire bonding. The wire bonding was carried out using a device manufactured by Micro-Swiss, Inc., and was carried out under the conditions of an ultrasonic output of 1.26 W, an application time of 22 msec, an increase of 80 g, and a platform temperature of 16 deg. & Further, the joint strength is as shown in Fig. 4, and the other end of the gold metal wire 41 bonded to the gold plating layer 23 is fixed to the fixed substrate 42, and the hook 43' hung on the gold H-line 41 is pulled to measure and gold-plated layer. The joint of 23 is peeled off, or the gold wire 41 is sharpened when it is cut. The results are shown in Table 1. Further, when the strength is 8 g or more, the gold metal 326\total file \91\91114598 VTF968021 15 M324288 line 41 is cut off', and the peeling of the joint portion with the shovel layer 23 is shown below [Table 1] Card hardness 厚度ι Nickel layer thickness (micron) _____ Climbing nickel layer surface roughness Rz (micron) 0. 5 1 2 3 4 400 (Example) 4 (Example) 5 10 10 9 6 3 (Example) 5 9 9 8 6 2 (Comparative Example) 3 5 5 4 4 350 (Example) 4 (Example) 5 10 10 9 6 3 (Example) 5 9 9 8 6 2 (Comparative Example) 3 5 5 4 4 300 (Comparative Example) 4 3 5 5 5 4 3 3 4 4 4 3 2 2 2 2 2 2 As a result, it is understood that if the nickel plating layer has a Vicker hardness of 350 or more and a thickness of 3 springs or more, although the thickness of the gold plating layer is It is as thin as 2 microns, but the joint strength of the foot can be obtained. Further, it is suitable that the surface roughness of the nickel layer is 1 to 3; at the same time, it is understood that the bonding strength is lowered at 0.5 or 4 μm. Further, it is also known that, in the case of the surface roughness as described above, if the thickness of the gold layer is increased, the joint strength can be improved, and a sufficiently practical strength can be secured. (Creation effect) As described above, the thickness, hardness, and surface roughness of the nickel plating layer formed in the terminal portion of the wiring pattern are adjusted, and the relationship of the bonding strength of the metal wire can be improved, and the thickness of the gold plating layer is reduced to the past. 7~1· 3 microns to 326, total file\91\91114598\TF968021 16

下但可發揮能夠確保屈AA 【圖式簡單說明】’、°勺金屬線接合強度的效果。 圖1是顯示有關本創作 每 美柄夕 只知形態之電子零件安裝用 基板之一例之概略俯視圖。 用 圖 2(a)、Cb")县!s -各 株容壯田甘)疋顯不有關本創作之一實施形態之電子零 衣:基板之-例之概略剖視圖。 圖3疋顯示對有關本創作之一實施形態之電子零件安裝 _用基板上安裝電子零件之狀態之一例之概略剖視圖。 圖4疋顯示有關本創作之一實施形態之電子零件安裝用 基板與電子零件之金屬線接合強度之測定方法之說明圖。 【主要元件符號說明】 1 絕緣薄膜 2 鏈輪孔 10電子零件安裝用基板 11 絕緣基材 φ 12 配線圖案 13 裝置側連接端子 • 14 外部連接端子 15 開縫 16 焊阻層 17 端子孔 19 黏接劑層 2〇 保護用薄膜 21 導電體箔 326\||if\91\91114598\TF968021 17 M324288 22 鍍鎳層 23 鍍金層 30 1C(電子零件) 31 接合用金屬線 33 封裝樹脂 41 黃金金屬線 42 固定基板 43 鉤However, it is possible to ensure the effect of the joint strength of the metal wire of the AA [simplified description]. Fig. 1 is a schematic plan view showing an example of an electronic component mounting substrate for each of the present inventions. Use Figure 2(a), Cb") County! s - each of the plants, Zhan Zhuang Tian Gan, is an outline of the electronic case of the embodiment of the present invention: a schematic view of the substrate. Fig. 3 is a schematic cross-sectional view showing an example of a state in which an electronic component is mounted on a substrate for mounting an electronic component according to an embodiment of the present invention. Fig. 4 is an explanatory view showing a method of measuring the bonding strength of the metal wires of the electronic component mounting substrate and the electronic component according to the embodiment of the present invention. [Main component symbol description] 1 Insulation film 2 Sprocket hole 10 Electronic component mounting substrate 11 Insulation substrate φ 12 Wiring pattern 13 Device side connection terminal • 14 External connection terminal 15 Slot 16 Solder resist layer 17 Terminal hole 19 Bonding Agent layer 2〇 Protective film 21 Conductor foil 326\||if\91\91114598\TF968021 17 M324288 22 Nickel plating 23 Gold plating 30 1C (electronic parts) 31 Bonding wire 33 Packaging resin 41 Gold wire 42 Fixed substrate 43 hook

326\總檔\91 \91114598\TF968021 18326\总档\91 \91114598\TF968021 18

Claims (1)

M324288 九、申請專利範圍: 1· 一種電子零件安裝用基板,其係具備有絕緣基材;形 成在邊絶緣基材之一方面上所形成之配線圖案;及覆蓋該 配線圖案之端子部除外之表面之焊阻層,並在前述端子部 之表面疊層有鍍鎳層及鍍金層者,其特徵為·· 前述鍍鎳層之厚度在3微米以上而維卡硬度為350以 上;且 前述鍍鎳層之表面粗糙度!^在1〜3微米之範圍;且 前述鍍金層之厚度在〇· 5微米以下。 2·如申請專利範圍第1項之電子零件安裝用基板,其 中,前述鍍金層之厚度在〇· 3微米以下。M324288 IX. Patent application scope: 1. A substrate for mounting electronic parts, which is provided with an insulating substrate; a wiring pattern formed on one side of the insulating substrate; and a terminal portion covering the wiring pattern a solder resist layer on the surface, and a nickel plating layer and a gold plating layer are laminated on the surface of the terminal portion, wherein the nickel plating layer has a thickness of 3 μm or more and a Vicat hardness of 350 or more; and the plating is performed. The surface roughness of the nickel layer is in the range of 1 to 3 μm; and the thickness of the gold plating layer is 〇·5 μm or less. 2. The substrate for mounting an electronic component according to the first aspect of the invention, wherein the thickness of the gold plating layer is 〇·3 μm or less. 326\||it\91\91114598\TF968021326\||it\91\91114598\TF968021
TW096209933U 2001-07-26 2002-07-02 Producing the wiring board TWM324288U (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001225695A JP2003037215A (en) 2001-07-26 2001-07-26 Substrate for packaging electronic component and method for manufacturing the same

Publications (1)

Publication Number Publication Date
TWM324288U true TWM324288U (en) 2007-12-21

Family

ID=19058645

Family Applications (2)

Application Number Title Priority Date Filing Date
TW091114598A TWI299886B (en) 2001-07-26 2002-07-02 Method for Producing the Wiring Board
TW096209933U TWM324288U (en) 2001-07-26 2002-07-02 Producing the wiring board

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW091114598A TWI299886B (en) 2001-07-26 2002-07-02 Method for Producing the Wiring Board

Country Status (3)

Country Link
JP (1) JP2003037215A (en)
KR (1) KR100531223B1 (en)
TW (2) TWI299886B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858475B2 (en) * 2003-06-30 2005-02-22 Intel Corporation Method of forming an integrated circuit substrate
JP5151438B2 (en) * 2007-12-10 2013-02-27 大日本印刷株式会社 Semiconductor device and manufacturing method thereof, and substrate for semiconductor device and manufacturing method thereof
KR101744078B1 (en) * 2016-01-08 2017-06-07 와이엠티 주식회사 Printed circuit board and method for preparing plating printed circuit board

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01251691A (en) * 1987-12-03 1989-10-06 Hitachi Chem Co Ltd Manufacture of wiring board
JPH03173195A (en) * 1989-11-30 1991-07-26 Ibiden Co Ltd Formation of conductor circuit in aluminum nitride substrate
JP3057832B2 (en) * 1991-08-28 2000-07-04 日本電気株式会社 Semiconductor device
US5310965A (en) * 1991-08-28 1994-05-10 Nec Corporation Multi-level wiring structure having an organic interlayer insulating film
US5910644A (en) * 1997-06-11 1999-06-08 International Business Machines Corporation Universal surface finish for DCA, SMT and pad on pad interconnections

Also Published As

Publication number Publication date
JP2003037215A (en) 2003-02-07
TWI299886B (en) 2008-08-11
KR20030010521A (en) 2003-02-05
KR100531223B1 (en) 2005-11-28

Similar Documents

Publication Publication Date Title
TWI358973B (en)
TWI258175B (en) Wiring board, method of manufacturing the same, and semiconductor device
US8146243B2 (en) Method of manufacturing a device incorporated substrate and method of manufacturing a printed circuit board
KR100831514B1 (en) Method for producing flexible printed wiring board and flexible printed wiring board
US7180006B2 (en) Tape substrate and method for fabricating the same
JP2008047655A (en) Wiring substrate and its manufacturing method
TW200805525A (en) Flexible circuit substrate for flip-chip-on-flex applications
JP2006294650A (en) Method of mounting electronic component
TW540260B (en) Substrate for mounting electronic component
JP2004247668A (en) Lamination forming mid wiring member, wiring board, and their manufacturing method
TW200837852A (en) Semiconductor device and manufacturing method thereof
TWI222688B (en) Film carrier tape for mounting electronic part
JP2003243563A (en) Metal wiring board, semiconductor device and its manufacturing method
JP2009277987A (en) Film-carrier tape for mounting electronic component and its manufacturing method, and semiconductor device
TWM324288U (en) Producing the wiring board
TW531818B (en) Resin encapsulated BGA-type semiconductor device
JP3726891B2 (en) Mounting structure of film carrier tape for mounting electronic components and manufacturing method of film carrier tape for mounting electronic components
JP4286965B2 (en) Wiring member manufacturing method
JP3608559B2 (en) Method for manufacturing element-embedded substrate
JP4249328B2 (en) Wiring member manufacturing method
JP4033090B2 (en) Manufacturing method of tape carrier for semiconductor device
JP2006093576A (en) Semiconductor device and its manufacturing method
JP2004087862A (en) Tape carrier for semiconductor device
JP2002208779A (en) Method of forming columnar metal body and conductive structure
JP2003282615A (en) Structure of bump, formation method of bump, semiconductor device and its manufacturing method, and electronic equipment

Legal Events

Date Code Title Description
MM4K Annulment or lapse of a utility model due to non-payment of fees