M260935 捌、新型說明： 【新型所屬之技術領域j 本創作係有關於一種電壓轉換緩衝電路，尤指利用一 CM〇s反相器、一 位準移動正反器以及- N通道MOS電晶體所組成的電壓轉換緩衝電路。 【先前技術】 電壓變換緩衝電路係i電子電路，其用以接收_輸人電壓信號，並 將其電壓位準變換至另-較高電壓位準或另一較低電壓位準後輸出，以便 適用於不同之裝置及/或系統之電源需求，例如，於中央處理單元(cp们和 記憶體之間就需要用到電壓變換緩衝電路。 在許多應用中，輸人電壓信號需要被反相，並將之改變至另一適合的 電壓位準以便適用於另-不同之裝置及/或系統，例如，第—圖所示之習知 電壓變換麟電路，岐-例。第—騎示之職變換緩衝電路係令一漏 反相器1接收-輸人電壓信號，並錢出—被反相的電壓信號到一位準移 動正反$ 2，用以移動此經反相之輸人賴信號之電壓位準。 π參考第圖所不之電壓變換緩衝電路，當輸入端糊為低邏輯位準 時，Ρ通道MQS電晶體M1導通⑽），而Ν通道電晶體呢截止㈣， 這使kCMGS反相ϋ 1之輪出維持在高邏輯位準狀態。所以ν通道廳電晶 體Μ4與Μ6力麟GN與GpF’因此，輸出端丽為—高邏輯轉（即vc⑵。 而田輸入端VIN為向邏輯位準日夺，p通道廳電晶體[截止㈣）， 而N通道MOS電曰曰體M2導通⑽），這使得CM〇s反相器丄之輸出維持在低 M260935 邏輯位準狀態。所以N通道娜電晶龍與M6分別為〇FF與⑽，因此， 輸出端VOUT為一低邏輯位準（即零伏特）。 第-圖之電壓變換緩衝電路之⑽D Pspice暫態分析模擬結果，如第 圖所示，、上升時間Tr(Risetime)為0. 7856US，而下降時間 time)為0. 44編，报鶴地，上升時間遠比下降_還要長。 上升時間遠比下降時間來得長的賴如下·.當輸人輕信號⑽由高 邏輯位準縣傾輯鱗時，⑽“姆丨的輸“由低賴辦轉變為 高邏輯鮮’但由於VCC1(3.3伏特）的電·準不夠高，所以_反相器 1在提供高邏輯辦給辦鶴正㈣2時_輪力較低（因位準移動正 反器2係使用5. 0鱗之電源電壓·)，因此，在位準移動正反器2中正 反器需要-較長的時間才能使得N通道電晶之汲極賴下降至足 以使P通道電晶體廳導通⑽），於是，連帶使得p通道電晶體奶由截止 (OFF)狀雜變鱗聊__，絲，輸㈣壓賊丽由低邏 輯位準轉變為高邏輯位準的上升時間拉長。 而s輸入電壓b虎VIN由低邏輯位準轉變為高邏輯位準時，VCC1的電 壓位準不夠高雖會使得N通道M0S電晶體M6之沒極電壓下降至足以使p通 道電晶體M3導通⑽)的時間拉長，但由於該N通道電晶體M6之問極 係直接連接至輸人龍親谓，耐如±述之輸出電廳號上升期間般， 需經- CMOS反相器1反相、延遲方輸入至N通道電晶龍之間極， 並俟N通道M0S電晶體M4之沒極電壓下降至足以使p通道電晶體㈣通 (ON)後’才可使輸出電壓信號由由低邏輯位準轉變為高邏輯位準，與輸出 M260935 間所經過的電晶體數較 電廢信號上升綱相比較，輸出輕信號下降期 少，所以，下降時間會小於上升時間。 對於許多應用而言’上述之上升時間高於下降時間係不欲見到的，由 於輸出電壓信號丽由低邏輯位準轉變為高邏輯位準的上升時間拉長，在 高速操作的環境下，將使得電壓變換緩衝電路動作本身無法發揮其作用。 為了解決上述問題’另—先前技藝（即中華民國專利申請案號第 87121232號專利案)被提出，其係、由—⑽反相器1、-位準移動正反器 2以及一延遲驅動器3所組成，如第三圖所示。其中，當輸入端谓為高 邏輯位準時，P通道職電晶體M1截止㈣)且N通道_晶顏導通 ⑽）使UOS反相@ 1之輸出維持在—低邏輯位準。所以n通道_ 電晶體M4與M6分別為輕娜而p通道電晶體M3與廳分別為 ON ,、OFF ’至於新增之p通道M〇s電晶體M7與鼎則分別處於響與⑽ 之狀態’ S此’輸㈣齡號聰為—低邏輯辦_零伏特）。當輸 入端⑽為低邏輯位準時’ p通道_電晶體祖導通㈣且n通道職田電 晶體M2截止(0FF)，使得⑽s反相器】之輸出維持在一高邏輯位準。所 以N通道m〇S電晶體M4與M6分別為〇N與〇FF，而p通道船s電晶體脱 與M5刀別為0FF與〇N，至於新增之p通道_電晶體取與腿則分別處 於ON與OFF之狀態，因此，輸出端丽為一高邏輯位準（亦即％⑵。 簡。之’經由輸入端VIN供應之輸入電壓信號(其電麼擺幅介於例如 伏特之VCC1與零伏特之間)被CM〇s反相器i施以反相，並將反相的資 料4 5虎藉由位準移動正反器2而移動至另一電磨位準後，輸出於輪出端 M260935 VOUT(其電壓擺幅被移動至例如5. 0伏特之VCC2與零伏特之間）。 睛再參考第三圖，當輸入端VIN之一輸入電壓信號由高邏輯位準變為 低邏輯位準時，p通道M0S電晶體Ml為ON，且n通道M0S電晶體M2與M6 均為OFF。所以，P通道M0S電晶體Ml將N通道M0S電晶體M4之閘極拉升 至高邏輯位準，以開啟N通道M0S電晶體财，接著並開啟p通道M〇s電晶 體M5與M7。此時，因所有的P通道M0S電晶體M5、M7、M8同時為ON， 所以，結合來自P通道M0S電晶體M5之驅動電流以及來自p通道m〇S電晶 體M7與M8之驅動電流會將輸出端V0UT較快速地拉升至高邏輯位準。然 後，輸出端V0UT之咼邏輯位準的輸出電壓信號經由延遲區塊4傳送後，關 P才 1 P通道M0S電晶體M8。所以’輸出端νουτ可根據在輸入端由低邏輯 位準變化至高賴位準_變信號，將輸出縣信號較快速地從低邏輯位 準提升至高邏輯位準。 雖說第三圖之先前技藝，於輸出電壓信號上升期間，可較快速地將輸 出端V0UT之輸出電壓信號由低邏輯位準轉換為高邏輯辦，但其結構複雜 (使用了延遲區塊4以及兩個新增之P通道M〇s電晶體M7及卿，並且因為 輸入端VIN之信號需經由N通道M〇s電晶體呢及M4之延遲後，才能使新 增之P通道電晶體阶導通，因此，在縮短上升時間方面仍有改月良匕空間 存在。 ^ 有鑑於此，權韻酬彻變換緩衝電 路，其不但能進-步縮短上升時間，並且兼具電路結構簡單、佔 面積小等多重功效。 曰曰^ M260935 本創作之次要目的係提出—種不需使_延遲電路之新穎架構之電廢 變換緩衝電路。 【新型内容】 本創作提出-贿齡構之顏變換缓衝電路，其包括—⑽反相器 卜位準移動正反器2以及- n通道·電晶體M1〇，其中該⑽反相器 1係由P通道MOS電晶體M1以及N通道電晶體M2所組成，並連接在第 -電源電壓VCC1與接地之間，該位準移動正反器2係由p通道船§電晶體 M3與M5以及N通道MGS電晶體M4與M6所組成，並連接在第二電源電壓 VCC2與接地之f曰1，而該N通道M〇s電晶體_係連接在第二電源電壓體 與輸出端丽之間，且制細轉收著由該⑽s反相器丨所輸出之反 相的輸入電壓信號。由於本創作於輸出電麼信號上升期間，輸入端之 輸入電壓信號僅需經由N通道MOS電晶體M2之延遲，即可使N通道M0S電 晶體M1G導通，因此，不但可較先前技藝具有更短之上升時間，並且因為 不需使用到延遲電路’因而也可有效簡化電路結構；此外，㈣道腿電晶 體M10亦可視情况调整其通道寬度（channei㈣也）w和零偏壓臨限電壓 (Zero-bias threshold voltage) Vt0之值，以改變或增加其驅動能力。 【實施方式】 根據上述之目的，本創作提出一種電壓變換緩衝電路，如第四圖所示， 其係由-CMOS反相器卜-位準移動器正反器2以及一 N通道腿電晶體 M260935 M10所組成。該CMOS反相器H系由一第一 PM0S電晶體M1以及一第一廳 電晶體M2所組成，其中，該第一 PM0S電晶體組之源極連接至第一電源電 壓vcc卜閘極連接至輸入端谓，而汲極則與第一職電晶體M2之没極 相連接；而該第-NM0S電晶體M2之源極接地，間極連接至輸入端，而 汲極則與第一 PM0S電晶體Ml之汲極相連接。 該位準移動正反器2係由第二PM0S電晶體M3、第二娜電晶體M、 第三PMGS電晶龍以及第三臓電晶體M6驗成，其巾，該第二臓 電晶體M3之源極連接至第二電源電壓·，閘極與第三職電晶體腿之 汲極相連接，錢_触端丽，祕鄉二職電· M4之祕相 連接並連接到第三臓電晶體M5之_ ;該第二麵M4之_ 接地，問極連接到該CM0S反相器i之輸出端，·極則與第二臓電晶 體M3之没極相接並連接到第三臓電晶體廳之閑極；該第三臓電晶 體M5之源極連接至第：電源電壓VCC2，閘極與第二顺〇s電晶舰之沒極 相連接並連接第—BIOS電晶體M3之没極，而沒極則與第三廳電晶體觀 之沒極相賴，錢接出端丽；_第三醜電晶顏之源極接 地，閘極接到輸入端VIN，沒極與第三簡s電晶體廳找極相接並連接至 輸出端V0UT。 〇月參考第四®本創作於第二電源電壓VCC2與輸出端腳τ之間增設 有- Ν通道M0S電晶體MU)，且其問極用以接收由該⑽反相器i所輸出 之反相的輸入電壓信號，因此’於輸出電壓信號上升期間，輸入端之 輸入電壓信號僅需經由N通道廳電晶體M2之延遲，即可先令n通道_ M260935 電晶體M10導通，並對輸出端V0UT充電。結果，可較先前技藝具有更短之 上升時間，並且可視情況調整該Ν通道M0S電晶體Ml0之通道寬度（channe^ width) W 和零偏壓臨限電壓（zero-bias threshold voltage) Vto 之值， 以改變或增加其驅動能力，進而改變或進一步縮短上升時間。 凊再參考第四圖，當輸入端VIN為高邏輯位準時，第一 pM〇s電晶體齟 截止(OFF)，而第一 NM0S電晶體M2導通(ON)，使得CMOS反相器1之輸出 維持在低賴位準狀態，所以第二與第三N通道電晶體M4與廳分別 為OFF與ON，而第二與第三p通道廳電晶體M3與M5分別為〇N與〇ff， 至於新增狀N通道MGS電晶體M1G職於GFF狀態，因此，輸出端職 為邏輯低位準（即零伏特）。 當輸入端VIN為低邏輯位準時，第一臟f晶體m導通⑽，而第 - _S電晶體M2截止_，使得⑽反補丨之輸峰持在高邏輯位 準狀心所以第一與第二N通道廳電晶體M4與分別為ON與卿，而 第一與第二P通道M〇s電晶體M3與M5分別為響與⑽，至於新增設之N 通道廳電晶體M1_乃處於〇FF狀態(該新增設之n通道·電晶麵 於CM〇S反相器1之輸出上升至該N通道隨電晶體_之臨限電壓 (eshold voltage)時開始導通，而於輸出端之電壓上升至第二電 源電壓TO2扣抵-該N通道MGS電晶義之臨限電壓後截止），因此， 輸出端丽為-高邏輯位準（亦即第二電源電壓體）。 而田輸入知VIN由高邏輯位準轉變為低邏輯位準時，第一臓電晶體 為導N)第_s電晶體脱為截止_)，使得圖反相器1之 M260935 輸出由低祕位準狀轉變為高糖鱗狀g，t該⑽s反撼丨之輸出 上升至N通道MOS電晶_〇之臨限電壓時，該N通道·電晶體刪開 始導通，於是可提早對輸出端丽進行充電動作，此時由於第二難電 晶體M4亦為導通⑽），因而可將該第二臓電晶體财之赌電壓往下拉， 俟該第二NMOS電晶體M4之沒極電壓下拉至第二電源電壓VCC2扣抵一第三 P通道MOS電晶體M5之臨限電壓的絕對值時’該第三p通道電晶體奶 開始導通’於是可藉雙電流路徑(一為來自N通道_電晶體削之電流路 徑，另-為來自第三P通道廳電晶體M5之電流路徑），快速拉升輸出端 丽之電壓’虽輸出端ν〇υτ之電壓快速上升至第二電源電壓順扣抵一 該Ν通道·電晶體_之臨限電壓後，該Ν通道·電晶體_隨即截 夺剩下來自第二ρ通道電晶體JJ5之電流路徑，將輸出端νουτ 之電壓上拉至第二電源電壓VCC2。 由上述之刀析可知，於輸出端丽之輸出電壓信號上升期間，輸入端 輸電壓仏號僅需經由第一 Ν通道mqs電晶體m2之延遲，即可使增 叹之Ν通道MOS電晶體隐〇導通，並且可藉雙電流路徑（一為來自ν通道舰 電曰曰體M10之電流路徑，另一為來自第三P通道MOS電晶體M5之電流路 D來决速拉升輪出端丽之電壓，因此，可較先前技藝具有更短之上 升時間’並且因為輪出電壓信號上升至第二電源電壓VCC2扣抵-該N通道 MOS電4M1G之臨限電壓後，即自動關閉該n通道腿電晶體削，因而 i不U延遲電路’所以亦可有效簡化電路結構。此外，N通道職電晶 體M10亦可視障况調整其通道寬度（㈤聰1 width) w和零偏壓臨限電壓 12 M260935 (Zero-bias threshold voltage) Vto之值，以改變或增加其驅動能力，進 而改變或進一步縮短該上升時間。 本創作所提出之電壓變換緩衝電路之〇rCAD PSpice暫態分模擬結果如 第五圖所示。第五圖係以level 3模型並使用〇· 35微米CM〇s製程參數加 以模擬（其PM0S電晶體和NM0S電晶體之零偏壓臨限電壓vTG分別為—iv和 IV)，且電源供應電壓VCC1等於3· 3伏特、VCC2等於5伏特，pm〇S電晶 體Ml、M3、M5之通道寬長比均為（2*〇_ 35μηι/0· 35μηι)，NM0S電晶體M2、 Μ4、Μ6之通道寬長比為（〇· 35μιη/0· 35μπ〇，而NM0S電晶體Μ10之通道寬長 比為（24*0· 35卿/0· 35Mm)、Ν通道M0S電晶體Μ10之零偏壓臨限電壓Vt〇 為0· 65伏特。由第五圖之結果可知，本創作之上升時間伃（以纪乜脈）為 0· 384us，而下降時間Tf (Fall time)為〇· 433US，很明顯地，可有效解 決先前技藝上升時間不夠快之問題。此外，亦可視情況調整N通道電 晶體M10之通道寬度（Channel width) W和零偏壓臨限電壓(Zer〇—bias threshold voltage) Vto之值，以使上升時間Tr等於下降時間Tf。 【創作功效】 本創作所提出之電壓變換緩衝電路，具有如下功效： (1)可有效縮短上升時間：由於本創作於輸出端贿之輸出㈣信號上升 期間，輸入端谓之輸入電壓信號僅需經由第一 N通道腦電晶體M2 之延遲，即可使增設之N通道MOS t晶體_導通，並且可藉雙電流 路徑(-為來自N通道_電晶體刚之電流路徑，另一為來自第三p 通道廳電晶體M5之電流路徑），來快速拉升輸出端丽之電壓，因 此，可有效縮短上升時間； 13 M260935 (2)利於裝置之小魏4於本解所提出之電顧換緩衝電路僅使用了3 個麵電晶體以及4個臓電晶體，並且不需設置延遲電路，因此不但 電路結構簡單、佔用的晶片面積小，並且也有利於裝置之小塑化。 作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術 之人士可膽任何形式或是細節上可能的變化均未脫離本創作的精神與範 圍。因此’所有相關技術料内之改變都包括在本創作之申請專利範圍内。 M260935 【圖式簡單說明】 第一圖係顯示先前技藝一之電壓變換缓衝電路圖。 第二圖係顯示第一圖電壓變換緩衝電路之輸入電壓信號及輸出電壓信號之 暫態分析時序圖。 第三圖係顯示先前技藝二之電壓變換緩衝電路圖。 第四圖係顯示本創作之電壓變換緩衝電路圖。 第五圖係顯示第四圖電壓變換緩衝電路之輸入電壓信號及輸出電壓信號之 暫態分析時序圖。 [元件符號說明] 1 CMOS反相器 2 位準移動正反器 3 延遲驅動器 4 延遲區塊 VIN 輸入端 V0UT 輸出端 VCC1 第一電源電壓 VCC2 第二電源電壓 Ml 第一 PM0S電晶體 M2 第一 NM0S電晶體 M3 第二PM0S電晶體 M4 第二丽0S電晶體 M5 第三PM0S電晶體 M6 第三NM0S電晶體 M7 P通道M0S電晶體 M8 P通道M0S電晶體M8 M10 NM0S電晶體 15M260935 新型 Description of the new type: [Technical field to which the new type belongs] This creation relates to a voltage conversion buffer circuit, especially using a CMOS inverter, a quasi-moving flip-flop and-N-channel MOS transistor Composition of the voltage conversion buffer circuit. [Prior art] The voltage conversion buffer circuit is an electronic circuit, which is used to receive and input a voltage signal and convert its voltage level to another-a higher voltage level or another lower voltage level and output it so that It is suitable for the power requirements of different devices and / or systems, for example, a voltage conversion buffer circuit is needed between the central processing unit (cps and memory). In many applications, the input voltage signal needs to be inverted. And change it to another suitable voltage level so as to be suitable for another-different device and / or system, for example, the conventional voltage conversion circuit shown in Fig. 1-Qi. The conversion buffer circuit is to make a leaking inverter 1 receive-input the voltage signal and save it-the inverted voltage signal to a quasi-moving positive and negative $ 2 to move this inverted input signal Refer to the voltage conversion buffer circuit shown in the figure. When the input terminal paste is at a low logic level, the P-channel MQS transistor M1 is turned on, and the N-channel transistor is turned off. This makes kCMGS inverse. Phase 1 Round 1 is maintained at high logic Quasi-state. Therefore, the ν channel hall transistors M4 and M6, Lilin GN and GpF ', therefore, the output terminal is-high logic transition (ie vc⑵.) And the input VIN of the field is to the logic level, and the p channel hall transistor [cut off] While the N-channel MOS circuit is turned on (the body M2 is turned on), this keeps the output of the CMOS inverter V at a low M260935 logic level. Therefore, N-channel Nanopower Crystal M6 and M6 are 0FF and 分别, respectively. Therefore, the output VOUT is a low logic level (ie, zero volts). Figure-The voltage conversion buffer circuit ⑽D Pspice transient analysis simulation results, as shown in the figure, the rise time Tr (Risetime) is 0.7856US, and the fall time time is 0.44 series, reported to Hedi, The rise time is much longer than the fall. The rise time is much longer than the fall time. When the light signal of the loser is shifted from a high logic level to a county, the "Mu's loss" is changed from a low-level office to a high-level logic, but due to VCC1 (3.3 volts) electricity is not high enough, so _inverter 1 when providing high logic to the crane crane ㈣2 _ wheel force is low (because the level moves the flip inverter 2 uses 5.0 scale power supply Voltage ·), so the flip-flop in the level-moving flip-flop 2 takes a longer time to make the drain of the N-channel transistor drop enough to make the P-channel transistor hall conductive ⑽), so, together As a result, the rise time of the p-channel transistor milk from the OFF state to the low-level logic level is changed from a low logic level to a high logic level. When the s input voltage b tiger VIN changes from a low logic level to a high logic level, the voltage level of VCC1 is not high enough to cause the infinite voltage of the N-channel M0S transistor M6 to drop enough to make the p-channel transistor M3 turn on. ) Time is long, but because the N-channel transistor M6 is directly connected to the input of the dragon, it is resistant to the inverse phase of the output electric hall number as described above, which needs to be inverted by-CMOS inverter 1 The delay side is input to the N-channel transistor, and the voltage of the N-channel M0S transistor M4 is not reduced enough to make the p-channel transistor ON. The logic level changes to a high logic level. Compared with the number of transistors that pass through the output M260935, the output light signal has a lower falling period than the rising level of the electrical waste signal. Therefore, the falling time will be shorter than the rising time. For many applications, the above-mentioned rise time is higher than the fall time, which is undesirable. Because the output voltage signal rises from a low logic level to a high logic level, the rise time is prolonged. In a high-speed operation environment, Will make the voltage conversion buffer circuit operation itself can not play its role. In order to solve the above-mentioned problem, another prior art (i.e., the Republic of China Patent Application No. 87121232) was proposed, which is composed of a ⑽-inverter 1, a level-shifting flip-flop 2 and a delay driver 3 The composition is shown in the third figure. Among them, when the input terminal is said to be at a high logic level, the P channel transistor M1 is turned off ㈣) and the N channel _ crystal face is turned on ⑽) The output of the UOS inversion @ 1 is maintained at a low logic level. Therefore, the n-channel transistor M4 and M6 are light and the p-channel transistor M3 and hall are ON and OFF respectively. As for the newly-added p-channel M0s transistor M7 and Ding, they are in a state of resounding and cricket respectively. 'S 此' loses the age number Satoshi-low logic office _ zero volts). When the input terminal is at a low logic level, the p-channel_transistor ancestor is turned on and the n-channel professional field transistor M2 is turned off (0FF), so that the output of the “s inverter” is maintained at a high logic level. Therefore, the N-channel m0S transistors M4 and M6 are 0N and 0FF respectively, while the p-channel boat transistor is disconnected from M5 and the cutoff is 0FF and 0N. As for the newly added p-channel_transistor, the leg is The states are ON and OFF respectively. Therefore, the output terminal is at a high logic level (ie,% ⑵.). The input voltage signal supplied by the input terminal VIN (whose voltage swing is between VCC1 and (Between zero volts) is inverted by the CM0s inverter i, and the inverted data 4 5 is moved to another electric grinding level by moving the flip-flop 2 to the level, and then output to the wheel The output M260935 VOUT (its voltage swing is moved to between VCC2 and zero volts, such as 5.0 volts.) Referring again to the third figure, when one of the input terminal VIN input voltage signal changes from high logic level to low At logic level, p-channel M0S transistor M1 is ON, and n-channel M0S transistor M2 and M6 are both OFF. Therefore, P-channel M0S transistor M1 pulls the gate of N-channel M0S transistor M4 to a high logic level To turn on the N-channel M0S transistors, and then turn on the p-channel M0s transistors M5 and M7. At this time, because all the P-channel M0S transistors M5, M 7. M8 is ON at the same time. Therefore, combining the drive current from the P-channel M0S transistor M5 and the p-channel m0S transistor M7 and M8 will drive the output V0UT to a higher logic level faster. Then, after the output voltage signal of the logic level of the output terminal V0UT is transmitted through the delay block 4, the P channel is turned off and the P channel M0S transistor M8 is turned off. Therefore, the output terminal νουτ can be changed from low logic level to high according to the input terminal. Relying on the level_change signal, the output county signal can be quickly raised from a low logic level to a high logic level. Although the prior art of the third figure, during the rise of the output voltage signal, the output of the output terminal V0UT can be faster The voltage signal is converted from a low logic level to a high logic office, but its structure is complicated (using the delay block 4 and two new P-channel M0s transistors M7 and Q8, and because the signal at the input VIN needs to pass After the N-channel M0s transistor and M4 delay, the newly added P-channel transistor stage can be turned on, so there is still room for improvement in terms of shortening the rise time. ^ In view of this, Quan Yunyu Thorough transition Circuit, which can not only further shorten the rise time, but also have multiple functions such as simple circuit structure and small area. Yue ^ M260935 The secondary purpose of this creation is to propose a novel architecture without the need to use a delay circuit. Electrical waste conversion buffer circuit. [New content] This creation proposes a bridging structure of the face conversion buffer circuit, which includes-an inverter, a level-shifting flip-flop 2 and-n-channel · transistor M1〇, of which The unitary inverter 1 is composed of a P-channel MOS transistor M1 and an N-channel transistor M2, and is connected between the -th power supply voltage VCC1 and the ground. The level moving flip-flop 2 is a p-channel ship§ The transistors M3 and M5 and the N-channel MGS transistors M4 and M6 are connected to the second power supply voltage VCC2 and the ground f is 1. The N-channel M0s transistor is connected to the second power voltage body. And the output terminal Li, and the system receives the inverted input voltage signal output by the ⑽s inverter. Since this creation is during the rise of the output electrical signal, the input voltage signal at the input terminal only needs to pass through the delay of the N-channel MOS transistor M2, so that the N-channel M0S transistor M1G can be turned on. Therefore, it can be shorter than the previous technology. The rise time of the circuit can also be simplified because no delay circuit is needed. In addition, the transistor M10 can also adjust its channel width (channei㈣) w and zero bias threshold voltage (Zero) -bias threshold voltage) Vt0 to change or increase its driving capability. [Embodiment] According to the above purpose, the present invention proposes a voltage conversion buffer circuit, as shown in the fourth figure, which is composed of a -CMOS inverter, a level shifter flip-flop 2 and an N-channel leg transistor. M260935 M10. The CMOS inverter H is composed of a first PM0S transistor M1 and a first hall transistor M2, wherein the source of the first PM0S transistor group is connected to the first power voltage vcc and the gate is connected to The input terminal is called, and the drain is connected to the non-pole of the first transistor M2; the source of the -NM0S transistor M2 is grounded, the middle is connected to the input, and the drain is connected to the first PM0S. The drain of the crystal M1 is connected. This level mobile flip-flop 2 is verified by the second PM0S transistor M3, the second nano transistor M, the third PMGS transistor, and the third unitary transistor M6. The second unitary transistor M3 The source is connected to the second power supply voltage. The gate is connected to the drain of the third transistor's leg. Qian_Tianli, Mixiang's second transistor · M4 is connected to the third transistor. The _ of M5; the _ of the second surface M4 is connected to the ground, and the interrogation pole is connected to the output terminal of the CM0S inverter i; Hall electrode; the source of the third transistor M5 is connected to the first: power supply voltage VCC2, the gate is connected to the second electrode of the second transistor 0s and connected to the first electrode of the BIOS transistor M3 , While the pole is related to the third hall transistor view, the money is connected to Duanli; _ the third ugly electricity crystal face the source is grounded, the gate is connected to the input terminal VIN, the pole and the third The transistor hall is connected to the pole and connected to the output terminal V0UT. 〇Refer to the fourth article. This article adds-N channel M0S transistor MU) between the second power supply voltage VCC2 and the output terminal τ), and its question pole is used to receive the inverse output from the ⑽ inverter i. Phase input voltage signal, so during the rise of the output voltage signal, the input voltage signal at the input terminal only needs to pass through the delay of the N-channel hall transistor M2, and then the n-channel _ M260935 transistor M10 can be turned on, and the output terminal V0UT is charged. As a result, it can have a shorter rise time than the previous technology, and the channel width (channe ^ width) W and zero-bias threshold voltage Vto of the N-channel M0S transistor M10 can be adjusted as appropriate. In order to change or increase its driving ability, and then change or further shorten the rise time.凊 Refer to the fourth figure again. When the input terminal VIN is at a high logic level, the first pM0s transistor is turned off, and the first NMOS transistor M2 is turned on, so that the output of CMOS inverter 1 is turned on. Maintained at a low level, so the second and third N-channel transistors M4 and Hall are OFF and ON, and the second and third p-channel transistors M3 and M5 are ON and 0ff, respectively. The newly added N-channel MGS transistor M1G is in the GFF state, so the output is at a logic low level (ie, zero volts). When the input terminal VIN is at a low logic level, the first dirty f crystal m is turned on, and the -S transistor M2 is turned off, so that the output peak of the complement is held at the center of the high logic level, so the first and the first The two N-channel hall transistors M4 and ON and Q are respectively, while the first and second P-channel M0s transistors M3 and M5 are ring and 分别 respectively. As for the newly-added N-channel hall transistor M1_, it is at 〇FF state (the newly added n-channel · transistor plane starts to conduct when the output of CM0S inverter 1 rises to the N-channel with eshold voltage of transistor_, and at the output end The voltage rises to the second power supply voltage TO2 to withstand-the threshold voltage of the N-channel MGS transistor is cut off). Therefore, the output terminal is at a high logic level (that is, the second power supply voltage body). When Tian input knows that VIN changes from a high logic level to a low logic level, the first transistor is turned on N) The _s transistor is turned off_), so that the output of M260935 in the inverter 1 from the low level The quasi-shape changes to a high-glycan scale g. When the output of the ⑽s rises to the threshold voltage of the N-channel MOS transistor _0, the N-channel transistor is turned on, so the output terminal can be performed early. Charging action, because the second transistor M4 is also turned on at this time, so the betting voltage of the second transistor can be pulled down, and the non-polar voltage of the second NMOS transistor M4 is pulled down to the second When the power supply voltage VCC2 is deducted from the absolute value of the threshold voltage of a third P-channel MOS transistor M5, 'the third p-channel transistor starts to conduct', so a dual current path (one from the N-channel_transistor cut The current path of the other, is the current path from the third P channel Hall transistor M5), the voltage at the output terminal Li is quickly raised, although the voltage at the output terminal ν〇υτ quickly rises to the second power supply voltage, which is offset by one After the threshold voltage of the channel · transistor_, the N channel · transistor_ The current path from the second p-channel transistor JJ5 is intercepted, and the voltage at the output terminal νουτ is pulled up to the second power supply voltage VCC2. From the above analysis, it can be known that during the rise of the output voltage signal of the output terminal, the input voltage input signal only needs to pass through the delay of the first N channel mqs transistor m2, so that the increased N channel MOS transistor can be hidden. It is on, and can use the dual current path (one is the current path from the ν channel ship electric body M10, and the other is the current path D from the third P channel MOS transistor M5 to determine the speed of the pull-up wheel. Therefore, it can have a shorter rise time than the previous technique, and because the wheel-out voltage signal rises to the second power supply voltage VCC2 and is deducted-after the threshold voltage of the N-channel MOS power 4M1G, the n-channel leg power is automatically turned off. The crystal is cut, so I do not delay the circuit, so it can effectively simplify the circuit structure. In addition, the N-channel professional transistor M10 can also adjust its channel width (宽度 聪 1 width) w and zero bias threshold voltage 12 M260935 depending on the obstacle. (Zero-bias threshold voltage) The value of Vto in order to change or increase its driving ability, and then change or further shorten the rise time. The rCAD PSpice transient branch simulation of the voltage conversion buffer circuit proposed in this creation. The results are shown in the fifth figure. The fifth figure is modeled using a level 3 model and using 0.35 micron CMOS process parameters (the zero bias threshold voltages vTG of the PM0S transistor and the NM0S transistor are −iv And IV), and the power supply voltage VCC1 is equal to 3.3 volts and VCC2 is equal to 5 volts. The channel width-to-length ratios of the pMOS transistors M1, M3, and M5 are all (2 * 〇_ 35μηι / 0 · 35μηι), NM0S. The channel width-to-length ratio of the transistors M2, M4, and M6 is (0.35μm / 0 · 35μπ〇, while the channel width-to-length ratio of the NM0S transistor M10 is (24 * 0 · 35nm / 0 · 35Mm), and the N channel M0S The threshold voltage Vt0 of the zero bias voltage of the transistor M10 is 0.65 volts. From the results of the fifth figure, it can be seen that the rise time 伃 (in the case of the Ji pulse) of this creation is 0 384us, and the fall time Tf (Fall time ) Is 433US, obviously, it can effectively solve the problem that the rise time of the previous technology is not fast enough. In addition, the channel width W of the N-channel transistor M10 and the zero bias threshold voltage (Zer) can be adjusted according to the situation. 〇—bias threshold voltage) The value of Vto, so that the rise time Tr is equal to the fall time Tf. [Creative effect] The voltage conversion buffer circuit proposed by this creation has the following effects: (1) It can effectively reduce the rise time: Since this creation is at the output of the output terminal, the input voltage signal only needs to pass through the first N The delay of the channel EEG crystal M2 can make the additional N channel MOS t crystal _ conductive, and can use the dual current path (-is the current path from the N channel _ transistor just, the other is from the third p channel hall The current path of transistor M5) is used to quickly increase the voltage at the output terminal, so it can effectively shorten the rise time; 13 M260935 (2) Xiaowei 4 which is beneficial to the device. Three surface transistors and four pseudotransistors do not need to be provided with a delay circuit. Therefore, not only the circuit structure is simple, the occupied area of the chip is small, but also the plasticization of the device is facilitated. The specific preferred embodiment is specifically disclosed and described, but anyone skilled in the art can take any form or detail of the possible changes without departing from the spirit and scope of this creation. Therefore, all the changes in the relevant technical materials are included in the scope of the patent application for this creation. M260935 [Schematic description] The first diagram is a circuit diagram of the voltage conversion buffer circuit of the previous technology 1. The second diagram is a timing chart of the transient analysis of the input voltage signal and the output voltage signal of the voltage conversion buffer circuit of the first diagram. The third diagram is a circuit diagram of the voltage conversion buffer circuit of the prior art 2. The fourth diagram is a circuit diagram of the voltage conversion buffer of this creation. The fifth diagram is a timing chart showing the transient analysis of the input voltage signal and the output voltage signal of the voltage conversion buffer circuit of the fourth diagram. [Explanation of component symbols] 1 CMOS inverter 2 quasi-moving flip-flop 3 delay driver 4 delay block VIN input terminal V0UT output terminal VCC1 first power voltage VCC2 second power voltage Ml first PM0S transistor M2 first NMOS Transistor M3 Second PM0S transistor M4 Second Li 0S transistor M5 Third PM0S transistor M6 Third NM0S transistor M7 P channel M0S transistor M8 P channel M0S transistor M8 M10 NM0S transistor 15