JP2001085977A - Interface circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an LVDS interface circuit where even a delay in one of differential input signals from the other causes no difference in amplitude of output differential signals. SOLUTION: The interface circuit 10 is provided with a 1st current switching circuit consisting of transistors(TRs) Qp1, Qn1 that selects a 1st current source Qpa or a 2nd current source Qna for the connection to a 1st output terminal 4 in response to a 1st input signal IN1 and with a 2nd current switching circuit consisting of TRs Qp2, Qn2 that selects the 1st current source Qpa or the 2nd current source Qna for the connection to a 2nd output terminal 5 in response to a 2nd input signal IN2, and receives signals inverted too each other as the 1st and 2nd input signals IN1, IN2 and outputs differential signals. The interface circuit 10 is also provided with a 3rd current switching circuit consisting of TRs Qp3, Qn3 that selects the 1st current source Qpa or the 2nd current source Qna for the connection to a dummy capacitor 12 in response to a 1st input signal Sg1 and the dummy capacitor 12 whoe one terminal is connected to a constant level point.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique useful when applied to, for example, an interface circuit for outputting a low-voltage differential signal at high speed, and more particularly to a semiconductor integrated circuit in which such an interface circuit is formed by CMOS. Related to useful technology.

[0002]

2. Description of the Related Art An LSI for high-speed communication equipped with a PLL (Phase Lock Loop) circuit and an LSI with a built-in high-speed interface equipped with a multiplexer, a demultiplexer, and the like.
In such cases, LVDS (Low Voltage Differential S)
ignals) An interface circuit may be mounted. The LVDS interface circuit is a high-speed interface circuit that converts a high-frequency output signal output from the PLL circuit, the multiplexer, and the demultiplexer into a low-voltage differential signal and outputs the signal.

FIG. 4 is a circuit diagram showing an example in which a simple communication system is configured using an LVDS interface model circuit.

A model circuit 10 of the LVDS interface shown in FIG. 4 includes a MOSFET Qpa as a first constant current source for supplying a constant current, and a MOSFET as a second constant current source for similarly drawing a constant current to the ground.
Qna, positive-phase-side output drive MOSFETs Qp1 and Qn that drive the load of output terminal 4 according to input signal IN1
1. Negative-phase output drive MOSF that drives the load of output terminal 5 in response to input signal IN2 having a phase opposite to that of input signal IN1.
ET Qp2, Qn2, and impedance matching terminating resistor R1 connected between output terminals 4 and 5.

According to such an LVDS interface circuit 10, ideally, two input signals IN1 and IN2 of a positive phase and a negative phase are simultaneously inputted, so that the first and second output terminals 5 is switched from the first constant current source Qpa to the second constant current source Qna or from the second constant current source Qna to the first constant current source Qpa at the same time, and a desired output offset voltage (center potential) is obtained. Differential signals OUT1 and OUT2 having amplitudes are output to signal lines 6 and 7.

The LVDS interface circuit 10 shown in FIG.
In this example, the input signal is divided into two just before the circuit, one of which is used as the positive-phase input signal IN1 and the other is used as the inverter circuit 2
And the inverted negative-phase input signal IN2. Then, the differential output signal O is output by the interface circuit 10.
UT1 and OUT2 are generated and transmitted through a pair of signal lines 6 and 7, and received by the amplifier 21 of the receiving IC 20.
The signal lines 6 and 7 are equivalently grounded via small-capacity load capacitors (capacitors) 8 and 9. In the receiving IC 20, a terminating resistor R2 for impedance matching is connected between input terminals for receiving differential signals.

[0007]

However, in the communication system using the above-mentioned LVDS interface circuit 10, only one input signal needs to pass through the inverter circuit 2, so that the signal when passing through the inverter circuit 2 is required. Two input signals IN of positive phase and negative phase due to delay
1 and IN2 are input with a time lag, and there is a problem that the positive phase side and the negative phase side become unbalanced.

FIG. 5A shows a positive-phase and a negative-phase input signals IN 1 and IN 1 inputted to the LVDS interface circuit 10.
FIG. 3B is a time chart showing signal waveforms of the differential output signals OUT1 and OUT2 output from the output terminals 4 and 5 of the LVDS interface circuit 10. FIG.

In FIG. 1, τ1 and τ2 are delay times of the input signal IN2 caused by the gate delay of the inverter circuit 2 described above. Then, as shown in FIG. 5B, due to the delay of the negative-phase input signal IN2, the amplitude of one of the differential signals OUT1 and OUT2 output from the output terminals 4 and 5 increases, and the other signal increases. A problem that the amplitude is reduced has occurred.

Such a phenomenon is considered to occur for the following reasons. That is, when the positive-phase input signal IN1 changes from the low level to the high level, the other input signal IN2 remains at the high level due to the delay. During this short period, the MOSF of the positive-phase output drive
ET Qp1 (Fig. 4) changes from ON to OFF, MOSFET
Qn1 is turned on from off, but Mn is
OSFET Qn2 turns on and MOSFET Q
p2 maintains the off state. That is, the connection of only the first output terminal 4 is switched to the second constant current source Qna, and the connection of the second output terminal 5 is not yet switched to the first constant current source Qpa, that is, both the output terminals 4 and 5 are connected. A transient period occurs in which the second constant current source Qna is connected.

In such a state, the first constant current source Qpa
Is not connected to the output terminal 5, the second constant current source Qn
“a” does not draw current from the first constant current source Qpa, but draws charge from the load capacitance 8 of the signal line 6 to greatly lower the voltage of the signal line 6. In other words, during the transition period, the potential OUT1 of the positive-phase output terminal 4 drops more than a predetermined low-level potential. Further, the second constant current source Qna attempts to extract charge from the load capacitance 9 of the negative-phase signal line 7.

Thereafter, the input signal IN2 on the delayed side changes from the high level to the low level, and the MOSFET Qp
When the switch 2 is turned on, the charge of the load capacitor 9 of the negative-phase signal line 7 is extraly extracted, so that the charge of the load capacitor 9 needs to be extra, and the voltage of the output terminal 5 is set to a predetermined high level. It takes extra time to reach the potential. In addition, when the operating frequency is high, the signal is switched before reaching the predetermined high-level potential, so that the potential of the negative-phase output terminal 5 remains lower than the predetermined high-level potential.

That is, as a result of the action during the transition period, as shown in FIG. 5, the positive-phase differential output signal OUT1 changes deeper by ΔV than the negative-phase differential output signal OUT2,
A difference of 2ΔV occurs in the amplitude.

Incidentally, IEEE (Institute of Elect)
rical and Electronics Engineers) P1596.3-
According to the standard of the LVDS interface circuit defined in 1995, the output offset voltage (= the center potential of the amplitude) of the differential output signal is “1125 to 1275 mV”.
In addition, the voltage amplitude of the high level and the low level of the differential output signal is defined as “250 to 400 mV”. However, in the circuit form as shown in FIG. 4 in which the amplitude of the pair of differential output signals OUT1 and OUT2 is different due to the delay of the input signal IN2 on the negative phase side as described above, the IEEE standard is used.
It became clear that there was a problem that the standard could not be met.

[0015] An object of the present invention is that even if one of a positive-phase input signal and a negative-phase input signal is delayed from the other on the input side of the LVDS interface circuit, this delay does not cause a difference in the amplitude of the differential output signal. An object of the present invention is to provide an interface circuit that can be configured as described above.

Another object of the present invention is to provide an LVD capable of satisfying the IEEE standard with respect to the amplitude of the differential output signal.
It is to provide an S interface circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, the first current source for supplying the predetermined current and the second current source for extracting the predetermined current, the first output terminal and the second output terminal, and the connection of the first output terminal according to the input signal are connected to the first current source. A first current switching circuit for switching to either the first current source or the second current source, and a second current switching circuit for switching the connection of the second output terminal to either the first current source or the second current source by a signal having a phase opposite to the input signal. A two-current switching circuit,
A dummy capacitance means having one terminal connected to a constant potential point;
A third current switching circuit for switching the connection of the dummy capacitance means to the first current source or the second current source in accordance with a signal input to the first current switching circuit; While inputting the input signal as it is,
The input signal is inverted and input to the second current switching circuit via the inverter circuit, and the first and second current switching circuits are controlled to output a differential signal from the first and second output terminals. , The third current switching circuit is the first current switching circuit.
When the current switching circuit of (1) connects the first current source to the first output terminal, a part of the current from the first current source flows through the dummy capacitance means, and the first current switching circuit is connected to the second current source. The first
A configuration is such that current is drawn from the dummy capacitance means when connected to the output terminal.

A terminating resistor for impedance matching is connected between the first output terminal and the second output terminal.

More specifically, the first current source and the second current source can be constituted by MOSFETs or resistors having a source terminal connected to the first or second power supply voltage terminal. In the first to third current switching circuits, the first current source may be a source terminal, the corresponding input terminal may be a gate terminal, the corresponding output terminal or the other terminal of the dummy capacitance means may be a drain terminal. Connected p-channel MOS
An FET and an n-channel MOSFET in which the second current source is connected to the source terminal, the corresponding input terminal is connected to the gate terminal, and the corresponding output terminal or the other terminal of the dummy capacitance means is connected to the drain terminal. It can be constituted by a CMOS circuit.

According to the means as described above, even when driven at a high frequency, it is possible to make the difference between the signal amplitudes of the differential signals output from the first and second output terminals hardly occur. I can do it.

The interface circuit is a CMO
Since the interface circuit can be configured by the S circuit, the above-described interface circuit and the internal logic circuit that outputs a signal to the interface circuit can be a semiconductor integrated circuit formed on a single semiconductor substrate by a CMOS circuit. Therefore, a semiconductor integrated circuit having the above-described interface circuit and low overall power consumption can be realized.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram showing an example of a communication system configured using an LVDS interface circuit 10 according to a preferred embodiment of the present invention.

The LVDS interface circuit 10 of this embodiment includes a p-channel MOSFET Qpa as a first constant current source for flowing a constant current from the power supply voltage Vcc, and an n-channel MOSFET as a second constant current source for drawing the constant current to the ground. Qna and the input signal are split into two to leave one input signal IN1 as it is and the other as an inverter circuit 2
And a p-channel MOSFET Qp1 for connecting or disconnecting the output terminal 4 to or from the first constant current source Qpa according to the voltage of the positive-phase input signal IN1 and an output. N-channel MOSFE for connecting / disconnecting terminal 4 to / from second constant current source Qna
A first current switching circuit comprising T Qn1 and an output terminal 5 connected to a first constant current source Qp according to the voltage of the negative-phase input signal IN2.
p-channel MOSFET Qp that connects or disconnects to a
2 and an n-channel MOSFET Qn2 for connecting or disconnecting the output terminal 5 to or from the second constant current source Qna.
A current switching circuit, a capacitor 12 having one terminal connected to a constant potential point such as a ground potential, and a capacitor 12 connected to a first constant current source Qpa in response to an input signal IN1 similarly to the first current switching circuit. P-channel MOSFET to connect or cut off
A third current switching circuit including an n-channel MOSFET Qn3 for connecting or disconnecting the Qp3 and the capacitive element 12 to / from the second constant current source Qna, an output termination resistor R1 for impedance matching, and the like.

Then, the differential amplifier 21 of the receiving IC 20 is connected to the output terminals 4 and 5 of the LVDS interface circuit 10 via a pair of signal lines 6 and 7, so that one signal is output. A communication system is configured that converts the signal into a differential output signal of a predetermined voltage and transmits and receives the signal. Reference numerals 8 and 9 denote wiring capacitances connected to the signal lines 6 and 7, respectively. The receiving IC 20 has input terminals 22 and 2.
3, a terminating resistor R2 is connected, and impedance matching with the signal lines 6, 7 is performed.

The first constant current source and the second constant current source each have a source terminal having a power supply voltage Vc of 2 V to 6.5 V, for example.
p and p-channel MOSF connected to ground potential (0 V)
ETQpa and an n-channel MOSFET Qna.
ef, this reference voltage Vref
The constant current according to the current flows.

The first to third current switching circuits respectively include p-channel MOSFETs Qp1 to Qp3 and n-channel MOSFETs.
It is composed of a CMOS circuit including SFETs Qn1 to Qn3. Specifically, the positive-phase input signal IN1 is input to the gate terminals of the MOSFETs of the first and third current switching circuits, and the inverted negative-phase input signal IN2 is input to the second terminal.
The signal is inputted to the gate terminal of the MOSFET of the current switching circuit. Further, a first constant current source is connected to a common source terminal of all p-channel MOSFETs Qp1 to Qp3 of the first to third current switching circuits, and all n of the first to third current switching circuits are
A second constant current source is connected to a common source terminal of the channel MOSFETs Qn1 to Qn3. The first output terminal 4 is connected to the common drain terminal of both MOSFETs Qp1 and Qn1 of the first current switching circuit,
The second output terminal 5 is connected to the common drain terminal of the SFETs Qp2 and Qn2, and both MOSFETs Qp of the third current switching circuit are connected.
A capacitance element 12 as a dummy capacitance means is connected to the common drain terminal of each of Qn3 and Qn3.

The capacitance element 12 adjusts the level fluctuation of the differential output signal due to the signal delay of the negative-phase input signal IN2 to almost zero. It can be configured using the gate capacitance between the gate electrode of the MOSFET and the substrate.

The capacitance of the capacitive element 12 is, for example,
Delay time τ1 of negative-phase input signal IN2 with respect to positive-phase input signal IN1, MOSFETs of first to third current switching circuits
Transistor size, power supply voltage Vcc, output terminal 4,
Using the capacitances of the load capacitances 8 and 9 on the fifth side as parameters, an optimum value for making the level fluctuation substantially zero can be obtained. For example, in the case of a general LVDS interface circuit conforming to the IEEE standard, a sufficient effect can be obtained even if the capacitance is about the wiring capacitance of the wiring formed on the semiconductor substrate.

Next, the operation of the LVDS interface circuit 10 having the above configuration will be described.

FIG. 2 shows a time chart of each signal of the LVDS interface circuit 10. FIG.
Is the signal waveforms of the positive and negative phase input signals IN1 and IN2,
(B) is a signal waveform of the differential output signals OUT1 and OUT2.

Here, the operation when the positive-phase input signal IN1 changes from a low level to a high level and the operation when the positive-phase input signal IN1 changes from a high level to a low level will be mainly described.

First, when the positive-phase input signal IN1 changes from low level to high level, the negative-phase input signal IN2 changes to high level due to the gate delay τ1 when passing through the inverter circuit 2. Will remain at high level for a while. At this time, the MOSFET Qp1 of the first current switching circuit in FIG. 1 is turned off from on and the MOSFET Qn1 is turned on from off, but in the second current switching circuit, the MOSFET Qn2 is on and the MOSFET Qp2 remains off. . In other words, at this time, only the first output terminal 4 is switched to the connection to the second constant current source Qna, and the second output terminal 5 is connected to the first constant current source Qpa for a period in which the connection has not been switched to the first constant current source Qpa. Both 4 and 5 are connected to the second constant current source Qna, and a transient period occurs in which the first constant current source Qpa is not connected to any of the output terminals 4 and 5.

At this time, the MO of the third current switching circuit
When the SFET Qp3 is turned off from on, the MOSFET Q
When n3 is turned on from off, the connection of the capacitive element 12 is switched from the first constant current source Qpa to the second constant current source Qna. That is, the state is switched to the second constant current source Qna while the capacitance element 12 is charged by the first constant current source Qpa.

In such a state, the following operation occurs. First, since the first constant current source Qpa is not connected anywhere, the second constant current source Qna cannot draw current from the first constant current source Qpa, but the MOSFET Q
Since the MOSFET Qn3 is also turned on at the same time when the n1 is turned on and the capacitive element 12 is connected to the second constant current source Qna, the second constant current source Qna transfers the charge of the load capacitance 8 of the signal line 6 of the first output terminal 4. At the same time, the electric charge of the capacitor 12 is also extracted. As described above, since the charge is also supplied from the capacitor 12, the amount of voltage drop of the signal line 6 is smaller than when the capacitor 12 is not provided, and the desired steady low level potential V
ol. As described above, since the voltage of the signal line 6 does not become lower than the desired steady low-level potential Vol, that is, the potential of the negative-phase signal line 7, the negative-phase signal is supplied by the MOSFET Qn1 which is turned on via the terminating resistor R1. The removal of charge from the load capacitance 9 on the line 7 is avoided.

That is, during the above-mentioned transition period, the electric charge is appropriately released from the capacitive element 12, so that the potential of the first output terminal 4, that is, the output differential signal OUT1 changes more slowly than when the capacitive element 12 is not provided. And the potential is lowered to a desired steady low level potential Vol.

When the positive-phase output differential signal OUT1 reaches the steady low-level potential Vol, the delayed negative-phase input signal IN2 changes from high level to low level, and the second current switching circuit MOSFET Qp2 is turned on. Then, the load capacitance 9 of the negative-phase signal line 7 connected to the second output terminal 5 is charged by the current from the first constant current source Qpa, and is raised to the steady high level potential Voh.
When the steady state is reached, the first constant current source Qp
The current from a flows to the second constant current source Qna via the output terminating resistor R1 and the like, and the potential difference between the signal lines 6 and 7, that is, the amplitude of the output differential signals OUT1 and OUT2 is kept constant.

As described above, in the LVDS interface circuit 10 of FIG. 1, from the timing when the positive-phase input signal starts to change from the low level to the high level, the delayed negative-phase input signal changes from the low level to the high level. By the time the change is completed, the output of the first output terminal 4 is changed from the steady high level to the low level, the output of the second output terminal 5 is changed from the steady low level to the high level, and the amplitudes of both are changed. Does not make a difference in the size of

Next, the case where the positive-phase input signal IN1 changes from the high level to the low level will be described.

When the positive-phase input signal IN1 changes from the high level to the low level, the negative-phase input signal IN2 remains for a while even if the input signal IN1 changes to the low level due to the gate delay τ1 when passing through the inverter circuit 2. During this period, it is maintained at the low level. At this time, the MOSFET Qn1 of the first current switching circuit in FIG. 1 is turned off from on, and the MOSFET Qp1 is turned on from off.
In the second current switching circuit, MOSFET Qp2 is on and M
OSFET Qn2 remains off. That is, at this time, only the first output terminal 4 has the first constant current source Qpa
And the second output terminal 5 is not yet connected to the second constant current source Qna, that is, both output terminals 4 and 5 are connected to the first constant current source Qpa and the second constant current source A transient period occurs when Qna is not connected to any of the output terminals 4 and 5.

At this time, the MO of the third current switching circuit
When the SFET Qn3 changes from on to off, the MOSFET Q
When p3 is turned on from off, the connection of the capacitive element 12 is switched from the second constant current source Qna to the first constant current source Qpa. In other words, the capacitor 12 is switched to the first constant current source Qpa while being discharged by the second constant current source Qna.

In such a state, the following operation occurs. First, since the second constant current source Qna is not connected anywhere, the first constant current source Qpa cannot supply current to the second constant current source Qna, but the MOSFET Qp3 is turned on at the same time when the MOSFET Qp1 is turned on, and the capacitive element is turned on. 1
2 is connected to the first constant current source Qpa, the first constant current source Qpa allows the charge to flow into the load capacitance 8 of the signal line 6 of the first output terminal 4 and also flows the charge to the capacitance element 12. As described above, since the electric charge is also supplied to the capacitor 12, the amount of voltage rise of the signal line 6 is smaller than when the capacitor 12 is not provided, and the potential is raised to a desired steady high level potential Voh. As described above, since the voltage of the signal line 6 does not become higher than the desired steady-state high-level potential Voh, that is, the potential of the negative-phase signal line 7, the negative-phase signal is supplied by the MOSFET Qp1 which is turned on via the terminating resistor R1. A charge is prevented from flowing into the load capacitance 9 of the line 7.

In other words, during the above-mentioned transition period, the appropriate charge absorption (charging) is performed on the capacitive element 12, so that the potential of the first output terminal 4, that is, the output differential signal OUT1 changes when the capacitive element 12 is not present. And the potential is increased to a desired steady high level potential Voh.

When the positive-phase output differential signal OUT1 reaches the steady high-level potential Voh, the delayed negative-phase input signal IN2 changes from low level to high level, and the second current switching circuit MOSFET Qn2 is turned on. Then, the load capacitance 9 of the negative-phase signal line 7 connected to the second output terminal 5 emits a current to the second constant current source Qna, and is lowered to the steady low level potential Vol. In addition,
In such a steady state, the current from the first constant current source Qpa is supplied to the second constant current source Qn via the output terminating resistor R1 and the like.
a, the potential difference between the signal lines 6 and 7, that is, the amplitude of the output differential signals OUT1 and OUT2 is kept constant.

As described above, in the LVDS interface circuit 10 of FIG. 1, from the timing when the positive-phase input signal starts to change from the high level to the low level, the delayed negative-phase input signal changes from the high level to the low level. By the time the change is completed, the output of the first output terminal 4 is changed from the steady low level to the high level, the output of the second output terminal 5 is changed from the steady high level to the low level, and the amplitudes of both are changed. Does not make a difference in the size of

As described above, according to the LVDS interface circuit 10 of this embodiment, the differential output signal O
There is almost no difference between the signal amplitudes of the UT1 and OUT2, and a differential output having a desired signal amplitude at a desired level can be obtained even when driven at a high frequency.

Since the LVDS interface circuit 10 can be constituted by a CMOS circuit, the LVDS
An S interface circuit 10 and an internal logic circuit for outputting a signal to the LVDS interface circuit 10 are both formed on a single semiconductor substrate by a CMOS circuit,
An OS semiconductor integrated circuit can be configured. Therefore, a semiconductor integrated circuit having the LVDS interface circuit 10 mounted thereon and having low overall power consumption can be realized.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

FIG. 3 shows an LVD suitable for applying the present invention.
FIG. 9 shows a circuit diagram of a modification of the S interface circuit.

In the above embodiment, an example is shown in which MOSFETs whose source terminals are connected to the power supply voltage Vcc or the ground potential are used as the first and second current sources.
As shown in (a) and (b), the first or second constant current source Q
na is replaced with a resistor R11 connected to the ground potential or a resistor R12 connected to the power supply voltage Vcc instead of the MOSFET, or as shown in FIG.
And the second constant current source Qna may be resistors R13 and R14 connected to the power supply voltage Vcc and the ground potential, respectively.

Although the MOSFET is used as the current switching element in the above embodiment, a bipolar transistor may be used. Further, the terminating resistor and the dummy capacitance means may be connected as external elements.

In the above description, the invention made mainly by the present inventor is based on the LVD which
Although the S interface circuit has been described, the present invention is not limited thereto, and can be widely used for an interface circuit that outputs a differential output signal.

[0055]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

In other words, according to the present invention, even when one of the differential input signals is delayed from the other, the magnitudes of the amplitudes of the positive phase and the negative phase change within the same defined level range. There is an effect that a dynamic output can be obtained.

This interface circuit is a CMO
Since it can be composed of S, a CMOS semiconductor integrated circuit can be formed together with an internal circuit that outputs a signal to this interface circuit, and there is an effect that a semiconductor integrated circuit with low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an example of a communication system configured using an LVDS interface circuit according to a preferred embodiment of the present invention.

FIGS. 2A and 2B are time charts showing signal waveforms of the LVDS interface circuit according to the embodiment, wherein FIG. 2A shows signal waveforms of positive-phase and negative-phase input signals, and FIG. 2B shows signal waveforms of differential output signals.

FIG. 3 is a circuit diagram showing a modified example of an LVDS interface circuit suitable for applying the present invention.

FIG. 4 is a circuit diagram illustrating an example of a communication system configured using a conventional LVDS interface model circuit.

5A and 5B are time charts showing signal waveforms of a conventional LVDS interface, wherein FIG. 5A shows signal waveforms of positive-phase and negative-phase input signals, and FIG. 5B shows signal waveforms of differential output signals.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Inverter circuit 4,5 First and second output terminals 8,9 Load capacity on output side 10 LVDS interface circuit 12 Load capacity (dummy capacity means) IN1 Positive input signal IN2 Negative input signal OUT1, OUT2 Differential output signal Qpa p-channel MOSFET (first constant current source) Qna n-channel MOSFET (second constant current source) Qp1 to Qp3 p-channel MOSFETs Qn1 to Qn3 of first to third current switching circuits Qn1 to Qn3 first to third N-channel MOSFET of current switching circuit Vcc power supply voltage R11 to R14 Resistance constituting constant current source

Claims (5)

[Claims] A first current source for supplying a predetermined current, a second current source for extracting the predetermined current, a first output terminal and a second output terminal, and a connection between the first output terminal according to an input signal and the first current. A first current switching circuit for switching to either the first current source or the second current source, and a second current switching circuit for switching the connection of the second output terminal to either the first current source or the second current source by a signal having a phase opposite to the input signal. A two-current switching circuit, dummy capacitance means having one terminal connected to a constant potential point,
A third current switching circuit for switching the connection of the dummy capacitance means to the first current source or the second current source in accordance with a signal input to the current switching circuit, wherein the first current switching circuit receives the input signal. While being input as it is, the input signal is inverted and input to the second current switching circuit via an inverter circuit, and the first and second current switching circuits are controlled to control the differential from the first and second output terminals. And outputting a signal to the dummy capacitance means when the first current switching circuit connects the first current source to the first output terminal. An interface circuit, wherein the first current switching circuit draws a current from the dummy capacitance means when the first current switching circuit connects the second current source to the first output terminal. 2. The interface circuit according to claim 1, wherein a terminating resistor for impedance matching is connected between said first output terminal and said second output terminal. 3. The first current source and the second current source include a first current source and a second current source.
Alternatively, an MO having a source terminal connected to the second power supply voltage terminal
3. The interface circuit according to claim 1, wherein the interface circuit is an SFET or a resistor. 4. The first to third current switching circuits according to claim 1, wherein the first current source is a source terminal, the corresponding input terminal is a gate terminal, the corresponding output terminal or the other terminal of the dummy capacitance means is A p-channel MOSFET connected to a drain terminal, a second current source serving as a source terminal, a corresponding input terminal serving as a gate terminal, a corresponding output terminal or the other terminal of the dummy capacitance means serving as a drain terminal, respectively. C consisting of connected n-channel MOSFET
4. The interface circuit according to claim 1, wherein the interface circuit comprises a MOS circuit. 5. The logic circuit and the interface circuit according to claim 4 are formed on one semiconductor substrate, and a signal from the logic circuit is converted into a differential signal by the interface circuit and transmitted. A semiconductor integrated circuit characterized by being made.