TWI847177B - Semiconductor device with substrate for electrical connection - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a first electronic component, a second electronic component, a bonding wire, and an encapsulant. The substrate has a lower surface and an upper surface opposite to the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component and the substrate and extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. The second electronic component has an active surface facing the substrate. The encapsulant is disposed on the upper surface of the substrate. The encapsulant extends within the substrate and encapsulates the bonding wire.

Description

Semiconductor device with electrical connection substrate

This application claims priority to U.S. Patent Application Nos. 17/742,549 and 17/743,044 (with a priority date of "May 12, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a substrate having a bonding wire passing through the substrate.

With the rapid development of the electronics industry, integrated circuits (ICs) have achieved high performance and miniaturization. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits.

Many technologies have been developed to integrate two electronic components. For example, electronic components can be stacked vertically to reduce the size of semiconductor components. Currently, stacked electronic components can use conductive pillars with different lengths, each conductive pillar connecting the corresponding electronic component to the substrate. This structure may require multiple semiconductor preparation processes, thereby increasing production costs. Therefore, a new semiconductor component and preparation method are needed to improve such problems.

The above "prior art" description is only to provide background technology, and does not admit that the above "prior art" description discloses the subject matter of this disclosure, does not constitute the prior art of this disclosure, and any description of the above "prior art" should not be regarded as any part of this case.

One aspect of the present disclosure provides a semiconductor component. The semiconductor component includes a substrate, a first electronic component, a second electronic component, a bonding wire and a package. The substrate has a lower surface and an upper surface opposite to the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component to the substrate and extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. The second electronic component has an active surface facing the substrate. The package is disposed on the upper surface of the substrate. The package extends within the substrate and encapsulates the bonding wire.

Another aspect of the present disclosure provides another semiconductor element. The semiconductor element includes a substrate, a first electronic element, a second electronic element, a bonding wire and a plurality of conductive pillars. The substrate has a lower surface, an upper surface opposite to the lower surface, and an inner surface extending between the upper surface and the lower surface. The first electronic element is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic element to the substrate and faces the inner surface of the substrate. The bonding wire extends within the substrate. The second electronic element is disposed on the upper surface of the substrate. Each conductive pillar is disposed on the upper surface of the substrate and electrically connects the second electronic element to the substrate.

Another aspect of the present disclosure provides a method for preparing a semiconductor element. The preparation method includes providing a substrate having a lower surface and an upper surface opposite to the lower surface. The preparation method also includes forming an opening extending between the upper surface and the lower surface of the substrate. The preparation method also includes attaching a first electronic component to the upper surface of the substrate. An active surface of the first electronic component faces the upper surface of the substrate. In addition, the preparation method also includes attaching a second electronic component to the first electronic component. An active surface of the second electronic component faces the upper surface of the substrate. The preparation method also includes forming a bonding wire on the substrate. The bonding wire passes through the opening of the substrate and electrically connects the substrate to one of the first electronic component or the second electronic component.

In the embodiment disclosed herein, the substrate has an opening through which a bonding wire passes. The bonding wire electrically connects the lower electronic component to the substrate (or connects the upper electronic component to the substrate). Therefore, the semiconductor preparation process for forming the conductive column can be omitted, thereby reducing costs and increasing component yield.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

10: Base

10r1: Opening

10r2: Opening

10s1: Surface

10s2: Surface

10s3: Surface

20: Electronic components

20s1: Surface

20s2: Surface

20s3: Surface

20s4: Surface

20s5: Surface

21:Terminal

22: Bonding line

24: Electrical connection

30: Electronic components

30s1: Surface

30s2: Surface

30s3: Surface

30s4: Surface

31: Circuit layer

32: Conductive column

32p1: Partial

32p2: Partial

32p3: Partial

33: Electrical connection

34:Terminal

35: Bonding line

40:Packaging

40p1: Partial

41: Adhesive

42: Adhesive

50: Electrical connection

100a:Semiconductor components

100b:Semiconductor components

100c:Semiconductor components

100d: semiconductor components

100d: semiconductor components

200: Preparation method

202: Operation

204: Operation

206: Operation

208: Operation

210: Operation

212: Operation

300: Preparation method

302: Operation

304: Operation

306: Operation

308: Operation

310: Operation

R1: Surface area

R2: Surface area

R3: Surface area

When referring to the embodiments and the drawings together with the scope of the patent application, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

FIG. 1A is a top view illustrating a semiconductor device of some embodiments of the present disclosure.

FIG. 1B is a cross-sectional view illustrating a cross-sectional view of the semiconductor device along the line AA' shown in FIG. 1A according to some embodiments of the present disclosure.

FIG2 is a top view illustrating semiconductor components of some embodiments of the present disclosure.

FIG3 is a cross-sectional view illustrating a semiconductor device of some embodiments of the present disclosure.

FIG4 is a cross-sectional view illustrating a semiconductor device of some embodiments of the present disclosure.

FIG5 is a flow chart illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 6A is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG6B is a cross-sectional view illustrating a cross-sectional view of the semiconductor device along the line AA' shown in FIG6A according to some embodiments of the present disclosure.

FIG. 7A is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 7B is a cross-sectional view illustrating a cross-sectional view of the semiconductor element along the line AA' shown in FIG. 7A in some embodiments of the present disclosure.

FIG. 8A is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG8B is a cross-sectional view illustrating a cross-sectional view of the semiconductor element along the line AA' shown in FIG8A in some embodiments of the present disclosure.

FIG. 9A is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 9B is a cross-sectional view illustrating a cross-sectional view of the semiconductor device along the line AA' shown in FIG. 9A in some embodiments of the present disclosure.

FIG. 10A is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 10B is a cross-sectional view illustrating a cross-sectional view of the semiconductor device along the line AA' shown in FIG. 10A in some embodiments of the present disclosure.

FIG. 11A is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 11B is a cross-sectional view illustrating a cross-sectional view of the semiconductor element along the line AA' shown in FIG. 11A in some embodiments of the present disclosure.

FIG12 is a flow chart illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 13 is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 14 is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 15 is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 16 is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

FIG. 17 is one or more preparation stages, illustrating a method for preparing a semiconductor device according to some embodiments of the present disclosure.

The embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally be made by a person of ordinary skill in the art to which the present disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference numeral.

It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part without departing from the teachings of the present inventive concept.

The terms used herein are only used to describe specific embodiments and are not intended to be limited to the concepts of the present invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprise" and "include", when used in this specification, indicate the presence of the features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.

FIG. 1A and FIG. 1B illustrate a semiconductor device 100a of some embodiments of the present disclosure, wherein FIG. 1A is a top view and FIG. 1B is a cross-sectional view along the A-A’ line shown in FIG. 1A.

In some embodiments, the semiconductor element 100a may include a substrate 10. In some embodiments, the substrate 10 may be or include, for example, a printed circuit board such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate.

In some embodiments, the substrate 10 may include a surface 10s1 and a surface 10s2 opposite to the surface 10s1. In some embodiments, the surface 10s1 may also be referred to as a lower surface. In some embodiments, the surface 10s2 may also be referred to as an upper surface.

In some embodiments, substrate 10 may include conductive pads, lines, vias, layers, or other interconnects. For example, substrate 10 may include one or more transmission lines (e.g., communication lines) and one or more ground lines and/or ground planes. For example, substrate 10 may include one or more conductive pads (not shown) close to, adjacent to, or embedded in and exposed at surface 10s1 and/or surface 10s2 of substrate 10. That is, surfaces 10s1 and 10s2 of substrate 10 may be used to electrically connect to other electronic components.

In some embodiments, the substrate 10 may define an opening 10r1. The opening 10r1 may extend between surfaces 10s1 and 10s2 of the substrate 10. The opening 10r1 may penetrate the substrate 10. Although the illustrated opening 10r1 of FIG. 1A has a rectangular profile, 10r1 may have other profiles, such as a circular profile, an elliptical profile, a trapezoidal profile, or other suitable profiles based on design requirements. The substrate 10 may have a surface 10s3 to define the opening 10r1. The surface 10s3 may extend between surfaces 10s1 and 10s2 of the substrate 10. In some embodiments, the surface 10s3 may also be referred to as an inner surface. In some embodiments, the inner surface may be surrounded by an outer surface (not labeled in the figure) of the substrate 10.

In some embodiments, the semiconductor device 100a may include an electronic device 20. In some embodiments, the electronic device 20 may be disposed on a surface 10s2 of the substrate 10. In some embodiments, the electronic device 20 may include a memory device, such as a dynamic random access memory (DRAM) device, a one-time programmable (OTP) memory device, a static random access memory (SRAM) device, or other suitable memory devices. In some embodiments, the electronic component 20 may include a logic component (e.g., a system on chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) component, a sensor component, a microelectromechanical system (MEMS) component, a signal processing component (e.g., a digital signal processing (DSP) component), a front-end component (e.g., an analog front-end (AFE) component), or other components.

The electronic component 20 may have a surface 20s1 and a surface 20s2 opposite to the surface 20s1. In some embodiments, the surface 20s1 may also be referred to as an active surface. In some embodiments, the surface 20s2 may also be referred to as a back surface. In some embodiments, the surface 20s1 of the electronic component 20 may face the surface 10s2 of the substrate 10. As used herein, the term "active surface" may refer to a surface where a terminal is provided to transmit and/or receive signals. In some embodiments, the surface 20s1 of the electronic component 20 may face the surface 10s2 of the substrate 10. The electronic component 20 may include a surface 20s3 and a surface 20s4 opposite to the surface 20s3. The surface 20s3 may extend between the surfaces 20s1 and 20s2. The surface 20s4 may extend between the surfaces 20s1 and 20s2. In some embodiments, each of the surfaces 20s3 and 20s4 may also be referred to as a side surface of the electronic component 20.

In some embodiments, the electronic element 20 may include a terminal 21. The terminal 21 may be disposed on a surface 20s1 of the electronic element 20. The terminal 21 may be, for example, a conductive pad. In some embodiments, the terminal 21 may include a metal, such as copper (Cu), tungsten (W), silver (Ag), gold (Au), ruthenium (Ru), iridium (Ir), nickel (Ni), zirconium (Os), ruthenium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or other suitable materials.

In some embodiments, the semiconductor device 100a may include a bonding wire 22. In some embodiments, the bonding wire 22 has a first end (not noted in the figure) bonded to the surface 10s1 of the substrate 10 and a second end (not noted in the figure) bonded to the surface 20s1 of the electronic component 20. In some embodiments, the bonding wire 22 may be bonded to the terminal 21 of the electronic component 20. In some embodiments, the bonding wire 22 may pass through the opening 10r1 of the substrate 10. In some embodiments, the bonding wire 22 may face the surface 10s3 of the substrate 10. In some embodiments, the bonding wire 22 may penetrate the substrate 10. In some embodiments, the bonding wire 22 may include a metal such as copper (Cu), silver (Ag), gold (Au), nickel (Ni), aluminum (Al), alloys thereof, combinations thereof, or other suitable materials.

In some embodiments, the semiconductor element 100a may include an electronic element 30. In some embodiments, the electronic element 30 may be disposed on the surface 10s2 of the substrate 10. In some embodiments, the electronic element 30 may be located on the electronic element 20. In some embodiments, the electronic element 30 may be stacked on the electronic element 20. In some embodiments, the electronic element 30 may be disposed on the surface 20s2 of the electronic element 20. In some embodiments, the electronic element 30 may include a memory element, such as a dynamic random access memory (DRAM) element, a one-time programming (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory elements. In some embodiments, the electronic component 30 may include a logic component (e.g., a system on chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) component, a sensor component, a microelectromechanical system (MEMS) component, a signal processing component (e.g., a digital signal processing (DSP) component), a front-end component (e.g., an analog front-end (AFE) component), or other components.

The electronic component 30 may have a surface 30s1 and a surface 30s2 opposite to the surface 30s1. In some embodiments, the surface 30s1 may also be referred to as an active surface. In some embodiments, the surface 30s2 may also be referred to as a back surface. In some embodiments, the surface 30s1 of the electronic component 30 may face the surface 10s2 of the substrate 10. In some embodiments, the surface 30s1 of the electronic component 30 may face the surface 20s2 of the electronic component 20. The electronic component 30 may have a surface 30s3 and a surface 30s4 opposite to the surface 30s3. The surface 30s3 may extend between the surfaces 30s1 and 30s2. The surface 30s4 may extend between the surfaces 30s1 and 30s2. In some embodiments, each of the surfaces 30s3 and 30s4 may also be referred to as a side of the electronic component 30.

As shown in FIG. 1A , the electronic component 20 may have a surface area R1, and the electronic component 30 may have a surface area R2. In some embodiments, the surface area R1 may be substantially equal to the surface area R2. In some embodiments, the geometric center (not noted in the figure) of the electronic component 20 is misaligned with the geometric center of the electronic component 30. In some embodiments, a portion of the surface 20s2 of the electronic component 20 may be exposed from the electronic component 30. In some embodiments, the electronic component 30 may overlap vertically with the opening 10r1 of the substrate 10. In some embodiments, the electronic component 30 may cover the opening 10r1 of the substrate 10.

In some embodiments, the electronic component 30 may include a circuit layer 31. The circuit layer 31 may be disposed on a surface 30s1 of the electronic component 30. The circuit layer 31 may include, for example, a redistribution layer having wiring and conductive vias in one or more dielectric layers.

In some embodiments, the semiconductor element 100a may include a conductive column 32. In some embodiments, the conductive column 32 may be disposed on the surface 30s1 of the electronic element 30. In some embodiments, the conductive column of the electronic element 30 may be configured to electrically connect the electronic element 30 to the substrate 10. In some embodiments, the conductive column 32 may include a metal such as copper (Cu), silver (Ag), gold (Au), nickel (Ni), aluminum (Al), alloys thereof, combinations thereof, or other suitable materials.

As shown in FIG. 1A , the conductive pillar 32 may face the surface 20s3 of the electronic component 20 . In some embodiments, the surface 20s4 of the electronic component 20 may face away from the conductive pillar 32 .

In some embodiments, the semiconductor element 100a may include an electrical connection 33. The electrical connection 33 may be disposed between the conductive pillar 32 and the substrate 10. The electrical connection 33 may include a solder material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

In some embodiments, the semiconductor element 100a may include a package 40. In some embodiments, the package 40 may be disposed on the surface 10s2 of the substrate 10. In some embodiments, the package 40 may cover the surface 10s2 of the substrate 10. In some embodiments, the package 40 may cover a portion of the surface 10s1 of the substrate 10. In some embodiments, a portion of the surface 10s1 of the substrate 10 may be exposed from the package 40. The package 40 may include an insulating or dielectric material. In some embodiments, the package 40 includes a molding material, which may include, for example, a Novolac-based resin, an epoxy resin, a silicone-based resin, or other suitable package. Suitable fillers such as powdered SiO2 may also be included.

In some embodiments, package 40 may encapsulate electronic component 20. In some embodiments, package 40 may encapsulate electronic component 30. In some embodiments, package 40 may encapsulate bonding wire 22. In some embodiments, package 40 may encapsulate conductive pillar 32. In some embodiments, package 40 may encapsulate electrical connection 33. In some embodiments, package 40 may fill opening 10r1 of substrate 10. In some embodiments, package 40 may protrude into substrate 10. In some embodiments, package 40 may have portion 40p1 within opening 10r1 of substrate 10. In some embodiments, portion 40p1 of package 40 may be surrounded by substrate 10. In some embodiments, portion 40p1 of package 40 may be surrounded by surface 10s3 of substrate 10. In some embodiments, portion 40p1 of package 40 may contact surface 10s3 of substrate 10. In some embodiments, portion 40p1 of package 40 may vertically overlap electronic component 20. In some embodiments, portion 40p1 of package 40 may vertically overlap electronic component 30.

In some embodiments, the semiconductor element 100a may include adhesives 41 and 42. In some embodiments, the adhesive 41 may be configured to attach the electronic element 20 to the surface 10s2 of the substrate 10. In some embodiments, the adhesive 41 may be disposed between the surface 20s1 of the electronic element 20 and the surface 10s2 of the substrate 10.

In some embodiments, the adhesive 42 may be configured to attach the electronic component 30 to the surface 20s2 of the electronic component 20. In some embodiments, the adhesive 42 may be disposed between the surface 20s2 of the electronic component 20 and the surface 30s2 of the electronic component 30. In some embodiments, a portion of the circuit layer 31 may be covered by the adhesive 42. In some embodiments, a portion of the circuit layer 31 may be exposed from the adhesive 42.

In some embodiments, the semiconductor element 100a may include an electrical connection 50. The electrical connection 50 may be disposed on the surface 10s1 of the substrate 10. In some embodiments, the electrical connection 50 may be configured to electrically connect the semiconductor element 100a to an external element (not shown). In some embodiments, the electrical connection 50 may include a solder material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

In a comparative example, both lower and upper electronic components are electrically connected to the substrate via conductive pillars. The conductive pillars have different lengths. For example, a shorter conductive pillar attaches the lower electronic component to the substrate, while a longer conductive pillar attaches the upper electronic component to the substrate. The formation of the conductive pillars on the electronic components may require more semiconductor preparation processes, which may result in higher costs and relatively lower yields.

In the embodiment disclosed herein, the substrate has an opening (e.g., 10r1) through which a bonding wire (e.g., 22) passes. The bonding wire electrically connects the lower electronic component (e.g., 20) to the substrate. The upper electronic component (e.g., 30) is electrically connected to the substrate through a conductive column (e.g., 32). Compared with the comparative example, only the upper electronic component requires a conductive column. Therefore, the semiconductor preparation process of forming a shorter conductive column can be omitted, thereby reducing costs and increasing component yield.

FIG. 2 is a top view illustrating a semiconductor device 100b of some embodiments of the present disclosure. The semiconductor device 100b is similar to the semiconductor device 100a shown in FIG. 1A , and the difference therebetween will be described below.

As shown in FIG. 2 , the electronic component 20 may have a surface 20s5 extending between the surfaces 20s3 and 20s4. The surface 20s5 may also be referred to as a side surface of the electronic component 20.

In some embodiments, the conductive column 32 may include portions 32p1 and 32p2. In some embodiments, the portion 32p1 of the conductive column 32 may be disposed on the surface 20s3 of the electronic component 20. In some embodiments, the portion 32p1 of the conductive column 32 may face the surface 20s3 of the electronic component 20. In some embodiments, the portion 32p2 of the conductive column 32 may be disposed on the surface 20s5 of the electronic component 20. In some embodiments, the portion 32p2 of the conductive column 32 may face the surface 20s5 of the electronic component 20.

A portion of the surface 20s5 of the electronic component 20 may not overlap with the conductive pillar 32. In some embodiments, the conductive pillar 32 may be arranged in an L-shaped profile, an inverted L-shaped profile, or other suitable profiles.

Since there are more conductive pillars (e.g., portion 32p2) connecting the electronic component 30 and the substrate 10, more input and/or output terminals can be used to transmit or receive signals, thereby improving the performance of the semiconductor component 100b.

FIG. 3 is a cross-sectional view illustrating a semiconductor device 100c of some embodiments of the present disclosure. The semiconductor device 100c is similar to the semiconductor device 100a shown in FIG. 1B , and the difference therebetween will be described below.

In some embodiments, the surface area R3 of the electronic component 30 may be different from the surface area R1 of the electronic component 20. In some embodiments, the surface area R3 of the electronic component 30 may be larger than the surface area R1 of the electronic component 20.

In some embodiments, the conductive post 32 may include a portion 32p3. In some embodiments, the portions 32p1 and 32p3 of the conductive post 32 may be disposed on opposite sides of the electronic component 20. In some embodiments, the portion 32p3 of the conductive post 32 may be disposed on the surface 20s4 of the electronic component 20. In some embodiments, the portion 32p3 of the conductive post 32 may face the surface 20s4 of the electronic component 20.

Since there are more conductive posts (e.g., portion 32p3) connecting the electronic component 30 and the substrate 10, more input and/or output terminals can be used to transmit or receive signals, thereby improving the performance of the semiconductor component 100c.

FIG. 4 is a cross-sectional view illustrating a semiconductor device 100d of some embodiments of the present disclosure. The semiconductor device 100d is similar to the semiconductor device 100a shown in FIG. 1B , and the difference therebetween will be described below.

In some embodiments, the substrate 10 may have an opening 10r2. The opening 10r2 may extend between the surfaces 10s1 and 10s2 of the substrate 10. In some embodiments, the opening 10r2 may not overlap vertically with the electronic element 20.

In some embodiments, the electronic element 20 can be electrically connected to the substrate 10 through the conductive pillar 23. In some embodiments, the conductive pillar 23 can be disposed between the surface 20s1 of the electronic element 20 and the surface 10s2 of the substrate 10. In some embodiments, the conductive pillar 23 can include metal, such as copper (Cu), silver (Ag), gold (Au), nickel (Ni), aluminum (Al), alloys thereof, combinations thereof, or other suitable materials.

In some embodiments, the package 40 may have a portion 40p1 within the opening 10r2 of the substrate 10. In some embodiments, the portion 40p1 of the package 40 may not vertically overlap with the electronic component 20. In some embodiments, the portion 40p1 of the package 40 may vertically overlap with the electronic component 30.

In some embodiments, the semiconductor element 100d may include an electrical connection 24. The electrical connection 24 may be disposed between the conductive pillar 23 and the substrate 10. The electrical connection 24 may include a solder material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

In some embodiments, the electronic component 30 may include a terminal 34. The terminal 34 may be disposed on a surface 30s1 of the electronic component 30. The material of the terminal 34 may be the same as or similar to the material of the terminal 21.

In some embodiments, the semiconductor element 100d may include a bonding wire 35. In some embodiments, the bonding wire 35 has a first end (not noted in the figure) bonded to the surface 10s1 of the substrate 10 and a second end (not noted in the figure) bonded to the surface 30s1 of the electronic element 30. In some embodiments, the bonding wire 35 may be bonded to the terminal 34 of the electronic element 30. In some embodiments, the bonding wire 35 may pass through the opening 10r2 of the substrate 10. In some embodiments, the bonding wire 35 may face the surface 10s3 of the substrate 10. In some embodiments, the material of the bonding wire 35 may be the same as or similar to the material of the bonding wire 22. In some embodiments, the bonding wire 35 may face the surface 20s3 of the electronic element 20. In some embodiments, the surface 20s4 of the electronic component 20 may face away from the bonding line 35.

In the embodiment disclosed herein, the substrate has an opening (e.g., 10r2) through which a bonding wire (e.g., bonding wire 35) passes. The bonding wire electrically connects the upper electronic component (e.g., 30) to the substrate. The lower electronic component (e.g., 20) is electrically connected to the substrate through a conductive column (e.g., 23). Compared with the comparative example, only the lower electronic component requires a conductive column. Therefore, the semiconductor manufacturing process of forming a longer conductive column can be omitted, thereby reducing costs and increasing component yield.

FIG5 is a flow chart illustrating a method 200 for preparing a semiconductor device according to some embodiments of the present disclosure.

Preparation method 200 begins with operation 202, in which a substrate may be provided. The substrate may have a lower surface and an upper surface opposite the lower surface. The substrate may include one or more conductive pads (not shown) near, adjacent to, or embedded in and exposed at the lower surface and/or the upper surface of the substrate.

The preparation method 200 continues with operation 204, where an opening may be formed. In some embodiments, an etching process may be performed to form the opening. The opening may extend between the lower surface and the upper surface of the substrate. The etching process may include, for example, dry etching, wet etching, or other suitable processes.

The preparation method 200 continues with operation 206, in which a first electronic component can be attached to the upper surface of the substrate. In some embodiments, the first electronic component can be attached to the upper surface of the substrate by an adhesive. In some embodiments, the first electronic component can be directly above the opening of the substrate. The first electronic component can have an active surface and a back surface opposite the active surface. In some embodiments, the first electronic component can have a terminal facing the upper surface of the substrate.

The preparation method 200 continues with operation 208, where a bonding wire may be formed to electrically connect the substrate to the first electronic component. In some embodiments, the bonding wire may have a first end bonded to the active surface of the first electronic component and a second end bonded to the lower surface of the substrate. In some embodiments, the bonding wire may pass through the opening of the substrate. In some embodiments, the bonding wire may be bonded to the terminal of the first electronic component.

The preparation method 200 continues with operation 210, wherein a second electronic component may be attached to the back surface of the first electronic component. In some embodiments, the second electronic component may be attached to the back surface of the first electronic component via an adhesive. In some embodiments, the second electronic component may be directly above the opening of the substrate.

The second electronic component may have an active surface and a back surface opposite to the active surface. In some embodiments, a plurality of conductive posts may be formed on the active surface of the second electronic component. The conductive posts may electrically connect the second electronic component to the substrate. In some embodiments, the conductive posts may be formed on the active surface of the second electronic component before attaching the second electronic component to the first electronic component.

The preparation method 200 continues with operation 212, wherein a package may be formed on the upper surface of the substrate and an electrical connection may be formed on the lower surface of the substrate, thereby producing a semiconductor component. In some embodiments, the package may encapsulate the first electronic component, the second electronic component, and the conductive pillar.

In the disclosed embodiment, the substrate has an opening through which a bonding wire passes. The bonding wire electrically connects the lower electronic component to the substrate. The upper electronic component is electrically connected to the substrate through a conductive column. Compared with the comparative example, only the upper electronic component requires a conductive column. Therefore, the semiconductor manufacturing process of forming a shorter conductive column on the lower electronic component can be omitted, thereby reducing costs and increasing the yield of components.

Preparation method 200 is merely an example and is not intended to limit the content of the present disclosure to the scope explicitly described in the scope of the application. Additional operations may be provided before, during, or after each operation of preparation method 200, and some of the operations described may be replaced, eliminated, or reordered for other embodiments of the preparation method. In some embodiments, preparation method 200 may include further operations not depicted in FIG. 5. In some embodiments, preparation method 200 may include one or more operations described in FIG. 5.

Figures 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A and 11B illustrate one or more preparation stages of a semiconductor device preparation method of some embodiments of the present disclosure, wherein Figures 6A, 7A, 8A, 9A, 10A and 11A are top views, and Figures 6B, 7B, 8B, 9B, 10B and 11B are cross-sectional views along the A-A' line shown in Figures 6A, 7A, 8A, 9A, 10A and 11A, respectively. In some embodiments, the semiconductor device 100a can be prepared by the operations described with respect to Figures 6A to 11A and 6B to 11B.

Referring to FIG. 6A and FIG. 6B , a substrate 10 may be provided. The substrate 10 may have a surface 10s1 and a surface 10s2 opposite to the surface 10s1. The substrate 10 may include one or more conductive pads (not shown) close to, adjacent to, or embedded in and exposed at the surface 10s1 and/or the surface 10s2 of the substrate 10.

Referring to FIG. 7A and FIG. 7B , an opening 10r1 may be formed. In some embodiments, an etching process may be performed to form the opening 10r1. The opening 10r1 may extend between surfaces 10s1 and 10s2 of the substrate 10. The etching process may include, for example, dry etching, wet etching, or other suitable processes.

Referring to FIG. 8A and FIG. 8B , the electronic component 20 may be attached to the surface 10s2 of the substrate 10. In some embodiments, the electronic component 20 may be attached to the surface 10s2 of the substrate 10 by an adhesive 41. In some embodiments, the electronic component 20 may be located directly above the opening 10r1 of the substrate 10. The electronic component 20 may have a surface 20s1 and a surface 20s2 opposite to the surface 20s1. In some embodiments, the electronic component 20 may have a terminal 21 facing the surface 10s2 of the substrate 10.

Referring to FIG. 9A and FIG. 9B , a bonding wire 22 may be formed to electrically connect the substrate 10 to the electronic component 20. In some embodiments, the bonding wire 22 may have a first end bonded to the surface 20s1 of the electronic component 20 and a second end bonded to the surface 10s1 of the substrate 10. In some embodiments, the bonding wire 22 may pass through the opening 10r1 of the substrate 10. In some embodiments, the bonding wire 22 may be bonded to the terminal 21 of the electronic component 20.

Referring to FIG. 10A and FIG. 10B , the electronic component 30 may be attached to the surface 20s2 of the electronic component 20. In some embodiments, the electronic component 30 may be attached to the surface 20s2 of the electronic component 20 by an adhesive 42. In some embodiments, the electronic component 30 may be directly located above the opening 10r1 of the substrate 10.

The electronic component 30 may have a surface 30s1 and a surface 30s2 opposite to the surface 30s1. In some embodiments, a plurality of conductive posts 32 may be formed on the surface 30s1 of the electronic component 30. The conductive posts 32 may electrically connect the electronic component 30 to the substrate 10. In some embodiments, the conductive posts 32 may be formed on the surface 30s1 of the electronic component 30 before attaching the electronic component 30 to the electronic component 20.

The manufacturing technology of the conductive pillar 32 may include a sputtering operation, an electroplating operation, and a lithography operation. For example, the manufacturing technology of the conductive pillar 32 may include a lithography operation of forming a patterned photosensitive layer (not shown) on the surface 30s1 of the electronic element 30, a sputtering operation of forming a seed layer on the opening of the patterned photosensitive layer, an electroplating operation of forming a conductive layer on the seed layer, and removing the patterned photosensitive layer.

Referring to FIG. 11A and FIG. 11B , a package 40 may be formed on the surface 10s2 of the substrate 10, and an electrical connection 50 may be formed on the surface 10s1 of the substrate 10, thereby producing a semiconductor element 100a. The manufacturing technology of the package 40 may include a molding operation. The molding flow may pass from the surface 10s2 of the substrate 10, through the opening 10r1, and enter the surface 10s1 of the substrate 10. Therefore, the package 40 may encapsulate the electronic components 20, 30 and the conductive pillar 32.

In the embodiment of the present disclosure, the electronic component 20 can be electrically connected to the substrate 10 using the bonding wire 22. The electronic component 30 is electrically connected to the substrate 10 through the conductive column 32. Compared with the comparative example, only the electronic component 30 requires the conductive column. Therefore, the semiconductor preparation process of forming the conductive column on the electronic component 20 can be omitted, thereby reducing costs and improving the yield of the component.

FIG. 12 is a flow chart illustrating a method 300 for preparing a semiconductor device according to some embodiments of the present disclosure.

Preparation method 300 begins with operation 302, which can be performed after operation 202. An opening defined by the substrate can be formed. The opening can extend between the lower surface and the upper surface of the substrate.

The preparation method 300 continues with operation 304, wherein a first electronic component may be attached to the upper surface of the substrate. In some embodiments, the first electronic component may be attached to the upper surface of the substrate by an adhesive. In some embodiments, the first electronic component does not vertically overlap the opening of the substrate. In some embodiments, a plurality of conductive posts may be formed on the active surface of the first electronic component. The conductive posts may electrically connect the first electronic component to the substrate. In some embodiments, the conductive posts may be formed on the active surface of the first electronic component before attaching the first electronic component to the substrate.

The preparation method 300 continues with operation 306, wherein a second electronic component may be attached to the back surface of the first electronic component. In some embodiments, the second electronic component may be attached to the back surface of the first electronic component by an adhesive. In some embodiments, the second electronic component may be directly above the opening of the substrate. The second electronic component may have a terminal on the active surface of the second electronic component.

The preparation method 300 continues with operation 308, where a bonding wire may be formed to electrically connect the substrate and the second electronic component. In some embodiments, the bonding wire may have a first end bonded to the active surface of the second electronic component and a second end bonded to the lower surface of the substrate. In some embodiments, the bonding wire may pass through the opening of the substrate. In some embodiments, the bonding wire may be bonded to the terminal of the second electronic component.

The preparation method 300 continues with operation 310, wherein a package may be formed on the upper surface of the substrate and an electrical connection may be formed on the lower surface of the substrate, thereby producing a semiconductor device.

In the embodiment disclosed herein, the second electronic component can be electrically connected to the substrate using a bonding wire. The first electronic component is electrically connected to the substrate through a conductive column. Compared with the comparative example, only the first electronic component requires a conductive column. Therefore, the semiconductor preparation process of forming a conductive column on the second electronic component can be omitted, thereby reducing costs and improving component yield.

Preparation method 300 is merely an example and is not intended to limit the present disclosure beyond the scope expressly mentioned in the scope of the application. Additional operations may be provided before, during, or after each operation of preparation method 300, and some operations described may be replaced, eliminated, or reordered for other embodiments of the preparation method. In some embodiments, preparation method 300 may include further operations not depicted in FIG. 12. In some embodiments, preparation method 300 may include one or more operations depicted in FIG. 12.

FIG. 13, FIG. 14, FIG. 15, FIG. 16, and FIG. 17 illustrate one or more preparation stages of a method for preparing a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100d can be prepared by the operations described with respect to FIG. 13 to FIG. 17.

Referring to FIG. 13 , the operation may be performed after the operation of FIG. 6A and FIG. 6B . An opening 10r2 may be formed. The opening 10r2 may extend between the surfaces 10s1 and 10s2 of the substrate 10 .

Referring to FIG. 14 , the electronic component 20 may be attached to the surface 10s2 of the substrate 10. In some embodiments, the electronic component 20 may be attached to the surface 10s2 of the substrate 10 by an adhesive 41. In some embodiments, the electronic component 20 may not overlap vertically with the opening 10r2 of the substrate 10. In some embodiments, a plurality of conductive posts 23 may be formed on the surface 20s1 of the electronic component 20. The conductive posts 23 may electrically connect the electronic component 20 to the substrate 10. In some embodiments, the conductive posts 23 may be formed on the surface 20s1 of the electronic component 20 before attaching the electronic component 20 to the substrate 10. The preparation process of the conductive posts 23 may be the same or similar to the preparation process of the conductive posts 32.

Referring to FIG. 15 , the electronic component 30 may be attached to the surface 20s2 of the electronic component 20. In some embodiments, the electronic component 30 may be attached to the surface 20s2 of the electronic component 20 by an adhesive 42. In some embodiments, the electronic component 30 may be directly located above the opening 10r2 of the substrate 10. The electronic component 30 may have a terminal 34 on the surface 30s1 of the electronic component 30.

Referring to FIG. 16 , a bonding wire 35 may be formed to electrically connect the substrate 10 to the electronic component 30. In some embodiments, the bonding wire 35 may have a first end bonded to the surface 30s1 of the electronic component 30 and a second end bonded to the surface 10s1 of the substrate 10. In some embodiments, the bonding wire 35 may pass through the opening 10r2 of the substrate 10. In some embodiments, the bonding wire 35 may be bonded to the terminal 34 of the electronic component 30.

Referring to FIG. 17 , a package 40 may be formed on the surface 10s2 of the substrate 10 and an electrical connection 50 may be formed on the surface 10s1 of the substrate 10, thereby producing a semiconductor device 100d.

In the embodiment disclosed herein, the substrate has an opening (e.g., 10r2) through which a bonding wire (e.g., 35) passes. The bonding wire electrically connects the upper electronic component (e.g., 30) to the substrate. The lower electronic component (e.g., 20) is electrically connected to the substrate through a conductive column (e.g., 23). Compared with the comparative example, only the lower electronic component requires a conductive column. Therefore, the semiconductor preparation process of forming a longer conductive column on the upper electronic component can be omitted, thereby reducing costs and increasing component yield.

One aspect of the present disclosure provides a semiconductor component. The semiconductor component includes a substrate, a first electronic component, a second electronic component, a bonding wire and a package. The substrate has a lower surface and an upper surface opposite to the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component to the substrate and extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. The second electronic component has an active surface facing the substrate. The package is disposed on the upper surface of the substrate. The package extends within the substrate and encapsulates the bonding wire.

Another aspect of the present disclosure provides another semiconductor element. The semiconductor element includes a substrate, a first electronic element, a second electronic element, a bonding wire and a plurality of conductive pillars. The substrate has a lower surface, an upper surface opposite to the lower surface, and an inner surface extending between the upper surface and the lower surface. The first electronic element is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic element to the substrate and faces the inner surface of the substrate. The bonding wire extends within the substrate. The second electronic element is disposed on the upper surface of the substrate. Each conductive pillar is disposed on the upper surface of the substrate and electrically connects the second electronic element to the substrate.

Another aspect of the present disclosure provides a method for preparing a semiconductor element. The preparation method includes providing a substrate having a lower surface and an upper surface opposite to the lower surface. The preparation method also includes forming an opening extending between the upper surface and the lower surface of the substrate. The preparation method also includes attaching a first electronic component to the upper surface of the substrate. An active surface of the first electronic component faces the upper surface of the substrate. In addition, the preparation method also includes attaching a second electronic component to the first electronic component. An active surface of the second electronic component faces the upper surface of the substrate. The preparation method also includes forming a bonding wire on the substrate. The bonding wire passes through the opening of the substrate and electrically connects the substrate to one of the first electronic component or the second electronic component.

In the disclosed embodiment, the substrate has an opening through which a bonding wire passes. The bonding wire electrically connects the lower (or upper) electronic component to the substrate. The upper (or lower) electronic component is electrically connected to the substrate through a conductive column, which is formed by performing multiple semiconductor preparation processes. Therefore, the semiconductor preparation process of forming the conductive column on the lower electronic component can be omitted, thereby reducing costs and increasing component yield.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined by the scope of the patent application. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacturing, material compositions, means, methods and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

10: Base

10r1: Opening

10s1: Surface

10s2: Surface

10s3: Surface

20: Electronic components

20s1: Surface

20s2: Surface

20s3: Surface

20s4: Surface

21:Terminal

22: Bonding line

30: Electronic components

30s1: Surface

30s2: Surface

30s3: Surface

30s4: Surface

31: Circuit layer

32: Conductive column

33: Electrical connection

40:Packaging

40p1: Partial

41: Adhesive

42: Adhesive

50: Electrical connection

100a:Semiconductor components

Claims (18)

A semiconductor component comprises: a substrate having a lower surface and an upper surface opposite to the lower surface; a first electronic component disposed on the upper surface of the substrate and supported by the substrate; an adhesive configured to directly attach the first electronic component to the upper surface of the substrate; a bonding wire electrically connecting the first electronic component to the substrate, wherein the bonding wire extends in the substrate; a second electronic component disposed on the upper surface of the substrate and comprising a circuit layer, wherein the second electronic component has an active surface facing the substrate, and the circuit layer is disposed on a portion of the active surface of the second electronic component; a package disposed on the upper surface of the substrate, wherein the package extends in the substrate and encapsulates the bonding wire; and a plurality of conductive posts extending between the active surface of the second electronic component and the upper surface of the substrate via the circuit layer. A semiconductor device as described in claim 1, wherein the second electronic device is located above the first electronic device, a portion of the package is surrounded by the substrate, and a portion of the package vertically overlaps with the second electronic device. A semiconductor device as described in claim 1, wherein a portion of the package is surrounded by the substrate, and a portion of the package does not vertically overlap with the second electronic device. A semiconductor device as described in claim 1, wherein the first electronic device has a first side and a second side opposite to the first side, and the plurality of conductive pillars are disposed on the first side of the first electronic device. A semiconductor element as described in claim 2, wherein the second side of the first electronic element does not face the plurality of conductive pillars. A semiconductor device as described in claim 5, wherein a first surface area of the first electronic device is substantially the same as a second surface area of the second electronic device. A semiconductor device as described in claim 4, wherein the first electronic device has a third side extending between the first side and the second side, and a portion of the plurality of conductive pillars faces the third side of the first electronic device. A semiconductor device as described in claim 4, wherein a portion of the plurality of conductive pillars faces the second side of the first electronic device, and a first surface area of the first electronic device is smaller than a second surface area of the second electronic device. A semiconductor device as described in claim 1, wherein the package encapsulates the plurality of conductive pillars, and the package contacts the lower surface of the substrate. A semiconductor element comprises: a substrate having a lower surface, an upper surface opposite to the lower surface, and an inner surface extending between the upper surface and the lower surface; a first electronic element disposed on the upper surface of the substrate and carried by the substrate; an adhesive configured to directly attach the first electronic element to the upper surface of the substrate; a bonding wire electrically connecting the first electronic element to the substrate, wherein the bonding wire faces the inner surface of the substrate; a second electronic element disposed on the upper surface of the substrate and comprising a circuit layer disposed on a portion of an active surface of the second electronic element; and a plurality of conductive posts disposed on the upper surface of the substrate, each conductive post electrically connecting the second electronic element to the substrate via the circuit layer. A semiconductor device as described in claim 10, wherein the second electronic device is located above the first electronic device. A semiconductor device as described in claim 10, wherein the first electronic device has a first side and a second side opposite to the first side, and the plurality of conductive pillars are disposed on the first side of the first electronic device. A semiconductor element as described in claim 12, wherein the second side of the first electronic element does not face the plurality of conductive pillars, and a first surface area of the first electronic element is substantially the same as a second surface area of the second electronic element. A semiconductor device as described in claim 12, wherein the first electronic device has a third side extending between the first side and the second side, and a portion of the plurality of conductive pillars faces the third side of the first electronic device. A semiconductor device as described in claim 12, wherein a portion of the plurality of conductive pillars faces the second side of the first electronic device, and a first surface area of the first electronic device is smaller than a second surface area of the second electronic device. The semiconductor device as described in claim 10 further includes: a package disposed on the upper surface of the substrate, wherein the package encapsulates the plurality of conductive pillars. A semiconductor device as described in claim 16, wherein the package contacts the lower surface of the substrate. A semiconductor device as described in claim 16, wherein the package has a portion surrounded by the inner surface of the substrate, and the portion of the package does not vertically overlap with the second electronic component.