TW200849500A - Integrated circuit package and the method for dissipating heat thereof - Google Patents

Integrated circuit package and the method for dissipating heat thereof Download PDF

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Publication number
TW200849500A
TW200849500A TW096120481A TW96120481A TW200849500A TW 200849500 A TW200849500 A TW 200849500A TW 096120481 A TW096120481 A TW 096120481A TW 96120481 A TW96120481 A TW 96120481A TW 200849500 A TW200849500 A TW 200849500A
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Taiwan
Prior art keywords
integrated circuit
carrier substrate
package
hole
heat dissipation
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TW096120481A
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Chinese (zh)
Inventor
Kuo-Chen Wen
I-Cheng Keng
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Nanya Technology Corp
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Priority to TW096120481A priority Critical patent/TW200849500A/en
Publication of TW200849500A publication Critical patent/TW200849500A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

An integrated circuit package and the method for dissipating heat thereof are provided. The integrated circuit package comprises a substrate having a first surface, a second surface and at least one holes passing through thereto; and a heat sink layer formed in the hole, and extending to the first surface and the second surface of the substrate. The integrated circuit package further comprises a die disposed on the second surface of the substrate and a conductive ball formed on the first surface thermally connected the heat sink layer and a printed circuit board. Heat produced by the die is transmitted from the second surface to the first surface of the substrate by passing through the hole. The heat on first surface is then transmitted to printed circuit board by the conductive ball. Efficiency of dissipating heat and life of the integrated circuit package is thus promoted.

Description

200849500 九、發明說明： 【發明所屬之技術領域】 本發明係有關於積體電路封裝體，特別是有關於一 種積體電路封裝體及其散熱方法。 【先前技彳标】 隨著積體電路晶圓的製程技術從次微米級發展至奈 米級，因為增加電晶體的數量，同時也增加元件中的漏電 流，由此，也會大大地增加由積體電路所產生的熱。因此， 積體電路的封裝及系統熱的效能也變得愈來愈重要。 在第1圖中，係顯示習知積體電路封裝體的剖面圖。 藉由黏著層14將晶片12貼附於承載基板10的表面上； 焊錫球16形成於承載基板10的表面上，且電性連接一印 刷電路板18;封裝樹脂20包覆上述晶片12。由於封裝樹 脂20與承載基板10兩者皆不是良好的導熱材料，以致於 晶片12所產生的熱會侷限在積體電路封裝體内，而導致 縮短積體電路的壽命或積體電路的操作異常。 據此，亟需要一種改良的積體電路封裝體及散熱方 法，以提昇積體電路封裝體的散熱效率。 【發明内容】 有鑑於此，本發明之一目係提供一種積體電路的封 裝體。上述積體電路的封裝體包含：一承載基板，具有 一第一表面、一第二表面以及至少一孔洞，其中該孔洞 貫穿該承載基板；以及一散熱層，形成該孔洞之中，且 延伸於該承載基板的第一表面及第二表面上。200849500 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit package, and more particularly to an integrated circuit package and a heat dissipation method therefor. [Previous technical standards] As the process technology of integrated circuit wafers has evolved from sub-micron to nano-scale, the number of transistors is increased, and the leakage current in the components is also increased, thereby greatly increasing The heat generated by the integrated circuit. Therefore, the packaging of integrated circuits and the thermal efficiency of the system have become more and more important. In Fig. 1, a cross-sectional view of a conventional integrated circuit package is shown. The wafer 12 is attached to the surface of the carrier substrate 10 by the adhesive layer 14; the solder ball 16 is formed on the surface of the carrier substrate 10, and is electrically connected to a printed circuit board 18; and the package resin 20 covers the wafer 12. Since both the encapsulating resin 20 and the carrier substrate 10 are not good thermal conductive materials, the heat generated by the wafer 12 is limited to the integrated circuit package, resulting in shortening the life of the integrated circuit or abnormal operation of the integrated circuit. . Accordingly, there is a need for an improved integrated circuit package and heat dissipation method to improve the heat dissipation efficiency of the integrated circuit package. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an package body of an integrated circuit. The package body of the integrated circuit includes: a carrier substrate having a first surface, a second surface, and at least one hole, wherein the hole penetrates the carrier substrate; and a heat dissipation layer formed in the hole and extending in the hole The carrier substrate is on the first surface and the second surface.

Client’s Docket No.:93038 TT5s Docket No:0548-A50789-TW/fmal/yungchieh/August 22, 2006 5 200849500 上述積體電路的封裝體更包含―晶片，設置於 基板的該第二表面上；-掩模層’形成於該承载基板的 该第二表面上；一黏著層’形成該掩模層與該晶片之間。 上述積體電路的封裝體更包含—導電球體，形成於 該第-表面的該散熱層上方’且熱連接一印刷電路板。 據此’晶片所產生的熱可藉由散熱層，將熱從承載基板 ，第二表面，過孔洞傳遞至承載基板的第一表面。接 著’傳遞至第-表面的熱再藉由導電球體傳遞至印刷電 路板上。因此，可提昇㈣f路封裝體的散熱效率及延 長積體電路封裝體的壽命。 本發之另一目的係提供一種積體電路封裝體的散埶 方法。上述積體電路封裝體的散熱方法包含：提供具有' 至少-孔洞的-承載基板，其中該孔洞貫穿於該承載基 板之中；形成一散熱層於該孔洞之中，且延伸於該承載 ^板的第-表面及第二表面上；以及設置—晶片於該承 載基板的該第二表面上’藉由該散熱層傳遞該晶片所產 生的熱，穿過該孔洞至該承載基板的該第一表面上。 、上述積體電路封裝體的散熱方法更包含形成一導電 球體於該第一表面上的該散熱層上，且藉由導電球體將 傳遞至該第一表面的熱，傳遞至一印刷電路板。 【實施方式】 接下來，將詳細說明本發明之較佳實施例及其製作的 方，。然而，可以了解的是，本發明提供許多可實施於廣 ，多樣之應用領域的發明概念。用來說明的具實施例，僅 疋利用本發明概念之具體實施方式的說明，並不限制本發Client's Docket No.: 93038 TT5s Docket No: 0548-A50789-TW/fmal/yungchieh/August 22, 2006 5 200849500 The package of the above integrated circuit further includes a "wafer, which is disposed on the second surface of the substrate; A mold layer 'is formed on the second surface of the carrier substrate; an adhesive layer' forms between the mask layer and the wafer. The package of the integrated circuit further includes a conductive ball formed over the heat dissipation layer of the first surface and thermally connected to a printed circuit board. According to this, the heat generated by the wafer can transfer heat from the carrier substrate, the second surface, and the via hole to the first surface of the carrier substrate by the heat dissipation layer. The heat transferred to the first surface is then transferred to the printed circuit board by the conductive balls. Therefore, the heat dissipation efficiency of the (four) f-channel package can be improved and the life of the integrated circuit package can be extended. Another object of the present invention is to provide a method of diverging an integrated circuit package. The heat dissipation method of the integrated circuit package includes: providing a carrier substrate having at least a hole, wherein the hole penetrates through the carrier substrate; forming a heat dissipation layer in the hole and extending the carrier plate On the first surface and the second surface; and disposing a wafer on the second surface of the carrier substrate, 'heat generated by transferring the wafer through the heat dissipation layer, passing through the hole to the first of the carrier substrate On the surface. The heat dissipation method of the integrated circuit package further includes forming a conductive ball on the heat dissipation layer on the first surface, and transmitting the heat transferred to the first surface by the conductive ball to a printed circuit board. [Embodiment] Next, a preferred embodiment of the present invention and a method of fabricating the same will be described in detail. However, it will be appreciated that the present invention provides many inventive concepts that can be implemented in a wide variety of applications. The embodiments used for the description only use the description of the specific embodiments of the inventive concept, and do not limit the present invention.

Clients Docket N〇.：93038 H s Docket No:0548-A50789 -TW/fmal/yungchieh/August 22, 2006 6 200849500 明的範圍。 第2A〜2F圖顯示根據本發明之實施例之製作積體電 路封裝體的剖面圖。第2A圖係顯示具有開口 42的承載 基板40，開口 42可以是位於承載基板40的中央部位。 形成多數孔洞44於上述承載基板40，且孔洞44貫穿承 載基板40，如第2B圖所示。其中第2B圖係在第2A圖 中A至A5線的剖面圖。 在一較佳實例中，承載基板40可以是包含玻璃纖維 及環氧樹脂的軟性印刷電路板。孔洞44形成的方式可以 是機械式的鑽孔、雷射光燒孔或電漿乾式蝕孔。 在第2C圖中，形成一散熱層46於孔洞之中，且散熱 層46延伸至承載基板40的一第一表面41及一第二表面 43。在一較佳實施例中，散熱層46例如可以是銅、金、 銀、銘或具有南熱傳導係數的材質。 在一較佳實施例中，形成散熱層46的方式可以是利 用電鍍在孔洞44的侧壁形成散熱層46。接著在承載基板 40的第一表面41及第二表面43上形成散熱層46。上述 在第一表面41及第二表面43形成散熱層46的方式可以 是物理氣相沈積（physical vapor deposition)、化學氣相沈 積（chemical vapor deposition)或一般習知的方式，接著再 以微影蝕刻的方式圖案化散熱層46。在另一實施例中， 第二表面43上的散熱層46也可以不圖案化，以增加與熱 的接觸面積，進而提昇散熱效率。 如第2D圖所示，接著形成一接合墊48於承載基板 40之上表面的散熱屠46上。在一較佳實例中，接合墊48 可以是，但不侷限於銅及其相似物。塗佈一掩模層50於Clients Docket N〇.:93038 H s Docket No:0548-A50789 -TW/fmal/yungchieh/August 22, 2006 6 200849500 The scope of the description. 2A to 2F are cross-sectional views showing the fabrication of an integrated circuit package in accordance with an embodiment of the present invention. Fig. 2A shows a carrier substrate 40 having an opening 42 which may be located at a central portion of the carrier substrate 40. A plurality of holes 44 are formed in the carrier substrate 40, and the holes 44 are inserted through the carrier substrate 40 as shown in Fig. 2B. Fig. 2B is a cross-sectional view taken along line A to line A5 in Fig. 2A. In a preferred embodiment, carrier substrate 40 can be a flexible printed circuit board comprising fiberglass and epoxy. The holes 44 may be formed by mechanical drilling, laser light burning or plasma dry etching. In FIG. 2C, a heat dissipation layer 46 is formed in the hole, and the heat dissipation layer 46 extends to a first surface 41 and a second surface 43 of the carrier substrate 40. In a preferred embodiment, the heat dissipation layer 46 can be, for example, copper, gold, silver, or a material having a south heat transfer coefficient. In a preferred embodiment, the heat dissipation layer 46 may be formed by electroplating forming a heat dissipation layer 46 on the sidewall of the hole 44. A heat dissipation layer 46 is then formed on the first surface 41 and the second surface 43 of the carrier substrate 40. The manner of forming the heat dissipation layer 46 on the first surface 41 and the second surface 43 may be physical vapor deposition, chemical vapor deposition or a conventional method, followed by lithography. The heat dissipation layer 46 is patterned in an etched manner. In another embodiment, the heat dissipation layer 46 on the second surface 43 may also be unpatterned to increase the contact area with heat, thereby improving heat dissipation efficiency. As shown in Fig. 2D, a bonding pad 48 is then formed on the heat sink 46 on the upper surface of the carrier substrate 40. In a preferred embodiment, bond pads 48 can be, but are not limited to, copper and the like. Applying a mask layer 50 to

Client’s Docket No.:93038 TT^ Docket No:0548-A50789-TW/final/yungchieh/August 22, 2006 7 200849500 承載基板40的第一表面41及第二表面43，且暴露接合 墊48。其中掩模層50可保護散熱層46而避免碰撞刮傷。 掩模層50可以是，但不侷限於熱烘烤硬化型環氧化樹脂 (Thermal Cured Epoxies)或紫外光烘烤硬化型丙稀酸酯 (UV Cured Acrylates)的綠漆焊料掩模（solder mask) 〇 在第2E圖中，以黏著層52將晶片54貼附於承載基 板40的第二表面43上，其中該黏著層52可以是，但不 侷限於環氧樹脂（Epoxy)。 接下來，參閱第2F圖，形成例如焊錫球56的導電體 球體於接合墊48上，且熱連接一印刷電路板58，以將内 部的熱藉由焊錫球56傳遞至印刷電路板58上，如箭頭 60所示。 第3圖係顯示根據本發明之實施例之積體電路封裝體 100的剖面圖。提供具有孔洞44的承載基板40，其中孔 洞44設置的位置可以是相鄰於焊錫球56的周圍。藉由黏 著層52將晶片54貼附於承載基板40上，且以金屬導線 電性連接晶片54與承載基板40。 接著，一封裝樹脂62包覆上述晶片54，以避免外界 的水氣或外力造成積體電路晶片的損壞。一散熱層46形 成於承載基板40的孔洞44之中，且延伸於承載基板40 的上下表面，上述散熱層46藉由焊錫球56熱連接印刷電 路板58。 值得注意的是，孔洞44設置的方式可以是選擇非傳 遞電子訊號之焊錫球56的周圍。也就是說，本發明之一 實施例可以是將孔洞44設置於非傳遞電子訊號的焊鍚球 的周圍，以及形成散熱層46於上述孔洞44之中，且延伸Client's Docket No.: 93038 TT^ Docket No: 0548-A50789-TW/final/yungchieh/August 22, 2006 7 200849500 The first surface 41 and the second surface 43 of the substrate 40 are carried, and the bonding pads 48 are exposed. The mask layer 50 protects the heat dissipation layer 46 from collision scratches. The mask layer 50 may be, but not limited to, a thermal paste epoxidized resin (Thermal Cured Epoxies) or a UV Cured Acrylates green paint solder mask. In FIG. 2E, the wafer 54 is attached to the second surface 43 of the carrier substrate 40 by an adhesive layer 52, which may be, but not limited to, epoxy resin (Epoxy). Next, referring to FIG. 2F, a conductor ball such as solder ball 56 is formed on the bonding pad 48, and a printed circuit board 58 is thermally connected to transfer the internal heat to the printed circuit board 58 by the solder ball 56. As indicated by arrow 60. Figure 3 is a cross-sectional view showing an integrated circuit package 100 in accordance with an embodiment of the present invention. A carrier substrate 40 having a hole 44 is provided, wherein the hole 44 is disposed adjacent to the periphery of the solder ball 56. The wafer 54 is attached to the carrier substrate 40 by the adhesive layer 52, and the wafer 54 and the carrier substrate 40 are electrically connected by metal wires. Next, an encapsulating resin 62 covers the wafer 54 to prevent damage of the integrated circuit wafer due to external moisture or external force. A heat dissipation layer 46 is formed in the hole 44 of the carrier substrate 40 and extends over the upper and lower surfaces of the carrier substrate 40. The heat dissipation layer 46 is thermally connected to the printed circuit board 58 by solder balls 56. It should be noted that the holes 44 may be arranged in such a manner as to select the periphery of the solder balls 56 that are not transmitting electronic signals. That is, an embodiment of the present invention may be such that the hole 44 is disposed around the solder ball of the non-transferred electronic signal, and the heat dissipation layer 46 is formed in the hole 44 and extends.

Client’s Docket No.:93038 TT's Docket No:0548-A50789-TW/final/yungchieh/August 22, 2006 8 200849500 於承載基板40第一表面41及第二表面43，藉以改善積 體電路封裝體100的散熱效率。 如第3圖所示，在一較佳實施例中，當晶片54在運 作時，可藉由金屬導線57將電子訊號傳遞至承載基板 40，接著由傳遞電子訊號的焊錫球55傳遞至印刷電板 5 8。同時，在晶片54運作時所產生熱，可以藉由黏著層 52、掩模層50把熱傳遞至承載基板40之第二表面43上 的散熱層46。接著，藉由散熱層46將晶片54所產生的 熱穿過孔洞44傳遞至承載基板40的第一表面41之非傳 遞電子訊號的焊錫球56，如箭頭60所示。最後，再由非 傳遞電子訊號的焊錫球56將熱傳遞至印刷電路板58上， 藉以改善積體電路封裝體的散熱效率。 值得注意的是，散熱層可以是與承載基板表面上電性 連接接合墊之間的線路相同材質，因此，不需要額外的材 料成本，即可達到改善積體電路封裝體的散熱效率。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作此許之更動與潤飾，因此本發明之保護 # V 範圍當視後附之申請專利範圍所界定為準。Client's Docket No.: 93038 TT's Docket No: 0548-A50789-TW/final/yungchieh/August 22, 2006 8 200849500 The first surface 41 and the second surface 43 of the carrier substrate 40 are used to improve the heat dissipation of the integrated circuit package 100. effectiveness. As shown in FIG. 3, in a preferred embodiment, when the wafer 54 is in operation, the electronic signal can be transmitted to the carrier substrate 40 by the metal wire 57, and then transferred to the printed battery by the solder ball 55 that transmits the electronic signal. Board 5 8. At the same time, heat generated during the operation of the wafer 54 can be transferred to the heat dissipation layer 46 on the second surface 43 of the carrier substrate 40 by the adhesive layer 52 and the mask layer 50. Next, the heat generated by the wafer 54 is transferred through the holes 44 to the solder balls 56 of the first surface 41 of the carrier substrate 40 by the heat dissipation layer 46, as indicated by the arrow 60. Finally, heat is transferred to the printed circuit board 58 by the solder balls 56 which are not transmitted electronic signals, thereby improving the heat dissipation efficiency of the integrated circuit package. It should be noted that the heat dissipation layer may be the same material as the line between the electrical connection pads on the surface of the carrier substrate, so that the heat dissipation efficiency of the integrated circuit package can be improved without additional material cost. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is to be understood that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The protection of the invention # V is defined in the scope of the patent application.

Client’s Docket No.:93038 TT5s Docket No:0548-A50789-TW/final/yungchieh/August 22, 2006 9 200849500 【圖式簡單說明】 第1圖顯示習知積體電路封裝體的剖面圖； 第2A〜2F圖顯示根據本發明之一實施例之製作積體 電路封裝體的剖面圖； 第3圖顯示根據本發明之實施例之積體電路封裝體的 剖面圖。 【主要元件符號說明】 10〜承載基板； 12〜晶片， 14〜黏著層； 16〜焊錫球； 18〜印刷電路板； 20〜封裝樹脂； 40〜承載基板； 41〜第一表面； 42〜開口； 43〜第二表面； 44〜孔洞； 46〜散熱層； 48〜接合墊； 50〜掩模層； 52〜黏著層； 54〜晶片； 55〜焊錫球； 56〜焊錫球； 57〜金屬導線； 58〜印刷電路板； 60〜熱傳導的方向； 62〜封裝樹脂； 100〜積體電路封裝體。Client's Docket No.:93038 TT5s Docket No:0548-A50789-TW/final/yungchieh/August 22, 2006 9 200849500 [Simplified Schematic] Figure 1 shows a cross-sectional view of a conventional integrated circuit package; 2A~ 2F is a cross-sectional view showing the fabrication of an integrated circuit package in accordance with an embodiment of the present invention; and FIG. 3 is a cross-sectional view showing the integrated circuit package in accordance with an embodiment of the present invention. [Main component symbol description] 10~bearing substrate; 12~ wafer, 14~ adhesive layer; 16~ solder ball; 18~ printed circuit board; 20~ package resin; 40~ carrier substrate; 41~ first surface; 43~ second surface; 44~ hole; 46~ heat sink layer; 48~ bond pad; 50~ mask layer; 52~ adhesive layer; 54~ wafer; 55~ solder ball; 56~ solder ball; ; 58 ~ printed circuit board; 60 ~ heat conduction direction; 62 ~ encapsulation resin; 100 ~ integrated circuit package.

Client’s Docket No.:93038 TT’s Docket No:0548-A50789-TW/final/yungchieh/August 22, 2006Client’s Docket No.:93038 TT’s Docket No:0548-A50789-TW/final/yungchieh/August 22, 2006

Claims (1)

200849500 十、申請專利範圍： L一種積體電路的封裝體，包含： 一承載基板，具有一第一表面、一第二表面以及至少 一孔洞，其中該孔洞貫穿該承載基板；以及 ^ 一散熱層，形成該孔洞之中，且延伸於該承載基板的 第一表面及第二表面上。 5 1如申請專利範圍第1項所述之積體電路的封裝體， 更包含一晶片，設置於該承載基板的該第二表面上。 3·如申請專利範圍第2項所述之積體電路的封裝體， 更包含： 一掩模層’形成於該承載基板的該第二表面上；以及 一黏著層，形成於該掩模層與該晶片之間。 4·如申請專利範圍第2項所述之積體電路的封裝體， 更包含： 一導電球體，形成於該第一表面的該散熱層上方，且 熱連接一印刷電路板。 5·如申請專利範圍第2項所述之積體電路的封裝體， 更包含一樹脂，包覆該積體電路。 6·如申請專利範圍第4項所述之積體電路的封裝體， 其中該孔洞位於該導電球體周圍。 7·如申請專利範圍第6項所述之積體電路的封裝體， 其中該導電球體包含非傳遞電子訊號的該導電球體。 8·如申請專利範圍第1項所述之積體電路的封裝體·， 其中該散熱層包含銅。 9·如申請專利範圍第1項所述之積體電路的封裝體， 其中该承载基板包含至少一玻璃纖維及一環氧樹脂。 Clint’s Docket Νο·:93〇38 Docket No-〇548-A50789-TW/fmal/yungchieh/August 22, 2006 ^ 200849500 10. 如申請專利範圍第4項所述之積體電路的封裝 體，其中該導電球體包含錫。 11. 如申專利範圍第2項所述之積體電路的封裝體， 更包含一金屬導線，電性連接該晶片與該承載基板。 12. —種積體電路封裝體的散熱方法，包括： 提供具有至少一孔洞的一承載基板，其中該孔洞貫穿 於該承載基板之中； 形成一散熱層於該孔洞之中，且延伸於該承載基板的 第一表面及第二表面上； ， 設置一晶片於該承載基板的該第二表面上，藉由該散 熱層傳遞該晶片所產生的熱，穿過該孔洞至該承載基板該 第一表面上；以及 形成一導電球體於該第一表面上的該散熱層上，藉以 將傳遞至該第一表面的熱，傳遞至一印刷電路板。 13. 如申請專利範圍第12項所述之積體電路封裝體的 散熱方法，更包括： 形成一掩模層於該承載基板的該第二表面及該散熱 層上；以及 i 形成一黏著層於該掩模層與該晶片之間，藉以將該晶 片所產生的熱，經該黏著層及該掩模層傳遞至該承載基板 的該第二表面上。 14. 如申請專利範圍第12項所述之積體電路封裝體的 散熱方法，更包括形成一樹脂包覆該積體電路。 15. 如申請專利範圍第12項所述之積體電路封裝體的 散熱方法，更包括設置一金屬導線，電性連接該晶片與該 承載基板。 Client’s Docket No.:93038 TT5s Docket No:0548-A50789-TW/final/yungchieh/August 22, 2006 12 200849500 16. 如申請專利範圍第12項所述之積體電路封裝體的 散熱方法，其中該散熱層包含銅、金、銀或鋁。 17. 如申請專利範圍第12項所述之積體電路封裝體的 散熱方法，其中該導電球體包含錫。 18. 如申請專利範圍第12項所述之積體電路封裝體的 散熱方法，其中該孔洞位於該導電球體周圍。 19. 如申請專利範圍第18項所述之積體電路封裝體的 散熱方法，其中該導電球體包含非傳遞電子訊號的該導電 球體。 Client’s Docket No.:93038 13 TT5s Docket No:0548-A50789-TW/final/yungchieh/August 22, 2006200849500 X. Patent application scope: L. A package body of an integrated circuit, comprising: a carrier substrate having a first surface, a second surface and at least one hole, wherein the hole penetrates the carrier substrate; and a heat dissipation layer Forming the hole and extending over the first surface and the second surface of the carrier substrate. The package of the integrated circuit of claim 1, further comprising a wafer disposed on the second surface of the carrier substrate. 3. The package of the integrated circuit of claim 2, further comprising: a mask layer formed on the second surface of the carrier substrate; and an adhesive layer formed on the mask layer Between the wafer and the wafer. 4. The package of the integrated circuit of claim 2, further comprising: a conductive ball formed over the heat dissipation layer of the first surface and thermally connected to a printed circuit board. 5. The package of the integrated circuit according to claim 2, further comprising a resin covering the integrated circuit. 6. The package of the integrated circuit of claim 4, wherein the hole is located around the conductive sphere. 7. The package of the integrated circuit of claim 6, wherein the conductive sphere comprises the conductive sphere that does not transmit an electronic signal. 8. The package of the integrated circuit according to claim 1, wherein the heat dissipation layer comprises copper. 9. The package of the integrated circuit of claim 1, wherein the carrier substrate comprises at least one glass fiber and an epoxy resin. Clint's Docket Νο·:93〇38 Docket No-〇548-A50789-TW/fmal/yungchieh/August 22, 2006 ^ 200849500 10. The package of the integrated circuit of claim 4, wherein the conductive The sphere contains tin. 11. The package of the integrated circuit of claim 2, further comprising a metal wire electrically connecting the wafer to the carrier substrate. 12. The method of dissipating heat of an integrated circuit package, comprising: providing a carrier substrate having at least one hole, wherein the hole penetrates through the carrier substrate; forming a heat dissipation layer in the hole and extending from the hole Carrying a first surface and a second surface of the substrate; and disposing a wafer on the second surface of the carrier substrate, wherein the heat generated by the wafer is transferred by the heat dissipation layer, and the hole is passed through the hole to the carrier substrate And forming a conductive sphere on the heat dissipation layer on the first surface, thereby transferring heat transferred to the first surface to a printed circuit board. 13. The method of dissipating heat of an integrated circuit package according to claim 12, further comprising: forming a mask layer on the second surface of the carrier substrate and the heat dissipation layer; and i forming an adhesive layer Between the mask layer and the wafer, heat generated by the wafer is transferred to the second surface of the carrier substrate via the adhesive layer and the mask layer. 14. The method of dissipating heat of an integrated circuit package according to claim 12, further comprising forming a resin-coated integrated circuit. 15. The method of dissipating heat of an integrated circuit package according to claim 12, further comprising providing a metal wire electrically connecting the wafer to the carrier substrate. Client's Docket No.: 93038 TT5s Docket No: 0548-A50789-TW/final/yungchieh/August 22, 2006 12 200849500. The heat dissipation method of the integrated circuit package according to claim 12, wherein the heat dissipation method The layer contains copper, gold, silver or aluminum. 17. The method of dissipating heat of an integrated circuit package according to claim 12, wherein the conductive sphere comprises tin. 18. The method of dissipating heat of an integrated circuit package according to claim 12, wherein the hole is located around the conductive ball. 19. The method of dissipating heat of an integrated circuit package according to claim 18, wherein the conductive sphere comprises the conductive sphere that does not transmit an electronic signal. Client’s Docket No.:93038 13 TT5s Docket No:0548-A50789-TW/final/yungchieh/August 22, 2006
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI387081B (en) * 2009-05-08 2013-02-21 Chenming Mold Ind Corp Integrated circuit package structure and packaging method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI387081B (en) * 2009-05-08 2013-02-21 Chenming Mold Ind Corp Integrated circuit package structure and packaging method

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