TW202345333A - Semiconductor device with substrate for electrical connection - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate, a first electronic component, a second electronic component, a bonding wire, and an encapsulant. The substrate has a lower surface and an upper surface opposite to the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component and the substrate and extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. The second electronic component has an active surface facing the substrate. The encapsulant is disposed on the upper surface of the substrate. The encapsulant extends within the substrate and encapsulates the bonding wire.

Description

Semiconductor component with electrical connection base

This application claims priority to U.S. Patent Application Nos. 17/742,549 and 17/743,044 (that is, the priority date is "May 12, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device, and in particular to a semiconductor device including a substrate having a bonding wire passing therethrough.

With the rapid development of the electronics industry, integrated circuits (ICs) have achieved high performance and miniaturization. Technological advances in integrated circuit materials and design have produced successive generations of integrated circuits, each of which has smaller, more complex circuits.

Many techniques have been developed for integrating two electronic components. For example, electronic components can be stacked vertically to reduce the size of semiconductor components. Current stacks of electronic components can utilize conductive posts of varying lengths, with each conductive post connecting a corresponding electronic component to a substrate. This structure may require multiple semiconductor fabrication processes, thus increasing production costs. Therefore, a new semiconductor component and preparation method are needed to improve such problems.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a semiconductor device. The semiconductor component includes a substrate, a first electronic component, a second electronic component, a bonding wire and a package. The base has a lower surface and an upper surface opposite to the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component to the substrate and extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. The second electronic component has an active surface facing the substrate. The package is disposed on the upper surface of the substrate. The encapsulant extends within the substrate and encapsulates the bond wire.

Another aspect of the present disclosure provides another semiconductor device. The semiconductor component includes a substrate, a first electronic component, a second electronic component, a bonding wire and a plurality of conductive pillars. The base has a lower surface, an upper surface opposite to the lower surface, and an inner surface extending between the upper surface and the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component to the substrate and faces the inner surface of the substrate. The bonding wire extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. Each conductive pillar is disposed on the upper surface of the substrate and electrically connects the second electronic component to the substrate.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate with a lower surface and an upper surface opposite to the lower surface. The preparation method also includes forming an opening extending between the upper surface and the lower surface of the substrate. The preparation method also includes attaching a first electronic component to the upper surface of the substrate. An active surface of the first electronic component faces the upper surface of the substrate. In addition, the preparation method further includes attaching a second electronic component to the first electronic component. An active surface of the second electronic component faces the upper surface of the substrate. The preparation method also includes forming a bonding wire on the substrate. The bonding wire passes through the opening of the substrate and electrically connects the substrate to one of the first electronic component or the second electronic component.

In an embodiment of the present disclosure, the substrate has an opening, and the bonding wire passes through the opening. The bonding wire electrically connects the lower electronic component to the substrate (or connects the upper electronic component to the substrate). Therefore, the semiconductor preparation process for forming the conductive pillars can be omitted, thereby reducing costs and increasing device yield.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment, even if they share the same reference number.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections, these elements, elements, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and "includes", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other Characteristic, integer, step, operation, element, component, or group thereof.

1A and 1B illustrate a semiconductor device 100a according to some embodiments of the present disclosure, wherein FIG. 1A is a top view, and FIG. 1B is a cross-sectional view along line A-A’ shown in FIG. 1A.

In some embodiments, semiconductor element 100a may include substrate 10. In some embodiments, the substrate 10 may be or include, for example, a printed circuit board such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate.

In some embodiments, substrate 10 may include surface 10s1 and surface 10s2 opposite surface 10s1. In some embodiments, surface 10s1 may also be referred to as the lower surface. In some embodiments, surface 10s2 may also be referred to as the upper surface.

In some embodiments, substrate 10 may include conductive pads, lines, vias, layers, or other interconnections. For example, substrate 10 may include one or more transmission lines (eg, communication wires) and one or more ground lines and/or ground planes. For example, substrate 10 may include one or more conductive pads (not shown) proximate, adjacent, or embedded and exposed at surface 10s1 and/or surface 10s2 of substrate 10 . That is to say, both the surfaces 10s1 and 10s2 of the substrate 10 can be used to electrically connect with other electronic components.

In some embodiments, substrate 10 may define opening 10r1. The opening 10r1 may extend between the surfaces 10s1 and 10s2 of the substrate 10 . The opening 10r1 can penetrate the substrate 10. Although the example opening 10r1 of FIG. 1A has a rectangular profile, 10r1 may have other profiles, such as a circular profile, an elliptical profile, a trapezoidal profile, or other suitable profiles based on design requirements. Substrate 10 may have surface 10s3 defining opening 10r1. Surface 10s3 may extend between surfaces 10s1 and 10s2 of substrate 10 . In some embodiments, surface 10s3 may also be referred to as the medial surface. In some embodiments, the inner surface may be surrounded by an outer surface (not labeled in the figure) of the substrate 10 .

In some embodiments, semiconductor component 100a may include electronic component 20. In some embodiments, the electronic component 20 may be disposed on the surface 10s2 of the substrate 10. In some embodiments, electronic device 20 may include memory devices, such as dynamic random access memory (DRAM) devices, one-time programming (OTP) memory devices, static random access memory (SRAM) devices, or other Suitable memory components. In some embodiments, electronic components 20 may include logic components (e.g., system on a chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), Radio frequency (RF) components, sensor components, microelectromechanical systems (MEMS) components, signal processing components (eg, digital signal processing (DSP) components), front-end components (eg, analog front-end (AFE) components), or other components.

The electronic component 20 may have a surface 20s1 and a surface 20s2 opposite the surface 20s1. In some embodiments, surface 20s1 may also be referred to as an active surface. In some embodiments, surface 20s2 may also be referred to as the back surface. In some embodiments, surface 20s1 of electronic component 20 may face surface 10s2 of substrate 10 . As used herein, the term "active surface" may refer to a surface on which terminals are positioned to transmit and/or receive signals. In some embodiments, surface 20s1 of electronic component 20 may face surface 10s2 of substrate 10 . The electronic component 20 may include a surface 20s3 and a surface 20s4 opposite the surface 20s3. Surface 20s3 may extend between surfaces 20s1 and 20s2. Surface 20s4 may extend between surfaces 20s1 and 20s2. In some embodiments, each of surfaces 20s3 and 20s4 may also be referred to as a side of electronic component 20 .

In some embodiments, electronic component 20 may include terminal 21. The terminal 21 may be provided on the surface 20s1 of the electronic component 20. The terminal 21 may be, for example, a conductive pad. In some embodiments, terminal 21 may include a metal such as copper (Cu), tungsten (W), silver (Ag), gold (Au), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium ( Os), ruthenium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof or other suitable materials.

In some embodiments, semiconductor element 100a may include bond wires 22. In some embodiments, the bonding wire 22 has a first end (not annotated in the figure) bonded to the surface 10s1 of the substrate 10 and a second end (not annotated in the figure) bonded to the surface 20s1 of the electronic component 20 ). In some embodiments, bond wire 22 may be bonded to terminal 21 of electronic component 20 . In some embodiments, the bonding wire 22 may pass through the opening 10r1 of the substrate 10 . In some embodiments, bond wire 22 may face surface 10s3 of substrate 10. In some embodiments, bond wire 22 may penetrate substrate 10 . In some embodiments, bonding wire 22 may include a metal such as copper (Cu), silver (Ag), gold (Au), nickel (Ni), aluminum (Al), alloys thereof, combinations thereof, or other suitable materials. .

In some embodiments, semiconductor component 100a may include electronic component 30. In some embodiments, the electronic component 30 may be disposed on the surface 10s2 of the substrate 10. In some embodiments, electronic component 30 may be located on electronic component 20 . In some embodiments, electronic component 30 may be stacked on electronic component 20 . In some embodiments, the electronic component 30 may be disposed on the surface 20s2 of the electronic component 20. In some embodiments, the electronic device 30 may include a memory device such as a dynamic random access memory (DRAM) device, a one-time programming (OTP) memory device, a static random access memory (SRAM) device, or other Suitable memory components. In some embodiments, electronic components 30 may include logic components (e.g., system on a chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), Radio frequency (RF) components, sensor components, microelectromechanical systems (MEMS) components, signal processing components (eg, digital signal processing (DSP) components), front-end components (eg, analog front-end (AFE) components), or other components.

The electronic component 30 may have a surface 30s1 and a surface 30s2 opposite the surface 30s1. In some embodiments, surface 30s1 may also be referred to as an active surface. In some embodiments, surface 30s2 may also be referred to as the back surface. In some embodiments, surface 30s1 of electronic component 30 may face surface 10s2 of substrate 10 . In some embodiments, surface 30s1 of electronic component 30 may face surface 20s2 of electronic component 20 . The electronic component 30 may have a surface 30s3 and a surface 30s4 opposite the surface 30s3. Surface 30s3 may extend between surfaces 30s1 and 30s2. Surface 30s4 may extend between surfaces 30s1 and 30s2. In some embodiments, each of surfaces 30s3 and 30s4 may also be referred to as a side of electronic component 30 .

As shown in FIG. 1A, electronic component 20 may have surface area R1, and electronic component 30 may have surface area R2. In some embodiments, surface area R1 may be substantially equal to surface area R2. In some embodiments, the geometric center of electronic component 20 (not annotated in the figure) is offset from the geometric center of electronic component 30 . In some embodiments, a portion of surface 20s2 of electronic component 20 may be exposed from electronic component 30. In some embodiments, the electronic component 30 may vertically overlap the opening 10r1 of the substrate 10 . In some embodiments, the electronic component 30 may cover the opening 10r1 of the substrate 10 .

In some embodiments, electronic component 30 may include circuit layer 31 . The circuit layer 31 may be disposed on the surface 30s1 of the electronic component 30. Circuit layer 31 may include, for example, a redistribution layer having lines and conductive vias within one or more dielectric layers.

In some embodiments, semiconductor element 100a may include conductive pillars 32. In some embodiments, the conductive pillars 32 may be disposed on the surface 30s1 of the electronic component 30 . In some embodiments, the conductive pillars of electronic component 30 may be configured to electrically connect electronic component 30 to substrate 10 . In some embodiments, conductive pillars 32 may include metals such as copper (Cu), silver (Ag), gold (Au), nickel (Ni), aluminum (Al), alloys thereof, combinations thereof, or other suitable materials.

As shown in FIG. 1A , the conductive pillar 32 may face the surface 20s3 of the electronic component 20 . In some embodiments, surface 20s4 of electronic component 20 may face away from conductive posts 32.

In some embodiments, semiconductor element 100a may include electrical connections 33. Electrical connections 33 may be provided between conductive posts 32 and substrate 10 . The electrical connection 33 may include a soldering material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

In some embodiments, semiconductor component 100a may include package 40. In some embodiments, the encapsulation 40 may be disposed on the surface 10s2 of the substrate 10. In some embodiments, encapsulant 40 may cover surface 10s2 of substrate 10. In some embodiments, encapsulant 40 may cover a portion of surface 10s1 of substrate 10 . In some embodiments, a portion of surface 10s1 of substrate 10 may be exposed from encapsulation 40 . Encapsulation 40 may include insulating or dielectric materials. In some embodiments, the encapsulant 40 includes a molding material, which may include, for example, Novolac-based resin, epoxy-based resin, silicone-based resin, or other suitable encapsulants. Suitable fillers such as powdered SiO2 may also be included.

In some embodiments, encapsulation 40 may encapsulate electronic component 20 . In some embodiments, enclosure 40 may encapsulate electronic component 30 . In some embodiments, encapsulant 40 may encapsulate bond wire 22 . In some embodiments, encapsulant 40 may encapsulate conductive posts 32 . In some embodiments, enclosure 40 may encapsulate electrical connection 33 . In some embodiments, the encapsulant 40 may fill the opening 10r1 of the substrate 10 . In some embodiments, encapsulation 40 may protrude into substrate 10 . In some embodiments, the package 40 may have a portion 40p1 within the opening 10r1 of the substrate 10 . In some embodiments, portion 40p1 of encapsulation 40 may be surrounded by substrate 10. In some embodiments, portion 40p1 of encapsulation 40 may be surrounded by surface 10s3 of substrate 10. In some embodiments, portion 40p1 of encapsulation 40 may be in contact with surface 10s3 of substrate 10. In some embodiments, portion 40p1 of package 40 may vertically overlap electronic component 20. In some embodiments, portion 40p1 of package 40 may vertically overlap electronic component 30.

In some embodiments, the semiconductor device 100a may include adhesives 41 and 42. In some embodiments, adhesive 41 may be configured to attach electronic component 20 to surface 10s2 of substrate 10. In some embodiments, the adhesive 41 may be disposed between the surface 20s1 of the electronic component 20 and the surface 10s2 of the substrate 10 .

In some embodiments, adhesive 42 may be configured to attach electronic component 30 to surface 20s2 of electronic component 20. In some embodiments, the adhesive 42 may be disposed between the surface 20s2 of the electronic component 20 and the surface 30s2 of the electronic component 30. In some embodiments, a portion of circuit layer 31 may be covered by adhesive 42 . In some embodiments, a portion of circuit layer 32 may be exposed from adhesive 42 .

In some embodiments, semiconductor component 100a may include electrical connections 50. Electrical connections 50 may be provided on surface 10s1 of substrate 10 . In some embodiments, electrical connection 50 may be configured to electrically connect semiconductor component 100a with external components (not shown). In some embodiments, the electrical connection 50 may include a soldering material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

In a comparative example, the electronic components in the lower layer and the upper layer are electrically connected to the substrate through conductive pillars. The conductive pillars have different lengths. For example, shorter conductive posts attach lower-level electronic components to the substrate, while longer conductive posts attach upper-level electronic components to the substrate. The formation of conductive pillars on electronic components may require more semiconductor preparation processes, which may result in higher costs and relatively lower yields.

In the embodiment of the present disclosure, the substrate has an opening (eg 10r1), and the bonding wire (eg 22) passes through the opening. The bonding wire electrically connects the underlying electronic component (such as 20) to the substrate. The upper electronic component (such as 30) is electrically connected to the substrate through the conductive pillar (such as 32). Compared with the comparative example, only the upper electronic components require conductive pillars. Therefore, the semiconductor fabrication process of forming shorter conductive pillars can be omitted, thereby reducing costs and increasing device yield.

FIG. 2 is a top view illustrating a semiconductor device 100b according to some embodiments of the present disclosure. The semiconductor element 100b is similar to the semiconductor element 100a shown in FIG. 1A, and the differences therebetween will be described below.

As shown in Figure 2, electronic component 20 may have surface 20s5 extending between surfaces 20s3 and 20s4. Surface 20 s 5 may also be referred to as a side surface of electronic component 20 .

In some embodiments, conductive pillar 32 may include portions 32p1 and 32p2. In some embodiments, the portion 32p1 of the conductive pillar 32 may be disposed on the surface 20s3 of the electronic component 20. In some embodiments, portion 32p1 of conductive post 32 may face surface 20s3 of electronic component 20. In some embodiments, portion 32p2 of conductive post 32 may be disposed on surface 20s5 of electronic component 20. In some embodiments, portion 32p2 of conductive post 32 may face surface 20s5 of electronic component 20.

A portion of the surface 20 s5 of the electronic component 20 may not overlap the conductive pillars 32 . In some embodiments, conductive pillars 32 may be arranged in an L-shaped profile, an inverted L-shaped profile, or other suitable profile.

Since there are more conductive pillars (eg, portion 32p2) connecting the electronic component 30 to the substrate 10, more input and/or output terminals can be utilized to transmit or receive signals, thus improving the performance of the semiconductor device 100b.

FIG. 3 is a cross-sectional view illustrating a semiconductor device 100c according to some embodiments of the present disclosure. The semiconductor element 100c is similar to the semiconductor element 100a shown in FIG. 1B, and the differences therebetween will be described below.

In some embodiments, surface area R3 of electronic component 30 may be different than surface area R1 of electronic component 20 . In some embodiments, surface area R3 of electronic component 30 may be larger than surface area R1 of electronic component 20 .

In some embodiments, conductive post 32 may include portion 32p3. In some embodiments, portions 32p1 and 32p3 of conductive pillars 32 may be disposed on opposite sides of electronic component 20 . In some embodiments, portion 32p3 of conductive post 32 may be disposed on surface 20s4 of electronic component 20. In some embodiments, portion 32p3 of conductive post 32 may face surface 20s4 of electronic component 20.

Since there are more conductive pillars (eg, portion 32p3) connecting the electronic component 30 to the substrate 10, more input and/or output terminals can be utilized to transmit or receive signals, thus improving the performance of the semiconductor device 100c.

FIG. 4 is a cross-sectional view illustrating a semiconductor device 100d according to some embodiments of the present disclosure. The semiconductor element 100d is similar to the semiconductor element 100a shown in FIG. 1B, and the differences therebetween will be described below.

In some embodiments, the substrate 10 may have an opening 10r2. The opening 10r2 may extend between the surfaces 10s1 and 10s2 of the substrate 10. In some embodiments, opening 10r2 may not vertically overlap electronic component 20.

In some embodiments, the electronic component 20 may be electrically connected to the substrate 10 through the conductive pillars 23 . In some embodiments, the conductive pillar 23 may be disposed between the surface 20s1 of the electronic component 20 and the surface 10s2 of the substrate 10 . In some embodiments, the conductive pillar 23 may include metal, such as copper (Cu), silver (Ag), gold (Au), nickel (Ni), aluminum (Al), alloys thereof, combinations thereof, or other suitable materials.

In some embodiments, the encapsulation 40 may have a portion 40p1 within the opening 10r2 of the substrate 10. In some embodiments, portion 40p1 of package 40 may not vertically overlap electronic component 20. In some embodiments, portion 40p1 of package 40 may vertically overlap electronic component 30.

In some embodiments, semiconductor element 100d may include electrical connections 24. Electrical connections 24 may be provided between conductive pillars 23 and substrate 10 . The electrical connection 24 may include a soldering material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

In some embodiments, electronic component 30 may include terminal 34. The terminal 34 may be provided on the surface 30s1 of the electronic component 30. The material of terminal 34 may be the same as or similar to the material of terminal 21 .

In some embodiments, semiconductor element 100d may include bond wires 35. In some embodiments, the bonding wire 35 has a first end (not annotated in the figure) bonded to the surface 10s1 of the substrate 10 and a second end (not annotated in the figure) bonded to the surface 30s1 of the electronic component 30 ). In some embodiments, bond wire 35 may be bonded to terminal 34 of electronic component 30 . In some embodiments, the bonding wire 35 may pass through the opening 10r2 of the substrate 10 . In some embodiments, bond wire 35 may face surface 10s3 of substrate 10. In some embodiments, the material of bond wire 35 may be the same as or similar to the material of bond wire 22 . In some embodiments, bond wire 35 may face surface 20s3 of electronic component 20. In some embodiments, surface 20s4 of electronic component 20 may face away from bond wire 35.

In the embodiment of the present disclosure, the substrate has an opening (eg, 10r2), and the bonding wire (eg, bonding wire 35) passes through the opening. The bonding wires electrically connect the upper electronic components (eg 30) to the substrate. The lower electronic components (such as 20) are electrically connected to the substrate through conductive pillars (such as 23). Compared with the comparative example, only the lower electronic components require conductive pillars. Therefore, the semiconductor manufacturing process of forming longer conductive pillars can be omitted, thereby reducing costs and increasing device yield.

FIG. 5 is a flowchart illustrating a method 200 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

The preparation method 200 begins with operation 202, where a substrate may be provided. The base may have a lower surface and an upper surface opposite to the lower surface. The substrate may include one or more conductive pads (not shown) proximate, adjacent, or embedded and exposed at the lower surface and/or the upper surface of the substrate.

The method 200 continues with operation 204 where an opening may be formed. In some embodiments, an etching process may be performed to form the opening. The opening may extend between the lower surface and the upper surface of the substrate. The etching process may include, for example, dry etching, wet etching, or other suitable processes.

The method 200 continues with operation 206 in which a first electronic component may be attached to the upper surface of the substrate. In some embodiments, the first electronic component may be attached to the upper surface of the substrate via an adhesive. In some embodiments, the first electronic component may be located directly above the opening in the substrate. The first electronic component may have an active surface and a back surface opposite to the active surface. In some embodiments, the first electronic component may have a terminal facing the upper surface of the substrate.

The method 200 continues with operation 208 , where a bonding wire may be formed to electrically connect the substrate to the first electronic component. In some embodiments, the bonding wire may have a first end bonded to the active surface of the first electronic component and a second end bonded to the lower surface of the substrate. In some embodiments, the bonding wire can pass through the opening of the substrate. In some embodiments, the bond wire can be bonded to the terminal of the first electronic component.

The method 200 continues with operation 210 where a second electronic component may be attached to the back surface of the first electronic component. In some embodiments, the second electronic component may be attached to the back surface of the first electronic component via an adhesive. In some embodiments, the second electronic component may be located directly above the opening in the substrate.

The second electronic component may have an active surface and a back surface opposite to the active surface. In some embodiments, a plurality of conductive pillars may be formed on the active surface of the second electronic component. The conductive pillar can electrically connect the second electronic component to the substrate. In some embodiments, the conductive pillars may be formed on the active surface of the second electronic component prior to attaching the second electronic component to the first electronic component.

The method 200 continues with operation 212, where a package may be formed on the upper surface of the substrate and electrical connections may be formed on the lower surface of the substrate, thereby creating a semiconductor device. In some embodiments, the encapsulant may encapsulate the first electronic component, the second electronic component and the conductive pillar.

In an embodiment of the present disclosure, the substrate has an opening, and the bonding wire passes through the opening. The bonding wires electrically connect the underlying electronic components to the substrate. The upper electronic components are electrically connected to the substrate through conductive pillars. Compared with the comparative example, only the upper electronic components require conductive pillars. As a result, the semiconductor manufacturing process of forming shorter conductive pillars on underlying electronic components can be eliminated, thus reducing costs and increasing component yield.

The preparation method 200 is only an example, and is not intended to limit the content of the present disclosure beyond what is explicitly stated in the patent application. Additional operations may be provided before, during, or after each operation of the preparation method 200, and some of the operations described may be replaced, eliminated, or reordered for other embodiments of the preparation method. In some embodiments, preparation method 200 may include further operations not depicted in Figure 5. In some embodiments, preparation method 200 may include one or more operations described in FIG. 5 .

6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A and 11B illustrate one or more methods of manufacturing semiconductor devices according to some embodiments of the present disclosure. Multiple preparation stages, of which Figures 6A, 7A, 8A, 9A, 10A and 11A are top views, while Figures 6B, 7B, 8B, 9B, 10B and 11B are along the lines of Figure 6A and Figure 11B respectively. Cross-sectional views along line AA′ shown in FIGS. 7A, 8A, 9A, 10A and 11A. In some embodiments, the semiconductor device 100a may be prepared by the operations described with respect to FIGS. 6A-11A and 6B-11B.

Referring to FIGS. 6A and 6B , a substrate 10 may be provided. The substrate 10 may have a surface 10s1 and a surface 10s2 opposite the surface 10s1. The substrate 10 may include one or more conductive pads (not shown) proximate to, adjacent to, or embedded and exposed at the surface 10s1 and/or the surface 10s2 of the substrate 10 .

Referring to FIGS. 7A and 7B , the opening 10r1 can be formed. In some embodiments, an etching process may be performed to form the opening 10r1. The opening 10r1 may extend between the surfaces 10s1 and 10s2 of the substrate 10 . The etching process may include, for example, dry etching, wet etching, or other suitable processes.

Referring to FIGS. 8A and 8B , the electronic component 20 may be attached to the surface 10s2 of the substrate 10 . In some embodiments, electronic component 20 may be attached to surface 10s2 of substrate 10 via adhesive 41. In some embodiments, the electronic component 20 may be located directly above the opening 10r1 of the substrate 10 . The electronic component 20 may have a surface 20s1 and a surface 20s2 opposite the surface 20s1. In some embodiments, electronic component 20 may have terminals 21 facing surface 10s2 of substrate 10.

Referring to FIGS. 9A and 9B , bonding wires 22 may be formed to electrically connect the substrate 10 and the electronic component 20 . In some embodiments, the bonding wire 22 may have a first end bonded to the surface 20s1 of the electronic component 20 and a second end bonded to the surface 10s1 of the substrate 10 . In some embodiments, the bonding wire 22 may pass through the opening 10r1 of the substrate 10 . In some embodiments, bond wire 22 may be bonded to terminal 21 of electronic component 20 .

Referring to FIGS. 10A and 10B , the electronic component 30 may be attached to the surface 20s2 of the electronic component 20 . In some embodiments, electronic component 30 may be attached to surface 20s2 of electronic component 20 via adhesive 42. In some embodiments, the electronic component 30 may be located directly above the opening 10r1 of the substrate 10 .

The electronic component 30 may have a surface 30s1 and a surface 30s2 opposite the surface 30s1. In some embodiments, a plurality of conductive pillars 32 may be formed on the surface 30s1 of the electronic component 30 . The conductive pillars 32 can electrically connect the electronic component 30 to the substrate 10 . In some embodiments, conductive pillars 32 may be formed on surface 30s1 of electronic component 30 before attaching electronic component 30 to electronic component 20.

The manufacturing technology of the conductive pillar 32 may include sputtering operation, electroplating operation and photolithography operation. For example, the manufacturing technology of the conductive pillar 32 may include a photolithography operation to form a patterned photosensitive layer (not shown) on the surface 30s1 of the electronic component 30, and forming a seed layer on the opening of the patterned photosensitive layer. The sputtering operation, the electroplating operation to form the conductive layer on the seed layer, and the removal of the patterned photosensitive layer.

Referring to FIGS. 11A and 11B , a package 40 may be formed on the surface 10s2 of the substrate 10, and an electrical connection 50 may be formed on the surface 10s1 of the substrate 10, thereby producing a semiconductor device 100a. Fabrication techniques for the package 40 may include molding operations. The molding flow may pass from the surface 10s2 of the substrate 10, through the opening 10r1, and into the surface 10s1 of the substrate 10. Therefore, the encapsulation 40 can encapsulate the electronic components 20 , 30 and the conductive pillars 32 .

In the embodiment of the present disclosure, the electronic component 20 and the substrate 10 can be electrically connected by using the bonding wire 22 . The electronic component 30 is electrically connected to the substrate 10 through the conductive pillars 32 . Compared with the comparative example, only the electronic component 30 requires conductive pillars. Therefore, the semiconductor preparation process of forming the conductive pillars on the electronic component 20 can be omitted, thereby reducing costs and increasing component yield.

FIG. 12 is a flowchart illustrating a method 300 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

The preparation method 300 begins with operation 302, which may be performed after operation 202. An opening defined by the base may be formed. The opening may extend between the lower surface and the upper surface of the substrate.

The method 300 continues with operation 304 where a first electronic component may be attached to the upper surface of the substrate. In some embodiments, the first electronic component may be attached to the upper surface of the substrate via an adhesive. In some embodiments, the first electronic component does not vertically overlap the opening of the substrate. In some embodiments, a plurality of conductive pillars may be formed on the active surface of the first electronic component. The conductive pillar can electrically connect the first electronic component to the substrate. In some embodiments, the conductive pillars may be formed on the active surface of the first electronic component prior to attaching the first electronic component to the substrate.

The method 300 continues with operation 306 where a second electronic component may be attached to the back surface of the first electronic component. In some embodiments, the second electronic component may be attached to the back surface of the first electronic component via an adhesive. In some embodiments, the second electronic component can be located directly above the opening in the substrate. The second electronic component may have a terminal on the active surface of the second electronic component.

The manufacturing method 300 continues with operation 308, where a bonding wire may be formed to electrically connect the substrate and the second electronic component. In some embodiments, the bonding wire may have a first end bonded to the active surface of the second electronic component and a second end bonded to the lower surface of the substrate. In some embodiments, the bonding wire can pass through the opening of the substrate. In some embodiments, the bond wire can be bonded to the terminal of the second electronic component.

The method 300 continues with operation 310, where a package may be formed on the upper surface of the substrate and electrical connections may be formed on the lower surface of the substrate, thereby creating a semiconductor device.

In embodiments of the present disclosure, bonding wires may be used to electrically connect the second electronic component to the substrate. The first electronic component is electrically connected to the substrate through the conductive pillar. Compared with the comparative example, only the first electronic component requires conductive pillars. Therefore, the semiconductor preparation process of forming the conductive pillars on the second electronic component can be omitted, thereby reducing costs and increasing component yield.

The preparation method 300 is merely an example and is not intended to limit the disclosure beyond what is expressly mentioned in the patent application. Additional operations may be provided before, during, or after each operation of the preparation method 300, and some of the operations described may be replaced, eliminated, or reordered for other embodiments of the preparation method. In some embodiments, preparation method 300 may include further operations not depicted in Figure 12. In some embodiments, preparation method 300 may include one or more operations depicted in Figure 12.

FIGS. 13 , 14 , 15 , 16 and 17 illustrate one or more manufacturing stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. In some embodiments, semiconductor element 100d may be prepared by the operations described with respect to FIGS. 13-17.

Referring to FIG. 13 , the operation may be performed after the operations of FIG. 6A and FIG. 6B . An opening 10r2 may be formed. The opening 10r2 may extend between the surfaces 10s1 and 10s2 of the substrate 10.

Referring to FIG. 14 , the electronic component 20 may be attached to the surface 10s2 of the substrate 10 . In some embodiments, electronic component 20 may be attached to surface 10s2 of substrate 10 via adhesive 41. In some embodiments, the electronic component 20 may not vertically overlap the opening 10r2 of the substrate 10. In some embodiments, a plurality of conductive pillars 23 may be formed on the surface 20s1 of the electronic component 20 . The conductive pillars 23 can electrically connect the electronic component 20 to the substrate 10 . In some embodiments, conductive pillars 23 may be formed on surface 20s1 of electronic component 20 before attaching electronic component 20 to substrate 10 . The preparation process of the conductive pillar 23 may be the same or similar to the preparation process of the conductive pillar 32 .

Referring to FIG. 15 , the electronic component 30 may be attached to the surface 20 s2 of the electronic component 20 . In some embodiments, electronic component 30 may be attached to surface 20s2 of electronic component 20 via adhesive 42. In some embodiments, the electronic component 30 may be located directly above the opening 10r2 of the substrate 10. The electronic component 30 may have terminals 34 on the surface 30s1 of the electronic component 30 .

Referring to FIG. 16 , bonding wires 35 may be formed to electrically connect the substrate 10 and the electronic component 30 . In some embodiments, the bonding wire 35 may have a first end bonded to the surface 30s1 of the electronic component 30 and a second end bonded to the surface 10s1 of the substrate 10 . In some embodiments, the bonding wire 35 may pass through the opening 10r2 of the substrate 10 . In some embodiments, bond wire 35 may be bonded to terminal 34 of electronic component 30 .

Referring to FIG. 17, a package 40 may be formed on the surface 10s2 of the substrate 10, and an electrical connection 50 may be formed on the surface 10s1 of the substrate 10, thereby producing a semiconductor element 100d.

In the embodiment of the present disclosure, the substrate has an opening (eg, 10r2), and the bonding wire (eg, eg, 35) passes through the opening. The bonding wires electrically connect the upper electronic components (eg 30) to the substrate. The lower electronic components (such as 20) are electrically connected to the substrate through conductive pillars (such as 23). Compared with the comparative example, only the lower electronic components require conductive pillars. Therefore, the semiconductor preparation process of forming longer conductive pillars on the upper electronic components can be omitted, thereby reducing costs and increasing component yield.

One aspect of the present disclosure provides a semiconductor device. The semiconductor component includes a substrate, a first electronic component, a second electronic component, a bonding wire and a package. The base has a lower surface and an upper surface opposite to the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component to the substrate and extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. The second electronic component has an active surface facing the substrate. The package is disposed on the upper surface of the substrate. The encapsulant extends within the substrate and encapsulates the bond wire.

Another aspect of the present disclosure provides another semiconductor device. The semiconductor component includes a substrate, a first electronic component, a second electronic component, a bonding wire and a plurality of conductive pillars. The base has a lower surface, an upper surface opposite to the lower surface, and an inner surface extending between the upper surface and the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component to the substrate and faces the inner surface of the substrate. The bonding wire extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. Each conductive pillar is disposed on the upper surface of the substrate and electrically connects the second electronic component to the substrate.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate with a lower surface and an upper surface opposite to the lower surface. The preparation method also includes forming an opening extending between the upper surface and the lower surface of the substrate. The preparation method also includes attaching a first electronic component to the upper surface of the substrate. An active surface of the first electronic component faces the upper surface of the substrate. In addition, the preparation method further includes attaching a second electronic component to the first electronic component. An active surface of the second electronic component faces the upper surface of the substrate. The preparation method also includes forming a bonding wire on the substrate. The bonding wire passes through the opening of the substrate and electrically connects the substrate to one of the first electronic component or the second electronic component.

In an embodiment of the present disclosure, the substrate has an opening, and the bonding wire passes through the opening. The bonding wire electrically connects the lower (or upper) electronic component to the substrate. The upper (or lower) electronic component is electrically connected to the substrate through conductive pillars, which are formed by performing multiple semiconductor preparation processes. Therefore, the semiconductor preparation process of forming conductive pillars on the underlying electronic components can be omitted, thereby reducing costs and increasing component yield.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as claimed. For example, many of the processes described above may be implemented in different ways and may be substituted for many of the processes described above with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, etc. can be used in accordance with the disclosure to have the same function or achieve substantially the same results as the corresponding embodiments described herein. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

10: Base 10r1:Open your mouth 10r2:Open your mouth 10s1: Surface 10s2: Surface 10s3: Surface 20: Electronic components 20s1: Surface 20s2: Surface 20s3: Surface 20s4: Surface 20s5: Surface 21:Terminal 22: Bonding wire 24: Electrical connection 30: Electronic components 30s1: Surface 30s2: Surface 30s3: Surface 30s4: Surface 31:Circuit layer 32:Conductive pillar 32p1: part 32p2: part 32p3: part 33: Electrical connection 34:Terminal 35: Bonding wire 40: Encapsulation 40p1: part 41: Adhesive 42: Adhesive 50: Electrical connection 100a: Semiconductor components 100b: Semiconductor components 100c: Semiconductor components 100d: Semiconductor components 100d: Semiconductor components 200:Preparation method 202:Operation 204:Operation 206:Operation 208:Operation 210:Operation 212:Operation 300:Preparation method 302: Operation 304: Operation 306: Operation 308: Operation 310: Operation R1: surface area R2: surface area R3: surface area

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1A is a top view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 1B is a cross-sectional view illustrating a cross-section along line AA' of the semiconductor device shown in FIG. 1A according to some embodiments of the present disclosure. FIG. 2 is a top view illustrating a semiconductor device according to some embodiments of the present disclosure. 3 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. 4 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 5 is a flow chart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 6A illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 6B is a cross-sectional view illustrating a cross-section along line AA′ of the semiconductor device shown in FIG. 6A according to some embodiments of the present disclosure. FIG. 7A illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 7B is a cross-sectional view illustrating a cross-section along line AA' of the semiconductor device shown in FIG. 7A according to some embodiments of the present disclosure. FIG. 8A illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. 8B is a cross-sectional view illustrating a cross-section along line AA' of the semiconductor device shown in FIG. 8A according to some embodiments of the present disclosure. FIG. 9A illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 9B is a cross-sectional view illustrating a cross-section along line AA' of the semiconductor device shown in FIG. 9A according to some embodiments of the present disclosure. FIG. 10A illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 10B is a cross-sectional view illustrating a cross-section along line AA' of the semiconductor device shown in FIG. 10A according to some embodiments of the present disclosure. FIG. 11A illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 11B is a cross-sectional view illustrating a cross-section along line AA′ of the semiconductor device shown in FIG. 11A according to some embodiments of the present disclosure. FIG. 12 is a flow chart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 13 illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 14 illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 15 illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 16 illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. FIG. 17 illustrates one or more fabrication stages illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

10: Base

10r1:Open your mouth

10s1: Surface

10s2: Surface

10s3: Surface

20: Electronic components

20s1: surface

20s2: surface

20s3: surface

20s4: Surface

21:Terminal

22: Bonding wire

30: Electronic components

30s1: Surface

30s2: Surface

30s3: Surface

30s4: Surface

31:Circuit layer

32:Conductive pillar

33: Electrical connection

40: Encapsulation

40p1: part

41: Adhesive

42: Adhesive

50: Electrical connection

100a: Semiconductor components

Claims (20)

A semiconductor component including: A base having a lower surface and an upper surface opposite to the lower surface; a first electronic component disposed on the upper surface of the substrate; a bonding wire electrically connecting the first electronic component to the substrate, wherein the bonding wire extends within the substrate; a second electronic component disposed on the upper surface of the substrate, wherein the second electronic component has an active surface facing the substrate; and An encapsulation is disposed on the upper surface of the base, wherein the encapsulation extends within the base and encapsulates the bonding wire. The semiconductor component of claim 1, wherein the second electronic component is located above the first electronic component, a portion of the package is surrounded by the substrate, and a portion of the package vertically overlaps the second electronic component. The semiconductor component of claim 1, wherein the first electronic component is located above the second electronic component, a portion of the package is surrounded by the substrate, and a portion of the package does not vertically overlap the second electronic component. The semiconductor component as described in claim 1 further includes: A plurality of conductive pillars extend between the active surface of the second electronic component and the upper surface of the substrate. The semiconductor component of claim 4, wherein the first electronic component has a first side and a second side opposite to the first side, and the plurality of conductive pillars are disposed on the third side of the first electronic component. On one side. The semiconductor component of claim 5, wherein the second side of the first electronic component does not face the plurality of conductive pillars. The semiconductor device of claim 6, wherein a first surface area of the first electronic component and a second surface area of the second electronic component are substantially the same. The semiconductor component of claim 5, wherein the first electronic component has a third side extending between the first side and the second side, and a portion of the plurality of conductive pillars faces the first electron This third side of the component. The semiconductor component of claim 5, wherein a portion of the plurality of conductive pillars faces the second side of the first electronic component, and a first surface area of the first electronic component is smaller than a first surface area of the second electronic component. Two surface areas. The semiconductor device of claim 4, wherein the package encapsulates the plurality of conductive pillars, and the package is in contact with the lower surface of the substrate. A semiconductor component including: A base having a lower surface, an upper surface opposite to the lower surface, and an inner surface extending between the upper surface and the lower surface; a first electronic component disposed on the upper surface of the substrate; A bonding wire electrically connects the first electronic component to the substrate, wherein the bonding wire faces the inner surface of the substrate. a second electronic component disposed on the upper surface of the substrate; and A plurality of conductive pillars are disposed on the upper surface of the substrate, and each conductive pillar electrically connects the second electronic component to the substrate. The semiconductor component of claim 11, wherein the second electronic component is located above the first electronic component The semiconductor component of claim 11, wherein the first electronic component is located above the second electronic component. The semiconductor component of claim 11, wherein the first electronic component has a first side and a second side opposite to the first side, and the plurality of conductive pillars are disposed on the first side of the first electronic component. On one side. The semiconductor component of claim 14, wherein the second side of the first electronic component does not face the plurality of conductive pillars, and a first surface area of the first electronic component is in contact with a first surface area of the second electronic component. The two surface areas are essentially the same. The semiconductor component of claim 14, wherein the first electronic component has a third side extending between the first side and the second side, and a portion of the plurality of conductive pillars faces the first electron This third side of the component. The semiconductor component of claim 14, wherein a portion of the plurality of conductive pillars faces the second side of the first electronic component, and a first surface area of the first electronic component is smaller than a first surface area of the second electronic component. Second surface area. The semiconductor component as described in claim 11 further includes: A package is disposed on the upper surface of the substrate, wherein the package packages the plurality of conductive pillars. The semiconductor device of claim 18, wherein the package is in contact with the lower surface of the substrate. The semiconductor component of claim 18, wherein the package has a portion surrounded by the inner surface of the substrate, and the portion of the package does not vertically overlap the second electronic component.