TW202349622A - Semiconductor device with supporter against which bonding wire is disposed and method for prparing the same - Google Patents

Abstract

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, a bonding wire, and a supporter. The electronic component is disposed on the substrate. The bonding wire includes a first terminal connected to the electronic component and a second terminal connected to the substrate. The bonding wire is disposed against the supporter.

Description

Semiconductor component with support disposed against bonding wire and method of manufacturing same

This application claims priority to U.S. Patent Application Nos. 17/829,515 and 17/829,601 (that is, the priority date is "June 1, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor component and a manufacturing method thereof. In particular, it relates to a semiconductor element having a support member disposed against a bonding wire.

With the rapid development of the electronics industry, integrated circuits (ICs) have achieved high performance and miniaturization. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits.

Many techniques have been developed for integrating an electronic component with a substrate. For example, the electronic component and the substrate may be connected by a bonding wire. In order to avoid the bonding wire being disposed against the corners of the electronic component, the bonding wire is lengthened, thereby increasing the size of the semiconductor component and its resistance. Therefore, there is a need for a new semiconductor component and a method for improving these problems.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor component includes a substrate, an electronic component, a bonding wire and a support. The electronic component is disposed on the substrate. The bonding wire includes a first terminal connected to the electronic component and a second terminal connected to the substrate. The bonding line is disposed against the support.

Another embodiment of the present disclosure provides a semiconductor device. The semiconductor component includes a substrate, an electronic component, a bonding wire and a support. The electronic component is disposed on the substrate. The bonding wire includes a first terminal connected to the electronic component and a second terminal connected to the substrate. The support member is disposed between the first terminal and the second terminal of the bonding wire.

Yet another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate. The preparation method also includes attaching an electronic component to the substrate. The preparation method also includes attaching a support member to the substrate. In addition, the preparation method includes forming a bonding wire to connect the substrate and the electronic component. The bonding line is disposed against the support.

In embodiments of the present disclosure, the semiconductor device may include a support member for fixing the bonding wire. The support member may be disposed between two terminals of the bonding wire. The support may provide a smooth area, such as a smooth surface, a smooth edge or a smooth corner on which the joining line is disposed. Thus, the bonding wire can be disposed against the support with a tolerable tension. The length of the bonding wire can be reduced, resulting in a relatively smaller size of the semiconductor element and a relatively low resistance of the bonding wire.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments or examples of the present disclosure illustrated in the drawings. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any modifications or improvements to the described embodiments, as well as any further applications of the principles described in this document, are within the realm of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment even if they share the same element number.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second device , component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

1A and 1B illustrate a semiconductor device 100a according to some embodiments of the present disclosure, wherein FIG. 1A is a schematic top view, and FIG. 1B is a schematic cross-sectional view along the cross-section line A-A’ in FIG. 1A.

In some embodiments, semiconductor device 100a includes a substrate 110. In some embodiments, for example, the substrate 110 may be or include a printed circuit board (PCB), such as a paper-based copper foil laminate, a composite copper laminate foil laminate) or a polymer-impregnated glass-fiber-based copper foil laminate.

In some embodiments, the substrate 110 may include a surface 110s1 and a surface 110s2 , and the surface 110s2 is relative to the surface 110s1 . In some embodiments, surface 110S1 may also be regarded as a lower surface. In some embodiments, surface 110s2 can also be regarded as an upper surface.

In some embodiments, substrate 110 may include conductive pads, traces, vias, layers, or other interconnect structures. For example, the substrate 110 may include one or more transmission lines (eg, communication cables) and one or more ground lines and/or ground planes. For example, substrate 110 may include one or more conductive pads (eg, 112 ) proximate to, adjacent to, or embedded in and exposed on surface 110s1 and/or surface 110s2 of substrate 110 at.

In some embodiments, the semiconductor device 110a may include an adhesive layer 120. In some embodiments, the adhesive layer 120 may be disposed on the surface 110s2 of the substrate 110.

In some embodiments, semiconductor component 110a may include an electronic component 130. In some embodiments, electronic component 130 may be disposed on surface 110s2 of substrate 110 . In some embodiments, the electronic component 130 may be attached to the surface 110s2 of the substrate 110 via the adhesive layer 120.

In some embodiments, the electronic device 130 may include a memory device, such as a dynamic random access memory (DRAM), a one-time programmable (OTP) memory device, a static random access memory (SRAM) ) component or other suitable memory component. In some embodiments, electronic component 130 may include a logic component (eg, system on chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microprocessor, etc.) , a radio frequency (RF) component, a sensor component, a microelectromechanical system (MEMS) component, a signal processing component (such as a digital signal processing (DSP) component), a front-end component (such as an analog front-end (AFE) component) or other components.

The electronic component 130 may have a surface 130s1 and a surface 130s2, and the surface 130s2 is relative to the surface 130s1. In some embodiments, surface 130s1 can also be regarded as a rear surface or a lower surface. In some embodiments, surface 130s2 can also be regarded as an active surface or an upper surface. As used herein, the term "active surface" may mean a surface on which terminals are disposed for transmitting and/or receiving signals. In some embodiments, surface 130s1 of electronic component 130 may face surface 110s2 of substrate 110 . The electronic component 130 may have a surface 130s3 (or one side surface) extending between the surface 130s1 and the surface 130s2 of the electronic component 130 .

In some embodiments, electronic component 130 may include a plurality of conductive pads 132 . The conductive pad 132 may be disposed on the surface 130s2 of the electronic component 130. In some embodiments, the conductive pads 132 may include metals such as copper (Cu), tungsten (W), silver (Ag), gold (Au), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof or other suitable materials.

In some embodiments, semiconductor component 100a may include one or more supports 140a. In some embodiments, the supports 140a may be disposed on the surface 110s2 of the substrate 110. In some embodiments, the supports 140a may be disposed on two opposite surfaces 130s3 of the electronic component 130. However, this disclosure is not limited thereto.

In some embodiments, the support 140a may be configured to provide an area, such as a surface, an edge, or a corner, against which a bonding wire (or a conductive wire) is disposed. In some embodiments, at least a portion of the support member 140a may have a convex surface, a convex edge, or a convex corner to resist a conductive line. In some embodiments, a portion of the spacer 142a may have a smooth surface, a smooth edge, or a smooth corner to abut a conductive line. As used herein, the term "smooth surface, edge or corner" may mean a relatively blunt surface, edge or corner.

In some embodiments, support 140a may contact surface 110s2 of substrate 110. In some embodiments, support 140a may contact surface 130s3 of electronic component 130. In some embodiments, support 140a may be disposed against electronic component 130. In some embodiments, support 140a may be disposed against surface 130s3 of electronic component 130. As used herein, the term "X is disposed against Y" may mean that X exerts a force or a stress on Y in addition to gravity.

In some embodiments, the support member 140a may include a spacer 142a and an adhesive element 144a. In some embodiments, at least a portion of the spacer 142a may have a convex surface, a convex edge, or a convex corner to resist a conductive line. In some embodiments, at least a portion of the spacer 142a may have a smooth surface, a smooth edge, or a smooth corner to abut a conductive line. In some embodiments, the spacer 142a may include an electrically isolating material or an electrically conductive material. In some embodiments, spacers 142a may include resin, glass, or other suitable materials. Spacers 142a may include metals, alloys, or other suitable materials. In some embodiments, spacers 142a may be circular, oval, or other contoured shapes.

In some embodiments, the adhesive element 144a may cover an outer surface (not labeled in the figure) of the spacer 142a. In some embodiments, adhesive element 144a may surround spacer 142a. In some embodiments, adhesive element 144a may be conformally disposed on spacer 142a. In some embodiments, adhesive element 144a may include an electrically isolating material.

In some embodiments, semiconductor device 100a may include one or more bond wires 150. In some embodiments, each bonding wire 150 may have a terminal 150t1 connected to (or bonded to) the surface 130s2 of the electronic component 130 and a terminal 150t2 connected to (or bonded to) the surface of the substrate 110 110s2. In some embodiments, terminal 150t1 of bond wire 150 may be bonded to conductive pad 132 of electronic component 130. In some embodiments, terminal 150t2 of bond wire 150 may be bonded to conductive pad 112 of substrate 110. In some embodiments, the support 140a may be disposed between the terminal 150t1 and the terminal 150t2 of the bonding wire 150. In some embodiments, the bonding wire 150 may include metal, such as copper (Cu), silver (Ag), gold (Au), nickel (Ni), aluminum (Al), alloys thereof, combinations thereof, or other suitable materials. .

In some embodiments, bonding wire 150 may be disposed on support 140a. In some embodiments, bonding wire 150 may be disposed against support 140a. In some embodiments, the bonding line 150 may be disposed against a smooth area 140s1 (or a rounded convex area), such as a surface, edge or corner of the support 140a. In some embodiments, bond wire 150 may contact support 140a, causing a force or a stress to be exerted on support 140a. Accordingly, the bonding wire 150 may be disposed against the electronic component 130 via the support 140a.

There may be a length L1 along the X-axis between the terminal 150t1 of the bonding wire 150 and the surface 130s3 of the electronic component 130. There may be a length L2 along the X-axis between the terminal 150t2 of the bonding wire 150 and the surface 130s3 of the electronic component 130. In some embodiments, length L1 may be substantially equal to or exceed length L2. In some embodiments, a ratio between the length L1 and the length L2 may range from about 1.1 to about 10, such as 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9 or 10.

When the ratio between the length L1 and the length L2 ranges from about 1.1 to about 3, the bonding wire 150 may be disposed against the support 140a with relatively small tension, thereby preventing the bonding wire 150 from breaking. Furthermore, the support member 140a can result in a relatively small sum of the length L1 and the length L2, thereby reducing the size of the semiconductor device 100a. Furthermore, when the length of the bonding wire 150 is reduced, the resistance of the bonding wire is relatively reduced.

There may be a length L3 along the Y-axis between the surface 130s2 of the electronic component 130 and the terminal 150t1 of the bonding wire 150. The support member 140a may have a length L4 (or thickness or diameter) along the Y-axis. In some embodiments, length L4 may exceed length L3. In some embodiments, the ratio between length L3 and length L4 may range from about 1.2 to about 1.8, such as 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, or 1.8.

When the ratio between the length L3 and the length L4 ranges from about 1.2 to about 1.8, the bonding wire 150 can be disposed against the support 140a with relatively small tension, thereby preventing the bonding wire 150 from breaking or contacting the electronic component. 130' corner.

As shown in FIG. 1A , multiple bonding wires 150 may share a common support 140a. In some embodiments, support 140a may contact multiple bond wires 150. In some embodiments, bond line 150 may extend along the X-axis. In some embodiments, support 140a may extend along the Y-axis.

In some embodiments, the semiconductor device 100a may include an encapsulant 160. In some embodiments, the encapsulation 160 may be disposed on the surface 110s2 of the substrate 110 . In some embodiments, encapsulation 160 may cover surface 110s2 of substrate 110 . In some embodiments, encapsulation 160 may encapsulate support 140a. In some embodiments, encapsulation 160 may encapsulate bonding wire 150 . Encapsulation 160 may include isolation or dielectric material. In some embodiments, the encapsulation member 160 may include molding material. For example, the molding material may include a Novolac-based resin, an epoxy-based resin, a Silicone-based resin or other suitable encapsulation components. Suitable fillers, such as powdered SiO ₂ , may also be included.

In some embodiments, the semiconductor device 100a may include a plurality of electrical connections 170 . The electrical connector 170 may be disposed on the surface 110s1 of the substrate 110 . In some embodiments, the electrical connector 170 may be configured to electrically connect the semiconductor device 100a to an external device (not shown). In some embodiments, the electrical connector 170 may include a solder material, such as an alloy solder of gold and tin or an alloy solder of silver and tin.

In a comparative example, the bond wires are connected between an electronic component and a substrate without a support. In this case, the length of the bonding wire should be greater than a predetermined value to prevent the bonding wire from abutting the corner of the electronic component. If this is not the case, the bonding wire may be susceptible to breakage due to relatively high tension. Therefore, the comparative example can have a relatively large width. In the embodiments of the present disclosure, the bonding wires may be disposed with relatively low tension against a smooth area of the support, such as a surface, an edge, or a corner. Furthermore, the length of the bonding wire can be reduced, resulting in a relatively small size and relatively low resistance of the semiconductor element.

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device 100b according to some embodiments of the present disclosure. Semiconductor element 100b is similar to semiconductor element 100a as shown in FIG. 1B, with differences as described below.

In some embodiments, the semiconductor device 100b includes a support 140b. Support member 140b may include a spacer 142b. In some embodiments, spacers 142b may be rectangular, square, or other suitable outline shapes. In some embodiments, the support member 140b may have a convex surface, a convex edge or a convex corner to abut against the disposed bonding line 150 . In some embodiments, at least a portion of the support member 140b may have a smooth surface, a smooth edge, or a smooth corner to abut the disposed joining line 150 .

In some embodiments, support 140b may fully contact surface 130s3 of electronic component 130. In some embodiments, at least a portion of the spacer 142b may have a convex surface, a convex edge, or a convex corner to abut the disposed bonding line 150 . In some embodiments, at least a portion of the spacer 142b may have a smooth surface, a smooth edge, or a smooth corner to abut the disposed bonding line 150 . Accordingly, the bonding wire 150 may have relatively little tension exerted on the bonding wire 150 .

FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device 100c according to some embodiments of the present disclosure. Semiconductor device 100c is similar to semiconductor device 100a as shown in FIG. 1B, and the differences therebetween are as follows.

In some embodiments, the semiconductor device 100c may include a support 140c. In some embodiments, the support 140c may be disposed on the surface 110s2 of the substrate 110 and spaced apart from the surface 130s3 of the electronic component 130. In some embodiments, the support member 140c may provide a smooth (or rounded) surface, edge, or corner to abut the disposed bonding line 150 . In some embodiments, at least a portion of the support member 140c may have a smooth surface, a smooth edge, or a smooth corner to abut the disposed joining line 150 .

When the support member 140c is spaced apart from the electronic component 130, the thickness (or diameter) of the support member 140c may be reduced. Therefore, the size of the semiconductor element 100c can be reduced.

FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device 100d according to some embodiments of the present disclosure. The semiconductor device 100d is similar to the semiconductor device 100a shown in FIG. 1B, and the differences therebetween are as follows.

In some embodiments, the semiconductor device 100d may include a support 140d. In some embodiments, the support 140d may be disposed on the surface 130s2 of the electronic component 130. In some embodiments, support 140s may be disposed against surface 130s2 of electronic component 130. In some embodiments, support 140s may contact surface 130s2 of electronic component 130. In some embodiments, support 140d may be spaced apart from surface 110s2 of substrate 110. In some embodiments, the support 140s may provide a smooth (or rounded) surface, edge, or corner to abut the disposed bonding line 150 .

When the support 140s is disposed on the electronic component 130, the length of the bonding line 150 along the X-axis can be reduced. Therefore, the size of the semiconductor element 100s can be reduced.

FIG. 5 is a schematic cross-sectional view illustrating a semiconductor device 100e according to some embodiments of the present disclosure. Semiconductor element 100e is similar to semiconductor element 100a as shown in FIG. 1B, and the differences therebetween are as follows.

In some embodiments, the semiconductor device 100e may include a support 140e. In some embodiments, the support 140e may be disposed on the surface 130s3 of the electronic component 130. In some embodiments, support 140e may contact surface 130s3 of electronic component 130. In some embodiments, support 140e may be spaced apart from surface 130s2 of electronic component 130. In some embodiments, support 140e may be spaced apart from surface 110s2 of substrate 110. In some embodiments, the support member 140e may provide a smooth (or rounded) surface, edge, or corner to abut the disposed bonding line 150 .

The tension of the bonding wire 150 can be adjusted by modifying the position of the support member 140e. Therefore, the length and tension of the bonding wire 150 can be optimized.

FIG. 6 is a top view schematic diagram illustrating a semiconductor device 100f according to some embodiments of the present disclosure. The semiconductor element 100f is similar to the semiconductor element 100a shown in FIG. 1A, and the differences therebetween are as follows.

In some embodiments, semiconductor element 100f may include a plurality of supports 140f. In some embodiments, each support member 140f may provide a smooth (or convex) surface, edge, or corner to abut the disposed bonding line 150 . Each support member 140f corresponds to one of the bonding lines 150. In some embodiments, each support member 140f may contact a corresponding bonding line 150.

FIG. 7 is a schematic flowchart illustrating a method 200 for manufacturing a semiconductor device according to some embodiments of the present disclosure.

The preparation method 200 begins with step 202, which is providing a substrate. The base may have a lower surface and an upper surface, and the upper surface is disposed relative to the lower surface. The substrate may include one or more conductive pads proximate to, adjacent to, or embedded in and exposed on the lower surface and/or the upper surface of the substrate 110 .

The preparation method 200 continues with step 204, in which an electronic component may be formed on the upper surface of the substrate. In some embodiments, the electronic component can be attached to the upper surface of the substrate through an adhesive layer. The electronic component has a rear surface, an active surface and a side surface extending between the rear surface and the active surface of the electronic component. The electronic component may have a conductive pad on the active surface of the electronic component.

The preparation method 200 continues with step 206, in which a support member may be formed on the upper surface of the substrate. In some embodiments, the support may contact the upper surface of the substrate. In some embodiments, the support may contact the side surface of the electronic component. In some embodiments, at least a portion of the support member may have a convex surface, a convex edge, or a convex corner. In some embodiments, at least a portion of the support member may have a smooth surface, a smooth edge, or a smooth corner.

In some embodiments, the support member may have a spacer and an adhesive element. In some embodiments, at least a portion of the spacer may have a convex surface, a convex edge, or a convex corner. In some embodiments, at least a portion of the spacer may have a smooth surface, a smooth edge, or a smooth corner. In some embodiments, the adhesive element is conformally formed on the spacer.

The method 200 continues with step 208 where a bonding wire may be formed. In some embodiments, the bonding wire may have a first terminal connected to the electronic component and a second terminal connected to the substrate. In some embodiments, the bonding line may be disposed against the support. In some embodiments, a portion of the bond line may contact the support. In some embodiments, at least a portion of the bonding line can be disposed against a smooth area of the support, such as a surface, an edge, or a corner.

The preparation method 200 continues with step 210, in which an encapsulation component may be formed on the upper surface of the substrate. In some embodiments, the encapsulant may encapsulate the electronic component, the support, and the bonding wire.

The manufacturing method 200 continues with step 212, in which a plurality of electrical connections may be formed on the lower surface of the substrate, thereby producing a semiconductor device.

In the embodiments of the present disclosure, the semiconductor device may include a support. The support member may be disposed between two terminals of the bonding wire. The bonding line may be disposed with relatively low tension against a smooth area of the support, such as a surface, an edge or a corner. Furthermore, the length of the bonding wire can be reduced, resulting in a relatively smaller size of the semiconductor device and a relatively low resistance of the bonding wire.

The preparation method 200 is only an example and is not intended to limit the disclosure beyond the scope explicitly stated in the patent application. Additional steps may be provided before, during, or after each step of the preparation method 200, and some of the steps described may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, preparation method 200 may include further steps not depicted in Figure 7. In some embodiments, the preparation method 200 may include one or more of the steps depicted in FIG. 7 .

8A to 8F are schematic cross-sectional views illustrating one or more stages of an exemplary method for preparing a semiconductor device according to some embodiments of the present disclosure. In some embodiments, semiconductor element 100a may be fabricated via the steps described with respect to FIGS. 8A-8F.

Referring to FIG. 8A, a substrate 110 may be provided. The substrate 110 may have a surface 110s1 and a surface 110s2, and the surface 110s2 is disposed opposite to the surface 110s1. Substrate 110 may include one or more conductive pads (eg, 112 ) proximate to, adjacent to, or embedded in and exposed to surface 110s1 and/or surface 110s2 of the substrate.

Referring to FIG. 8B , an electronic component 130 may be formed on the surface 110s2 of the substrate 110 . In some embodiments, the electronic component 130 can be attached to the surface 110s2 of the substrate 110 through an adhesive layer 120. The electronic component 130 may have a surface 130s1, a surface 130s2, and a surface 130s3, and the surface 130s3 extends between the surface 130s1 and the surface 130s2 of the electronic component 130. The electronic component 130 may have a conductive pad 132 on the surface 130s2 of the electronic component 130.

Referring to FIG. 8C, a support member 140a may be formed on the surface 110s2 of the substrate 110. In some embodiments, support 140a may contact surface 110s2 of substrate 110. In some embodiments, support 140a may contact surface 130s3 of electronic component 130. In some embodiments, at least a portion of the support member 140a may have a convex surface, a convex edge, or a convex corner. In some embodiments, at least a portion of the support member 140a may have a smooth surface, a smooth edge, or a smooth corner.

In some embodiments, the support member 140a may have a spacer 142a and an adhesive element 144a. In some embodiments, at least a portion of the spacer 142a may have a convex surface, a convex edge, or a convex corner. In some embodiments, at least a portion of the spacer 142a may have a smooth surface, a smooth edge, or a smooth corner. In some embodiments, adhesive elements 144a are conformally formed on spacers 142a.

Referring to FIG. 8D , a bonding line 150 may be formed. In some embodiments, the bonding wire 150 may have a terminal 150t1 connected to the electronic component 130 and a terminal 150t2 connected to the substrate 110 . In some embodiments, bonding wire 150 may be disposed against support 140a. In some embodiments, at least a portion of the bonding line 150 may be disposed against a smooth area 140s1 of the support 140a, such as a surface, an edge, or a corner. In some embodiments, a portion of bond line 150 may contact support 140a.

Referring to FIG. 8E , an encapsulation member 160 may be formed on the surface 110s2 of the substrate 110 . The manufacturing technique of the encapsulation component 160 may include a molding operation. In some embodiments, encapsulation 160 may encapsulate electronic component 130, support 140a, and bonding wire 150.

Referring to FIG. 8F, a plurality of electrical connections 170 may be formed on the surface 110s1 of the substrate 110, thereby producing the semiconductor device 100a. The electrical connector 170 may include a solder material.

It is envisaged in FIG. 8C that if the support member is disposed on the surface 110s2 of the substrate 110 and is separated from the surface 130s3 of the electronic component 130, the same or similar semiconductor component 100c as shown and described with reference to FIG. 3 can be formed. A semiconductor component.

It is assumed in FIG. 8C that if the support member is disposed on the surface 130s2 of the electronic component 130 and separated from the substrate 110, a semiconductor component that is the same or similar to the semiconductor component 100d shown and described with reference to FIG. 4 can be formed. .

It is assumed in FIG. 8C that if the support member is disposed on the surface 130s3 of the electronic component 130 and is separated from the substrate 110, a semiconductor component that is the same or similar to the semiconductor component 100e shown and described with reference to FIG. 5 can be formed. .

It is assumed in FIG. 8C that if a plurality of supports, each of which can be used to fix a corresponding bonding wire 150, are disposed on the surface 110s2 of the substrate 110, the same semiconductor device 100f as shown and described with reference to FIG. 6 can be formed. or a similar semiconductor device.

In the embodiments of the present disclosure, the semiconductor device may include a support. The support member may be disposed between two terminals of the bonding wire. The bonding line may be disposed with relatively low tension against a smooth area of the support, such as a surface, an edge or a corner. Furthermore, the length of the bonding wire can be reduced, resulting in a relatively smaller size of the semiconductor device and a relatively low resistance of the bonding wire.

An embodiment of the present disclosure provides a semiconductor device. The semiconductor component includes a substrate, an electronic component, a bonding wire and a support. The electronic component is disposed on the substrate. The bonding wire includes a first terminal connected to the electronic component and a second terminal connected to the substrate. The bonding line is disposed against the support.

Another embodiment of the present disclosure provides a semiconductor device. The semiconductor component includes a substrate, an electronic component, a bonding wire and a support. The electronic component is disposed on the substrate. The bonding wire includes a first terminal connected to the electronic component and a second terminal connected to the substrate. The support member is disposed between the first terminal and the second terminal of the bonding wire.

Yet another embodiment of the present disclosure provides a method of manufacturing a semiconductor device. The preparation method includes providing a substrate. The preparation method also includes attaching an electronic component to the substrate. The preparation method also includes attaching a support member to the substrate. In addition, the preparation method includes forming a bonding wire to connect the substrate and the electronic component. The bonding line is disposed against the support.

In embodiments of the present disclosure, the semiconductor device may include a support member for fixing the bonding wire. The support member may be disposed between two terminals of the bonding wire. The support may provide a smooth area, such as a smooth surface, a smooth edge or a smooth corner on which the joining line is disposed. Thus, the bonding wire can be disposed against the support with a tolerable tension. The length of the bonding wire can be reduced, resulting in a relatively smaller size of the semiconductor element and a relatively low resistance of the bonding wire.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

100a: Semiconductor components 100b: Semiconductor components 100c: Semiconductor components 100d: Semiconductor components 100e: Semiconductor components 100f: Semiconductor components 110: Base 110s1: Surface 110s2: Surface 112:Conductive pad 120:Adhesive layer 130:Electronic components 130s1: Surface 130s2: Surface 130s3: Surface 132:Conductive pad 140a:Support 140b:Support 140c:Support 140d:Support 140e:Support 140f:Support 140s1: Smooth area 142a: Gap 142b: Gap 144a: Adhesive components 150:Joining wire 150t1: terminal 150t2: terminal 160: Encapsulated parts 170: Electrical connectors 200:Preparation method 202:Step 204:Step 206:Step 208:Step 210: Step 212: Step L1:Length L2: length L3: length L4:Length X: axis Y: axis Z: axis

A more complete understanding of the present disclosure can be obtained by referring to the detailed description and patent claims. The present disclosure should also be understood to be associated with the drawing element numbering which represents similar elements throughout the description. FIG. 1A is a top view schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 1B is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the cross-section line A-A’ of the semiconductor device shown in FIG. 1A . FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. 4 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 5 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 6 is a top view schematic diagram illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 7 is a schematic flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. 8A is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 8B is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 8C is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 8D is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 8E is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure. 8F is a cross-sectional schematic diagram illustrating one or more stages of an exemplary method for fabricating a semiconductor device according to some embodiments of the present disclosure.

100a: Semiconductor components

110: Base

110s1: Surface

110s2: Surface

112:Conductive pad

120:Adhesive layer

130:Electronic components

130s1: Surface

130s2: Surface

130s3: Surface

132:Conductive pad

140a:Support

140s1: Smooth area

142a: Gap

144a: Adhesive components

150:Joining wire

150t1: terminal

150t2: terminal

160: Encapsulated parts

170: Electrical connectors

L1:Length

L2: length

L3: length

L4:Length

X: axis

Y: axis

Z: axis

Claims (19)

A semiconductor component including: a base; An electronic component is provided on the substrate; a bonding wire including a first terminal connected to the electronic component and a second terminal connected to the substrate; and A support member is disposed on the base, wherein the bonding line is disposed against the support member. The semiconductor component according to claim 1, wherein the support member and the electronic component are arranged side by side. The semiconductor component of claim 1, wherein the support member contacts the electronic component. The semiconductor component of claim 3, wherein the support member contacts an upper surface of the electronic component. The semiconductor component of claim 3, wherein the support member contacts one side surface of the electronic component. The semiconductor component according to claim 5, wherein the support member partially contacts one side surface of the electronic component. The semiconductor component as claimed in claim 5, wherein the support member completely contacts one side surface of the electronic component. The semiconductor component of claim 3, wherein the support member is disposed against the electronic component. The semiconductor component of claim 1, wherein the support member is separated from the electronic component. The semiconductor device of claim 1, wherein the support member is separated from the substrate. The semiconductor device according to claim 1, wherein the support member includes a spacer and an adhesive component, and the adhesive component covers the spacer. The semiconductor component of claim 1, wherein the first terminal of the bonding wire and one side surface of the electronic component have a first length along a first direction, and the first direction is substantially perpendicular to the surface of the electronic component. The side surface, the second terminal and the side surface of the electronic component have a second length along the first direction, and the second length is smaller than the first length. The semiconductor device of claim 12, wherein a ratio between the first length and the second length ranges from about 1.1 to about 3. The semiconductor component of claim 1, wherein an upper surface of the electronic component and the second terminal of the bonding wire have a third distance along a second direction, and the second direction is perpendicular to the The upper surface and the support member have a thickness along the second direction, and the thickness of the support member is greater than the third distance. The semiconductor device of claim 1, wherein the thickness of the support member is greater than 1.5 times the first length. A method for preparing semiconductor components, including: provide a base; Attach an electronic component to the substrate; Attach a support member to the substrate; and forming a bonding wire to connect the substrate and the electronic component; The bonding line is disposed against the support member. The preparation method as claimed in claim 16, wherein the support member is attached to an upper surface of the substrate. The preparation method of claim 16, wherein the support member is attached to an upper surface of the electronic component. The preparation method as claimed in claim 16, wherein the support member is attached to one side surface of the electronic component.