TWI844866B - Memory device - Google Patents

Abstract

A memory device includes at least one memory cell block, a first edge block, a second edge block, a plurality of first sense amplifiers and a plurality of second sense amplifiers. The first edge block is coupled to a plurality of first word lines, where at least one of the first word lines receives an enabled first word line signal. The second edge block is coupled to a plurality of second word lines, where at least one of the second word lines receives an enabled second word line signal. The first sense amplifiers are coupled between the first edge block and the memory cell block. The second sense amplifiers are coupled between the second edge block and the memory cell block.

Description

Memory device

The present invention relates to a memory device, and more particularly to a memory device capable of reducing layout area and maintaining load balance.

In a DRAM with an open bit-line architecture, sense amplifiers are placed on both sides of each memory cell block. Each memory cell block is split into two equal parts and read and written through sense amplifiers on both sides.

Under this architecture, the two memory cell blocks at the edge of the learning memory cannot be read or written normally because only half of them are connected to the sense amplifier. In other words, there will be two full-sized memory cell blocks in the learning memory that cannot be used, resulting in a waste of layout area. Such a configuration may not be significant in large-sized memories. However, in small-sized memories (such as memories used in artificial intelligence calculations), the ratio of unusable memory cell blocks to the circuit size of the memory will increase significantly, thereby greatly affecting the manufacturing cost.

The present invention provides a memory device which effectively reduces the area required for circuit layout while maintaining load balance between two input terminals of a sense amplifier.

The memory device of the present invention includes at least one memory cell block, a first boundary block, a second boundary block, a plurality of first sense amplifiers, and a plurality of second sense amplifiers. The first boundary block is coupled to a plurality of first word lines, wherein at least one of the first word lines receives an enabled first word line signal. The second boundary block is coupled to a plurality of second word lines, wherein at least one of the second word lines receives an enabled second word line signal. The first sense amplifier is disposed between the first boundary block and the memory cell block, and is respectively coupled to a plurality of first bit lines of the memory cell block, and is respectively coupled to a plurality of second bit lines of the first boundary block. The second sense amplifier is arranged between the second boundary block and the memory cell block, and is respectively coupled to a plurality of third bit lines of the memory cell block, and is respectively coupled to a plurality of fourth bit lines of the second boundary block.

Based on the above, the present invention sets a first boundary block and a second boundary block on both sides of the memory cell block, respectively, and enables part of the word lines in the first boundary block and the second boundary block to provide loads to the corresponding sense amplifiers, so that the loads of the two input terminals of the sense amplifiers can be balanced, thereby improving the response rate of the sensing action of the sense amplifiers.

Please refer to FIG. 1, which shows a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 100 includes a memory cell block MBK, boundary blocks BK1, BK2, and sense amplifiers (SA) 111-11N and 121-12N. In this embodiment, the boundary blocks BK1 and BK2 can be respectively arranged at two different sides of the memory cell block MBK. The boundary block BK1 is coupled to a plurality of word lines AWL1-AWLK, wherein at least one of the word lines AWL1-AWLK receives a word line signal to maintain being enabled. The boundary block BK2 is coupled to a plurality of word lines BWL1 -BWLL, wherein at least one of the word lines BWL1 -BWLL also receives a word line signal to maintain being enabled.

The sense amplifiers (SA) 111-11N are coupled between the memory cell block MBK and the boundary block BK1. The first input terminals of the sense amplifiers (SA) 111-11N are respectively coupled to a plurality of bit lines BL11-BL1N of the memory cell block MBK. The second input terminals of the sense amplifiers (SA) 111-11N are respectively coupled to a plurality of bit lines BL21-BL2N of the memory cell block MBK.

The sense amplifiers (SA) 121~12N are coupled between the memory cell block MBK and the boundary block BK2. The first input terminals of the sense amplifiers (SA) 121~12N are respectively coupled to the multiple bit lines BL31~BL3N of the memory cell block MBK. The second input terminals of the sense amplifiers (SA) 121~12N are respectively coupled to the multiple bit lines BL41~BL4N of the memory cell block MBK. The bit lines BL11~BL1N and the bit lines BL31~BL3N of the memory cell block MBK are different bit lines. The bit lines BL11~BL1N are, for example, the odd bit lines in the memory cell block MBK, and the bit lines BL31~BL3N are, for example, the even bit lines in the memory cell block MBK.

Please note that in this embodiment, the number of word lines AWL1 to AWLK of the boundary block BK1 is less than the total number of word lines WL1 to WLM of the memory cell block MBK. The number of word lines BWL1 to BWLL of the boundary block BK2 is also less than the total number of word lines WL1 to WLM of the memory cell block MBK. Furthermore, the number of word lines AWL1 to AWLK of the boundary block BK1 and the number of word lines BWL1 to BWLL of the boundary block BK2 may be the same or different.

Please note that in this embodiment, the number of word line signals received by the boundary block BK1 from among the multiple word lines AWL1~AWLK coupled to the boundary block BK1 can be determined according to the load on the first input terminal of the corresponding sense amplifier (SA) 111~11N. In this embodiment, the boundary block BK1 has a plurality of load elements LC1 arranged in an array. Each of the load elements LC1 is coupled to the corresponding word lines AWL1~AWLK and the corresponding bit lines BL21~BL2N. The load element LC1 can provide a capacitive load and provide a capacitive load to the corresponding bit line when the corresponding word line receives the enabled word line signal. Therefore, in this embodiment, the load on each bit line BL21 to BL2N can be adjusted by controlling the number of word lines AWL1 to AWLK receiving the enabled word line signal.

Similarly, in the present embodiment, the number of word line signals received by the boundary block BK2 from among the multiple word lines BWL1-BWLL that are coupled can be determined according to the load on the first input terminal of the corresponding sense amplifier (SA) 121-12N. In the present embodiment, the boundary block BK2 has a plurality of load elements LC2 arranged in an array. Each of the load elements LC2 is coupled to the corresponding word lines BWL1-BWLL and the corresponding bit lines BL41-BL4N. The load element LC2 can provide a capacitive load, and when the corresponding word line receives the enabled word line signal, the capacitive load is provided to the corresponding bit line. Therefore, in this embodiment, the load on each bit line BL41 to BL4N can be adjusted by controlling the number of word lines BWL1 to BWLL that receive the enabled word line signal.

Here, by adjusting the number of word line signals enabled by word lines AWL1-AWLK and BWL1-BWLL, the load on the two input terminals of each of the sense amplifiers (SA) 111-11N and the sense amplifiers (SA) 121-12N can be balanced to maintain the accuracy of the sensing action of the sense amplifiers (SA) 111-11N and the sense amplifiers (SA) 121-12N. It is worth mentioning that the embodiment of the present invention can adjust the number of word line signals received and enabled in word lines AWL1-AWLN and BWL1-BWLL so as to make the difference in load between the two input terminals of each of the sense amplifiers (SA) 111-11N and the sense amplifiers (SA) 121-12N less than a preset critical value (or make the load between the two input terminals equal) to maintain the load balance.

Incidentally, the load elements LC1, LC can be a memory cell, a capacitor or other electronic elements that can provide capacitive loads, without specific limitations. In addition, the word lines AWL1~AWLN and BWL1~BWLL that do not receive the enabled word line signal can receive the disabled word line signal.

In addition, the memory cell block MBK includes a plurality of memory cells MC. Each memory cell MC is coupled to corresponding bit lines BL11-BL1N, BL31-BL3N, and corresponding word lines WL1-WLM. In this embodiment, the memory cell MC may be a dynamic random access memory cell or other types of memory cells, and the memory device 100 may be a dynamic random access memory device with an open bit-line architecture.

The sense amplifiers (SA) 111 - 11N and the sense amplifiers (SA) 121 - 12N of this embodiment can be implemented by using any sense amplifier circuit known to those skilled in the art without any particular limitation.

Since the boundary blocks BK1 and BK2 provided in the present embodiment have only a small number of word lines, the layout area required for each of the boundary blocks BK1 and BK2 can be smaller than the layout area of a complete memory cell block MBK. Therefore, under the premise of maintaining the load balance of the sense amplifiers (SA) 111-11N and the sense amplifiers (SA) 121-12N, the circuit layout area required for the memory device 100 of the present embodiment can be effectively reduced, thereby reducing the cost required for the circuit.

Next, please refer to FIG. 2, which shows a schematic diagram of a memory device of another embodiment of the present invention. The memory device 200 includes a memory cell block MBK, boundary blocks BK1, BK2, sense amplifiers (SA) 211~214 and 221~224, and a controller 240. In this embodiment, the coupling relationship between the memory cell block MBK, the boundary blocks BK1, BK2, and the sense amplifiers (SA) 211~214 and 221~224 is the same as that of the aforementioned embodiment, and will not be described in detail here. Unlike the aforementioned embodiment, a controller 240 is provided in the memory device 200. The controller 240 is coupled to the boundary blocks BK1, BK2. The controller 240 is used to generate control signals CT1 and CT2, and provide the control signals CT1 and CT2 to the boundary blocks BK1 and BK2 respectively to control the number of word line signals enabled received by the word lines AWL1-AWLK and BWL1-BWLL on the boundary blocks BK1 and BK2.

In detail, word lines AWL1-AWLK can be coupled to a switch circuit 231, and word lines BWL1-BWLL can be coupled to a switch circuit 232. Switch circuits 231 and 232 receive control signals CT1 and CT2, respectively. Switch circuit 231 can make a first portion of word lines AWL1-AWLK receive an enable voltage EWN and a second portion of word lines AWL1-AWLK receive a disable voltage DISW according to control signal CT1. The load on an input terminal of sense amplifiers (SA) 211-214 is thereby adjusted. Switch circuit 232 can make a first portion of word lines BWL1-BWLL receive an enable voltage EWN and a second portion of word lines BWL1-BWLL receive a disable voltage DISW according to control signal CT2. The load on an input terminal of the sense amplifier (SA) 221-224 is thereby adjusted.

In this embodiment, the controller 240 does not need to perform actual detection operations on the loads at the input terminals of the sense amplifiers (SA) 211-214 and 221-224, but adjusts the number of word lines enabled in the corresponding coupled word lines AWL1-AWLK and BWL1-BWLL according to the response rate of the sensing operations of the sense amplifiers (SA) 211-214 and 221-224.

In another embodiment, the controller 240 may also detect the load on the input end of the sense amplifiers (SA) 211-214 coupled to the memory cell array MBK, and generate the control signal CT1 according to the detection result. The controller 240 may also detect the load on the input end of the sense amplifiers (SA) 221-224 coupled to the memory cell array MBK, and generate the control signal CT2 according to the detection result. Regarding the load detection action, the controller 240 may apply a current (or voltage) to the end point to be detected, and calculate the load by measuring the voltage (or current) on the end point.

The switch circuit 231 includes a plurality of switches, each of which is used to select the corresponding word line (one of the word lines AWL1 to AWLK) to receive the enable voltage EWN or the disable voltage DISW according to one bit of the control signal CT1. The enable voltage EWN is equal to the enabled word line signal, and the disable voltage DISW is equal to the disabled word line signal. In the embodiment of the present invention, the enable voltage EWN is greater than the disable voltage DISW. The switch circuit 232 may have the same circuit structure and operation as the switch circuit 231, which will not be described in detail here.

It is worth mentioning that the controller 240 can be a circuit (e.g., a digital circuit) embedded in the memory device 200, and during the operation of the memory device 200, it can generate control signals CT1 and CT2 in real time and perform load balancing operations on the input ends of the sense amplifiers (SA) 211 to 224. In other embodiments, the controller 240 can also be a circuit (e.g., an external test circuit) outside the memory device 200. In this case, the controller 240 can provide control signals CT1 and CT2 to tie a fixed number of word lines among the word lines AWL1 to AWLK and BWL1 to BWLL to receive the enable voltage EWN.

Please refer to FIG. 3, which is a schematic diagram of a memory device of another embodiment of the present invention. The memory device 300 includes memory cell blocks MBK1, MBK2, boundary blocks BK1, BK2, and sense amplifiers (SA) 311-334. Different from the aforementioned embodiments, the memory device 300 of this embodiment has a plurality of memory cell blocks MBK1, MBK2. The memory cell blocks MBK1, MBK2 are sequentially coupled between the boundary block BK1 and the boundary block BK2. The memory cell blocks MBK1 and MBK2 are coupled to the word lines WL11-WL1M and the word lines WL21-WL2M, respectively. The total number of word lines WL11-WL1M and the total number of word lines WL21-WL2M may be equal. The number of word lines AWL1-AWLM coupled to the boundary block BK1 and the number of word lines BWL1-BWLL coupled to the boundary block BK2 are both less than the total number of word lines WL11-WL1M and the total number of word lines WL21-WL2M. For example, if each of the memory cell blocks MBK1 and MBK2 has a memory capacity of 4 million bytes, the memory device 300 may have a memory capacity of 8 million bytes.

In one example, each of the memory cell blocks MBK1 and MBK2 can be coupled to 512 word lines, and the boundary blocks BK1 and BK2 can be coupled to only a few or dozens of word lines. That is, the layout area of each of the boundary blocks BK1 and BK2 is much smaller than the layout area of each of the memory cell blocks MBK1 and MBK2.

In addition, in other examples, three or more memory cell blocks may be disposed between the boundary blocks BK1 and BK2, wherein the number of memory cell blocks is not limited.

In summary, the memory device of the present invention provides a load to the input terminal of the adjacent sense amplifier by setting a boundary block in the memory device. Furthermore, the memory device of the present invention adjusts the number of enabled bit lines on the boundary block to adjust the corresponding provided load, so that the load between the two input terminals of the sense amplifier can be balanced, thereby improving the response rate of the sense amplifier.

100, 200, 300: memory devices 111~11N, 121~12N, 211~214, 221~224, 311~314, 321~324, 331~334: sense amplifier (SA) 240: controller AWL1~AWLK, BWL1~BWLL, WL1~WLM: word line BK1, BK2: boundary block BL11~BL1N, BL21~BL2N, BL31~BL3N, BL41~BL4N: bit line CT1, CT2: control signal DIS: disable voltage EWN: enable voltage LC1, LC2: load components MBK, MBK1, MBK2: memory cell block MC: Memory Cell

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a memory device according to another embodiment of the present invention. FIG. 3 is a schematic diagram of a memory device according to another embodiment of the present invention.

100: memory device 111~11N, 121~12N: sense amplifier (SA) AWL1~AWLK, BWL1~BWLL, WL1~WLM: word line BK1, BK2: boundary block BL11~BL1N, BL21~BL2N, BL31~BL3N, BL41~BL4N: bit line LC1, LC2: load element MBK: memory cell block MC: memory cell

Claims (9)

A memory device includes: at least one memory cell block; a first boundary block coupled to a plurality of first word lines, wherein at least one of the first word lines receives an enabled first word line signal; a second boundary block coupled to a plurality of second word lines, wherein at least one of the second word lines receives an enabled second word line signal; a plurality of first sense amplifiers disposed between the first boundary block and the at least one memory cell block, and respectively coupled to the plurality of first word lines of the at least one memory cell block; A first word line, and coupled to a plurality of second bit lines of the first boundary block respectively; and a plurality of second sense amplifiers, arranged between the second boundary block and the at least one memory cell block, and coupled to a plurality of third bit lines of the at least one memory cell block respectively, and coupled to a plurality of fourth bit lines of the second boundary block respectively, wherein the total number of the first word lines is less than the total number of word lines of the at least one memory cell block, and the total number of the second word lines is less than the total number of word lines of the at least one memory cell block. A memory device as described in claim 1, wherein the first input terminal of each of the first sense amplifiers is coupled to each of the first bit lines, the second input terminal of each of the first sense amplifiers is coupled to each of the second bit lines, and the number of the first word lines that maintain receiving the enabled first word line signal is determined according to the load on the first input terminal of each of the first sense amplifiers. A memory device as described in claim 2, wherein the load on the first input terminal of each first sense amplifier is equal to the load on the second input terminal of each first sense amplifier. A memory device as described in claim 1, wherein the first input terminal of each second sense amplifier is coupled to each third bit line, the second input terminal of each second sense amplifier is coupled to each fourth bit line, and the number of the second word lines that maintain receiving the enabled second word line signal is determined according to the load on the first input terminal of each second sense amplifier. A memory device as described in claim 4, wherein the difference between the load on the first input terminal of each second sense amplifier and the load on the second input terminal of each second sense amplifier is less than a preset critical value. The memory device as described in claim 1, wherein the first boundary block further includes a plurality of first load elements, each of which is coupled to the corresponding first word line and the corresponding second bit line, and the second boundary block further includes a plurality of second load elements, each of which is coupled to the corresponding second word line and the corresponding fourth bit line. The memory device as described in claim 1 further includes: a controller coupled to the first boundary block and the second boundary block, for controlling a first number of the first word lines to maintain the reception of the enabled first word line signal, and controlling a second number of the second word lines to maintain the reception of the enabled second word line signal. A memory device as described in claim 7, wherein the controller adjusts the first quantity according to the load on the first input terminal of each of the first sense amplifiers or the response rate of each of the first sense amplifiers. A memory device as described in claim 7, wherein the controller adjusts the second quantity according to the load on the first input terminal of each second sense amplifier or the response rate of each second sense amplifier.

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