TWI837940B - Memory device capable of performing in-memory computing - Google Patents

Abstract

A memory device capable of performing in-memory computing is provided, which includes a memory cell array, a sense amplifier, a voltage control circuit, a wordline decoding circuit. The memory cell array includes a plurality of memory cells arranged in a two-dimensional array. The memory cells on each row of the memory cell array are connected to a corresponding wordline, and the memory cells on each column of the memory cell array are connected to a corresponding bitline. The sense amplifier detects a voltage level on the activated bitline and an inverse bitline corresponding to the bitline. The voltage control circuit select a detection voltage provided to the sense amplifier according to a control signal from a memory controller. The wordline decoding circuit activates a first wordline and a second wordline among the wordlines according to the control signal.

Description

A memory device that can perform in-memory operations

The present invention relates to a memory device, and more particularly to a memory device capable of executing in-memory operations.

Traditional computer devices usually use the Von Neumann architecture to transfer data between the CPU and the memory device. However, when the data transfer volume between the CPU and the memory device is extremely large, a data transfer bottleneck often occurs between the CPU and the memory device, which is called the Von Neumann bottleneck. Therefore, a memory device that can perform in-memory operations is needed to solve the above problem.

The present invention provides a memory device capable of executing in-memory operations, comprising: a memory cell array, comprising a plurality of memory cells arranged in a two-dimensional array, wherein the memory cells on each row of the memory cell array are connected to corresponding word lines, and the memory cells on each column of the memory cell array are connected to corresponding bit lines; A sense amplifier is used to detect the voltage level on the turned-on bit line and the inverted bit line corresponding to the bit line, a voltage control circuit is used to select the detection voltage provided to the sense amplifier according to a control signal from a memory controller; and a word line decoding circuit is used to turn on the first word line and the second word line among the word lines according to the control signal.

FIG. 1 is a schematic diagram of a computing device according to an embodiment of the present invention. As shown in FIG. 1, the computing device 10 includes a central processing unit 110 and a memory device 120. The central processing unit 110 is electrically connected to the memory device 120, wherein the memory device 120 is, for example, a dynamic random access memory (DRAM), but the present invention is not limited thereto. The memory device 120 includes, for example, a plurality of memory banks, and each memory bank includes a plurality of memory cell arrays, wherein each memory cell array is, for example, arranged in a two-dimensional array (e.g., M columns*N rows), wherein each column and each row of the above-mentioned memory cell array are respectively connected to corresponding word lines and bit lines. In addition, each memory cell can store 1 bit or M bits of data, where M is an integer greater than 1.

The CPU 110 includes, for example, a memory controller 111, an arithmetic logic unit (ALU) 112, and a cache memory 113. The memory controller 111 is used to control data access of the memory device 120. It should be noted that the control signal 115 sent by the memory controller 111 to the memory device 120 can control the memory device 120 to perform in-memory computing, such as performing bitwise AND/OR operations. The memory controller 111 can also receive data processed by bitwise operations or general data that has not been processed by logical operations from the memory device 120.

The ALU 112 performs corresponding arithmetic operations and/or logic operations according to the instructions executed by the CPU 110. In some embodiments, in order to reduce the data bandwidth requirement between the CPU 110 and the memory device 120, the memory controller 111 of the CPU 110 will send a corresponding control signal 115 to the memory device 120 to hand over part of the logic operation (for example, bitwise AND/OR operation) to the memory device 120 for execution, and receive the data processed by the above logic operation from the memory device 120 (for example, through the data bus 116), and then transmit the above data to the arithmetic logic unit 112 for subsequent processing.

The memory device 120 includes, for example, a plurality of memory libraries 121 to 12N, and each memory library 121 to 12N includes a plurality of memory unit arrays 1211 to 121N.

FIG. 2A is a circuit diagram of the memory cell array in the embodiment of FIG. 1 of the present invention. Please refer to FIG. 1 and FIG. 2A at the same time.

In FIG. 2A, the memory cell array 1211 is used for illustration, and the circuit diagrams of other memory cell arrays 1212~121N are similar to FIG. 2A. The memory cell array 1211 includes a plurality of memory cells 201 arranged in a two-dimensional array, and each row of memory cells 201 is connected to a corresponding word line 202, and each row of memory cells 201 is connected to a corresponding bit line 203. In addition, each bit line 203 is connected to a corresponding sense amplifier 204.

Figure 2B is a circuit diagram of the memory unit in the embodiment of Figure 2A of the present invention. Figure 2C is a schematic diagram of the reading process of the memory unit in the embodiment of Figure 2B of the present invention.

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的示意圖。 Referring to FIG. 2B , the memory cell 201 includes a transistor 2011 and a capacitor 2012 , wherein the logic level of the word line 202 controls the on and off of the transistor 2011 . In addition, FIG. 2C shows five states of the memory cell 201 in the access process.

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Schematic diagram of .

V _DD 。接著，記憶體單元201存取操作會被記憶體單元201所相應的字元線202上的ACT指令所觸發以進入狀態2。在狀態2中，字元線202開啟，故其電壓位準會達到電壓V _DD 。此時，感測放大器204仍處於關閉狀態。狀態3表示電荷分享狀態，儲存於電容2012的電荷會從記憶體單元201流向位元線203，使得位元線203的電壓位準提高至電壓

V _DD +δ。此時，感測放大器204仍處於關閉狀態。在狀態4中，感測放大器204開啟以感測位元線203的電壓位準與電壓

V _DD 之間的偏差值δ(可為正偏差值或負偏差值)，並將該偏差值δ放大直到位元線203之電壓位準到達電壓V _DD ，意即進入狀態5。此時，因為電容2012仍然連接至位元線203，故電容2012所儲存之電位會被充電至原本的完全充電狀態。 In FIG. 2C , the capacitor 2012 of the memory cell 201 is in a fully charged state. State 1 represents the initial pre-charge state, where the logic level of the word line 202 is 0 and the sense amplifier 204 is off, and the voltage level of the bit line 203 is pre-charged to a voltage

V _DD . Then, the memory cell 201 access operation is triggered by the ACT instruction on the word line 202 corresponding to the memory cell 201 to enter state 2. In state 2, the word line 202 is turned on, so its voltage level reaches the voltage V _DD . At this time, the sense amplifier 204 is still in the off state. State 3 represents the charge sharing state, and the charge stored in the capacitor 2012 flows from the memory cell 201 to the bit line 203, causing the voltage level of the bit line 203 to increase to the voltage

VDD ₊ δ. At this time, the sense amplifier 204 is still in the off state. In state 4, the sense amplifier 204 is turned on to sense the voltage level of the bit line 203 and the voltage

V _DD , and amplifies the deviation δ until the voltage level of the bit line 203 reaches the voltage V _DD , which means entering state 5. At this time, because the capacitor 2012 is still connected to the bit line 203, the potential stored in the capacitor 2012 will be charged to the original fully charged state.

Figure 3 is a schematic diagram of a memory cell array according to an embodiment of the present invention. Please refer to Figures 1 and 3 at the same time.

The memory cell array 1211 includes memory cells 301A, 301B, and 301C, and the memory cells 301A-301C are connected to the same bit line BL, and the sense amplifier 304 is used to sense the voltage level of the bit line BL and the inverted bit line bBL. In addition, the word lines WLR, WL1, and WL2 corresponding to the memory cells 301A-301C can be turned on at the same time to connect the memory cells 301A-301C to the bit line BL. Therefore, the charges stored in the capacitors _CSR , _CS1 , and _CS2 in the memory cells 301A-301C are charge-shared, and the deviation value of the voltage level of the bit line BL after charge sharing is It will be toward the majority value of the voltage levels stored by the capacitors _CSR , _CS1 and _CS2 of the three memory cells 301A-301C.

For example, if at least two of the capacitors _CSR , _CS1 and _CS2 of the memory cells 301A-301C are initially in a charged state, the voltage level of the bit line BL will have a positive deviation. Conversely, if at most one of the capacitors _CSR , _CS1 and _CS2 of the memory cells 301A-301C is initially in a charged state, the voltage level of the bit line BL will have a negative deviation.

In detail, the memory cell 301A can be regarded as a reference memory cell, and the voltage level R stored in the capacitor _CSR can be used to control the memory cell array 1211 to perform a bitwise AND operation or a bitwise OR operation. For the sake of convenience, the voltage levels stored in the capacitors _CS1 and _CS2 are A and B, respectively, and the voltage levels R, A and B can be regarded as the logic states of the memory cells 301A, 301B and 301C, respectively. Therefore, after the word lines WLR, WL1 and WL2 are turned on at the same time, the logic state OUT sensed by the sense amplifier 304 can be expressed by equation (1) or equation (2):

Therefore, if the initial logic state of the voltage level R is 1, the logic state OUT of the bit line BL after charge sharing is a bitwise OR operation of the voltage levels A and B. If the initial logic state of the voltage level R is 0, the logic state OUT of the bit line BL after charge sharing is a bitwise AND operation of the voltage levels A and B. Therefore, the truth tables of the memory cells 301A-301C performing the bitwise AND operation and the bitwise OR operation can be represented by Table 1 and Table 2 respectively: Bitwise AND operation (R=0) A B OUT 0 0 0 0 1 0 1 0 0 1 1 1 Table 1 Bitwise AND (OR) operation (R=1) A B OUT 0 0 0 0 1 1 1 0 1 1 1 1 Table 2

The deviation of the voltage level between the bit line BL and the reverse bit line bBL detected by the sense amplifier 304 in FIG. , which can be expressed by formula (3):

。 Where m represents the number of memory cells with a storage voltage level of V _BLH (i.e., a high logic state) before charge sharing; n represents the number of word lines turned on on the same bit line, where n is, for example, an integer between 0 and 3. If three word lines are turned on at the same time, n=3. If two word lines are turned on at the same time, n=2, and so on. In some embodiments, the voltage

.

1.6，則可利用表1、表2以及式(3)以推導出在同時開啟三條字元線WLR、WL1及WL2時(即n=3)，感測放大器204所偵測到的偏差值△V _BL 以及相應的位元線BL之邏輯狀態OUT，例如分別如表3及表4所示：

表3 按位或(OR)運算 (R=1) 且同時開啟三條字元線 (n=3) A B m OUT 0 0 0 -0.104V 0 0 1 1 +0.104V 1 1 0 1 +0.104V 1 1 1 2 +0.315V 1 表4 In one embodiment, assume that the voltages V _DD = 1V; V _BLH = 1V; _CS1 = _CS2 = 17fF; C _BL = 27fF;

1.6, Table 1, Table 2 and formula (3) can be used to deduce the deviation value △ V _BL detected by the sense amplifier 204 and the logic state OUT of the corresponding bit line BL when the three word lines WLR, WL1 and WL2 are turned on at the same time (i.e., n=3), as shown in Table 3 and Table 4 respectively:

table 3 Bitwise OR operation (R=1) and enable three word lines at the same time (n=3) A B m OUT 0 0 0 -0.104V 0 0 1 1 +0.104V 1 1 0 1 +0.104V 1 1 1 2 +0.315V 1 Table 4

FIG. 4A is a schematic diagram of a memory cell array in another embodiment of the present invention. FIG. 4B is a circuit diagram of a voltage control circuit in the embodiment of FIG. 4A of the present invention. Please refer to FIG. 1 and FIGS. 4A-4B at the same time.

The memory cell array 400 includes memory cells 401 and 402, a sense amplifier 404, a voltage control circuit 405, and a word line decoding circuit 406. The memory cells 401 and 402 are connected to the same bit line BL, and the sense amplifier 404 is used to sense the voltage levels of the bit line BL and the inverted bit line bBL. In addition, the word lines WL1 and WL2 corresponding to the memory cells 401 and 402 can be turned on at the same time so that the memory cells 401 and 402 are connected to the bit line BL. In this embodiment, the memory cell array 400 can charge-share the data stored in the memory cells 401 and 402 through the voltage control circuit 405 and the word line decoding circuit 406 to achieve a bitwise AND operation or a bitwise OR operation.

The voltage control circuit 405 can, for example, select the detection voltage V _BLEQ provided to the sense amplifier 404 according to the control signal 115 from the memory controller 111. In some embodiments, the voltage control circuit 405 can be , and The voltage level of the detection voltage V _BLEQ is selected between, but the present invention is not limited thereto. For example, the control signal 115 may include a control signal related to the memory operation and an address signal for turning on a related word line of the memory cell array 400. The control signal related to the memory operation includes a normal read control signal Normal_Read, or an operation control signal OR_Cal and an operation control signal AND_Cal, and at most only one of the three control signals is in a high logic state to enable the memory cell array 400 to perform a corresponding operation.

For example, when the normal read control signal Normal_Read is in a high logic state, the memory cell array 400 will perform a normal read operation, that is, the word line decoding circuit 406 will open one of the word lines according to the relevant address signal in the control signal 115 to access the data of the memory cell on the word line. At this time, the transistor Q3A in FIG. 4B will be turned on to raise the voltage as the detection voltage V _BLEQ .

When the OR operation control signal OR_Cal is in a high logic state, the memory cell array 400 will perform a bitwise OR operation. At this time, the address signal in the control signal 115 will also change to enable two word lines (e.g., word lines WL1 and WL2) at the same time to perform a bitwise OR operation on the data stored in the corresponding memory cells (e.g., memory cells 401 and 402). In addition, the transistor Q3B in FIG. 4B will turn on to turn the voltage as the detection voltage V _BLEQ .

When the AND operation control signal AND_Cal is in a high logic state, the memory cell array 400 will perform a bitwise AND operation. At this time, the address signal in the control signal 115 will also change to enable two word lines (e.g., word lines WL1 and WL2) at the same time to perform a bitwise AND operation on the data stored in the corresponding memory cells (e.g., memory cells 401 and 402). In addition, the transistor Q3C in FIG. 4B will turn on to turn the voltage as the detection voltage V _BLEQ .

Regardless of whether the memory cell array 400 performs a bitwise OR operation or a bitwise AND operation, the charge sharing mechanism of the memory cells 401 and 402 on the bit line BL can still refer to equation (3), but this time, because two word lines WL1 and WL2 are turned on at the same time, the value of n is equal to 2.

In the embodiment of FIG. 4A-4B, it is assumed that voltage levels A and B can be regarded as the logical states of memory cells 401 and 402, respectively. According to similar data of the embodiment of FIG. 3: voltage =1V; V _BLH =1V; C _S1 =C _S2 =17fF; C _BL =27fF; , it can be deduced that when two word lines WL1 and WL2 are turned on at the same time (ie n=2), the deviation value detected by the sense amplifier 404 is And the corresponding logic state OUT of the bit line BL are shown in Table 5 and Table 6 respectively: Bitwise AND operation (AND_Cal=1) and enable two word lines at the same time (n=2) A B m V _BLEQ OUT 0 0 0 -0.417V 0 0 1 1 -0.139V 0 1 0 1 -0.139V 0 1 1 2 +0.139V 1 table 5 Bitwise OR operation (OR_Cal=1) and turn on two word lines at the same time (n=2) A B m V _BLEQ OUT 0 0 0 -0.139V 0 0 1 1 +0.139V 1 1 0 1 +0.139V 1 1 1 2 +0.417V 1 Table 6

Combining the embodiments of FIG. 3 and FIG. 4A-4B, it can be deduced that the deviation value of opening three word lines at the same time and opening two word lines at the same time is The impact is shown in Table 7: Bitwise operations A B - AND 0 0 -0.315V -0.417V 102mV 0 1 -0.104V -0.139V 35mV 1 0 -0.104V -0.139V 35mV 1 1 +0.104V +0.139V 35mV OR 0 0 -0.104V -0.139V 35mV 0 1 +0.104V +0.139V 35mV 1 0 +0.104V +0.139V 35mV 1 1 +0.315V +0.417V 102mV Table 7

in, Indicates the deviation value in Figure 4A-4B ; Indicates the deviation value in Figure 3 Therefore, it can be seen from Table 7 that when the memory cell array 400 performs a bitwise AND operation, when the voltage levels (A, B) are (0,0), (0,1), (1,0) and (1,1) respectively, the deviation value The signal margin is greater than the deviation value In addition, when the memory cell array 400 performs a bitwise OR operation, when the voltage levels (A, B) are (0,0), (0,1), (1,0) and (1,1), respectively, the deviation value The signal margin is also greater than the deviation value. In other words, compared to the memory cell array 300 in FIG. 3 , the memory cell array 400 in FIG. 4A has a larger signal range, so the sense amplifier 404 can more easily and accurately determine the logic level of the bit line BL and has a greater tolerance for semiconductor process variations.

In summary, the present invention provides a memory device capable of performing in-memory operations, which includes a memory cell array that can use a word line decoding circuit to simultaneously open multiple word lines to perform charge sharing for corresponding memory cells, and use a voltage control circuit to select an appropriate detection voltage to perform a bitwise AND operation or a bitwise OR operation. Therefore, the memory cell array of the present invention can have a larger signal range and a greater tolerance for semiconductor process variations.

10: Computing device 110: Central processing unit 111: Memory controller 112: Arithmetic logic unit 113: Cache memory 115: Control signal 116: Data bus 120: Memory device 121-12N: Memory bank 1211-121N: Memory cell array 201: Memory cell 202: Word line 203: Bit line 204: Sense amplifier 2011: Transistor 2012: Capacitor 301A-301C: Memory cell 304: Sense amplifier 400: Memory cell array 401, 402: Memory cell 404: Sense amplifier 405: Voltage control circuit 406: Word line decoding circuit V _DD , V _BLH : Voltage V _BLEQ : Detection voltage : Deviation value 1~5: State BL: Bit line bBL: Reverse bit line WLR, WL1, WL2: Word line Q1A, Q1B, Q1C, Q2A, Q2B: Transistor Q3A, Q3B, Q3C: Transistor C _BL , C _SR , C _S1 , C _S2 : Capacitor Normal_Read: Normal read control signal OR_Cal: Or operation control signal AND_Cal: And operation control signal

FIG. 1 is a schematic diagram of an operation device according to an embodiment of the present invention. FIG. 2A is a circuit diagram of a memory cell array according to the embodiment of FIG. 1 of the present invention. FIG. 2B is a circuit diagram of a memory cell according to the embodiment of FIG. 2A of the present invention. FIG. 2C is a schematic diagram of a read program of a memory cell according to the embodiment of FIG. 2B of the present invention. FIG. 3 is a schematic diagram of a memory cell array according to an embodiment of the present invention. FIG. 4A is a schematic diagram of a memory cell array according to another embodiment of the present invention. FIG. 4B is a circuit diagram of a voltage control circuit according to the embodiment of FIG. 4A of the present invention.

115: Control signal

400: Memory cell array

401, 402: memory unit

404: Sense amplifier

405: Voltage control circuit

406: Character line decoding circuit

BL: Bit Line

bBL: reverse bit line

WL1, WL2: character line

Q2A, Q2B: Transistor

C _BL , _CS1 , _CS2 : Capacitor

V _BLEQ : Detection voltage

Claims (10)

A memory device capable of executing in-memory operations comprises: a memory cell array, comprising a plurality of memory cells arranged in a two-dimensional array, wherein the memory cells on each row of the memory cell array are connected to a corresponding word line, and the memory cells on each column of the memory cell array are connected to a corresponding bit line; a sense amplifier for detecting the voltage level on the turned-on bit line and the inverted bit line corresponding to the bit line, and a voltage control circuit for controlling the voltage level of the turned-on bit line according to a memory control circuit; A control signal from a memory controller is used to select a detection voltage provided to the sense amplifier; and a word line decoding circuit is used to turn on the first word line and the second word line among the word lines according to the control signal; wherein the memory cell array is operated according to the control signal from the memory controller, and the control signal includes a normal read control signal, an OR operation control signal and an AND operation control signal, and one of the normal read control signal, the OR operation control signal and the AND operation control signal is in a high logic state. A memory device capable of performing in-memory operations as in claim 1, wherein the voltage control circuit selects a first voltage, a second voltage, or a third voltage as the detection voltage provided to the sense amplifier according to the control signal from the memory controller. A memory device capable of performing in-memory operations as in claim 2, wherein the third voltage is greater than the first voltage, and the first voltage is greater than the second voltage. A memory device capable of performing in-memory operations as in claim 2, wherein the high logic state of the bit line has a first voltage level, and the first voltage is 1/2 of the first voltage level, the second voltage is 1/4 of the first voltage level, and the third voltage is 3/4 of the first voltage level. A memory device capable of performing in-memory operations as in claim 2, wherein the memory cell array includes a first memory cell and a second memory cell connected to the first word line and the second word line respectively, and the first memory cell and the second memory cell are simultaneously connected to the bit line. A memory device capable of performing in-memory operations as in claim 5, wherein the first capacitor of the first memory cell and the second capacitor of the second memory cell respectively store a first data voltage and a second data voltage in an initial state, wherein when the OR operation control signal or the AND operation control signal is in the high logic state, the word line decoding circuit turns on the first word line and the second word line simultaneously according to the address signal in the control signal, and the first capacitor of the first memory cell and the second capacitor of the second memory cell perform charge sharing to change a precharge voltage of the bit line to a result voltage, and the result voltage is the precharge voltage plus an offset value. A memory device capable of performing in-memory operations as claimed in claim 6, wherein when the OR operation control signal is in the high logic state, the voltage control circuit selects the second voltage as the detection voltage provided to the sense amplifier, wherein the voltage level of the bit line detected by the sense amplifier is a bitwise OR operation of the first data voltage and the second data voltage. A memory device capable of performing in-memory operations as claimed in claim 7, wherein when the first data voltage and the second data voltage are in a low logic state, the voltage level of the bit line detected by the sense amplifier is in the low logic state, and when at least one of the first data voltage and the second data voltage is in the high logic state, the voltage level of the bit line detected by the sense amplifier is in the high logic state. A memory device capable of performing in-memory operations as claimed in claim 6, wherein when the AND operation control signal is in the high logic state, the voltage control circuit selects the third voltage as the detection voltage provided to the sense amplifier, wherein the voltage level of the bit line detected by the sense amplifier is a bitwise AND operation performed on the first data voltage and the second data voltage. A memory device capable of performing in-memory operations as claimed in claim 9, wherein when at least one of the first data voltage and the second data voltage is in a low logic state, the voltage level of the bit line detected by the sense amplifier is in the low logic state, and when both the first data voltage and the second data voltage are in the high logic state, the voltage level of the bit line detected by the sense amplifier is in the high logic state.

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