CN118136063A - Memory device capable of executing in-memory operation - Google Patents

Abstract

A memory device operable to perform in-memory operations, comprising: memory cell array, sense amplifier, voltage control circuit and word line decoding circuit. The memory cell array includes a plurality of memory cells arranged in a two-dimensional array. The memory cells on each column in the memory cell array are connected to a respective word line, and the memory cells on each row in the memory cell array are connected to a respective bit line. The sense amplifier detects the voltage level on the bit line that has been turned on and the inverted bit line corresponding to the bit line. The voltage control circuit selects a detection voltage provided to the sense amplifier according to a control signal from the memory controller. The word line decoding circuit starts a first word line and a second word line of the plurality of word lines according to the control signal. The memory cell array of the present invention can have a larger signal range and can have a larger tolerance for semiconductor process variations.

Description

Memory device capable of executing in-memory operation

Technical Field

The present invention relates to a memory device, and more particularly, to a memory device capable of performing in-memory operations.

Background

Conventional computer devices typically use Von Neumann (Von Neumann) architecture for data transfer between the central processor and the memory devices. However, when the data transfer amount between the cpu and the memory device is extremely large, a bottleneck of data transfer, which is called von neumann bottleneck, is often generated between the cpu and the memory device. Accordingly, there is a need for a memory device that can perform in-memory operations to solve the above-described problems.

Disclosure of Invention

The invention provides a memory device capable of executing in-memory operation, comprising: a memory cell array comprising a plurality of memory cells arranged in a two-dimensional array, wherein the plurality of memory cells on each column of the memory cell array are connected to respective word lines and the plurality of memory cells on each row of the memory cell array are connected to respective bit lines; a sense amplifier for detecting the voltage level on the turned-on bit line and the inverted bit line corresponding to the bit line, a voltage control circuit for selecting the detection voltage supplied to the sense amplifier according to a control signal from a memory controller; and a word line decoding circuit for turning on the first word line and the second word line of the plurality of word lines according to the control signal.

The memory cell array of the present invention can have a larger signal range and can have a larger tolerance for semiconductor process variations.

Drawings

Fig. 1 is a schematic diagram of an arithmetic device according to an embodiment of the invention.

FIG. 2A is a circuit diagram of the memory cell array of the embodiment of FIG. 1 according to the present invention.

FIG. 2B is a circuit diagram of the memory cell of the embodiment of FIG. 2A according to the present invention.

FIG. 2C is a schematic diagram of a memory cell reading process according to the embodiment of FIG. 2B.

FIG. 3 is a schematic diagram of a memory cell array according to an embodiment of the invention.

FIG. 4A is a schematic diagram of a memory cell array according to another embodiment of the invention.

Fig. 4B is a circuit diagram of the voltage control circuit in the embodiment of fig. 4A according to the present invention.

Reference numerals:

10 arithmetic device

110 Central processing unit

111 Memory controller

112 Arithmetic logic unit

113 Cache memory

115 Control signal

116 Data bus

120 Memory device

121-12N memory bank

1211-121N memory cell array

201 Memory cell

202 Word line

203 Bit line

204 Sense amplifier

2011 Transistor

2012 Capacitor

301A-301C memory cells

304 Sense amplifier

400 Memory cell array

401. 402 Memory cell

404 Sense amplifier

405 Voltage control Circuit

406 Word line decoding circuit

V _DD、V_BLH Voltage

V _BLEQ detection voltage

Delta deviation value

①～⑤ Status of

BL bit line

BBL opposite bit line

WLR, WL1, WL2 word lines

Q1A, Q1B, Q1C, Q2A, Q B transistor

Q3A, Q3B, Q C transistor

C _BL、C_SR、C_S1、C_S2 capacitance

Normal_read Normal Read control signal

OR_Cal OR operation control signal

AND_Cal, arithmetic control Signal

Detailed Description

Fig. 1 is a schematic diagram of an arithmetic device according to an embodiment of the invention. As shown in fig. 1, the computing device 10 includes a central processing unit 110 and a memory device 120. The cpu 110 is electrically connected to the memory device 120, wherein the memory device 120 is, for example, a Dynamic Random Access Memory (DRAM), but the present invention is not limited thereto. The memory device 120 includes, for example, a plurality of memory banks (memory banks), and each memory bank includes a plurality of memory cell arrays, wherein the memory cell arrays are arranged in, for example, a two-dimensional array (e.g., M columns by N rows), and each column and each row of the memory cell arrays are respectively connected to a corresponding word line and bit line. In addition, each memory cell may store 1 bit or M bits of data, where M is an integer greater than 1.

The CPU 110 includes, for example, a memory controller 111, an arithmetic logic unit (ARITHMETIC LOGIC UNIT, ALU) 112, and a cache 113. The memory controller 111 is used for controlling data access of the memory device 120. It should be noted that the control signal 115 sent from the memory controller 111 to the memory device 120 may control the memory device 120 to perform an in-memory computing (in-memory computing), such as a bitwise AND (AND)/OR (OR) operation. The memory controller 111 may further receive the bitwise data or general data not subjected to the logic operation from the memory device 120.

The ALU 112 performs corresponding arithmetic and/or logical operations according to instructions executed by the CPU 110. In some embodiments, to reduce the data bandwidth requirement between the CPU 110 AND the memory device 120, the memory controller 111 of the CPU 110 sends corresponding control signals 115 to the memory device 120 to perform part of the logic operations (e.g., bitwise AND (AND)/OR (OR) operations) on the memory device 120, AND receives the data (e.g., via the data bus 116) from the memory device 120 after the logic operations, AND then sends the data to the ALU 112 for subsequent processing.

The memory device 120 includes, for example, a plurality of memory banks 121 to 12N, and each memory bank 121 to 121N includes a plurality of memory cell arrays 1211 to 121N.

FIG. 2A is a circuit diagram of the memory cell array of the embodiment of FIG. 1 according to the present invention. Please refer to fig. 1 and fig. 2A simultaneously.

In FIG. 2A, a memory cell array 1211 is illustrated, and the circuit diagram of the other memory cell arrays 1212-121N is similar to that of FIG. 2A. The memory cell array 1211 includes a plurality of memory cells 201 arranged in a two-dimensional array, with each column of memory cells 201 connected to a respective word line 202 and each row of memory cells 201 connected to a respective bit line 203. In addition, each bit line 203 is connected to a respective sense amplifier 204.

FIG. 2B is a circuit diagram of the memory cell of the embodiment of FIG. 2A according to the present invention. FIG. 2C is a schematic diagram of a memory cell reading process according to the embodiment of FIG. 2B.

Referring to fig. 2B, the memory cell 201 includes a transistor 2011 and a capacitor 2012, wherein the logic level of the word line 202 controls the transistor 2011 to be turned on and off. In addition, fig. 2C is a schematic diagram showing five states ①～⑤ of the memory unit 201 performing the access procedure.

In fig. 2C, the capacitance 2012 of the memory cell 201 is in a fully charged state. State 1 represents an initial precharge state, at which the word line 202 logic level is 0 and the sense amplifier 204 is turned off, and the bit line 203 voltage level is precharged to a voltageThen, the memory cell 201 access operation is triggered by the ACT command on the corresponding word line 202 of the memory cell 201 to enter state 2. In state 2, the word line 202 is turned on, so that its voltage level reaches the voltage V _DD. At this time, the sense amplifier 204 is still in the off state. State 3 represents a charge sharing state in which charge stored in the capacitor 2012 flows from the memory cell 201 to the bit line 203 such that the voltage level of the bit line 203 is increased to a voltage/>At this time, the sense amplifier 204 is still in the off state. In state 4, the sense amplifier 204 is turned on to sense the voltage level and voltage of the bit line 203A deviation delta (which may be a positive or negative deviation) between the two, and amplifying the deviation delta until the voltage level of the bit line 203 reaches the voltage/>I.e. enter state 5. At this time, since the capacitor 2012 is still connected to the bit line 203, the potential stored in the capacitor 2012 is charged to the original fully charged state.

FIG. 3 is a schematic diagram of a memory cell array according to an embodiment of the invention. Please refer to fig. 1 and fig. 3 simultaneously.

Memory cell array 1211 includes memory cells 301A, 301B, and 301C, with memory cells 301A-301C connected to the same bit line BL and sense amplifier 304 for sensing the voltage levels of bit line BL and inverted bit line bBL. In addition, the corresponding word lines WLR, WL1 and WL2 of memory cells 301A-301C may be turned on simultaneously to connect memory cells 301A-301C to bit line BL. Therefore, the charges stored in the capacitors C _SR、C_S1 and C _S2 of the memory cells 301A-301C are charge-shared, and the voltage level deviation delta of the bit line BL after the charge sharing is toward the majority of the voltage levels stored in the capacitors C _SR、C_S1 and C _S2 of the three memory cells 301A-301C.

For example, if at least two of the capacitances C _SR、C_S1 and C _S2 of the memory cells 301A-301C are initially in a charged state, then a positive deviation in the voltage level of the bit line BL occurs. Conversely, if at most one of the capacitances C _SR、C_S1 and C _S2 of the memory cells 301A-301C is initially in the charged state, then a negative deviation in the voltage level of the bit line BL occurs.

In detail, the memory cell 301A can be considered a reference memory cell, AND the voltage level R stored by the capacitor C _SR can be used to control the memory cell array 1211 to perform a bitwise AND (AND) operation, OR a bitwise OR (OR) operation. For ease of illustration, the voltage levels stored by the capacitors C _S1 and C _S2 are A and B, respectively, and the voltage levels R, A and B can be considered the logic states of the memory cells 301A, 301B, and 301C, respectively. Thus, after simultaneously turning on word lines WLR, WL1 and WL2, the logic state OUT sensed by sense amplifier 304 may be represented by either equation (1) or equation (2):

OUT＝RA+RB+AB (1)

Therefore, if the initial logic state of the voltage level R is 1, the bit line BL performs a bitwise OR (OR) operation with the charge-shared logic state OUT being the voltage levels a and B. If the initial logic state of the voltage level R is 0, the bit line BL performs a bitwise AND (AND) operation with the charge-shared logic state OUT being the voltage levels a AND B. Thus, the truth tables for memory cells 301A-301C performing a bitwise AND (AND) operation, as well as a bitwise OR (OR) operation, can be represented by tables 1 AND 2, respectively:

TABLE 1

TABLE 2

For the deviation DeltaV _BL of the voltage level between the bit line BL and the inverted bit line bBL detected by the sense amplifier 304 in FIG. 3, the following equation (3) can be used:

Where m represents the number of memory cells storing a voltage level V _BLH (i.e., representing a high logic state) prior to charge sharing; n represents the number of word lines that are on the same bit line, where n is, for example, an integer between 0 and 3. If three word lines are turned on simultaneously, n=3. If both word lines are turned on at the same time, n=2, and so on. In some embodiments, the voltage

In one embodiment, assume that voltage V _DD＝1V;V_BLH＝1V;C_S1＝C_S2＝17fF;C_BL = 27fF; Then, table 1, table 2 and equation (3) can be used to derive the deviation Δv _BL detected by the sense amplifier 204 and the logic state OUT of the corresponding bit line BL when the three word lines WLR, WL1 and WL2 are turned on simultaneously (i.e., n=3), as shown in, for example, tables 3 and 4, respectively:

TABLE 3 Table 3

TABLE 4 Table 4

FIG. 4A is a schematic diagram of a memory cell array according to another embodiment of the invention. Fig. 4B is a circuit diagram of the voltage control circuit in the embodiment of fig. 4A according to the present invention. Please refer to fig. 1 and fig. 4A-4B.

The memory cell array 400 includes memory cells 401 and 402, a sense amplifier 404, a voltage control circuit 405, and a word line decoding circuit 406. Memory cells 401 and 402 are connected to the same bit line BL, and sense amplifier 404 is used to sense the voltage levels of bit line BL and inverted bit line bBL. In addition, the corresponding word lines WL1 and WL2 of memory cells 401 and 402 may be turned on simultaneously to connect memory cells 401 and 402 to bit line BL. In this embodiment, the memory cell array 400 can be used to perform charge sharing on the data stored in the memory cells 401 AND 402 through the voltage control circuit 405 AND the word line decoding circuit 406 to achieve a bit-wise AND (AND) operation OR a bit-wise OR (OR) operation.

The voltage control circuit 405 may select the detection voltage V _BLEQ provided to the sense amplifier 404, for example, according to the control signal 115 from the memory controller 111. In some embodiments, the voltage control circuit 405 may be at a voltage />The voltage level of the detection voltage V _BLEQ is selected, but the present invention is not limited thereto. For example, the control signals 115 may include associated control signals for memory operations, and address signals for turning on associated word lines of the memory cell array 400. The related control signals for the memory operation include a Normal Read control signal normal_read, an operation control signal or_cal, AND an AND operation control signal AND_cal, AND at most only one of the three control signals is in a high logic state to enable the memory cell array 400 to perform the corresponding operation.

For example, when the Normal Read control signal normal_read is in a high logic state, the memory cell array 400 performs a Normal Read operation, i.e., the word line decoding circuit 406 turns on one of the word lines according to the associated address signal in the control signal 115 to access data to the memory cells on the word line. At this time, the transistor Q3A in FIG. 4B is turned on to apply the voltageAs the detection voltage V _BLEQ.

When the OR_Cal signal is in a high logic state, the memory cell array 400 performs a bit-wise OR operation. At this time, the address signal in the control signal 115 is also changed to enable both word lines (e.g., word lines WL1 and WL 2) simultaneously to perform a bitwise OR (OR) operation on the data stored in the corresponding memory cells (e.g., memory cells 401 and 402). In addition, the transistor Q3B in FIG. 4B is turned on to apply the voltageAs the detection voltage V _BLEQ.

When the AND operation control signal AND_Cal is in a high logic state, the memory cell array 400 performs a bitwise AND operation. At this time, the address signal in the control signal 115 is also changed to enable two word lines (e.g., word lines WL1 AND WL 2) simultaneously to perform a bitwise AND (AND) operation on the data stored in the corresponding memory cells (e.g., memory cells 401 AND 402). In addition, the transistor Q3C in FIG. 4B is turned on to apply the voltageAs the detection voltage V _BLEQ.

Whether the memory cell array 400 performs a bit-wise OR operation OR a bit-wise AND operation, the charge sharing mechanism on the bit lines BL of the memory cells 401 AND 402 can still refer to (3), except that the value of n is equal to 2 because both word lines WL1 AND WL2 are turned on at the same time.

In the embodiment of fig. 4A-4B, it is assumed that voltage levels a and B can be considered as logic states of memory cells 401 and 402, respectively, according to similar data as the embodiment of fig. 3: voltage V _DD＝1V;V_BLH＝1V;C_S1＝C_S2＝17fF;C_BL = 27fF; it can be deduced that when two word lines WL1 and WL2 are simultaneously turned on (i.e., n=2), the bias value Δv _BL detected by the sense amplifier 404 and the logic state OUT of the corresponding bit line BL are shown in, for example, tables 5 and 6, respectively:

TABLE 5

TABLE 6

Combining the embodiments of fig. 3 and fig. 4A-4B, the effect of simultaneously turning on 3 word lines and simultaneously turning on 2 word lines on the bias value Δv _BL can be deduced, as shown in table 7:

TABLE 7

Wherein Δv _{BL_2WL} represents the deviation value Δv _BL;ΔV_{BL_3WL} in fig. 4A-4B, and Δv _BL in fig. 3. Thus, as can be seen from table 7, when the memory cell array 400 performs the bitwise AND (AND) operation, the signal range (SIGNAL MARGIN) of the offset Δv _{BL_2WL} is larger than the signal range of the offset Δv _{BL_3WL} when the voltage levels (a, B) are (0, 0), (0, 1), (1, 0), AND (1, 1), respectively. In addition, when the memory cell array 400 performs a bit-wise OR operation, the signal range (SIGNAL MARGIN) of the offset Δv _{BL_2WL} is also larger than the signal range of the offset Δv _{BL_3WL} when the voltage levels (a, B) are (0, 0), (0, 1), (1, 0), and (1, 1), respectively. In other words, the memory cell array 400 in fig. 4A has a larger signal range than the memory cell array 300 in fig. 3, so that the sense amplifier 404 can determine the logic level of the bit line BL more easily and accurately, and has a larger tolerance to semiconductor process variations.

In summary, the present invention provides a memory device capable of performing an in-memory operation, which includes a memory cell array capable of performing a bit-wise AND (AND) operation OR a bit-wise OR (OR) operation by simultaneously turning on a plurality of word lines to charge-share the corresponding memory cells by using a word line decoding circuit AND selecting an appropriate detection voltage by using a voltage control circuit. Therefore, the memory cell array of the present invention can have a larger signal range and can have a larger tolerance for semiconductor process variations.

Claims (11)

1. A memory device operable to perform in-memory operations, comprising:

a memory cell array comprising a plurality of memory cells arranged in a two-dimensional array, wherein the plurality of memory cells on each column of the memory cell array are connected to respective word lines and the plurality of memory cells on each row of the memory cell array are connected to respective bit lines;

A sense amplifier for detecting the voltage level on the turned-on bit line and the inverted bit line corresponding to the bit line,

A voltage control circuit for selecting the detection voltage provided to the sense amplifier according to a control signal from a memory controller; and

And the word line decoding circuit is used for starting a first word line and a second word line in the plurality of word lines according to the control signal.

2. The memory device of claim 1, wherein the voltage control circuit selects a first voltage, a second voltage, or a third voltage as the detection voltage provided to the sense amplifier according to the control signal from the memory controller.

3. The memory device of claim 2, wherein the third voltage is greater than the first voltage and the first voltage is greater than the second voltage.

4. The memory device of claim 2, wherein the high logic state of the bit line has a first voltage level, the first voltage is 1/2 of the first voltage level, the second voltage is 1/4 of the first voltage level, and the third voltage is 3/4 of the first voltage level.

5. The memory device of claim 2, wherein the control signal comprises a normal read control signal, an OR control signal, and a AND control signal, and wherein one of the normal read control signal, the OR control signal, and the AND control signal is in a high logic state.

6. The memory device of claim 5, wherein the memory cell array comprises a first memory cell and a second memory cell connected to the first word line and the second word line, respectively, and the first memory cell and the second memory cell are simultaneously connected to the bit line.

7. The memory device of claim 6, wherein the first capacitor of the first memory cell and the second capacitor of the second memory cell store a first data voltage and a second data voltage, respectively, in an initial state,

When the OR control signal or the AND control signal is in the high logic state, the word line decoding circuit simultaneously starts the first word line and the second word line according to an address signal in the control signal, and the first capacitor of the first memory cell and the second capacitor of the second memory cell are subjected to charge sharing so as to change a precharge voltage of the bit line to a result voltage, and the result voltage is the precharge voltage plus an offset value.

8. The memory device of claim 7, wherein when the OR control signal is in the high logic state, the voltage control circuit selects the second voltage as the sense voltage provided to the sense amplifier,

The voltage level of the bit line detected by the sense amplifier is the first data voltage and the second data voltage for bit-wise OR operation.

9. The memory device of claim 8, wherein when the first data voltage and the second data voltage are in a low logic state, the voltage level of the bit line detected by the sense amplifier is in the low logic state,

Wherein the voltage level of the bit line detected by the sense amplifier is in the high logic state when at least one of the first data voltage and the second data voltage is in the high logic state.

10. The memory device of claim 7, wherein when the AND operation control signal is in the high logic state, the voltage control circuit selects the third voltage as the detection voltage provided to the sense amplifier,

The voltage level of the bit line detected by the sense amplifier is the first data voltage and the second data voltage for bit-wise operation.

11. The memory device of claim 10, wherein when at least one of the first data voltage and the second data voltage is in a low logic state, the voltage level of the bit line detected by the sense amplifier is in the low logic state,

Wherein the voltage level of the bit line detected by the sense amplifier is in the high logic state when the first data voltage and the second data voltage are both in the high logic state.