TWI842807B - Semiconductor light emitting element and method for manufacturing the same - Google Patents

Abstract

The purpose of the present invention is to improve the reliability of semiconductor light-emitting devices. The semiconductor light-emitting device 10 of the present invention comprises: an n-type semiconductor layer 24; an active layer 26 disposed in a first region on the n-type semiconductor layer 24; a p-type semiconductor layer 30 disposed on the active layer 26; a first cover layer 34 made of aluminum oxide (Al ₂ O ₃ ) and is arranged in a manner to cover a second region different from the first region on the n-type semiconductor layer 24, a side surface of the active layer 26 and the p-type semiconductor layer 30; an n-side contact electrode 36 passes through the first cover layer 34 and contacts the n-type semiconductor layer 24; a p-side contact electrode 40 passes through the first cover layer 34 and contacts the p-type semiconductor layer 30; and a second cover layer 44 is arranged in a manner to cover the first cover layer 34, the n-side contact electrode 36 and the p-side contact electrode 40.

Description

Semiconductor light emitting element and method for manufacturing semiconductor light emitting element

The present invention relates to a semiconductor light-emitting element and a method for manufacturing the semiconductor light-emitting element.

The deep ultraviolet light emitting element has an aluminum gallium nitride (AlGaN) system n-type clad layer, an active layer, and a p-type clad layer stacked in sequence on a substrate. An n-side electrode is formed on a portion of the n-type clad layer exposed by etching, and a p-side electrode is formed on the p-type clad layer. A protective insulating film such as silicon oxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ ) is provided on the n-side electrode and the p-side electrode (see, for example, Patent Document 1).

[Prior Art Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent No. 5985782.

It is better to be able to cover the surface of the light-emitting element more appropriately.

This invention is developed in view of the above-mentioned issues. One of the exemplary purposes of this invention is to improve the reliability of semiconductor light-emitting elements.

The semiconductor light emitting device of one embodiment of the present invention comprises: an n-type semiconductor layer, which is an n-type aluminum gallium nitride (AlGaN) semiconductor material and is disposed on a substrate; an active layer, which is an AlGaN semiconductor material and is disposed in a first region on the n-type semiconductor layer; a p-type semiconductor layer, which is a p-type AlGaN semiconductor material and is disposed on the active layer; a first cover layer, which is made of aluminum _oxide ( _Al2O3 ) and is arranged in a manner of covering a second region different from a first region on the n-type semiconductor layer, a side surface of the active layer, and a p-type semiconductor layer; an n-side contact electrode penetrates the first covering layer and contacts the n-type semiconductor layer; and a p-side contact electrode penetrates the first covering layer and contacts the p-type semiconductor layer. type semiconductor layer; a second cover layer is arranged in a manner of covering the first cover layer, the n-side contact electrode and the p-side contact electrode; an n-side pad electrode penetrates the second cover layer and is connected to the n-side contact electrode; and a p-side pad electrode penetrates the second cover layer and is connected to the p-side contact electrode.

According to this aspect, since the n-type semiconductor layer, the active layer, and the p-type semiconductor layer composed of the AlGaN-based semiconductor material are covered with aluminum oxide (Al ₂ O ₃ ) having excellent moisture resistance, the surfaces of these semiconductor layers can be covered more appropriately. Furthermore, a second covering layer is provided to further cover the first covering layer, the n-side contact electrode, and the p-side contact electrode, thereby protecting the first covering layer and appropriately covering the surface of the contact electrode. In this way, a semiconductor light-emitting element with high reliability can be provided.

It may further include a third cover layer made of aluminum oxide (Al ₂ O ₃ ) and provided to cover at least a portion of the surface of the substrate, the second cover layer, the side surface of the n-side pad electrode, and the side surface of the p-side pad electrode.

It may also further include: a mounting substrate including an n-side mounting electrode connected to the n-side pad electrode and a p-side mounting electrode connected to the p-side pad electrode. It may also be that the third covering layer is further provided in a manner of covering at least a portion of the surface of the mounting substrate.

The concentration of hydrogen contained in the first covering layer is lower than the concentration of hydrogen contained in the third covering layer.

The semiconductor device may further include a protective insulating layer made of silicon oxide (SiO ₂ ) or silicon oxynitride (SiON) and disposed between the p-type semiconductor layer and the first capping layer.

Alternatively, the molar fraction of the n-type semiconductor layer of aluminum nitride (AlN) may be greater than 20%, and the active layer may be configured to emit ultraviolet light with a wavelength of less than 350nm.

Another aspect of the present invention is a method for manufacturing a semiconductor light-emitting device. The method for manufacturing a semiconductor light-emitting device comprises: sequentially stacking the following layers on a substrate: an n-type semiconductor layer, which is an n-type aluminum gallium nitride (AlGaN) semiconductor material; an active layer, which is an AlGaN semiconductor material on the n-type semiconductor layer; and a p-type semiconductor layer, which is a p-type AlGaN semiconductor material on the active layer; removing a portion of the p-type semiconductor layer, a portion of the active layer, and a portion of the n-type semiconductor layer in a manner that a portion of the n-type semiconductor layer is exposed; forming an aluminum oxide ( _{Al2O3 )} layer in a manner that covers the exposed region of the n-type semiconductor layer, the side of the active layer, and the p-type semiconductor layer; ) formed by the first covering layer; the step of partially removing the first covering layer and forming an n-side contact electrode contacting the n-type semiconductor layer; the step of partially removing the first covering layer and forming a p-side contact electrode contacting the p-type semiconductor layer; forming the first covering layer, the n-side The invention further comprises a step of forming a second covering layer covering the p-side contact electrode and the p-side contact electrode; a step of partially removing the second covering layer and forming an n-side pad electrode connected to the n-side contact electrode; and a step of partially removing the second covering layer and forming a p-side pad electrode connected to the p-side contact electrode.

According to this aspect, since the n-type semiconductor layer, the active layer, and the p-type semiconductor layer composed of the AlGaN-based semiconductor material are covered with aluminum oxide (Al ₂ O ₃ ) having excellent moisture resistance, the surfaces of these semiconductor layers can be covered more appropriately. Furthermore, a second covering layer is provided to further cover the first covering layer, the n-side contact electrode, and the p-side contact electrode, thereby protecting the first covering layer and appropriately covering the surface of the contact electrode. In this way, a semiconductor light-emitting element with high reliability can be provided.

Alternatively, the first covering layer may be formed by an atomic layer deposition method using an organic aluminum compound and oxygen (O ₂ ) plasma or ozone (O ₃ ) as raw materials.

There may be _a further step of forming a third covering layer made of aluminum oxide ( _Al2O3 ) so as to cover the surface of the substrate, the second covering layer, the side surface of the n-side pad electrode, and at least a portion of the side surface of the p-side pad electrode. The third covering layer is formed by an atomic layer deposition method using an organic aluminum compound and water ( _H2O ) as raw materials.

According to the present invention, the reliability of semiconductor light-emitting elements can be improved.

10,110:Semiconductor light-emitting element

12,112: Bare crystal

14: Install the substrate

16n,16p:Metal bonding material

18: Covering layer (third covering layer)

20: Substrate

20a: first main surface

20b: Second main surface

20c: Outer surface

20d: Side

22: Buffer layer

24: n-type coating layer

24a: first upper surface

24b: Second upper surface

26: Active layer

28:Electron blocking layer

30: p-type coating layer

32: Protect the insulating layer

34: First covering layer

36: n-side contact electrode

38: n-side protective metal layer (protective metal layer)

40: p-side contact electrode

42: p-side protective metal layer (protective metal layer)

44: Second covering layer

46: n-side pad electrode (pad electrode)

48: p side pad electrode (pad electrode)

50: Base

50a: first main surface

50b: Second main surface

50c: Side

52n:n side mounted electrode

52p:p side mounted electrode

54n: n-side external terminal

54p:p side external terminal

61: First mask

62: Second mask

63: The third mask

64: The fourth mask

65: The fifth mask

66: The sixth mask

67: The Seventh Mask

71,72,73,75,76,77: Dry etching

81: First opening

82: Second opening

83: The third opening

84: The fourth opening

85: The fifth opening

86: The sixth opening

87: The seventh opening

88: The eighth opening

89: The ninth opening

144: Second covering layer

144a: First level

144b: Second level

W1: The first area (exposed area)

W2: The second area (peripheral area)

W3n,W5n,W6n,W7n: n-side electrode region

W3p,W5p,W6p,W7p: p-side electrode region

W4: The fourth area

[Figure 1] is a cross-sectional view schematically showing the structure of a semiconductor light-emitting element.

[Figure 2] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 3] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 4] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 5] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 6] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 7] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 8] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 9] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 10] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 11] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 12] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 13] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 14] is a diagram schematically showing the structure of another embodiment of a semiconductor light-emitting element.

[Figure 15] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 16] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 17] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

[Figure 18] is a diagram schematically showing the manufacturing steps of a semiconductor light-emitting element.

Below, the form for implementing the present invention is described in detail with reference to the drawings. In addition, the same symbol is given to the same element in the description and repeated descriptions are omitted as appropriate. In addition, in order to help understand the description, the size ratio of each component in each drawing may not necessarily be consistent with the size ratio of the actual light-emitting element.

FIG1 is a cross-sectional view schematically showing the structure of a semiconductor light-emitting element 10 of an embodiment. The semiconductor light-emitting element 10 is an LED (Light Emitting Diode) chip configured to emit "deep ultraviolet light" with a central wavelength λ of about 360nm or less. In order to output deep ultraviolet light of such a wavelength, the semiconductor light-emitting element 10 is composed of an aluminum gallium nitride (AlGaN) semiconductor material with a bandgap of about 3.4eV or more. In this embodiment, the case of emitting deep ultraviolet light with a central wavelength λ of about 240nm to 350nm is particularly shown.

In this specification, the so-called "AlGaN-based semiconductor material" refers to a semiconductor material containing at least aluminum nitride (AlN) and gallium nitride (GaN), and also includes a semiconductor material containing other materials such as indium nitride (InN). Thus, the "AlGaN-based semiconductor material" referred to in this specification can be represented by the composition of _{In1-xyAlxGayN (} 0<x+y≦1, 0<x<1, 0<y<1), for example, and includes aluminum gallium nitride (AlGaN) or indium aluminum gallium nitride (InAlGaN). The "AlGaN-based _{semiconductor} material" in this specification is, for example, a material in which the molar fraction of each of AlN and GaN is 1% or more, preferably 5% or more, 10% or more, or 20% or more.

In addition, in order to distinguish materials that do not contain AlN, it is called "GaN-based semiconductor materials". "GaN-based semiconductor materials" include GaN or InGaN. Similarly, in order to distinguish materials that do not contain GaN, it is called "AlN-based semiconductor materials". "AlN-based semiconductor materials" include AlN or InAlN.

The semiconductor light emitting device 10 includes a bare chip (die) 12 , a mounting substrate 14 , metal bonding materials 16 n and 16 p , and a cover layer (also called a third cover layer) 18 . The bare crystal 12 has a substrate 20, a buffer layer 22, an n-type cladding layer 24, an active layer 26, an electron block layer 28, a p-type cladding layer 30, a protective insulating layer 32, a first capping layer 34, an n-side contact electrode 36, an n-side protective metal layer 38, a p-side contact electrode 40, a p-side protective metal layer 42, a second capping layer 44, an n-side pad electrode 46, and a p-side pad electrode 48.

In FIG. 1 , the direction from the substrate 20 toward the mounting substrate 14 is also referred to as the "upper side". This is because in the manufacturing steps of FIG. 2 to FIG. 12 described later, after laminating each layer on the substrate 20, the direction of the bare die 12 is reversed upside down and mounted on the mounting substrate 14.

The substrate 20 is a substrate that is transparent to the deep ultraviolet light emitted by the semiconductor light-emitting element 10, such as a sapphire (Al ₂ O ₃ ) substrate. The substrate 20 has a first main surface 20a and a second main surface 20b on the opposite side of the first main surface 20a. The first main surface 20a is a main surface that becomes a crystal growth surface, and the crystal growth surface is used to grow each layer above the buffer layer 22. An outer peripheral surface 20c with a height different from that of the first main surface 20a is provided on the periphery of the first main surface 20a. The second main surface 20b is a main surface that becomes a light extraction surface, and the light extraction surface is used to extract the deep ultraviolet light emitted by the active layer 26 to the outside. In a modified example, the substrate 20 can be an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate.

The buffer layer 22 is formed on the first main surface 20a of the substrate 20. The buffer layer 22 is a base layer (template layer) used to form the layers above the n-type cladding layer 24. The buffer layer 22 is, for example, an undoped AlN layer, specifically, an AlN (HT-AlN (High Temperature AlN; high temperature aluminum nitride)) layer grown at a high temperature. The buffer layer 22 may also include an undoped AlGaN layer formed on the AlN layer. In a modified example, when the substrate 20 is an AlN substrate or an AlGaN substrate, the buffer layer 22 may also be composed only of an undoped AlGaN layer. That is, the buffer layer 22 includes at least one of an undoped AlN layer and an undoped AlGaN layer.

The n-type cladding layer 24 is an n-type semiconductor layer and is formed on the buffer layer 22. The n-type cladding layer 24 is an n-type AlGaN-based semiconductor material layer, for example, an AlGaN layer doped with silicon (Si) as an n-type impurity. The n-type cladding layer 24 is formed by selecting a composition ratio in a manner to transmit deep ultraviolet light emitted through the active layer 26, for example, in a manner in which the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The n-type cladding layer 24 is formed in a manner to have an energy gap larger than the wavelength of the deep ultraviolet light emitted by the active layer 26, for example, in a manner in which the energy gap is 4.3 eV or more. Preferably, the n-type cladding layer 24 is formed in such a way that the molar fraction of AlN is less than 80%, that is, the energy gap is less than 5.5 eV, and more preferably, the molar fraction of AlN is less than 70% (that is, the energy gap is less than 5.2 eV). The n-type cladding layer 24 has a thickness of about 1 μm to 3 μm, for example, a thickness of about 2 μm.

The n-type cladding layer 24 is formed in such a manner that the concentration of silicon (Si) as an impurity becomes 1×10 ¹⁸ /cm ³ or more and 5×10 ¹⁹ /cm ³ or less. Preferably, the n-type cladding layer 24 is formed in such a manner that the Si concentration becomes 5×10 ¹⁸ /cm ³ or more and 3×10 ¹⁹ /cm ³ or less, and more preferably, it is formed in such a manner that the Si concentration becomes 7×10 ¹⁸ /cm ³ or more and 2×10 ¹⁹ /cm ³ or less. In one embodiment, the Si concentration of the n-type cladding layer 24 is about 1×10 ¹⁹ /cm ³ and is in the range of 8×10 ¹⁸ /cm ³ or more and 1.5×10 ¹⁹ /cm ³ or less.

The active layer 26 is made of AlGaN semiconductor material, and is sandwiched between the n-type cladding layer 24 and the electron blocking layer 28 to form a double heterojunction structure. The active layer 26 may also have a single-layer or multi-layer quantum well structure, for example, it may also be composed of a laminate of a barrier layer and a well layer, the barrier layer being formed of an undoped AlGaN semiconductor material, and the well layer being formed of an undoped AlGaN semiconductor material. The active layer 26 is constructed in such a way that the energy gap becomes 3.4 eV or more in order to output deep ultraviolet light with a wavelength below 355 nm, for example, the AlN composition ratio is selected in such a way that deep ultraviolet light with a wavelength below 310 nm can be output. The active layer 26 is disposed on the first upper surface 24a of the n-type cladding layer 24 but not on the second upper surface 24b adjacent to the first upper surface 24a. That is, the active layer 26 is not formed on the entire surface of the n-type cladding layer 24 but is formed only on a portion of the n-type cladding layer 24.

The electron blocking layer 28 is formed on the active layer 26. The electron blocking layer 28 is an undoped AlGaN-based semiconductor material layer, for example, formed in a manner in which the molar fraction of AlN is 40% or more, preferably 50% or more. The electron blocking layer 28 can also be formed in a manner in which the molar fraction of AlN is 80% or more, or can also be formed by an AlN-based semiconductor material that does not contain GaN. The electron blocking layer has a thickness of about 1nm to 10nm, for example, a thickness of about 2nm to 5nm. The electron blocking layer 28 can also be a p-type AlGaN-based semiconductor material layer.

The p-type cladding layer 30 is a p-type semiconductor layer and is formed on the electron blocking layer 28. The p-type cladding layer 30 is a p-type AlGaN-based semiconductor material layer, for example, an AlGaN layer doped with magnesium (Mg) as a p-type impurity. The p-type cladding layer 30 has a thickness of about 300nm to 700nm, for example, a thickness of about 400nm to 600nm. The p-type cladding layer 30 can also be formed of a p-type GaN-based semiconductor material that does not contain AlN.

The protective insulating layer 32 is provided on the p-type cladding layer 30. The protective insulating layer 32 is made of silicon oxide (SiO ₂ ) or silicon oxynitride (SiON). The protective insulating layer 32 is made of a material having a lower refractive index for deep ultraviolet light output from the active layer 26 than the p-type cladding layer 30. The refractive index of the AlGaN-based semiconductor material constituting the p-type cladding layer 30 is about 2.1 to 2.56 depending on the composition ratio. On the other hand, the refractive index of SiO ₂ constituting the protective insulating layer 32 is about 1.4, and the refractive index of SiON is about 1.4 to 2.1. By providing the protective insulating layer 32 with a low refractive index, more ultraviolet light from the active layer 26 can be totally reflected at the interface between the p-type cladding layer 30 and the protective insulating layer 32 and directed toward the second main surface 20b of the substrate 20, which is the light extraction surface. In particular, since there is a large difference in refractive index between silicon oxide (SiO ₂ ) and the p-type cladding layer 30, the reflection characteristics can be further improved. The thickness of the protective insulating layer 32 is 50 nm or more, and can be, for example, 100 nm or more and 500 nm or less.

The first cover layer 34 is provided to cover the protective insulating layer 32, the second upper surface 24b of the n-type cover layer 24, the side surface of the n-type cover layer 24, the side surface of the active layer 26, and the side surface of the electron blocking layer 28. The first cover layer 34 may also cover the side surface of the buffer layer 22 and the outer peripheral surface 20c of the substrate 20 in the manner shown in the figure. The first cover layer 34 is made of aluminum oxide (Al ₂ O ₃ ). The aluminum oxide (Al ₂ O ₃ ) constituting the first cover layer 34 is more resistant to moisture than silicon oxide (SiO ₂ ). Therefore, the first cover layer 34 covers _the entire upper surface and side surface of the semiconductor layer, thereby providing a protective function with excellent moisture resistance. In addition, since the aluminum oxide ( _Al2O3 ) constituting the first cover layer 34 has a low absorption rate for deep ultraviolet light output from the active layer 26, the reduction in light output due to the provision of the first cover layer 34 can also be suppressed. The thickness of the first cover layer 34 can be set to be greater than 10nm and less than 50nm, for example, can be set to about 10nm to 30nm.

The Al ₂ O ₃ film constituting the first capping layer 34 preferably has a dense structure with a high film density, and is preferably formed using, for example, an atomic layer deposition (ALD) method. In addition, the first capping layer 34 preferably has a low hydrogen concentration. If the first capping layer 34 contains a high concentration of hydrogen (H), hydrogen diffuses into the active layer 26 and the p-type cladding layer 30 and causes degradation of these semiconductor layers. In order to use Al ₂ O ₃ with a low hydrogen concentration, it is preferred to use oxygen (O ₂ ) plasma or ozone (O ₃ ) as a supply source of oxygen atoms instead of water (H ₂ O). That is, it is preferred that the first cover layer 34 is formed by an ALD method using an organic aluminum compound such as trimethyl aluminum (TMA), O ₂ plasma or O ₃ as raw materials.

The n-side contact electrode 36 is disposed on the second upper surface 24b of the n-type cladding layer 24, and contacts the n-type cladding layer 24 through an opening that penetrates the first cladding layer 34 on the second upper surface 24b of the n-type cladding layer 24. The n-side contact electrode 36 includes, for example, a Ti layer that contacts the n-type cladding layer 24 and an Al layer that contacts the Ti layer. The thickness of the Ti layer is about 1 nm to 10 nm, preferably less than 5 nm, and more preferably less than 2 nm. By reducing the thickness of the Ti layer, the ultraviolet light reflectivity of the n-side contact electrode 36 when viewed from the n-type cladding layer 24 can be improved. The thickness of the Al layer is about 100nm to 1000nm, preferably more than 200nm, and more preferably more than 300nm. By increasing the thickness of the Al layer, the ultraviolet light reflectivity of the n-side contact electrode 36 can be improved. In addition, it is preferred that the n-side contact electrode 36 does not contain gold (Au) which may be a factor in reducing the ultraviolet light reflectivity.

The p-side contact electrode 40 is disposed on the p-type cladding layer 30 and contacts the p-type cladding layer 30 through the openings penetrating the protective insulating layer 32 and the first cladding layer 34 on the p-type cladding layer 30. The p-side contact electrode 40 is made of a transparent conductive oxide (TCO) such as tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (ITO), etc. The thickness of the p-side contact electrode 40 is about 20 nm to 500 nm, preferably 50 nm or more, and more preferably 100 nm or more.

The n-side protective metal layer 38 is disposed on the n-side contact electrode 36, and the p-side protective metal layer 42 is disposed on the p-side contact electrode 40. The n-side protective metal layer 38 and the p-side protective metal layer 42 (also collectively referred to as protective metal layers 38 and 42) are formed of a metal material having high adhesion to the second cover layer 44, and are composed of a single metal film or a metal laminate film. In order for the protective metal layers 38 and 42 to function as a stop layer in the dry etching step for forming an opening penetrating the second cover layer 44, it is preferably composed of a metal material having high resistance to etching gas. As the material of the protective metal layers 38 and 42, for example, platinum group metals can be used, and palladium (Pd) can be used. The thickness of the protective metal layers 38 and 42 is preferably greater than 50nm, and more preferably greater than 100nm.

The second capping layer 44 is provided to cover the first capping layer 34, the n-side contact electrode 36, the n-side protective metal layer 38, the p-side contact electrode 40, and the p-side protective metal layer 42. The second capping layer 44 is made of insulating oxide, nitride, or oxynitride, such as silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum nitride (AlN), silicon oxynitride (SiON), or aluminum oxynitride (AlON). The thickness of the second capping layer 44 is greater than 50 nm, preferably greater than 100 nm. The thickness of the second capping layer 44 may also be about 500 nm to 1000 nm. By increasing the thickness of the second cover layer 44 , the n-side contact electrode 36 , the p-side contact electrode 40 , and the protective metal layers 38 and 42 , which are thicker than the semiconductor layer, can be properly covered.

The n-side pad electrode 46 and the p-side pad electrode 48 (also collectively referred to as pad electrodes 46, 48) are the bonding parts when the bare die 12 is mounted on the mounting substrate 14. The n-side pad electrode 46 is disposed on the n-side protection metal layer 38 and contacts the n-side protection metal layer 38 through the opening penetrating the second cover layer 44. The n-side pad electrode 46 is electrically connected to the n-side contact electrode 36 through the n-side protection metal layer 38. The p-side pad electrode 48 is disposed on the p-side protective metal layer 42 and contacts the p-side protective metal layer 42 through an opening that penetrates the second cover layer 44. The p-side pad electrode 48 is electrically connected to the p-side contact electrode 40 through the p-side protective metal layer 42.

The pad electrodes 46 and 48 are formed in a manner including gold (Au) from the viewpoint of corrosion resistance, and are formed in a multilayer structure of, for example, nickel (Ni)/Au, titanium (Ti)/Au, or Ti/platinum (Pt)/Au. When the pad electrodes 46 and 48 are bonded with gold tin (AuSn), the pad electrodes 46 and 48 may also contain an AuSn layer as a metal bonding material.

The bare crystal 12 is mounted on the mounting substrate 14. The mounting substrate 14 has a base 50, an n-side mounting electrode 52n, a p-side mounting electrode 52p, an n-side external terminal 54n, and a p-side external terminal 54p. The base 50 is a plate-shaped member made of a ceramic material such as aluminum nitride (AlN). The n-side mounting electrode 52n and the p-side mounting electrode 52p are provided on the first main surface 50a of the base 50. The n-side mounting electrode 52n and the p-side mounting electrode 52p are metal electrodes bonded to the pad electrodes 46 and 48 of the bare crystal 12, and are formed in a manner including gold (Au) from the viewpoint of corrosion resistance. The n-side external terminal 54n and the p-side external terminal 54p are metal terminals used to solder the semiconductor light-emitting element 10 to a printed circuit board, etc., and are disposed on the second main surface 50b opposite to the first main surface 50a of the base 50. Inside the base 50, the n-side mounting electrode 52n is electrically connected to the n-side external terminal 54n, and the p-side mounting electrode 52p is electrically connected to the p-side external terminal 54p.

The metal bonding materials 16n and 16p bond the bare die 12 to the mounting substrate 14. The metal bonding materials 16n and 16p are made of solder materials of the AuSn or SnZn series. The n-side metal bonding material 16n bonds the n-side pad electrode 46 to the n-side mounting electrode 52n, and the p-side metal bonding material 16p bonds the p-side pad electrode 48 to the p-side mounting electrode 52p.

The third cover layer 18 is provided to cover the entire surface of the bare die 12, a portion of the surface of the mounting substrate 14, and the metal bonding materials 16n and 16p. The third cover layer 18 covers the second main surface 20b and the side surface 20d of the substrate 20, the surface of the second cover layer 44, the side surface of the n-side pad electrode 46, and the side surface of the p-side pad electrode 48. In addition, the third cover layer 18 covers the first main surface 50a and the side surface 50c of the mounting substrate 14, the surface of the n-side mounting electrode 52n, and the surface of the p-side mounting electrode 52p.

The third capping layer 18 is made of aluminum oxide (Al ₂ O ₃ ) and is preferably formed by atomic layer deposition (ALD) in a manner to form a dense structure with a high film density, similar to the first capping layer 34 described above. On the other hand, since the third capping layer 18 is not in direct contact with the semiconductor layer such as the active layer 26 of the bare wafer 12, it is not necessary to have a low hydrogen concentration. In other words, the hydrogen concentration of the third capping layer 18 may be higher than that of the first capping layer 34. Thus, water ( _H2O ) can be used as a supply source of oxygen atoms of _Al2O3 constituting the third capping layer 18, or the _third capping layer ₁₈ can be formed by an ALD method using an organic aluminum compound such as TMA and _H2O as raw materials. By using _H2O as a raw material, it is easier to spread the raw material to a narrow gap than when using _O2 plasma or _O3 , and dense _Al2O3 can be properly formed even in a narrow gap between the bare die 12 and the mounting substrate 14. The thickness of the third capping layer 18 can be set to be greater than 10nm and less than 50nm, for example, about 10nm to 30nm.

Next, the manufacturing method of the semiconductor light-emitting element 10 is described. Figures 2 to 13 schematically show the manufacturing steps of the semiconductor light-emitting element 10. First, as shown in Figure 2, a buffer layer 22, an n-type cladding layer 24, an active layer 26, an electron blocking layer 28, a p-type cladding layer 30, and a protective insulating layer 32 are sequentially formed on the first main surface 20a of the substrate 20.

The substrate 20 is a sapphire (Al ₂ O ₃ ) substrate, and a buffer layer 22 is formed on the (0001) plane of the sapphire substrate, for example. The buffer layer 22 includes, for example, a high temperature grown AlN (HT-AlN) layer and an undoped AlGaN (u-AlGaN) layer. The n-type cladding layer 24, the active layer 26, the electron blocking layer 28, and the p-type cladding layer 30 are layers formed of AlGaN-based semiconductor materials, AlN-based semiconductor materials, or GaN-based semiconductor materials, and can be formed using a known epitaxial growth method such as metal organic chemical vapor deposition (MOVPE) or molecular beam epitaxy (MBE). The protective insulating layer 32 is made of SiO ₂ or SiON and can be formed using a known technique such as chemical vapor deposition (CVD).

Then, as shown in FIG. 3 , a first mask 61 is formed on the protective insulating layer 32, and the protective insulating layer 32, the p-type cladding layer 30, the electron blocking layer 28, the active layer 26, and a portion of the n-type cladding layer 24 in the first region W1 where the first mask 61 is not formed are removed. Thus, the second upper surface 24b (exposed surface) of the n-type cladding layer 24 is formed in the first region (also referred to as the exposed region) W1. In the step of forming the exposed surface of the n-type cladding layer 24, each layer can be removed by dry etching 71. For example, reactive ion etching caused by plasmatization of the etching gas can be used, or etching such as inductively coupled plasma (ICP; Inductive Coupled Plasma) can be used. Afterwards, the first mask 61 is removed.

Then, as shown in FIG. 4 , a second mask 62 is formed on the protective insulating layer 32 and the second upper surface 24b of the n-type cladding layer 24. Thereafter, the protective insulating layer 32, the p-type cladding layer 30, the electron blocking layer 28, the active layer 26, and the n-type cladding layer 24 in the second region W2 (also referred to as the peripheral region) where the second mask 62 is not formed are removed by dry etching 72. The second region W2 is a separation region between elements in the case where a plurality of light-emitting elements (bare crystal) are formed on a substrate. In the second region W2, the buffer layer 22 may be partially removed, or the buffer layer 22 may be completely removed to expose the substrate 20. In the second area W2, a portion of the substrate 20 may be removed to expose the outer peripheral surface 20c of the substrate 20 having a height different from that of the first main surface 20a. Afterwards, the second mask 62 is removed.

Then, as shown in FIG5 , a first cover layer 34 is formed to cover the entire upper surface of the device structure. The first cover layer 34 is made of Al ₂ O ₃ , and is formed, for example, by an ALD method using TMA and O ₂ plasma or O ₃ as raw materials. The first cover layer 34 is formed to cover the protective insulating layer 32, the second upper surface 24b of the n-type cladding layer 24, the n-type cladding layer 24, the active layer 26, the electron blocking layer 28, and the side surface of the p-type cladding layer 30. The protective insulating layer 32 may also cover the side surface of the buffer layer 22, or may also cover the outer peripheral surface 20c of the substrate 20 or at least a portion of the side surface.

Then, as shown in FIG. 6 , a third mask 63 is formed on the first cover layer 34. The third mask 63 is formed except for the n-side electrode region W3n on the second upper surface 24b of the n-type cover layer 24 and the p-side electrode region W3p on the p-type cover layer 30. Next, the first cover layer 34 is removed by dry etching 73 in the n-side electrode region W3n and the p-side electrode region W3p. Thereby, a first opening 81 is formed in the n-side electrode region W3n to expose the n-type cover layer 24, and a second opening 82 is formed in the p-side electrode region W3p to expose the protective insulating layer 32. Thereafter, the third mask 63 is removed.

Then, as shown in FIG. 7 , an n-side contact electrode 36 is formed by stacking on the first cover layer 34 and the n-type cover layer 24 exposed in the first opening 81, and an n-side protective metal layer 38 is formed on the n-side contact electrode 36. The n-side contact electrode 36 is, for example, a multilayer structure of a Ti layer and an Al layer, and the n-side protective metal layer 38 is, for example, a Pd layer. The n-side contact electrode 36 and the n-side protective metal layer 38 can be formed by sputtering or electron beam (EB; electron beam) evaporation.

Then, as shown in FIG. 8 , a fourth mask 64 is formed in the fourth region W4 except for the second opening 82. Next, the protective insulating layer 32 is removed by wet etching in the fourth region to form a third opening 83 that exposes the p-type cladding layer 30. The protective insulating layer 32 can be removed using, for example, buffered hydrofluoric acid (BHF) which is a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH ₄ F). By wet etching the protective insulating layer 32, the damage to the p-type cladding layer 30 exposed in the third opening 83 can be reduced compared to the case where the protective insulating layer 32 is dry etched. Thereafter, the fourth mask 64 is removed.

Then, as shown in FIG. 9 , a p-side contact electrode 40 is formed by stacking on the first cover layer 34 and the p-type cladding layer 30 exposed in the third opening 83, and a p-side protective metal layer 42 is formed on the p-side contact electrode 40. The p-side contact electrode 40 is, for example, an ITO layer, and the p-side protective metal layer 42 is, for example, a Pd layer. The p-side contact electrode 40 and the p-side protective metal layer 42 can be formed by sputtering or electron beam (EB) evaporation.

Then, as shown in Fig. 10, a second cover layer 44 is formed to cover the entire upper surface of the device structure. The second cover layer 44 is formed to cover the first cover layer 34 and to cover the n-side contact electrode 36, the n-side protective metal layer 38, the p-side contact electrode 40, and the p-side protective metal layer 42. The second cover layer 44 is, for example, a _SiO2 layer and is formed using a known technique such as a chemical vapor deposition (CVD) method.

Then, as shown in FIG. 11 , a fifth mask 65 is formed on the second cover layer 44. The fifth mask 65 is formed except for the n-side electrode region W5n corresponding to the n-side contact electrode 36 and the p-side electrode region W5p corresponding to the p-side contact electrode 40. Next, the second cover layer 44 is removed in the n-side electrode region W5n and the p-side electrode region W5p by dry etching 75. The second cover layer 44 can be dry-etched using a CF-based etching gas, such as hexafluoroethane (C ₂ F ₆ ). In the dry etching step, the n-side protection metal layer 38 and the p-side protection metal layer 42 function as an etching stop layer to prevent damage to the n-side contact electrode 36 and the p-side contact electrode 40 under the n-side protection metal layer 38 and the p-side protection metal layer 42. Thus, a fourth opening 84 exposing the n-side protection metal layer 38 in the n-side electrode region W5n and a fifth opening 85 exposing the p-side protection metal layer 42 in the p-side electrode region W5p are formed. Thereafter, the fifth mask 65 is removed.

Then, as shown in FIG. 12 , an n-side pad electrode 46 is formed on the n-side protective metal layer 38 exposed by the fourth opening 84, and a p-side pad electrode 48 is formed on the p-side protective metal layer 42 exposed by the fifth opening 85. The pad electrodes 46 and 48 can be formed by, for example, stacking a Ni layer or a Ti layer and stacking an Au layer on the Ni layer or the Ti layer. Other metal layers can also be further provided on the Au layer, for example, a Sn layer, an AuSn layer, or a Sn/Au stacking structure can also be formed. The bare crystal 12 of FIG. 1 is completed by the above steps.

Then, as shown in FIG. 13 , the bare crystal 12 is mounted on the mounting substrate 14. First, the bare crystal 12 is arranged so that the n-side pad electrode 46 is located on the n-side mounting electrode 52n and the p-side pad electrode 48 is located on the p-side mounting electrode 52p. Next, the metal bonding material 16n, 16p such as gold tin (AuSn) or solder is melted, and the pad electrodes 46, 48 are bonded to the n-side mounting electrode 52n and the p-side mounting electrode 52p.

Thereafter, the third cover layer 18 is formed to cover the entire surface of the die 12 mounted on the mounting substrate 14. The third cover layer 18 is made of Al ₂ O ₃ and is formed by, for example, ALD using TMA and H ₂ O as raw materials. Thus, the semiconductor light emitting device 10 shown in FIG. 1 is completed.

According to the present embodiment, the first capping layer 34 directly in contact with the semiconductor layers such as the n-type cladding layer 24, the active layer 26, and the electron blocking layer 28 is formed as an Al ₂ O ₃ layer by the ALD method, thereby improving the moisture resistance of these semiconductor layers. In addition, water (H ₂ O) is not used as a raw material for the first capping layer 34, thereby reducing the hydrogen concentration contained in the first capping layer 34. That is, the hydrogen concentration of the first capping layer 34 can be made lower than that of the third capping layer 18. In this way, the degradation of the semiconductor layer due to the diffusion of hydrogen contained in the first capping layer 34 into the semiconductor layer can be appropriately prevented.

According to the present embodiment, the protection function of the bare die 12 can be improved by further providing the second covering layer 44 on the first covering layer 34. Since the first covering layer ₃₄ composed of _Al2O3 is formed by the ALD method, it is difficult to increase the film thickness, and a thickness of about 50nm becomes the upper limit in practical use. On the other hand, since the film thickness of the n-side contact electrode 36 and the p-side contact electrode 40 is greater than 50nm, preferably greater than 100nm, there is a risk that the covering performance of the contact electrode will be reduced if there is only the first covering layer 34. On the other hand, since the second covering layer 44 formed by the CVD method or the like can be easily set to a film thickness of more than 100nm, it can appropriately cover the contact electrode with a large film thickness. According to this embodiment, a first cover layer 34 which is dense but thin in thickness is combined with a second cover layer 44 which is thick in thickness, thereby improving the packaging performance of the bare die 12.

According to the present embodiment, after the bare die 12 is mounted on the mounting substrate 14, the entire die is further covered with the third cover layer 18, so that the packaging of the semiconductor light-emitting element 10 can be improved. In particular, by covering the surfaces of metal materials such as the pad electrodes 46, 48, the n-side mounting electrode 52n, the p-side mounting electrode 52p, and the metal bonding materials 16n, _16p , corrosion of the metal materials can be appropriately prevented. In addition, by forming the third cover layer 18 with _Al2O3 , the adhesion with the metal material containing gold (Au) can be improved, and the reduction in reliability due to the peeling of the third cover layer 18 can be suppressed.

According to the present embodiment, the third cover layer 18 is formed by the ALD method using water (H ₂ O) as a raw material, thereby forming the third cover layer 18 in a manner that covers the entirety of the die 12 and the mounting substrate 14 even when the die 12 and the mounting substrate 14 are bonded. Assuming that O ₂ plasma or O ₃ is used as a raw material as in the first cover layer 34, activated oxygen is deactivated before reaching the gap between the die 12 and the mounting substrate 14, and the Al ₂ O ₃ layer may not be properly formed. On the other hand, when H ₂ O is used as a raw material, since it is not necessary to set it to a plasma state, the raw material can be fully spread throughout the gap between the die 12 and the mounting substrate 14, and the Al ₂ O ₃ layer can be formed more appropriately. Thereby, the reliability of the third cover layer 18 can be improved.

According to this embodiment, by providing a protective insulating layer 32 between the p-type cladding layer 30 and the first cladding layer 34, the damage to the p-type cladding layer 30 during the etching step for exposing the p-type cladding layer 30 can be reduced. In this way, the contact resistance of the p-side contact electrode 40 can be improved, and the output characteristics of the semiconductor light-emitting element 10 can be enhanced.

FIG. 14 is a cross-sectional view schematically showing the structure of a semiconductor light-emitting element 110 of another embodiment. In this embodiment, the second covering layer 144 is a two-layer structure of a first layer 144a and a second layer 144b, which is different from the above embodiment. Hereinafter, this embodiment will be described with the focus on the differences from the above embodiment.

The semiconductor light-emitting element 110 has a bare die 112, a mounting substrate 14, metal bonding materials 16n, 16p, and a third covering layer 18. The mounting substrate 14, metal bonding materials 16n, 16p, and the third covering layer 18 are constructed in the same manner as the above-mentioned embodiment.

The bare crystal 112 has a substrate 20, a buffer layer 22, an n-type cladding layer 24, an active layer 26, an electron blocking layer 28, a p-type cladding layer 30, a protective insulating layer 32, a first capping layer 34, an n-side contact electrode 36, an n-side protective metal layer 38, a p-side contact electrode 40, a p-side protective metal layer 42, a second capping layer 144, an n-side pad electrode 46, and a p-side pad electrode 48. The bare crystal 112 is constructed in the same manner as the bare crystal 12 of the above-mentioned embodiment except that the second capping layer 144 is a two-layer structure.

The second cover layer 144 includes a first layer 144a and a second layer 144b. The first layer 144a is provided in direct contact with the first cover layer 34, the n-side contact electrode 36, the n-side protective metal layer 38, the p-side contact electrode 40, and the p-side protective metal layer 42. The second layer 144b is provided in a manner covering the first layer 144a and is provided separately from the first cover layer 34, the n-side contact electrode 36, the n-side protective metal layer 38, the p-side contact electrode 40, and the p-side protective metal layer 42.

The first layer 144a is made of, for example, _SiO2 , and has a lower refractive index than the first cover layer 34 and the second layer 144b. The first layer 144a is formed in a manner that is thicker than the first cover layer 34 and the second layer 144b. The thickness of the first layer 144a is greater than 100nm, for example, about 500nm to 1000nm. The thickness of the first layer 144a is formed in a manner that is more than 10 times the thickness of the first cover layer 34. The thickness of the first layer 144a may also be greater than the thickness of the n-side contact electrode 36 and the p-side contact electrode 40. The thickness of the first layer 144 a may be greater than the sum of the thicknesses of the n-side contact electrode 36 and the n-side protective metal layer 38 , and may also be greater than the sum of the thicknesses of the p-side contact electrode 40 and the p-side protective metal layer 42 .

The second layer 144b is made of a different material from the first layer 144a, and is made of a nitride such as AlN or SiN. The second layer 144b is made of, for example, SiN, and has a higher refractive index than the protective insulating layer 32, the first cover layer 34, and the first layer 144a. For ultraviolet light with a wavelength of 280nm, the refractive index of _SiO2 is 1.49, the refractive index of _Al2O3 is 1.82, the refractive index of SiN is 2.18, _and the refractive index of AlN is 2.28. Thus, the refractive index (2.18 or 2.28) of the second layer 144b composed of SiN or AlN is greater than the refractive index (1.49) of the protective insulating layer 32 and the first layer 144a composed of _SiO2 , and greater than the refractive _index (1.82) of the first cover layer 34 composed of _Al2O3 . The thickness of the second layer 144b is smaller than the thickness of the first layer 144a, which is about 50nm to 200nm. The thickness of the second layer 144b is smaller than the thickness of the protective insulating layer 32. The thickness of the second layer 144b can also be greater than the thickness of the first cover layer 34 and the third cover layer 18.

According to this embodiment, a second layer 144b having a material different from that of the first layer 144a is deposited on the first layer 144a, thereby appropriately plugging the pinholes that may occur in the first layer 144a, thereby improving the packaging performance caused by the second covering layer 144.

According to the present embodiment, when the refractive index of the material of the protective insulating layer 32 is set to n1, the refractive index of the material of the first cover layer 34 is set to n2, the refractive index of the first layer 144a of the second cover layer 144 is set to n3, and the refractive index of the second layer 144b of the second cover layer 144 is set to n4, the relationship of n1<n2<n4 and the relationship of n3<n2<n4 are established. According to the present embodiment, the refractive index n3 of the first layer 144a is set to be smaller than the refractive index n2 of the first cover layer 34, so that the deep ultraviolet light generated in the active layer 26 can be totally reflected at the interface between the first cover layer 34 and the first layer 144a and directed toward the second main surface 20b which becomes the light extraction surface. This can improve the light extraction efficiency of the semiconductor light-emitting element 10. In addition, by covering the first layer 144a with the second layer 144b composed of a nitride with a higher refractive index than the material of the first layer 144a, the packaging and reliability of the second covering layer 144 can be improved.

Next, the manufacturing method of the semiconductor light-emitting element 110 is described. A part of the manufacturing steps of the semiconductor light-emitting element 110 is common with a part of the manufacturing steps of the semiconductor light-emitting element 10 described above, and the steps shown in Figures 2 to 9 are first performed. Figures 15 to 18 are diagrams schematically showing the manufacturing steps of the semiconductor light-emitting element 110, showing the steps after Figure 9.

As shown in FIG. 15 , the second cover layer 144 is formed to cover the entire upper surface of the device structure. The second cover layer 144 includes a first layer 144a and a second layer 144b. The first layer 144a is formed to cover the exposed surface of the first cover layer 34 and to cover the exposed surfaces of the n-side contact electrode 36, the n-side protective metal layer 38, the p-side contact electrode 40, and the p-side protective metal layer 42. The second layer 144b is formed to cover the exposed surface of the first layer 144a. The first layer 144a is, for example, a _SiO2 layer, and can be formed using a known technique such as a plasma CVD method. The second layer 144b is, for example, a SiN layer, and can be formed using a known technique such as a plasma CVD method.

Then, as shown in FIG. 16 , a sixth mask 66 is formed on the second capping layer 144. The sixth mask 66 is formed except for the n-side electrode region W6n corresponding to the n-side contact electrode 36 and the p-side electrode region W6p corresponding to the p-side contact electrode 40. Next, the second layer 144b of the second capping layer 144 in the n-side electrode region W6n and the p-side electrode region W6p is removed by dry etching 76. The second capping layer 144 can be dry-etched using a CF-based etching gas, such as hexafluoroethane (C ₂ F ₆ ). The dry etching step is performed until the second layer 144b is removed and the first layer 144a is exposed in the n-side electrode region W6n and the p-side electrode region W6p. Thus, the sixth opening 86 is formed in the n-side electrode region W6n to expose the first layer 144a, and the seventh opening 87 is formed in the p-side electrode region W6p to expose the p-side protective metal layer 42. In addition, as shown in FIG. 16 , in the dry etching step, the exposed portion of the first layer 144a can be further removed to a predetermined depth. That is, a step difference can also be formed on the upper surface of the first layer 144a. Thereafter, the sixth mask 66 is removed.

Then, as shown in FIG. 17 , a seventh mask 67 is formed on the second cover layer 144. The seventh mask 67 is formed except for the n-side electrode region W7n corresponding to the n-side contact electrode 36 and the p-side electrode region W7p corresponding to the p-side contact electrode 40. The seventh mask 67 is provided in a manner to completely cover the second layer 144b, and is provided in a manner to cover and protect the side walls of the second layer 144b in the sixth opening 86 and the seventh opening 87. In this way, the opening width of the n-side electrode region W7n of the seventh mask 67 is smaller than the opening width of the n-side electrode region W6n of the sixth mask 66. Similarly, the opening width of the p-side electrode region W7p of the seventh mask 67 is smaller than the opening width of the p-side electrode region W6p of the sixth mask 66. Next, the first layer 144a of the second cover layer 144 in the n-side electrode region W7n and the p-side electrode region W7p is removed by dry etching 77. The second cover layer 144 can be dry etched using a CF-based etching gas, such as hexafluoroethane (C ₂ F ₆ ). The dry etching step is performed until the first layer 144a in the n-side electrode region W7n and the p-side electrode region W7p is removed and the n-side protection metal layer 38 and the p-side protection metal layer 42 are exposed. In the dry etching step, the n-side protection metal layer 38 and the p-side protection metal layer 42 function as an etching stop layer to prevent damage to the n-side contact electrode 36 and the p-side contact electrode 40 under the n-side protection metal layer 38 and the p-side protection metal layer 42. Thereby, an eighth opening 88 for exposing the n-side protective metal layer 38 is formed in the n-side electrode region W7n, and a ninth opening 89 for exposing the p-side protective metal layer 42 is formed in the p-side electrode region W7p. Thereafter, the seventh mask 67 is removed.

Then, as shown in FIG. 18 , an n-side pad electrode 46 is formed on the n-side protective metal layer 38 exposed by the eighth opening 88, and a p-side pad electrode 48 is formed on the p-side protective metal layer 42 exposed by the ninth opening 89. The pad electrodes 46 and 48 can be formed by, for example, stacking a Ni layer or a Ti layer and stacking an Au layer on the Ni layer or the Ti layer. Other metal layers can also be further provided on the Au layer, for example, a Sn layer, an AuSn layer, or a Sn/Au stacking structure can also be formed. The above steps complete the bare crystal 112 shown in FIG. 14 .

Next, similarly to FIG13 , the bare die 112 is mounted on the mounting substrate 14, and a third covering layer 18 is formed to cover the entire surface of the bare die 112 mounted on the mounting substrate 14. The third covering layer 18 is made of Al ₂ O ₃ and is formed by, for example, an ALD method using TMA and H ₂ O as raw materials. Thus, the semiconductor light emitting device 110 shown in FIG14 is completed.

The present invention is described above based on the embodiments. The present invention is not limited to the above embodiments, and may have various design changes and various variations, and those with ordinary knowledge in the technical field to which the present invention belongs can understand that such variations also fall within the scope of the present invention.

In the above-mentioned embodiment, when the Al ₂ O ₃ layer is formed by the ALD method, the first step of introducing TMA and the second step of introducing O ₂ plasma, O ₃ or H ₂ O are repeated alternately. At this time, the first step may be performed initially, so that the surface to be covered with the Al ₂ O ₃ layer is initially covered with TMA. That is, it is also possible to adopt a method that does not cause damage to the surface to be covered with the Al ₂ O ₃ layer due to oxidation or etching by O ₂ plasma, etc. caused by the initial execution of the second step. In particular, when the first covering layer 34 covering the side surface of the active layer 26 is formed, TMA is introduced initially, thereby preventing damage to the side surface of the active layer 26. Thereby, the reliability of the semiconductor light emitting elements 10 and 110 can be improved.

In the above-mentioned embodiment, an n-side protective layer made of conductive titanium nitride (TiN) may be used instead of the n-side protective metal layer 38. Similarly, a p-side protective layer made of titanium nitride (TiN) may be used instead of the p-side protective metal layer 42. Even in the case of using the n-side protective layer and the p-side protective layer made of TiN, the TiN layer can still function as a stop layer in the dry etching step. In addition, by using TiN, the adhesion to the second cover layer 44 or the second cover layer 144 can be improved, and the second cover layer 44 or the second cover layer 144 can be appropriately prevented from being peeled off from the n-side contact electrode 36 and the p-side contact electrode 40.

In the above-mentioned embodiment, semiconductor light-emitting elements 10 and 110 are shown in which bare die 12 and 112 are mounted on the mounting substrate 14. In other embodiments, bare die 12 and 112 that are not mounted on the mounting substrate 14 can also be used as semiconductor light-emitting elements. In this case, a third covering layer 18 can be provided on the surface of the bare die 12 and 112, or the third covering layer 18 can be omitted.

10: Semiconductor light-emitting element

12: Bare crystal

14: Install the baseboard

16n,16p:Metal bonding material

18: Covering layer (third covering layer)

20: Substrate

20a: first main surface

20b: Second main surface

20c: Outer surface

20d: Side

22: Buffer layer

24: n-type coating layer

24a: first upper surface

24b: Second upper surface

26: Active layer

28:Electron blocking layer

30: p-type coating layer

32: Protect the insulating layer

34: First covering layer

36: n-side contact electrode

38: n-side protective metal layer (protective metal layer)

40: p-side contact electrode

42: p-side protective metal layer (protective metal layer)

44: Second covering layer

46: n-side pad electrode (pad electrode)

48: p side pad electrode (pad electrode)

50: Base

50a: first main surface

50b: Second main surface

50c: Side

52n:n side mounted electrode

52p:p side mounted electrode

54n: n-side external terminal

54p:p side external terminal

Claims (12)

A semiconductor light emitting element comprises: an n-type semiconductor layer, which is an n-type aluminum gallium nitride semiconductor material and is disposed on a substrate; an active layer, which is an aluminum gallium nitride semiconductor material and is disposed in a first region on the n-type semiconductor layer; a p-type semiconductor layer, which is a p-type aluminum gallium nitride semiconductor material and is disposed on the active layer; a first covering layer, which is composed of aluminum oxide and has a film thickness of not less than 10 nm and not more than 50 nm and is disposed in a manner of covering a second region different from the first region on the n-type semiconductor layer, a side surface of the active layer, and the p-type semiconductor layer; an n-side contact electrode, which passes through the first covering layer and contacts the n-type semiconductor layer, and is stacked on the first covering layer; a cover layer; a p-side contact electrode that penetrates the first cover layer and contacts the p-type semiconductor layer and is stacked on the first cover layer; a second cover layer that has a film thickness of more than 100 nm and is provided in a manner covering the first cover layer, the n-side contact electrode and the p-side contact electrode; an n-side pad electrode that penetrates the first cover layer and contacts the p-type semiconductor layer and is stacked on the first cover layer; The second covering layer is connected to the aforementioned n-side contact electrode; and the p-side pad electrode passes through the aforementioned second covering layer and is connected to the aforementioned p-side contact electrode; the aforementioned second covering layer includes: a silicon oxide layer having a thickness more than 10 times that of the aforementioned first covering layer; the aforementioned second covering layer further includes a nitride layer covering the aforementioned silicon oxide layer. A semiconductor light emitting element comprises: an n-type semiconductor layer, which is an n-type aluminum-gallium nitride semiconductor material and is disposed on a substrate; an active layer, which is an aluminum-gallium nitride semiconductor material and is disposed in a first region on the n-type semiconductor layer; a p-type semiconductor layer, which is a p-type aluminum-gallium nitride semiconductor material and is disposed on the active layer; a first covering The cap layer is made of aluminum oxide and is arranged to cover a second region different from the first region on the n-type semiconductor layer, a side of the active layer, and the p-type semiconductor layer; the n-side contact electrode penetrates the first cap layer and contacts the n-type semiconductor layer, and is stacked on the first cap layer; the p-side contact electrode The electrode is passed through the first cover layer and contacts the p-type semiconductor layer and is stacked on the first cover layer; the second cover layer is provided in a manner of covering the first cover layer, the n-side contact electrode and the p-side contact electrode; the n-side pad electrode is passed through the second cover layer and connected to the n-side contact electrode; and a p-side pad electrode, which passes through the aforementioned second covering layer and is connected to the aforementioned p-side contact electrode; the aforementioned second covering layer comprises: a first layer, which is composed of a material with a lower refractive index than the material of the aforementioned first covering layer; and a second layer, which is composed of a material with a higher refractive index than the material of the aforementioned first covering layer and covers the aforementioned first layer. The semiconductor light-emitting element as described in claim 1 or 2 further comprises: a third covering layer, which is composed of aluminum oxide and is arranged to cover at least a portion of the surface of the substrate, the second covering layer, the side surface of the n-side pad electrode, and the side surface of the p-side pad electrode. The semiconductor light-emitting element as described in claim 3 further comprises: a mounting substrate including an n-side mounting electrode connected to the aforementioned n-side pad electrode and a p-side mounting electrode connected to the aforementioned p-side pad electrode; the aforementioned third covering layer is further provided in a manner covering at least a portion of the surface of the aforementioned mounting substrate. The semiconductor light-emitting element as described in claim 3, wherein the concentration of hydrogen contained in the first coating layer is lower than the concentration of hydrogen contained in the third coating layer. The semiconductor light-emitting element as described in claim 1 or 2 further comprises: a protective insulating layer composed of silicon oxide or silicon oxynitride and disposed between the aforementioned p-type semiconductor layer and the aforementioned first cover layer. The semiconductor light-emitting element as described in claim 2, wherein the second covering layer comprises: a silicon oxide layer having a thickness that is more than 10 times the thickness of the first covering layer. The semiconductor light-emitting element as described in claim 7, wherein the second covering layer further comprises a nitride layer covering the silicon oxide layer. A semiconductor light-emitting element as described in claim 1 or 2, wherein the molar fraction of the n-type semiconductor layer is aluminum nitride is greater than 20%; and the active layer is configured to emit ultraviolet light with a wavelength of less than 350nm. A method for manufacturing a semiconductor light-emitting element comprises the steps of: sequentially stacking the following layers on a substrate: an n-type semiconductor layer, which is an n-type aluminum-gallium nitride semiconductor material; an active layer, which is an aluminum-gallium nitride semiconductor material on the n-type semiconductor layer; and a p-type semiconductor layer, which is a p-type aluminum-gallium nitride semiconductor material on the active layer; and exposing a portion of the n-type semiconductor layer. The steps of removing a portion of the p-type semiconductor layer, a portion of the active layer, and a portion of the n-type semiconductor layer in a manner of forming a first covering layer composed of aluminum oxide and having a film thickness of not less than 10 nm and not more than 50 nm in a manner covering the exposed region of the n-type semiconductor layer, the side surface of the active layer, and the p-type semiconductor layer; and partially removing the first covering layer. The step of removing the first covering layer and forming an n-side contact electrode in contact with the n-type semiconductor layer; the step of partially removing the first covering layer and forming a p-side contact electrode in contact with the p-type semiconductor layer; the step of forming a second covering layer having a film thickness of 100 nm or more and covering the first covering layer, the n-side contact electrode and the p-side contact electrode; the step of partially removing the second covering layer and forming The step of forming an n-side pad electrode connected to the aforementioned n-side contact electrode; and the step of partially removing the aforementioned second covering layer and forming a p-side pad electrode connected to the aforementioned p-side contact electrode; the step of forming the aforementioned second covering layer includes: the step of forming a silicon oxide layer having a thickness of more than 10 times the thickness of the aforementioned first covering layer; and the step of forming a nitride layer covering the aforementioned silicon oxide layer. A method for manufacturing a semiconductor light-emitting element comprises the steps of: sequentially stacking the following layers on a substrate: an n-type semiconductor layer, which is an n-type aluminum-gallium nitride semiconductor material; an active layer, which is an aluminum-gallium nitride semiconductor material on the n-type semiconductor layer; and a p-type semiconductor layer, which is a p-type aluminum-gallium nitride semiconductor material on the active layer; exposing a portion of the n-type semiconductor layer; The steps of removing a portion of the p-type semiconductor layer, a portion of the active layer, and a portion of the n-type semiconductor layer in a manner of removing the p-type semiconductor layer, a portion of the active layer, and a portion of the n-type semiconductor layer; forming a first covering layer composed of aluminum oxide in a manner of covering the exposed region of the n-type semiconductor layer, the side of the active layer, and the p-type semiconductor layer; partially removing the first covering layer and forming a first covering layer in contact with the n-type semiconductor layer; The step of partially removing the aforementioned first covering layer and forming a p-side contact electrode contacting the aforementioned p-type semiconductor layer; the step of forming a second covering layer covering the aforementioned first covering layer, the aforementioned n-side contact electrode and the aforementioned p-side contact electrode; the step of partially removing the aforementioned second covering layer and forming an n-side pad electrode connected to the aforementioned n-side contact electrode; and the step of removing the aforementioned first covering layer and forming a p-side pad electrode connected to the aforementioned n-side contact electrode. The second covering layer is partially removed and a p-side pad electrode connected to the p-side contact electrode is formed; the step of forming the second covering layer includes: forming a first layer composed of a material with a lower refractive index than the material of the first covering layer; and forming a second layer composed of a material with a higher refractive index than the material of the first covering layer and covering the first layer. The method for manufacturing a semiconductor light-emitting element as described in claim 10 or 11 further comprises the step of forming a third covering layer composed of aluminum oxide in a manner covering the surface of the substrate, the second covering layer, the side of the n-side pad electrode, and at least a portion of the side of the p-side pad electrode; the first covering layer is formed by an atomic layer stacking method using an organic aluminum compound and oxygen plasma or ozone gas as raw materials; and the third covering layer is formed by an atomic layer stacking method using an organic aluminum compound and water as raw materials.

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