JP7049186B2 - Manufacturing method of semiconductor light emitting device and semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device and a method for manufacturing a semiconductor light emitting device.

The light emitting device for deep ultraviolet light has an aluminum gallium nitride (AlGaN) -based n-type clad layer, an active layer, and a p-type clad layer that are sequentially laminated on the substrate. An n-side electrode having a laminated structure of, for example, Ti / Al / Ti / Au is formed on the n-type clad layer. It is known that the contact contact resistance between the n-type clad layer and the n-side electrode increases as the AlN mole fraction of the n-type clad layer increases, making good ohmic contact difficult. In order to improve the output characteristics, it has been proposed to increase the contact area of the n-side electrode and form an Al / Ti / Au reflective electrode on the n-side electrode (see, for example, Patent Document 1).

Japanese Patent No. 5594530

According to the findings of the present inventors, it is known that the reflection characteristics of the n-side electrode deteriorate due to the energization of the light emitting element, which leads to a decrease in the output of the light emitting element. It is preferable that the deterioration of the n-side electrode due to the use of energization can be suppressed.

The present invention has been made in view of these problems, and one of its exemplary purposes is to improve the reliability and output characteristics of a semiconductor light emitting device.

The semiconductor light emitting element of one embodiment of the present invention includes an n-type semiconductor layer of an n-type aluminum nitride gallium nitride (AlGaN) -based semiconductor material, an n-side electrode provided in a partial region on the n-type semiconductor layer, and an n-type semiconductor layer. The active layer of the AlGaN-based semiconductor material provided in a region different from the above partial region, the p-type semiconductor layer of the p-type AlGaN-based semiconductor material provided on the active layer, and the p-side provided on the p-type semiconductor layer. It is equipped with an electrode. The n-side electrode includes an n-side contact layer including an aluminum (Al) layer, an n-side indium tin oxide (ITO) layer on the n-side contact layer, and an n-side palladium (Pd) layer on the n-side ITO layer. , The n-side pad electrode layer on the n-side Pd layer, and the like. The p-side electrode includes a p-side indium tin oxide (ITO) layer, a p-side palladium (Pd) layer on the p-side ITO layer, and a p-side pad electrode layer on the p-side Pd layer.

According to this aspect, since the ITO layer is inserted between the Al layer functioning as a reflective electrode and the pad electrode layer, the ITO layer prevents the metal component contained in the pad electrode layer from diffusing into the Al layer by the use of electricity. Can be prevented. As a result, deterioration of the reflection characteristics of the Al layer can be suppressed. Further, by inserting the Pd layer between the ITO layer and the pad electrode layer, the adhesion between the ITO layer and the pad electrode layer can be enhanced, and peeling of the pad electrode layer from the ITO layer can be suitably prevented. This makes it possible to provide a light emitting element having improved reliability and output characteristics.

The p-side ITO layer is provided on the p-type first indium tin oxide (ITO) layer in contact with the p-type semiconductor layer, and on the p-type first ITO layer and the p-type so as to cover the p-type first ITO layer. It may have a p-type second indium tin oxide (ITO) layer provided in contact with both on the semiconductor layer.

The n-side ITO layer may be provided in contact with both the n-type contact layer and the n-side semiconductor layer so as to cover the n-type contact layer.

The n-side ITO layer may be provided in contact with the Al layer of the n-type contact layer.

The n-type contact layer does not have to contain gold (Au).

Another aspect of the present invention is a method for manufacturing a semiconductor light emitting device. In this method, an n-type semiconductor layer of an n-type aluminum nitride gallium nitride (AlGaN) -based semiconductor material, an active layer of an AlGaN-based semiconductor material on an n-type semiconductor layer, and a p-type semiconductor layer of a p-type AlGaN-based semiconductor material on an active layer are used. A step of laminating in order, a step of removing a part of the p-type semiconductor layer, the active layer and the n-type semiconductor layer so that a part of the n-type semiconductor layer is exposed, and a step of aluminum on the exposed region of the n-type semiconductor layer. The step of forming the n-type contact layer including the (Al) layer and the mask in which the n-side opening is provided on the n-type contact layer and the p-side opening is provided on the p-type semiconductor layer are exposed in the exposed region of the n-type semiconductor layer. A step of forming on the upper and p-type semiconductor layers, a step of forming an indium oxide (ITO) layer in the n-side opening and the p-side opening of the mask, and a step in the n-side opening and the p-side opening of the mask. It includes a step of forming a palladium (Pd) layer on the ITO layer and a step of forming a pad electrode layer on the Pd layer.

According to this aspect, since the ITO layer is inserted between the Al layer functioning as a reflective electrode and the pad electrode layer, the ITO layer prevents the metal component contained in the pad electrode layer from diffusing into the Al layer by the use of electricity. Can be prevented. As a result, deterioration of the reflection characteristics of the Al layer can be suppressed. Further, by inserting the Pd layer between the ITO layer and the pad electrode layer, the adhesion between the ITO layer and the pad electrode layer can be enhanced, and peeling of the pad electrode layer from the ITO layer can be suitably prevented. This makes it possible to provide a light emitting element having improved reliability and output characteristics.

The step of forming the ITO layer may include a step of forming the first ITO layer and a step of forming the second ITO layer under the condition of a higher film formation rate than the first ITO layer.

A step of forming the first ITO layer on the p-type semiconductor layer before forming the ITO layer may be further provided. The step of forming the ITO layer is a step of forming a second ITO layer on the n-type contact layer in the n-side opening of the mask and forming a second ITO layer on the first ITO layer in the p-side opening of the mask. There may be. The second ITO layer may be formed under conditions of a higher film formation rate than the first ITO layer.

The first ITO layer may be formed at a film formation rate of 2 nm / min or more and 5 nm / min or less.

After removing the mask, silicon oxide (SiO ₂ ), silicon oxynitride (SiON) or silicon nitride (SiN) is used on the exposed region of the n-type semiconductor layer and on the p-type semiconductor layer so as to cover the ITO layer and the Pd layer. A step of forming a constituent protective layer and a step of removing a part of the protective layer to expose the Pd layer may be further provided. The pad electrode layer may be formed on the Pd layer exposed by removing a part of the protective layer.

According to the present invention, the reliability and output characteristics of the semiconductor light emitting device can be improved.

It is sectional drawing which shows schematic the structure of the semiconductor light emitting element which concerns on embodiment. It is a graph which shows the relationship between the thickness of a Ti layer and the ultraviolet light reflectance. It is a graph which shows the relationship between the film formation rate of an ITO layer, and the contact resistance. It is a figure which shows roughly the manufacturing process of a semiconductor light emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light emitting device. It is a figure which shows roughly the manufacturing process of a semiconductor light emitting device. It is sectional drawing which shows schematic the structure of the semiconductor light emitting element which concerns on the modification. It is a figure which shows schematic manufacturing process of the semiconductor light emitting element which concerns on a modification.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the description, the same elements are designated by the same reference numerals, and duplicate description will be omitted as appropriate. Further, in order to help understanding the explanation, the dimensional ratio of each component in each drawing does not necessarily match the dimensional ratio of the actual light emitting element.

FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor light emitting device 10 according to the embodiment. The semiconductor light emitting device 10 is an LED (Light Emitting Diode) chip configured to emit "deep ultraviolet light" having a center wavelength λ of about 360 nm or less. In order to output deep ultraviolet light having such a wavelength, the semiconductor light emitting device 10 is made of an aluminum nitride gallium (AlGaN) -based semiconductor material having a band gap of about 3.4 eV or more. In this embodiment, a case where deep ultraviolet light having a center wavelength λ of about 240 nm to 350 nm is emitted is particularly shown.

As used herein, the term "AlGaN-based semiconductor material" refers to a semiconductor material mainly containing aluminum nitride (AlN) and gallium nitride (GaN), and a semiconductor containing other materials such as indium nitride (InN). It shall include materials. Therefore, the “AlGaN-based semiconductor material” referred to in the present specification has, for example, a composition of In _{1-xy Al x} Gay N (0 ≦ x + y ≦ 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1). It can be represented and includes AlN, GaN, AlGaN, indium aluminum nitride (InAlN), indium gallium nitride (InGaN), and indium aluminum gallium nitride (InAlGaN).

Further, among the "AlGaN-based semiconductor materials", the "GaN-based semiconductor material" may be used to distinguish a material that does not substantially contain AlN. The "GaN-based semiconductor material" mainly includes GaN and InGaN, and also includes a material containing a trace amount of AlN. Similarly, among the "AlGaN-based semiconductor materials", the "AlN-based semiconductor material" may be used to distinguish a material that does not substantially contain GaN. The "AlN-based semiconductor material" mainly contains AlN and InAlN, and also includes a material containing a trace amount of GaN.

The semiconductor light emitting device 10 includes a substrate 20, a buffer layer 22, an n-type clad layer 24, an active layer 26, an electron block layer 28, a p-type clad layer 30, an n-side electrode 40, and a p-side electrode 42. And a protective layer 50.

The substrate 20 is a substrate having transparency to the deep ultraviolet light emitted by the semiconductor light emitting device 10, and is, for example, a sapphire (Al ₂ O ₃ ) substrate. The substrate 20 has a first main surface 20a and a second main surface 20b on the opposite side of the first main surface 20a. The first main surface 20a is one main surface that serves as a crystal growth surface for growing each layer above the buffer layer 22. The second main surface 20b is one main surface that serves as a light extraction surface for extracting deep ultraviolet light emitted by the active layer 26 to the outside. In the modification, the substrate 20 may be an aluminum nitride (AlN) substrate or an aluminum nitride gallium (AlGaN) substrate.

The buffer layer 22 is formed on the first main surface 20a of the substrate 20. The buffer layer 22 is a base layer (template layer) for forming each layer above the n-type clad layer 24. The buffer layer 22 is, for example, an undoped AlN layer, specifically, an AlN (HT-AlN; High Temperature AlN) layer grown at a high temperature. The buffer layer 22 may include an undoped AlGaN layer formed on the AlN layer. In the modification, when the substrate 20 is an AlN substrate or an AlGaN substrate, the buffer layer 22 may be composed of only an undoped AlGaN layer. That is, the buffer layer 22 includes at least one of the undoped AlN layer and the AlGaN layer.

The n-type clad layer 24 is an n-type semiconductor layer formed on the buffer layer 22. The n-type clad layer 24 is an n-type AlGaN-based semiconductor material layer, for example, an AlGaN layer to which silicon (Si) is doped as an n-type impurity. The composition ratio of the n-type clad layer 24 is selected so as to transmit the deep ultraviolet light emitted by the active layer 26. For example, the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. Is formed like this. The n-type clad layer 24 has a bandgap larger than the wavelength of deep ultraviolet light emitted by the active layer 26, and is formed so that the bandgap is, for example, 4.3 eV or more. The n-type clad layer 24 is preferably formed so that the molar fraction of AlN is 80% or less, that is, the band gap is 5.5 eV or less, and the molar fraction of AlN is 70% or less (that is, the band). It is more desirable that the gap is formed so as to be 5.2 eV or less). The n-type clad layer 24 has a thickness of about 1 μm to 3 μm, and has a thickness of, for example, about 2 μm.

The n-type clad layer 24 is formed so that the concentration of silicon (Si), which is an impurity, is 1 × 10 ¹⁸ / cm ³ or more and 5 × 10 ¹⁹ / cm ³ or less. The n-type clad layer 24 is preferably formed so that the Si concentration is 5 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less, and 7 × 10 ¹⁸ / cm ³ or more and 2 × 10 ¹⁹ /. It is preferably formed so as to be cm ³ or less. In one embodiment, the Si concentration of the n-type clad layer 24 is around 1 × 10 ¹⁹ / cm ³ , and is in the range of 8 × 10 ¹⁸ / cm ³ or more and 1.5 × 10 ¹⁹ / cm ³ or less.

The active layer 26 is made of an AlGaN-based semiconductor material and is sandwiched between the n-type clad layer 24 and the electron block layer 28 to form a double heterojunction structure. The active layer 26 may have a single-layer or multi-layer quantum well structure. For example, a barrier layer formed of an undoped AlGaN-based semiconductor material and a well layer formed of an undoped AlGaN-based semiconductor material are laminated. It may be composed of a body. The active layer 26 is configured to have a bandgap of 3.4 eV or more in order to output deep ultraviolet light having a wavelength of 355 nm or less. For example, the AlN composition ratio is selected so that deep ultraviolet light having a wavelength of 310 nm or less can be output. Will be done. The active layer 26 is formed on the first upper surface 24a of the n-type clad layer 24, and is not formed on the second upper surface 24b adjacent to the first upper surface 24a. The active layer 26 is not formed on the entire surface of the n-type clad layer 24, but is formed only on a part of the n-type clad layer 24.

The electron block layer 28 is formed on the active layer 26. The electron block layer 28 is an undoped AlGaN-based semiconductor material layer, and is formed so that, for example, the molar fraction of AlN is 40% or more, preferably 50% or more. The electron block layer 28 may be formed so that the molar fraction of AlN is 80% or more, or may be formed of an AlN-based semiconductor material that does not substantially contain GaN. The electron block layer has a thickness of about 1 nm to 10 nm, and has a thickness of, for example, about 2 nm to 5 nm. The electron block layer 28 may be a p-type AlGaN-based semiconductor material layer.

The p-type clad layer 30 is a p-type semiconductor layer formed on the electron block layer 28. The p-type clad layer 30 is a p-type AlGaN-based semiconductor material layer, and is, for example, an AlGaN layer doped with magnesium (Mg) as a p-type impurity. The p-type clad layer 30 has a thickness of about 300 nm to 700 nm, and has a thickness of, for example, about 400 nm to 600 nm. The p-type clad layer 30 may be formed of a p-type GaN-based semiconductor material that does not substantially contain AlN.

The n-side electrode 40 is formed on the second upper surface 24b of the n-type clad layer 24. The n-side electrode 40 includes an n-side contact layer 32, an n-side indium tin oxide (ITO; Indium Tin Oxide) layer 34, an n-side palladium (Pd) layer 36, and an n-side pad electrode layer 38.

The n-side contact layer 32 includes a titanium (Ti) layer 32a and an aluminum (Al) layer 32b. The Ti layer 32a is provided so as to be in contact with the n-type clad layer 24, and the Al layer 32b is provided so as to be in contact with the Ti layer 32a. The thickness of the Ti layer 32a is about 1 nm to 10 nm, and the thickness of the Al layer 32b is about 20 nm to 1000 nm. It is preferable that the n-side contact layer 32 does not contain gold (Au), which can cause a decrease in the ultraviolet light reflectance.

The thickness of the Ti layer 32a is preferably 5 nm or less, and more preferably 2 nm or less. By reducing the thickness of the Ti layer 32a, the ultraviolet light reflectance of the n-side contact layer 32 when viewed from the n-type clad layer 24 can be increased. Further, by setting the annealing temperature of the n-side contact layer 32 to a temperature lower than the melting point of aluminum (660 ° C.), specifically, about 650 ° C., 600 ° C., and 550 ° C., ultraviolet light reflection of the n-side contact layer 32 is performed. The rate can be 70% or more or 80% or more.

FIG. 2 is a graph showing the relationship between the thickness of the Ti layer 32a and the ultraviolet light reflectance, and is the n-side contact layer 32 seen from the n-type clad layer 24 when the thickness of the Ti layer 32a and the annealing temperature are changed. It shows the change in ultraviolet light reflectance. As shown in the figure, the reflectance of the n-side contact layer 32 tends to decrease after heating as compared with before heating, and the ultraviolet light reflectance particularly decreases significantly after annealing at 700 ° C., which exceeds the melting point of Al. You can see that it does. Further, it can be seen that by setting the thickness of the Ti layer 32a to 5 nm or less or 2 nm or less, the n-side contact layer 32 having a higher ultraviolet light reflectance can be obtained. Further, since the flatness of the n-side contact layer 32 tends to increase as the ultraviolet light reflectance of the Ti layer 32a increases, it is also possible to obtain the n-side contact layer 32 having high flatness by lowering the annealing temperature. can.

Returning to FIG. 1, the n-side ITO layer 34 has an n-side first ITO layer 34a and an n-side second ITO layer 34b. The n-side first ITO layer 34a is an ITO layer formed at a relatively low film formation rate, and the n-side second ITO layer 34b is an ITO layer formed at a relatively high film formation rate. The n-side first ITO layer 34a is provided so as to be in contact with the Al layer 32b, and the n-side second ITO layer 34b is provided so as to be in contact with the n-side first ITO layer 34a. The n-side ITO layer 34 is provided so as to cover the entire n-side contact layer 32. The n-side ITO layer 34 is provided so as to cover the upper surface and the side surface of the n-side contact layer 32, for example.

The n-side ITO layer 34 functions as a shielding layer for preventing components contained in the n-side Pd layer 36 and the n-side pad electrode layer 38 from diffusing into the n-side contact layer 32 when the semiconductor light emitting device 10 is energized. .. By providing the n-side ITO layer 34, deterioration of the n-side contact layer 32 due to energization can be prevented, and high reflectance of the n-side contact layer 32 can be maintained. The n-side ITO layer 34 preferably has a thickness of 20 nm or more and preferably 100 nm or more in order to function as a shielding layer.

The n-side ITO layer 34 is provided in a second region W2 wider than the first region W1 in which the n-side contact layer 32 is formed, and a part thereof is in contact with the second upper surface 24b of the n-type clad layer 24. It will be provided. As a result, the function of the n-side ITO layer 34 as a shielding layer can be enhanced. In the modified example, the n-side ITO layer 34 may be formed so that the first region W1 and the second region W2 are the same. In this case, the n-side ITO layer 34 may be formed so as not to be in contact with the second upper surface 24b of the n-type clad layer 24.

The n-side Pd layer 36 is provided in contact with the n-side ITO layer 34. The n-side Pd layer 36 functions as an adhesive layer that enhances the adhesion between the n-side ITO layer 34 and the n-side pad electrode layer 38. By providing the Pd layer having high adhesion to the ITO layer, it is possible to prevent the n-side pad electrode layer 38 from peeling off and to improve the reliability of the n-side electrode 40. The thickness of the n-side Pd layer 36 can be about 1 nm to 100 nm.

The n-side pad electrode layer 38 is a portion to be bonded when the semiconductor light emitting element 10 is mounted on a package substrate or the like. The n-side pad electrode layer 38 is configured to contain gold (Au) from the viewpoint of corrosion resistance, and is, for example, nickel (Ni) / Au, titanium (Ti) / Au or Ti / platinum (Pt) / Au. It is composed of a laminated structure. In order to improve the adhesiveness with the Pd layer, for example, the n-side pad electrode layer 38 is configured so that the Ti layer is in contact with the n-side Pd layer 36. When the n-side pad electrode layer 38 is joined with gold tin (AuSn), the n-side pad electrode layer 38 may include an AuSn layer for the joining.

The p-side electrode 42 is formed on the p-type clad layer 30. The p-side electrode 42 includes a p-side ITO layer 44, a p-side Pd layer 46, and a p-side pad electrode layer 48.

The p-side ITO layer 44 has a p-side first ITO layer 44a and a p-side second ITO layer 44b, similarly to the n-side ITO layer 34 described above. The p-side first ITO layer 44a is an ITO layer formed at a relatively low film formation rate, and the p-side second ITO layer 44b is an ITO layer formed at a relatively high film formation rate. The p-side first ITO layer 44a is provided so as to be in contact with the p-type clad layer 30, and functions as a p-side contact layer. The p-side second ITO layer 44b is provided so as to be in contact with the p-side first ITO layer 44a.

FIG. 3 is a graph showing the relationship between the film formation rate of the p-side first ITO layer and the contact resistance. The film formation rate of the p-side first ITO layer 44a is preferably less than 10 nm / min, and preferably 2 nm / min or more and 5 nm / min or less. By forming the first ITO layer having a low film formation rate, the contact resistance with the p-type clad layer 30 can be reduced, and a contact resistance of about 1 × 10 ⁻² Ω · cm ² can be realized. Further, when the thickness of the p-side ITO layer 44 is increased by combining the p-side second ITO layer 44b having a high film formation rate, the contact resistance of the p-side ITO layer 44 is prevented from significantly increasing the manufacturing time. Can be suppressed from increasing. The thickness of the p-side ITO layer 44 is, for example, 50 nm or more, preferably 100 nm or more.

Returning to FIG. 1, the p-side Pd layer 46 is provided in contact with the p-side ITO layer 44. The p-side Pd layer 46 functions as an adhesive layer in the same manner as the n-side Pd layer 36. The thickness of the p-side Pd layer 46 can be about 1 nm to 100 nm. The p-side pad electrode layer 48 is a portion to be bonded and bonded when the semiconductor light emitting element 10 is mounted on a package substrate or the like, and is configured in the same manner as the n-side pad electrode layer 38.

Next, a method for manufacturing the semiconductor light emitting device 10 will be described. 4 to 10 are diagrams schematically showing a manufacturing process of the semiconductor light emitting device 10. In FIG. 4, first, the buffer layer 22, the n-type clad layer 24, the active layer 26, the electron block layer 28, and the p-type clad layer 30 are sequentially formed on the first main surface 20a of the substrate 20.

The substrate 20 is a sapphire (Al ₂ O ₃ ) substrate, which is a growth substrate for forming an AlGaN-based semiconductor material. For example, the buffer layer 22 is formed on the (0001) plane of the sapphire substrate. The buffer layer 22 includes, for example, an AlN (HT-AlN) layer grown at a high temperature and an undoped AlGaN (u-AlGaN) layer. The n-type clad layer 24, the active layer 26, the electron block layer 28, and the p-type clad layer 30 are layers formed of an AlGaN-based semiconductor material, an AlN-based semiconductor material, or a GaN-based semiconductor material, and are organic metal chemical vapor phase growth. It can be formed by using a well-known epitaxial growth method such as (MOVPE) method or molecular beam epitaxy (MBE) method.

Next, one of the p-type clad layer 30, the electron block layer 28, the active layer 26, and the n-type clad layer 24 in the exposed region 16 in which the mask 12 is formed on the p-type clad layer 30 and the mask 12 is not formed. The part is removed. As a result, the second upper surface 24b (exposed surface) of the n-type clad layer 24 is formed in the exposed region 16. In the step of forming the exposed surface of the n-type clad layer 24, each layer can be removed by dry etching 14. For example, reactive ion etching by plasma conversion of the etching gas can be used, and for example, inductively coupled plasma (ICP) etching can be used.

Next, as shown in FIG. 5, a Ti layer 32a is formed on the second upper surface 24b (exposed surface) of the n-type clad layer 24, and then an Al layer 32b is formed to form an n-side contact layer 32. The n-side contact layer 32 is preferably formed by a sputtering method. Although these layers can be formed by an electron beam (EB) vapor deposition method, a metal layer having a low film density can be formed by using a sputtering method. When the Al layer is formed by a sputtering method, the film density of the Al layer is 2.6 g / cm ³ or more and less than 2.7 g / cm ³ , for example, about 2.61 to 2.69 g / cm ³ . On the other hand, when the Al layer is formed by the EB vapor deposition method, the film density is 2.7 g / cm ³ or more, for example, 2.71 to 2.75 g / cm ³ . By lowering the film density of the Al layer, suitable contact resistance can be realized at a relatively low annealing temperature.

Next, the n-side contact layer 32 is annealed. The annealing treatment of the n-side contact layer 32 is performed at a temperature lower than the melting point of Al (about 660 ° C.), and it is preferable to anneal at a temperature of 560 ° C. or higher and 650 ° C. or lower. By setting the film density of the Al layer to less than 2.7 g / cm ³ and the annealing temperature to 560 ° C. or higher and 650 ° C. or lower, the contact resistance of the n-side electrode 40 can be set to 0.1 Ω · cm ² or lower. Further, by setting the annealing temperature to 560 ° C. or higher and 650 ° C. or lower, the flatness of the n-side electrode 40 after annealing can be improved, and the ultraviolet light reflectance can be 30% or more. Further, by annealing at a temperature lower than the melting point of Al, suitable contact resistance can be obtained even if an annealing treatment of 1 minute or more, for example, an annealing treatment of about 5 minutes to 30 minutes is performed. When multiple element parts are formed on one substrate, the temperature uniformity in the substrate at the time of annealing is improved by lengthening the annealing time (1 minute or more), and a semiconductor light emitting element with little variation in characteristics can be obtained. Multiple can be formed at the same time.

Subsequently, after removing the mask 12, a mask 60 having an n-side opening 61 and a p-side opening 62 is formed as shown in FIG. The mask 60 is formed on the second upper surface 24b of the n-type clad layer 24 and the p-type clad layer 30. The n-side opening 61 is a region where the above-mentioned n-side ITO layer 34 is formed, and is formed so that a second region W2 wider than the first region W1 where the n-side contact layer 32 is formed opens. .. The p-side opening 62 is a region where the above-mentioned p-side ITO layer 44 is formed.

Next, as shown in FIG. 7, the first ITO layers 34a and 44a are formed in the n-side opening 61 and the p-side opening 62 at a low film formation rate, and the second ITO layer 34b is formed on the first ITO layers 34a and 44a. , 44b are formed at a high film formation rate. The film formation rate of the first ITO layers 34a and 44a is, for example, 2 nm / min or more and 5 nm / min or less. On the other hand, the film formation rate of the second ITO layers 34b and 44b is, for example, 10 nm / min or more. Subsequently, the Pd layers 36 and 46 are formed on the second ITO layers 34b and 44b in the n-side opening 61 and the p-side opening 62. The ITO layers 34, 44 and the Pd layers 44, 46 can be formed by a well-known method such as a sputtering method or an electron beam vapor deposition method.

The n-side first ITO layer 34a and the p-side first ITO layer 44a can be simultaneously formed by using a common mask 60. Further, the n-side second ITO layer 34b and the p-side second ITO layer 44b can be simultaneously formed by using the common mask 60, and the n-side Pd layer 36 and the p-side Pd layer 46 can also be simultaneously formed by using the common mask 60. In the modified example, each of the n-side ITO layer 34 and the p-side ITO layer 44 may be formed in a separate step. In that case, the n-side ITO layer 34 can be formed by using a mask having only the n-side opening 61, and the p-side ITO layer 44 can be formed by using another mask having only the p-side opening 62. Similarly, each of the n-side Pd layer 36 and the p-side Pd layer 46 may be formed in a separate step.

Subsequently, after removing the mask 60, the protective layer 50 is formed as shown in FIG. The protective layer 50 is formed so as to cover the entire upper surface of the element structure. The protective layer 50 covers the ITO layers 34, 44 and the Pd layers 36, 46, and also covers the second upper surface 24b of the n-type clad layer 24 and the p-type clad layer 30. The protective layer 50 can be made of silicon oxide (SiO ₂ ), silicon nitriding (SiON) or silicon nitride (SiN).

Next, as shown in FIG. 9, a mask 64 having an n-side opening 65 and a p-side opening 66 is formed on the protective layer 50. The n-side opening 65 is a region where the n-side pad electrode layer 38 is formed, and is provided in a third region W3 which is narrower than the second region W2 where the n-side Pd layer 36 is formed. The p-side opening 66 is a region where the p-side pad electrode layer 48 is formed, and is provided in the fifth region W5 which is narrower than the fourth region 4 where the p-side Pd layer 46 is formed.

Subsequently, as shown in FIG. 10, the protective layer 50 in the n-side opening 65 and the p-side opening 66 is removed by performing etching 18 from above the mask 64. By removing the protective layer 50 in the n-side opening 65, the first opening 51 in which the n-side Pd layer 36 is exposed is formed, and by removing the protective layer 50 in the p-side opening 66, the p-side Pd layer 46 is formed. An exposed second opening 52 is formed. The protective layer 50 can be dry-etched using a CF-based etching gas, and for example, ethane hexafluoride ( _C2 F ₆ ) can be used. Since the Pd layers 36 and 46 have higher etching resistance to CF-based gas than the protective layer 50 composed of silicon oxide (SiO ₂ ) or the like, the Pd layers 36 and 46 can function as a stop layer for the etching process. can. This makes it possible to expose the Pd layers 36, 46 while preventing damage to the Pd layers 36, 46 and the ITO layers 34, 36.

Subsequently, the pad electrode layers 38 and 48 are formed in the n-side opening 65 and the p-side opening 66 of the mask 64. The pad electrode layers 38 and 48 can be formed, for example, by depositing a Ni layer or a Ti layer so as to be in contact with the Pd layers 36 and 46, and depositing an Au layer on the Ni layer or the Ti layer. Another metal layer may be provided on the Au layer, and for example, a laminated structure of Sn layer, AuSn layer, and Sn / Au may be formed. After that, by removing the mask 64, the semiconductor light emitting device 10 of FIG. 1 is completed.

According to the present embodiment, by providing the n-side ITO layer 34 on the n-side electrode 40, deterioration of the n-side contact layer 32 due to the energization of the semiconductor light emitting device 10 can be prevented. In particular, it is possible to prevent the gold (Au) from the n-side pad electrode layer 38 from diffusing into the n-side contact layer 32 and deteriorating the n-side contact layer 32. As a result, it is possible to prevent a decrease in the ultraviolet light reflectance of the n-side contact layer 32 and suppress a decrease in the light output characteristics due to the use of energization.

According to the present embodiment, in each of the n-side electrode 40 and the p-side electrode 42, the pad electrode layer is formed by inserting the Pd layers 36 and 46 between the ITO layers 34 and 44 and the pad electrode layers 38 and 48. Can be suitably prevented from peeling off. As a comparative example, when a pad electrode layer (Ni / Au layer) is formed directly on the ITO layer, 10 out of 10 elements are subjected to a high temperature and high humidity test (temperature 60 ° C., humidity 90%) by continuous energization for 500 hours. Peeling was seen on the pad electrode of. On the other hand, when a Pd layer is provided on the ITO layer and a pad electrode layer (Ti / Au layer) is formed on the Pd layer as in the present embodiment, a high temperature and high humidity test (temperature 60 ° C., No peeling was observed in the pad electrodes of all 10 elements at a humidity of 90%). Therefore, according to the present embodiment, it is possible to prevent the pad electrode layer from peeling off and improve the reliability of the semiconductor light emitting device 10.

According to the present embodiment, by using palladium (Pd) as the adhesive layer of the n-side electrode 40 and the p-side electrode 42, it is possible to improve the electrical characteristics of the electrodes as compared with the case where other materials are used. can. The electric conductivity of Pd is 105 nΩm, which is equivalent to that of platinum (Pt) and superior to that of Ti (427 nΩm). Therefore, the Pd layer can function as a current dispersion layer, and the luminous efficiency of the entire element can be improved.

According to the present embodiment, the p-side ITO layer 44 of the p-side electrode 42 has a two-layer structure, and the p-side first ITO layer 44a having a low film formation rate is in contact with the p-type clad layer 30. The contact resistance of the side electrode 42 can be improved. As a comparative example, it was found that when the second ITO layer having a high film formation rate (10 nm / min or more) was brought into contact with the p-type clad layer 30, the contact resistance was 1 Ω · cm ² or more. On the other hand, according to the present embodiment, the first ITO layer having a low film formation rate (2 nm / min or more and 5 nm / min or less) is in contact with the p-type clad layer 30, so that the contact resistance is 1 × 10 ⁻² Ω · cm. It can be reduced to about ² . Therefore, according to the present embodiment, the forward voltage _VF of the semiconductor light emitting device 10 can be lowered to improve the luminous efficiency.

The present invention has been described above based on the examples. It is understood by those skilled in the art that the present invention is not limited to the above embodiment, various design changes are possible, various modifications are possible, and such modifications are also within the scope of the present invention. It is about to be.

In the above-described embodiment, the case where the n-side ITO layer 34 has a two-layer structure of the n-side first ITO layer 34a and the n-side second ITO layer 34b is shown. In the modified example, the n-side ITO layer 34 may be composed of only the ITO layer having a high film formation rate.

FIG. 11 is a cross-sectional view schematically showing the configuration of the semiconductor light emitting device 110 according to the modified example. The semiconductor light emitting device 110 differs from the above-described embodiment in the configurations of the n-side electrode 140 and the p-side electrode 142. Specifically, the n-side electrode 140 is provided with only the n-side ITO layer 134 having a high film formation rate, and is not provided with the n-side first ITO layer 34a having a low film formation rate according to the above-described embodiment. Further, the region (sixth region W6) in which the p-side first ITO layer 144a having a low film formation rate of the p-side electrode 142 is provided is relatively narrow, and the region in which the p-side second ITO layer 144b having a high film formation rate is provided (situation). The fourth region W4) is relatively wide. As a result, the p-side second ITO layer 144b is partially in contact with the p-type clad layer 30. According to this modification, since the entire p-side first ITO layer 144a that realizes low contact resistance can be covered with the p-side second ITO layer 144b, the reliability of the p-side electrode 142 can be improved.

FIG. 12 is a diagram schematically showing a manufacturing process of the semiconductor light emitting device 110 according to the modified example, and corresponds to the manufacturing process of FIG. 7 described above. In this modification, after the step of FIG. 5 described above, the first ITO layer (p-side first ITO layer 144a) having a low film formation rate is formed only on the p-type clad layer 30, and then the mask 60 of FIG. 6 is formed. Then, a second ITO layer (p-side second ITO layer 144b and n-side ITO layer 134) having a high film formation rate is formed in both the n-side opening 61 and the p-side opening 62 via the mask 60. After that, the semiconductor light emitting device 110 shown in FIG. 11 can be formed by going through the same steps as those in the above-described embodiment.

In the above-described embodiment, the ITO layer is provided, but in the modified example, other conductive oxides such as zinc oxide (ZnO) and tin oxide (InO ₂ ) may be used instead of the ITO layer. good. Further, instead of the ITO layer alone, the ITO layer and another conductive oxide layer may be used in combination.

10 ... semiconductor light emitting device, 20 ... substrate, 24 ... n-type clad layer, 26 ... active layer, 30 ... p-type clad layer, 32 ... n-side contact layer, 34 ... n-side ITO layer, 36 ... n-side Pd layer, 38 ... n-side pad electrode layer, 40 ... n-side electrode, 42 ... p-side electrode, 44 ... p-side ITO layer, 46 ... p-side Pd layer, 48 ... p-side pad electrode layer, 50 ... protective layer.

Claims (7)

An n-type semiconductor layer made of an n-type aluminum nitride gallium (AlGaN) -based semiconductor material,
The n-side electrode provided in a part of the n-type semiconductor layer and
An active layer of an AlGaN-based semiconductor material provided in a region different from the partial region on the n-type semiconductor layer,
The p-type semiconductor layer of the p-type AlGaN-based semiconductor material provided on the active layer and the p-type semiconductor layer
A p-side electrode provided on the p-type semiconductor layer is provided.
The n-side electrode is provided in contact with both the n-side contact layer including the aluminum (Al) layer and the n-side contact layer and the n-type semiconductor layer so as to cover the n-side contact layer. A side indium tin oxide (ITO) layer, an n-side palladium (Pd) layer on the n-side ITO layer, and an n-side pad electrode layer on the n-side Pd layer are included.
The p-side electrode is on the p-side first ITO layer so as to cover the p- side first indium tin oxide (ITO) layer provided in contact with the p-type semiconductor layer and the p-side first ITO layer. The p-side second indium tin oxide (ITO) layer provided in contact with both of the p-type semiconductor layer, the p-side palladium (Pd) layer on the p-side second ITO layer, and the p-side Pd. A semiconductor light emitting element comprising a p-side pad electrode layer on the layer. An n-type semiconductor layer made of an n-type aluminum nitride gallium (AlGaN) -based semiconductor material,
The n-side electrode provided in a part of the n-type semiconductor layer and
An active layer of an AlGaN-based semiconductor material provided in a region different from the partial region on the n-type semiconductor layer,
The p-type semiconductor layer of the p-type AlGaN-based semiconductor material provided on the active layer and the p-type semiconductor layer
The p-side electrode provided on the p-type semiconductor layer and
Silicon oxide (SiO) ₂ ), With a protective layer composed of silicon nitride (SiON) or silicon nitride (SiN).
The n-side electrode includes an n-side contact layer including an aluminum (Al) layer, an n-side indium tin oxide (ITO) layer on the n-side contact layer, and n-side palladium (Pd) on the n-side ITO layer. ) Layer and an n-side pad electrode layer on the n-side Pd layer.
The p-side electrode includes a p-side indium tin oxide (ITO) layer, a p-side palladium (Pd) layer on the p-side ITO layer, and a p-side pad electrode layer on the p-side Pd layer. ,
The protective layer has a first opening provided on the n-side Pd layer and a second opening provided on the p-side Pd layer, and at a position different from the first opening and the second opening. Covers the n-type semiconductor layer, the p-type semiconductor layer, the n-side ITO layer, the n-side Pd layer, the p-side ITO layer, and the p-side Pd layer.
The n-side pad electrode layer is provided on the n-side Pd layer exposed at the first opening, and the p-side pad electrode layer is provided on the p-side Pd layer exposed at the second opening. A semiconductor light emitting device characterized by being able to be used. The semiconductor light emitting device according to claim 1 or 2 , wherein the n-side ITO layer is provided in contact with the Al layer of the n- side contact layer. The semiconductor light emitting device according to any one of claims 1 to 3 , wherein the n- side contact layer does not contain gold (Au). The n-type semiconductor layer of the n-type aluminum nitride gallium nitride (AlGaN) -based semiconductor material, the active layer of the AlGaN-based semiconductor material on the n-type semiconductor layer, and the p-type semiconductor layer of the p-type AlGaN-based semiconductor material on the active layer are laminated in this order. Process and
A step of removing the p-type semiconductor layer, the active layer, and a part of the n-type semiconductor layer so that a part of the n-type semiconductor layer is exposed.
A step of forming an n- side contact layer including an aluminum (Al) layer on an exposed region of the n-type semiconductor layer, and a step of forming the n-side contact layer.
The step of forming the first indium oxide (ITO) layer on the p-type semiconductor layer and
A step of forming a mask having an n-side opening on the n- side contact layer and a p-side opening on the p-type semiconductor layer on the exposed region of the n-type semiconductor layer and on the p-type semiconductor layer. ,
A step of forming a second ITO layer on the n-side contact layer in the n-side opening of the mask and on the first ITO layer in the p-side opening.
A step of forming a palladium (Pd) layer on the second ITO layer in the n-side opening and the p-side opening of the mask.
A step of forming a pad electrode layer on the Pd layer is provided .
A method for manufacturing a semiconductor light emitting device , wherein the second ITO layer is formed under conditions of a higher film formation rate than the first ITO layer . The n-type semiconductor layer of the n-type aluminum nitride gallium nitride (AlGaN) -based semiconductor material, the active layer of the AlGaN-based semiconductor material on the n-type semiconductor layer, and the p-type semiconductor layer of the p-type AlGaN-based semiconductor material on the active layer are laminated in this order. Process and
A step of removing the p-type semiconductor layer, the active layer, and a part of the n-type semiconductor layer so that a part of the n-type semiconductor layer is exposed.
A step of forming an n-side contact layer including an aluminum (Al) layer on an exposed region of the n-type semiconductor layer, and a step of forming the n-side contact layer.
A step of forming a mask having an n-side opening on the n-side contact layer and a p-side opening on the p-type semiconductor layer on the exposed region of the n-type semiconductor layer and on the p-type semiconductor layer. ,
A step of forming an indium oxide (ITO) layer in the n-side opening and the p-side opening of the mask, and
A step of forming a palladium (Pd) layer on the ITO layer in the n-side opening and the p-side opening of the mask.
A step of forming a pad electrode layer on the Pd layer is provided.
The steps for forming the ITO layer include a step of forming the first ITO layer at a film forming rate of 2 nm / min or more and 5 nm / min or less, and a step of forming the second ITO layer under conditions of a higher film forming rate than the first ITO layer. A method for manufacturing a semiconductor light emitting device, which comprises a step of performing the process. The n-type semiconductor layer of the n-type aluminum nitride gallium nitride (AlGaN) -based semiconductor material, the active layer of the AlGaN-based semiconductor material on the n-type semiconductor layer, and the p-type semiconductor layer of the p-type AlGaN-based semiconductor material on the active layer are laminated in this order. Process and
A step of removing the p-type semiconductor layer, the active layer, and a part of the n-type semiconductor layer so that a part of the n-type semiconductor layer is exposed.
A step of forming an n-side contact layer including an aluminum (Al) layer on an exposed region of the n-type semiconductor layer, and a step of forming the n-side contact layer.
A step of forming a mask having an n-side opening on the n-side contact layer and a p-side opening on the p-type semiconductor layer on the exposed region of the n-type semiconductor layer and on the p-type semiconductor layer. ,
A step of forming an indium oxide (ITO) layer in the n-side opening and the p-side opening of the mask, and
A step of forming a palladium (Pd) layer on the ITO layer in the n-side opening and the p-side opening of the mask.
After removing the mask, silicon oxide (SiO) is placed on the exposed region of the n-type semiconductor layer and on the p-type semiconductor layer so as to cover the ITO layer and the Pd layer. ₂ ), The step of forming a protective layer composed of silicon nitride (SiON) or silicon nitride (SiN), and
A step of removing a part of the protective layer to expose the Pd layer, and
A method for manufacturing a semiconductor light emitting device, comprising a step of forming a pad electrode layer on the Pd layer exposed by removing a part of the protective layer.

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