TWI842063B - Operating voltage supply circuit - Google Patents

Abstract

An operating voltage supply circuit is provided. The operating voltage supply circuit includes an operating circuit and a charge pump circuit. The operating circuit provides pumping clock signals under different load states. The charge pump circuit receives the pumping clock signal and provides an operating voltage based on a duty cycle of the pumping clock signal. The load states are alternately switched in a time interval. Duty cycles of the pumping clock signals are not identical completely.

Description

Operating voltage supply circuit

The present invention relates to an operating voltage supply circuit, and in particular to an operating voltage supply circuit with low power consumption.

Generally speaking, electronic devices (such as touch devices, display devices, or touch display devices) operate using an operating voltage. The operating voltage supply circuit provides the operating voltage through the pumping operation of the charge pump circuit. However, in order to maintain the high working efficiency of the charge pump circuit, the charge pump circuit is always in a fixed working state to provide the operating voltage. Therefore, the power consumption of the operating voltage supply circuit does not decrease.

The present invention provides an operating voltage supply circuit with low power consumption.

The operating voltage supply circuit of the present invention includes an operating circuit and a charge pump circuit. The operating circuit provides multiple pump-up clock signals under different multiple load states. The charge pump circuit is coupled to the operating circuit. The charge pump circuit receives the pump-up clock signal and provides an operating voltage based on the duty cycle of the pump-up clock signal. The multiple load states are switched alternately in the time interval of different load states. In a specific mode, the duty cycles of the multiple pump-up clock signals provided under the multiple load states are not completely the same.

Based on the above, the operating circuit provides a pump-up clock signal under different multiple load conditions. The working cycles of the multiple pump-up clock signals are not exactly the same. In this way, the power consumption of the operating voltage supply circuit can be intermittently reduced in a single time period.

In order to make the above features and advantages of the present invention more clearly understood, the following is a detailed description of the embodiments with the accompanying drawings.

100: Operating voltage supply circuit

110, 210, 310, 410: Operation circuit

120, 220-1, 220-2, 220-3, 220-4: Charge pump circuit

211, 311, 411: Select circuit

212, 312, 412: Clock signal generation circuit

221, 222-1, 222-2: Voltage regulation circuit

CC, CCA: Capacitor

CCK1, CCK2: Charging timing signal

DT: Time Zone

DTC1, DTC2, DTC3: working cycle

ED: Electronic devices

GND: Ground

MUX, MUX1, MUX2: Multiplexer

MUXC: Multiplexer circuit

PCK1, PCK2, PCK3: pump up clock signal

PCKH, PCKL: Gate voltage pump rising clock signal

REG1, REG2, REG3: registers

S101~S109, S201~S212: Steps

SS, SS1, SS2: Select signal

ST1, ST2, ST2’, ST3: Load status

STG1~STG9, STG5’~STG7’: stage

SV1, SV2, SV3: Status data

SW1~SW11: switch

VCI: Charging voltage

VGH: Gate high voltage

VGL: Gate Low Voltage

VR, VR1, VR2: voltage regulation

VRI: Reference voltage

VSN, VSP: operating voltage

FIG1 is a schematic diagram of an operating voltage supply circuit according to the first embodiment of the present invention.

FIG2 is a schematic diagram and a state diagram showing the load state and the working cycle of the pump-up clock signal according to an embodiment of the present invention.

FIG3 is a schematic diagram of an operating voltage supply circuit according to the second embodiment of the present invention.

Figures 4A to 4C are schematic diagrams of a charge pump circuit according to an embodiment of the present invention.

Figure 5 is a state diagram based on Figure 3.

FIG6 is a schematic diagram of a charge pump circuit according to an embodiment of the present invention.

Figure 7 is a state diagram based on Figure 6.

FIG8 is a schematic diagram of an operating circuit according to an embodiment of the present invention.

FIG9 is a schematic diagram of an operating circuit according to another embodiment of the present invention.

FIG10 is a schematic diagram of an operating circuit according to another embodiment of the present invention.

Figure 11 is an operation flow chart drawn according to an embodiment of the present invention.

Figure 12 is an operation flow chart drawn according to another embodiment of the present invention.

FIG13 is a schematic diagram and a state diagram showing the load state and the working cycle of the pump-up clock signal according to another embodiment of the present invention.

Some embodiments of the present invention will be described in detail with the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More precisely, these embodiments are only examples within the scope of the patent application of the present invention.

Please refer to FIG. 1, which is a schematic diagram of an operating voltage supply circuit according to an embodiment of the present invention. In this embodiment, the operating voltage supply circuit 100 is used to provide an operating voltage VSP to an electronic device ED. The electronic device ED operates based on the operating voltage VSP. The electronic device ED can be a touch device, a display device, or a touch display device in a portable device or a wearable device. In this embodiment, the operating voltage supply circuit 100 includes an operating circuit 110 and a charge pump circuit 120. The operating circuit 110 provides a pump-up clock signal under multiple different load states. The multiple load states are switched alternately in a single time interval DT of a specific mode. In addition, the working cycles of the multiple pump-up clock signals are not exactly the same. For example, taking the present embodiment as an example, the operating circuit 110 provides a pump-up clock signal PCK1 under the load state ST1. The operating circuit 110 provides a pump-up clock signal PCK2 under the load state ST2. The load state ST1 is different from the load state ST2. The power consumption of the load state ST1 is different from the power consumption of ST2. The duty cycle of the pump-up clock signal PCK1 is different from the duty cycle of the pump-up clock signal PCK2. In addition, the load states ST1 and ST2 are switched alternately in the time period DT in different load states. In other words, in the time period DT, the operating circuit 110 is in a specific mode and provides the pump-up clock signals PCK1 and PCK2 alternately. For example, the specific mode can be various types of standby modes. For example, the specific mode (or standby mode) includes at least one of a dark screen touch mode and an always-on display (AOD) mode.

In this embodiment, the charge pump circuit 120 is coupled to the operating circuit 110. The charge pump circuit 120 receives the pump-up clock signal provided by the operating circuit 110, and provides the operating voltage VSP based on the duty cycle of the received pump-up clock signal.

It is worth mentioning here that the operating cycle of the pump-up clock signal provided by the operating circuit 110 under different multiple load states is not exactly the same. The multiple load states are switched alternately in a single time interval DT. The multiple power consumptions of the multiple load states are different from each other. In this way, the power consumption of the operating voltage supply circuit 100 can be intermittently reduced in a single time interval.

For ease of explanation, this embodiment uses two load states ST1 and ST2 as examples. The number of load states of the present invention can be multiple and is not limited to this embodiment.

Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a schematic diagram and a state diagram of a load state and a duty cycle of a pump-up clock signal according to an embodiment of the present invention. In this embodiment, in the time interval DT, the operating circuit 110 provides a pump-up clock signal PCK1 under the load state ST1. The pump-up clock signal PCK1 has a duty cycle DTC1. The operating circuit 110 provides a pump-up clock signal PCK2 under the load state ST2. The pump-up clock signal PCK2 has a duty cycle DTC2. The operating circuit 110 can alternately provide the pump-up clock signals PCK1 and PCK2 in a specific mode.

For example, the electronic device ED is a touch display device. The operating circuit 110 can alternately provide pump-up clock signals PCK1 and PCK2 in the dark screen touch mode of the electronic device ED. The dark screen touch mode is the touch mode of the electronic device ED when the display panel stops displaying the picture. Therefore, the charge pump circuit 120 provides the operating voltage VSP according to the duty cycles DTC1 and DTC2. In this example, the load state ST1 is the touch sensing state of the electronic device ED. In the load state ST1, the operating circuit 110 provides a pump-up clock signal PCK1 with a duty cycle DTC1. The duty cycle DTC1 is, for example, 50% (the present invention is not limited to this). Therefore, the charge pump circuit 120 provides an operating voltage VSP based on the duty cycle DTC1 in the load state ST1. The load state ST2 is an idle state of the electronic device ED. The operating circuit 110 provides a pump-up clock signal PCK2 having a duty cycle DTC2. The duty cycle DTC2 is less than the duty cycle DTC1. The duty cycle DTC2 is, for example, 12% (the present invention is not limited thereto). Therefore, the charge pump circuit 120 provides an operating voltage VSP based on the duty cycle DTC2 in the load state ST2. The operating voltage VSP is used to drive the touch sensing circuit of the electronic device ED.

It should be noted that the duty cycle DTC1 is greater than the duty cycle DTC2. The power consumption generated by the charge pump circuit 120 operating based on the duty cycle DTC2 is less than the power consumption generated by the operation based on the duty cycle DTC1. Therefore, in the dark screen touch mode, the power consumption of the charge pump circuit 120 can be reduced.

In addition, in this embodiment, the duration of the load state ST1 is shorter than the duration of the load state ST2. For example, in the time period DT when the electronic device ED operates in the dark screen touch mode, the alternation cycle of the load states ST1 and ST2 is about 15 Hz (the present invention is not limited thereto). The operation duration of the load state ST1 is 2 milliseconds (the present invention is not limited thereto). The operation duration of the load state ST2 is 62 milliseconds (the present invention is not limited thereto). The operation duration of the load state ST2 is appropriately extended to reduce the power consumption of the charge pump circuit 120.

For another example, the electronic device ED is a display device. The operating circuit 110 can alternately provide pump-up clock signals PCK1 and PCK2 in the always-on display (AOD) mode of the electronic device ED. The always-on display mode is the display mode of the electronic device ED when the display panel stops scanning the display screen. Therefore, the charge pump circuit 120 provides the operating voltage VSP according to the duty cycles DTC1 and DTC2. In this example, the load state ST1 is the scanning state or data update state of the electronic device ED. In the load state ST1, the operating circuit 110 provides a pump-up clock signal PCK1 with a duty cycle DTC1. The duty cycle DTC1 is, for example, 50% (the present invention is not limited to this). Therefore, the charge pump circuit 120 provides the operating voltage VSP based on the duty cycle DTC1 in the load state ST1. The load state ST2 is the idle state of the electronic device ED. The operating circuit 110 provides the pump-up clock signal PCK2 with the duty cycle DTC2. The duty cycle DTC2 is less than the duty cycle DTC1. The duty cycle DTC2 is, for example, 12% (the present invention is not limited thereto). Therefore, the charge pump circuit 120 provides the operating voltage VSP based on the duty cycle DTC2 in the load state ST2. The operating voltage VSP is used to drive the display panel of the electronic device ED.

It should be noted that the duty cycle DTC1 is greater than the duty cycle DTC2. The power consumption generated by the charge pump circuit 120 operating based on the duty cycle DTC2 is less than the power consumption generated by the operation based on the duty cycle DTC1. Therefore, in the permanent display mode, the power consumption of the charge pump circuit 120 can be reduced.

In addition, in this embodiment, the duration of the load state ST1 is shorter than the duration of the load state ST2. For example, in the time period DT when the electronic device ED operates in the dark screen touch mode, the rotation cycle of the load states ST1 and ST2 is about 15 Hz (the present invention is not limited thereto). The operation duration of the load state ST1 is 16 milliseconds (the present invention is not limited thereto). The operation duration of the load state ST2 is 48 milliseconds (the present invention is not limited thereto).

Please refer to Figure 3, which is a schematic diagram of an operating voltage supply circuit according to the second embodiment of the present invention. In this embodiment, the operating voltage supply circuit 200 includes an operating circuit 210 and a charge pump circuit 220. The operating circuit 210 provides a pump-up clock signal PCK1 and a charging clock signal CCK1 under the load state ST1. The operating circuit 210 provides a pump-up clock signal PCK2 and a charging clock signal CCK2 under the load state ST2. The power consumption of the load state ST1 is different from the power consumption of ST2. The working cycle of the pump-up clock signal PCK1 is different from the working cycle of the pump-up clock signal PCK2. In addition, the load states ST1 and ST2 are switched alternately in the time interval DT. The charge pump circuit 220 is coupled to the operating circuit 210. The charge pump circuit 220 receives the pump-up clock signal provided by the operating circuit 210, and provides an operating voltage VSP based on the received pump-up clock signal and the charging clock signal.

Next, an example is given to illustrate the implementation details of the charge pump circuit 220.

4A~4C are schematic diagrams of a charge pump circuit according to an embodiment of the present invention. First, please refer to FIG. 4A. In this embodiment, the charge pump circuit 220-1 includes a capacitor CC and switches SW1~SW4. The first end of the switch SW1 receives the charging voltage VCI. The second end of the switch SW1 is coupled to the first end of the capacitor CC. The control end of the switch SW1 receives the charging clock signal CCK1 under the load state ST1, and receives the charging clock signal CCK2 under the load state ST2. The first end of the switch SW2 receives a reference low voltage (for example, ground GND). The second end of the switch SW2 is coupled to the second end of the capacitor CC. The control end of the switch SW2 receives the charging clock signal CCK1 under the load state ST1, and receives the charging clock signal CCK2 under the load state ST2. The first end of the switch SW3 is coupled to the first end of the capacitor CC. The second end of the switch SW3 is used to output the operating voltage VSP. The control end of the switch SW3 receives the pump-up clock signal PCK1 under the load state ST1, and receives the pump-up clock signal PCK2 under the load state ST2. The first end of the switch SW4 is coupled to the second end of the capacitor CC. The second end of the switch SW4 receives the regulating voltage VR. The control end of the switch SW4 receives the pump-up clock signal PCK1 under the load state ST1, and receives the pump-up clock signal PCK2 under the load state ST2.

In the charging stage of the load state ST1, switches SW1 and SW2 will react to the charging clock signal CCK1 being turned on. Switches SW3 and SW4 will react to the pump-up clock signal PCK1 being turned off. Therefore, there will be a charging voltage difference between the first end of capacitor CC and the second end of capacitor CC. In the pump-up stage of the load state ST1, Switches SW1 and SW2 will react to the charging clock signal CCK1 being turned off. Switches SW3 and SW4 will react to the pump-up clock signal PCK1 being turned on. Therefore, the voltage value of the operating voltage VSP will be roughly equal to the sum of the voltage value of the regulating voltage VR and the charging voltage difference.

For example, the voltage value of the charging voltage VCI is equal to 3.3 volts. The voltage value of the regulating voltage VR is equal to 2.7 volts. Therefore, in the charging stage of the load state ST1, the charging voltage difference is approximately equal to 3.3 volts. In the pump-up stage of the load state ST1, the voltage value of the operating voltage VSP will be approximately equal to 6 volts. For another example, the voltage value of the charging voltage VCI is equal to 6 volts. The voltage value of the regulating voltage VR is equal to 1 volt. Therefore, in the charging stage of the load state ST1, the charging voltage difference is approximately equal to 6 volts. In the pump-up stage of the load state ST1, the voltage value of the operating voltage VSP will be approximately equal to 7 volts. The operating voltage VSP can be used as a gate high voltage (VGH) for pixel scanning and/or as a power supply for touch sensing.

The operation of the charge pump circuit 220-1 in the charging phase of the load state ST2 is roughly similar to the operation in the charging phase of the load state ST1. The operation of the charge pump circuit 220-1 in the pumping phase of the load state ST2 is roughly similar to the operation in the pumping phase of the load state ST1. The difference between the operation of the charge pump circuit 220-1 in the load states ST1 and ST2 is mainly that the working cycle of the pumping clock signal PCK1 is different from the working cycle of the pumping clock signal PCK2.

Please refer to FIG. 4B. In this embodiment, the charge pump circuit 220-2 includes a capacitor CC, switches SW1~SW4 and a voltage regulating circuit 221. The configuration and operation of the capacitor CC and the switches SW1~SW4 have been clearly described in the embodiment of FIG. 4A, so they are not repeated here. In this embodiment, the voltage regulating circuit 221 is coupled to the second end of the switch SW4. The voltage regulating circuit 221 provides a regulating voltage VR according to a reference voltage VRI. The voltage regulating circuit 221 can be operated to use the reference voltage VRI to determine the voltage value of the regulating voltage VR.

Please refer to Figure 4C. In this embodiment, the charge pump circuit 220-3 includes a capacitor CC, switches SW1~SW4 and a voltage regulating circuit 221. The first end of the switch SW1 receives the charging voltage VCI. The second end of the switch SW1 is coupled to the first end of the capacitor CC. The control end of the switch SW1 receives the charging clock signal CCK1 under the load state ST1, and receives the charging clock signal CCK2 under the load state ST2. The first end of the switch SW2 receives a reference low voltage (for example, ground). The second end of the switch SW2 is coupled to the second end of the capacitor CC. The control end of the switch SW2 receives the charging clock signal CCK1 under the load state ST1, and receives the charging clock signal CCK2 under the load state ST2. The first end of the switch SW3 is coupled to the first end of the capacitor CC. The second end of the switch SW3 receives the regulated voltage VR. The control end of the switch SW3 receives the pump-up clock signal PCK1 under the load state ST1, and receives the pump-up clock signal PCK2 under the load state ST2. The first end of the switch SW4 is coupled to the second end of the capacitor CC. The first end of the switch SW4 is used to output the operating voltage VSN. The control end of the switch SW4 receives the pump-up clock signal PCK1 under the load state ST1, and receives the pump-up clock signal PCK2 under the load state ST2. In this embodiment, the voltage regulating circuit 221 is coupled to the second end of the switch SW3. The voltage regulating circuit 221 provides the regulated voltage VR based on the reference voltage VRI. In the charging stage of the load state ST1, switches SW1 and SW2 will react to the charging clock signal CCK1 being turned on. Switches SW3 and SW4 will react to the pump-up clock signal PCK1 being turned off. Therefore, there will be a charging voltage difference between the first end of capacitor CC and the second end of capacitor CC. In the pump-up stage of the load state ST1, switches SW1 and SW2 will react to the charging clock signal CCK1 being turned off. Switches SW3 and SW4 will react to the pump-up clock signal PCK1 being turned on.

For example, the voltage value of the charging voltage VCI is equal to 3.3 volts. The voltage value of the regulating voltage VR is equal to 0 volts. Therefore, in the charging stage of the load state ST1, the charging voltage difference is approximately equal to 3.3 volts. In the pump-up stage of the load state ST1, the voltage value of the operating voltage VSN will be approximately equal to -3.3 volts. For another example, the voltage value of the charging voltage VCI is equal to 3.3 volts. The voltage value of the regulating voltage VR is equal to -3.7 volts. Therefore, in the charging stage of the load state ST1, the charging voltage difference is approximately equal to 3.3 volts. In the pump-up phase of the load state ST1, the voltage value of the operating voltage VSP is approximately equal to -7 volts. The operating voltage VSP can be used as a gate low voltage (VGL) for pixel scanning and/or a reference low voltage for the pixel.

In some embodiments, the charge pump circuit 220 shown in FIG. 3 may be implemented by one of the charge pump circuits 220-1, 220-2, and 220-3. In some embodiments, the charge pump circuit 220 shown in FIG. 3 may be implemented by a combination of the charge pump circuits 220-2 and 220-3.

Please refer to FIG. 3 and FIG. 5 at the same time. FIG. 5 is a state diagram according to FIG. 3. In this embodiment, the load states ST1 and ST2 are switched alternately in a single time interval DT. For example, the charge pump circuit 220 will at least sequentially perform multiple stages STG1 to STG4 in the load state ST1. In this embodiment, stage STG1 is a charging stage. Stage STG2 is a pump-up stage. Stage STG3 is a charging stage. Stage STG4 is a pump-up stage. In stages STG1 and STG3 (charging stages), the charge pump circuit 220 operates based on the charging clock signal CCK1. In stages STG2 and STG4 (pump-up stages), the charge pump circuit 220 operates based on the pump-up clock signal PCK1. In this embodiment, the charging stages STG1 and STG3 and the pump-up stages STG2 and STG4 have the same duty cycle DTC1. Therefore, the duration of stages STG1 to STG4 is roughly the same. The duty cycle DTC1 is, for example, 50%.

In the present embodiment, the charge pump circuit 220, for example, in the load state ST2, will at least sequentially perform multiple stages STG5~STG9. Stage STG5 is the charging stage. Stage STG6 is the pump-up stage. Stage STG7 is the additional stage. Stage STG8 is the charging stage. Stage STG9 is the pump-up stage. In stages STG5 and STG8, the charge pump circuit 220 operates based on the charging clock signal CCK2. In stages STG6 and STG9, the charge pump circuit 220 operates based on the pump-up clock signal PCK2. In the present embodiment, stages STG5 and STG8 have a working cycle DTC1. Stages STG6 and STG9 have a duty cycle DTC2. For example, duty cycles DTC1 and DTC2 are 50%. The operation of the charge pump circuit 220 in stage STG7 is substantially equal to the operation of a single stage STG5 or repeats stage STG5 at least twice. Therefore, the time interval between the pumping operations of the charge pump circuit 220 is lengthened. The power consumption of the charge pump circuit 220 can be reduced.

In this embodiment, stage STG7 can be ignored. The duty cycle DTC2 is designed to be smaller than the duty cycle DTC1. Therefore, the power consumption of the charge pump circuit 220 can be reduced.

Please refer to FIG. 6, which is a schematic diagram of a charge pump circuit according to an embodiment of the present invention. In this embodiment, the charge pump circuit 220-4 includes a capacitor CCA and switches SW5~SW11. The first end of the switch SW5 receives the operating voltage VSP. The second end of the switch SW5 is coupled to the first end of the capacitor CCA. The control end of the switch SW5 receives the charging clock signal CCK1 under the load state ST1, and receives the charging clock signal CCK2 under the load state ST2. The first end of the switch SW6 receives the operating voltage VSN. The second end of the switch SW6 is coupled to the second end of the capacitor CC. The control end of the switch SW6 receives the charging clock signal CCK1 under the load state ST1, and receives the charging clock signal CCK2 under the load state ST2.

The first end of the switch SW7 is coupled to the first end of the capacitor CCA. The second end of the switch SW7 is used to output the gate high voltage VGH. The control end of the switch SW7 receives the gate voltage pump rise clock signal PCKH with different working cycles under different load states ST1 and ST2. The first end of the switch SW8 is coupled to the second end of the capacitor CCA. The second end of the switch SW8 receives the regulation voltage VRP. The control end of the switch SW8 receives the gate voltage pump rise clock signal PCKH with different working cycles under different load states ST1 and ST2. The first end of the switch SW9 is coupled to the first end of the capacitor CCA. The second end of the switch SW9 receives the regulation voltage VRN. The control end of the switch SW9 receives the gate voltage pump rising clock signal PCKL with different working cycles under different load states ST1 and ST2. The first end of the switch SW10 is coupled to the second end of the capacitor CC. The second end of the switch SW10 is used to output the gate low voltage VGL. The control end of the switch SW10 receives the gate voltage pump rising clock signal PCKL with different working cycles under different load states ST1 and ST2.

In this embodiment, in the charging stage of the load state ST1, ST2, switches SW5, SW6 are turned on. Switches SW7~SW10 are turned off. Therefore, there is a charging voltage difference between the first end of capacitor CCA and the second end of capacitor CCA. In the pump-up stage of the gate high voltage VGH in the load state ST1, ST2, switches SW5, SW6, SW9, SW10 are turned off. Switches SW7, SW8 are turned on. Therefore, the voltage value of the gate high voltage VGH can be pumped up based on the regulation voltage VRP. In the pump-up stage of the gate low voltage VGL in the load state ST1, ST2, switches SW5~SW8 are turned off. Switches SW9, SW10 are turned on. Therefore, the voltage value of the gate low voltage VGL can be pumped up based on the regulation voltage VRN. Based on the above, the charge pump circuit 220-4 can be used to provide the gate low voltage VGL and the gate high voltage VGH.

In this embodiment, the charge pump circuit 220-4 also includes voltage regulating circuits 222-1 and 222-2. The voltage regulating circuit 222-1 is coupled to the second end of the switch SW8. The voltage regulating circuit 222-1 provides a regulating voltage VRP. The voltage regulating circuit 222-2 is coupled to the second end of the switch SW9. The voltage regulating circuit 222-2 provides a regulating voltage VRN.

In this embodiment, the charge pump circuit 220-4 further includes a switch SW11. The first end of the switch SW11 is coupled to the second end of the capacitor CCA. The second end of the switch SW11 receives a reset voltage value VRST (e.g., 0 volts). When the switch SW11 is turned on, the voltage value at the second end of the capacitor CCA is reset.

In some embodiments, the charge pump circuit 220 shown in FIG. 3 may be implemented by combining charge pump circuits 220-2, 220-3, and 220-4.

Please refer to FIG. 6 and FIG. 7 at the same time. FIG. 7 is a state diagram according to FIG. 6. In this embodiment, the charge pump circuit 220-4 operates based on the alternating switching of the load states ST1 and ST2. In the load state ST1, the charge pump circuit 220-4, for example, performs multiple stages STG1 to STG4 in sequence. Stage STG1 is a charging stage. Stage STG2 is a pump-up stage of the gate high voltage VGH. Stage STG3 is a charging stage. Stage STG4 is a pump-up stage of the gate low voltage VGL. In stage STG2, the charge pump circuit 220-4 operates based on the gate voltage pump-up clock signal PCKH. In stage STG4, the charge pump circuit 220-4 operates based on the gate voltage pump rising clock signal PCKL. The gate voltage pump rising clock signal PCKH of stage STG2 has a duty cycle DTC1. The gate voltage pump rising clock signal PCKL of stage STG4 has a duty cycle DTC1. For example, the duty cycle DTC1 is 25%.

Under the load state ST2, the charge pump circuit 220-4, for example, sequentially performs multiple stages STG5~STG8. Stage STG5 is a charging stage. Stage STG6 is a pump-up stage of the gate high voltage VGH. Stage STG7 is a charging stage STG7. Stage STG8 is a pump-up stage of the gate low voltage VGL. In stage STG6, the charge pump circuit 220-4 operates based on the gate voltage pump-up clock signal PCKH. In stage STG8, the charge pump circuit 220-4 operates based on the gate voltage pump-up clock signal PCKL. The gate voltage pump rising clock signal PCKH of stage STG6 has a duty cycle DTC2. The gate voltage pump rising clock signal PCKL of stage STG8 has a duty cycle DTC2. For example, the duty cycle DTC1 is 12.5%.

It should be noted that the duty cycle DTC2 is smaller than the duty cycle DTC1. Therefore, the charge pump circuit 220-4 has lower power consumption under the load state ST2.

The charge pump circuit 220-4 can also operate based on the alternating switching of the load states ST1 and ST2'. In the load state ST2', the charge pump circuit 220-4 will sequentially perform multiple stages STG5'~STG7'. Stage STG5' is the charging stage. Stage STG6' is the pump-up stage of the gate high voltage VGH. Stage STG7' is the pump-up stage of the gate low voltage VGL. In stage STG6', the charge pump circuit 220-4 operates based on the gate voltage pump-up clock signal PCKH. In stage STG7', the charge pump circuit 220-4 operates based on the gate voltage pump boost clock signal PCKL. The gate voltage pump boost clock signal PCKH of stage STG6' has a duty cycle DTC2. The gate voltage pump boost clock signal PCKL of stage STG7' has a duty cycle DTC2. For example, the duty cycle DTC1 is 12.5%. In addition, the duration of stage STG5' is roughly equal to the sum of the durations of stages STG1 and STG3.

Please refer to FIG. 1 and FIG. 8 simultaneously. FIG. 8 is a schematic diagram of an operating circuit according to an embodiment of the present invention. In this embodiment, the operating circuit 210 includes a selection circuit 211 and a clock signal generating circuit 212. The selection circuit 211 stores different state data SV1 and SV2 corresponding to the load states ST1 and ST2. The selection circuit 211 uses one of the state data SV1 and SV2 as the selected state data in a rotating manner and outputs the selected state data. The clock signal generating circuit 212 is coupled to the selection circuit 211 and the charge pump circuit 120. The clock signal generating circuit 212 responds to the selected state data to provide a corresponding pump-up clock signal corresponding to the selected state data. The duty cycle of the corresponding pumped-up clock signal corresponds to the selected state data. For example, when the selected state data is state data SV1, the clock signal generating circuit 212 provides the pumped-up clock signal PCK1. When the selected state data is state data SV2, the clock signal generating circuit 212 provides the pumped-up clock signal PCK2. The duty cycle of the pumped-up clock signal PCK1 is different from the duty cycle of the pumped-up clock signal PCK2.

In this embodiment, the state data SV1 includes generation parameters related to the pump-up clock signal PCK1. The generation parameters related to the pump-up clock signal PCK1 are, for example, at least one of the frequency, waveform, duration, and duty cycle of the pump-up clock signal PCK1. The state data SV2 includes generation parameters related to the pump-up clock signal PCK2. The generation parameters related to the pump-up clock signal PCK2 are, for example, at least one of the frequency, waveform, duration, and duty cycle of the pump-up clock signal PCK2.

For example, state data SV1 corresponds to load state ST1. State data SV2 corresponds to load state ST2. Load states ST1 and ST2 are switched alternately in a single time interval DT. Therefore, the selection circuit 211, for example, will output state data SV1 first. The clock signal generating circuit 212 responds to state data SV1 to provide a pumped clock signal PCK1. Next, the selection circuit 211 outputs state data SV2. The clock signal generating circuit 212 responds to state data SV2 to provide a pumped clock signal PCK2.

In some embodiments, the operating circuit 210 can alternately provide the pump-up clock signals PCK1 and PCK2 in the dark screen touch mode of the electronic device ED. In some embodiments, the operating circuit 210 can alternately provide the pump-up clock signals PCK1 and PCK2 in the constant display mode of the electronic device ED.

Please refer to FIG. 9, which is a schematic diagram of an operating circuit according to another embodiment of the present invention. In this embodiment, the operating circuit 310 includes a selection circuit 311 and a clock signal generating circuit 312. The selection circuit 311 includes registers REG1, REG2 and a multiplexer circuit MUXC. The register REG1 stores state data SV1. The register REG2 stores state data SV2. The multiplexer circuit MUXC is coupled to the registers REG1 and REG2. The multiplexer circuit MUXC receives the state data SV1, SV2 and the selection signal SS. The multiplexer circuit MUXC responds to the selection signal SS to use one of the state data SV1 and SV2 as the selected state data in a rotating manner. The selection circuit 311 provides the selected state data to the clock signal generating circuit 312. Therefore, the clock signal generating circuit 312 responds to the selected state data to provide a corresponding pumped clock signal corresponding to the selected state data.

In this embodiment, the multiplexer circuit MUXC includes a multiplexer MUX. The first input end of the multiplexer MUX is coupled to the register REG1 to receive the state data SV1. The second input end of the multiplexer MUX is coupled to the register REG2 to receive the state data SV2. The selection end of the multiplexer MUX receives the selection signal SS. The output end of the multiplexer MUX is coupled to the clock signal generating circuit 312. The output end of the multiplexer MUX is used to output the selected state data.

Please refer to FIG. 10, which is a schematic diagram of an operating circuit according to another embodiment of the present invention. In this embodiment, the operating circuit 410 includes a selection circuit 411 and a clock signal generating circuit 412. The selection circuit 411 includes registers REG1, REG2, REG3 and a multiplexer circuit MUXC. Register REG1 stores state data SV1. Register REG2 stores state data SV2. Register REG3 stores state data SV3. The multiplexer circuit MUXC is coupled to registers REG1, REG2, REG3. The multiplexer circuit MUXC receives state data SV1, SV2, SV3 and selection signals SS1, SS2. The multiplexer circuit MUXC responds to the selection signals SS1 and SS2 to use one of the state data SV1, SV2, and SV3 as the selected state data in a rotating manner. The selection circuit 411 provides the selected state data to the clock signal generation circuit 412. Therefore, the clock signal generation circuit 412 responds to the selected state data to provide a corresponding pumped clock signal corresponding to the selected state data. For example, when the selected state data is the state data SV1, the clock signal generation circuit 412 provides the pumped clock signal PCK1. When the selected state data is the state data SV2, the clock signal generation circuit 412 provides the pumped clock signal PCK2. When the selected state data is state data SV3, the clock signal generating circuit 412 will provide the pumped clock signal PCK3. The working cycles of the pumped clock signals PCK1, PCK2, and PCK3 are not exactly the same.

In this embodiment, the multiplexer circuit MUXC includes multiplexers MUX1 and MUX2. The first input end of the multiplexer MUX1 is coupled to the register REG1 to receive the state data SV1. The second input end of the multiplexer MUX1 is coupled to the register REG2 to receive the state data SV2. The selection end of the multiplexer MUX1 receives the selection signal SS1. The first input end of the multiplexer MUX2 is coupled to the output end of the multiplexer MUX1. The second input end of the multiplexer MUX2 is coupled to the register REG3 to receive the state data SV3. The selection end of the multiplexer MUX1 receives the selection signal SS2. The output end of the multiplexer MUX2 is coupled to the clock signal generating circuit 412. The output end of the multiplexer MUX2 is used to output the selected state data.

Please refer to FIG. 1 and FIG. 11 at the same time. FIG. 11 is an operation flow chart according to an embodiment of the present invention. In this embodiment, the electronic device ED enters a specific mode in step S101. The specific mode can be one of a dark screen touch mode and a constant display mode. In step S102, in the specific mode, the operating voltage supply circuit 100 will determine the rotation mode of multiple load states. Further, based on the specific mode, the operating voltage supply circuit 100 selects at least two load states and arranges the rotation mode of the load states. In step S103, the operating voltage supply circuit 100 will determine the current load state. Taking the present embodiment as an example, the operating circuit 110 selects the load states ST1 and ST2, and arranges the load state ST1 as the priority load state (the present invention is not limited to this). Therefore, the operating circuit 110 provides a pump-up clock signal PCK1 having a first working cycle in step S104. In step S105, the operating voltage supply circuit 100 operates based on the load state ST1. Further, the charge pump circuit 120 provides the operating voltage VSP based on the first working cycle of the pump-up clock signal PCK1. In step S106, the operating voltage supply circuit 100 determines whether the load state ST1 ends. For example, the load state ST1 has an operating time length. When the running time length of the load state ST1 has not reached the preset time length, the operating voltage supply circuit 100 will determine that the load state ST1 has not ended. Therefore, the operating circuit 110 will return to the operation of step S104. On the other hand, when the running time length of the load state ST1 reaches the preset time length, the operating voltage supply circuit 100 will determine that the load state ST1 has ended. Therefore, the operating circuit 110 will return to the operation of step S102.

When the load state ST1 ends, the operating circuit 110 determines in step S103 that the current load state is the load state ST2. Therefore, the operating circuit 110 provides a pump-up clock signal PCK2 having a second working cycle in step S107. In step S108, the operating voltage supply circuit 100 operates based on the load state ST2. Further, the charge pump circuit 120 provides the operating voltage VSP based on the second working cycle of the pump-up clock signal PCK2. In step S109, the operating voltage supply circuit 100 determines whether the load state ST2 ends. For example, the load state ST2 has an operating time length. When the running time length of the load state ST2 has not reached the preset time length, the operating voltage supply circuit 100 will determine that the load state ST2 has not ended. Therefore, the operating circuit 110 will return to the operation of step S107. On the other hand, when the running time length of the load state ST2 reaches the preset time length, the operating voltage supply circuit 100 will determine that the load state ST2 has ended. Therefore, the operating circuit 110 will return to the operation of step S102. When the load state ST2 ends, the operating circuit 110 will determine in step S103 that the current load state is the load state ST1.

Please refer to Figure 1 and Figure 12 at the same time. Figure 12 is an operation flow chart drawn according to another embodiment of the present invention. In this embodiment, the electronic device ED enters a specific mode in step S201. The specific mode can be at least one of a dark screen touch mode and a constant display mode. In step S202, in the specific mode, the operating voltage supply circuit 100 will determine the rotation method of multiple load states. Further, based on the specific mode, the operating voltage supply circuit 100 selects multiple load states and arranges the rotation method of the load state. In step S203, the operating voltage supply circuit 100 will determine the current load state. Taking the present embodiment as an example, the operating circuit 110 selects the load states ST1, ST2, and ST3, and arranges the load state ST1 as the priority load state (the present invention is not limited to this). Therefore, the operating circuit 110 provides a pump-up clock signal PCK1 having a first working cycle in step S204. In step S205, the operating voltage supply circuit 100 operates based on the load state ST1. The charge pump circuit 120 provides the operating voltage VSP based on the first working cycle of the pump-up clock signal PCK1. In step S206, the operating voltage supply circuit 100 determines whether the load state ST1 ends. When the operating voltage supply circuit 100 determines that the load state ST1 has not ended, the operating circuit 110 returns to the operation of step S204. On the other hand, when the operating voltage supply circuit 100 determines that the load state ST1 has ended, the operating circuit 110 returns to the operation of step S202. The determination method of step S206 has been clearly explained in the implementation content of step S106, so it will not be repeated here.

When the load state ST1 ends, the operating circuit 110 determines in step S203 that the current load state is the load state ST2. Therefore, the operating circuit 110 provides a pump-up clock signal PCK2 having a second working cycle in step S207. In step S208, the operating voltage supply circuit 100 operates based on the load state ST2. The charge pump circuit 120 provides the operating voltage VSP based on the second working cycle of the pump-up clock signal PCK2. In step S209, the operating voltage supply circuit 100 determines whether the load state ST2 ends. When the operating voltage supply circuit 100 determines that the load state ST2 has not ended, the operating circuit 110 returns to the operation of step S207. On the other hand, when the operating voltage supply circuit 100 determines that the load state ST2 has ended, the operating circuit 110 returns to the operation of step S202.

When the load state ST2 ends, the operating circuit 110 determines in step S203 that the current load state is the load state ST3. Therefore, the operating circuit 110 provides a pump-up clock signal PCK3 having a third working cycle in step S210. In step S211, the operating voltage supply circuit 100 operates based on the load state ST3. The charge pump circuit 120 provides the operating voltage VSP based on the third working cycle of the pump-up clock signal PCK3. In step S212, the operating voltage supply circuit 100 determines whether the load state ST3 ends. When the operating voltage supply circuit 100 determines that the load state ST3 has not ended, the operating circuit 110 returns to the operation of step S210. On the other hand, when the operating voltage supply circuit 100 determines that the load state ST3 has ended, the operating circuit 110 returns to the operation of step S202.

Please refer to Figure 1 and Figure 13 at the same time. Figure 13 is a schematic diagram and a state diagram of the load state and the working cycle of the pump-up clock signal drawn according to another embodiment of the present invention. In this embodiment, the specific mode can be a combination of a dark screen touch mode and a constant display mode. In this embodiment, the constant display mode includes a display scanning state and a display idle state. The dark screen touch mode includes a touch idle state and a touch sensing state. Since the state cycle of the dark screen touch mode (e.g., 0.032 seconds) is different from the state cycle of the constant display mode (e.g., 0.064 seconds), the combined mode will include three load states ST1, ST2, and ST3. In this embodiment, when the display scanning state and the touch idle state occur, the operating voltage supply circuit 100 operates in the load state ST1. When the display scanning state and the display idle state occur, the operating voltage supply circuit 100 operates in the load state ST2. In addition, when the touch idle state and the display idle state occur, the operating voltage supply circuit 100 operates in the load state ST3.

As shown in FIG. 13, the state sequence is carried out in the order of load state ST1, load state ST2, load state ST3, load state ST1, load state ST3, load state ST2... Based on the change of the state sequence of the dark screen touch mode and the constant display mode, the order of load states ST1~ST3 will also change accordingly. The order of load states ST1~ST3 of the present invention is not limited to this embodiment.

In this embodiment, the operating circuit 110 provides a pump-up clock signal PCK1 in the load state ST1. The pump-up clock signal PCK1 has a duty cycle DTC1. The operating circuit 110 provides a pump-up clock signal PCK2 in the load state ST2. The pump-up clock signal PCK2 has a duty cycle DTC2. The operating circuit 110 provides a pump-up clock signal PCK3 in the load state ST3. The pump-up clock signal PCK3 has a duty cycle DTC3. For example, the duty cycle DTC1 is 25%. The duty cycle DTC2 is 50%. The duty cycle DTC3 is 12.5%. Therefore, the power consumption of the charge pump circuit 120 in the load states ST1 and ST3 can be intermittently reduced. For another example, the duty cycle DTC1 is 50%. The duty cycle DTC2 is 50%. The duty cycle DTC3 is 12.5%. Therefore, the power consumption of the charge pump circuit 120 in the load state ST3 can be intermittently reduced. In this embodiment, the duty cycles DTC1, DTC2, and DTC3 are not exactly the same. The duty cycles DTC1, DTC2, and DTC3 can be different from each other. Any two of the duty cycles DTC1, DTC2, and DTC3 can be the same.

This embodiment can be applied to the operation flow chart shown in Figure 12.

In summary, the operating cycle of the pump-up clock signal provided by the operating circuit of the operating voltage supply circuit under different multiple load states is not exactly the same. The multiple load states are switched alternately in a single time interval. The multiple power consumptions of the multiple load states are different from each other. In this way, the power consumption of the operating voltage supply circuit can be intermittently reduced in a single time interval.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

100: Operating voltage supply circuit

110: Operation circuit

120: Charge pump circuit

DT: Time Zone

ED: Electronic devices

PCK1, PCK2: pump up pulse signal

ST1, ST2: Load status

VSP: operating voltage

Claims (12)

An operating voltage supply circuit includes: an operating circuit configured to provide a plurality of pump-up clock signals under different multiple load states; and a charge pump circuit coupled to the operating circuit, configured to receive the multiple pump-up clock signals and provide an operating voltage based on a duty cycle of the received pump-up clock signals, wherein the multiple load states are switched alternately in time intervals of different load states, wherein the multiple pump-up clock signals provided under the multiple load states in a specific mode are switched alternately in time intervals of different load states. The multiple duty cycles of the signal are not completely the same, wherein the multiple load states include a first load state and a second load state, and the operating circuit provides a first pump-up clock signal with a first duty cycle in the first load state, and provides a second pump-up clock signal with a second duty cycle in the second load state, wherein the power consumption of the first load state is greater than the power consumption of the second load state, and the first duty cycle is greater than the second duty cycle. An operating voltage supply circuit as described in claim 1, wherein: the multiple load states also include a third load state, and the operating circuit provides a third pump-up clock signal with a third working cycle under the third load state. An operating voltage supply circuit as described in claim 1, wherein the first operating cycle is substantially equal to 50%. An operating voltage supply circuit as described in claim 1, wherein the duration of the first load state is shorter than the duration of the second load state. An operating voltage supply circuit as described in claim 1, wherein the operating circuit provides a first charging clock signal under the first load state and provides a second charging clock signal under the second load state. An operating voltage supply circuit as described in claim 5, wherein the charge pump circuit comprises: a capacitor; a first switch, wherein a first end of the first switch receives a charging voltage, a second end of the first switch is coupled to the first end of the capacitor, a control end of the first switch receives the first charging clock signal under the first load state and receives the second charging clock signal under the second load state; a second switch, wherein a first end of the second switch receives a reference low voltage, a second end of the second switch is coupled to the second end of the capacitor, a control end of the second switch receives the first charging clock signal under the first load state and receives the second charging clock signal under the second load state. a third switch, wherein the first end of the third switch is coupled to the first end of the capacitor, the second end of the third switch is used to output the operating voltage, the control end of the third switch receives the first pump-up clock signal under the first load state and receives the second pump-up clock signal under the second load state; and a fourth switch, wherein the first end of the fourth switch is coupled to the second end of the capacitor, the second end of the fourth switch receives the first regulating voltage, the control end of the fourth switch receives the first pump-up clock signal under the first load state and receives the second pump-up clock signal under the second load state. An operating voltage supply circuit as described in claim 6, wherein the charge pump circuit further comprises: a voltage regulating circuit coupled to the second end of the fourth switch, configured to provide the first regulating voltage based on a reference voltage. An operating voltage supply circuit as described in claim 5, wherein the operating circuit comprises: a capacitor; a first switch, wherein a first end of the first switch receives a charging voltage, a second end of the first switch is coupled to the first end of the capacitor, a control end of the first switch receives the first charging clock signal in the first load state and receives the second charging clock signal in the second load state; a second switch, wherein a first end of the second switch receives a reference low voltage, a second end of the second switch is coupled to the second end of the capacitor, a control end of the second switch receives the first charging clock signal in the first load state and receives the second charging clock signal in the second load state receiving the second charging clock signal; a third switch, wherein the first end of the third switch is coupled to the first end of the capacitor, the second end of the third switch receives the first regulating voltage, the control end of the third switch receives the first pump-up clock signal under the first load state and receives the second pump-up clock signal under the second load state; and a fourth switch, wherein the first end of the fourth switch is coupled to the second end of the capacitor, the second end of the fourth switch is used to output the operating voltage, the control end of the fourth switch receives the first pump-up clock signal under the first load state and receives the second pump-up clock signal under the second load state. An operating voltage supply circuit as described in claim 1, wherein the operating circuit comprises: a selection circuit configured to store a plurality of different state data corresponding to the plurality of load states, to use one of the plurality of state data as selected state data in a rotating manner, and to output the selected state data; and a clock signal generating circuit coupled to the selection circuit and the charge pump circuit, configured to respond to the selected state data to provide a corresponding pump-up clock signal corresponding to the selected state data, wherein the duty cycle of the corresponding pump-up clock signal corresponds to the selected state data. An operating voltage supply circuit as described in claim 9, wherein the selection circuit comprises: a plurality of registers, each configured to store one of the plurality of state data; and a multiplexer circuit, coupled to the plurality of registers and the clock signal generating circuit, configured to receive the plurality of state data and a selection signal, and in response to the selection signal, to select one of the plurality of state data as the selected state data in an alternating manner. An operating voltage supply circuit as described in claim 1, wherein the specific mode is a standby mode. An operating voltage supply circuit as described in claim 11, wherein the standby mode includes at least one of a dark screen touch mode and a permanent display mode.

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