JP2003088103A - Charge pump system power circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge pump system power circuit capable of reducing power consumption, being miniaturized, and improving responsibility, by setting optimum voltage boost for generating a drive voltage and by increasing voltage boosting steps when a load current increases. SOLUTION: This circuit has a load fluctuation detecting circuit 7 that uses the voltage-boosting output of a charge pump system voltage-boosting circuit 1 and the load current detection voltage from a drive voltage generation circuit 4 as inputs; as optimum voltage-boosting step detecting circuit 8 that uses an input voltage Vcc of the charge pump system voltage-boosting circuit 1, and a voltage 1/2Vo corresponding to the drive voltage Vo from the drive voltage generating circuit 4 as inputs; and a voltage-boosting step setting circuit 9 that sets the number of the voltage-boosting steps of the charge pump system voltage-boosting circuit 1, in accordance with the output for the number of voltage-boosting steps of the optimum voltage-boosting step detecting circuit 8 and the output of the load fluctuation detecting circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump type power supply circuit, and more particularly to a charge pump type power supply circuit for driving a liquid crystal.

[0002]

2. Description of the Related Art At present, an LCD display device as a portable terminal occupies an important position and is required to have low power consumption, downsizing and high speed response. The LCD display device is composed of a liquid crystal driving power supply circuit, a source driver and a gate driver, and power is supplied to the source driver and the gate driver by the liquid crystal driving power supply circuit.

Since the liquid crystal driving power source requires a high voltage, the power source supplied from a battery or the like is boosted using a charge pump type booster circuit to be used as the liquid crystal driving power source. The output impedance of a normally used charge pump type booster circuit changes depending on the boosting clock frequency, and the higher the frequency, the smaller the output impedance. However, the higher the frequency, the more the current consumption tends to increase. Even if the frequency is increased, the output impedance cannot be set to 0Ω, so as the load increases, boosted output HV _CC
Will decrease. Since the LCD display device tends to change the load current according to the image pattern to be displayed, it is necessary to set the boosted output voltage with a margin so that the drive voltage V _O does not decrease.

FIG. 21 shows a charge pump type power supply circuit for driving a liquid crystal in the prior art. Boosting the V _CC voltage input to the charge pump type booster circuit 1 to the boosting capacitor Ch connected to the output terminal of the charge pump type booster circuit 1 at the cycle of the boosting clock CK input to the charge pump type booster circuit 1. in outputting the boosted output HV _CC, to drive the load RL of the liquid crystal driver by boosting output HV _CC capacitor driving voltage stabilization from the drive voltage generating circuit 4 to supply a C _O is connected to liquid crystal drive voltage V _O .

FIG. 22 shows the rising characteristics of the boosted output HV _CC and the drive voltage V _O when the power is turned on in the prior art. In the prior art, since the number of boosting stages is fixed, the drive voltage V _O gradually increases from the time when V _CC is input as shown in FIG. 22, so that the liquid crystal drive voltage V _O is normally output. Time T1 was long.

A case where the load on the liquid crystal drive voltage V _O is increased will be described with reference to FIG. FIG. 23 is a waveform when the load current to the liquid crystal drive voltage V _O in the conventional example increases, but as the load current increases, the boosted output HV _CC decreases due to the output impedance of the charge pump type booster circuit, The liquid crystal drive voltage V _O drops during the period T4 when the boosted output HV _CC becomes lower than the normal liquid crystal drive voltage V _O.

[0007]

As described above, in the prior art, the time T until the liquid crystal drive voltage V _O is normally output is T.
1 becomes longer, and the liquid crystal drive voltage V _O decreases during the period T4.

Therefore, an object of the present invention is to solve such a problem, to set the optimum boosting for generating the drive voltage, and to increase the number of boosting stages when the load current increases, which results in low power consumption and small size. It is an object of the present invention to provide a charge pump type power supply circuit that can improve performance and response.

[0009]

The features of the present invention include an input voltage and drive voltage generating circuit for a charge pump type booster circuit,
Preferably, it has an optimum booster stage number detection circuit that receives a voltage corresponding to the drive voltage from the liquid crystal drive voltage generation circuit as an input,
A charge pump type power supply circuit having a boost stage number setting circuit for setting the boost stage number of the charge pump type boost circuit according to the boost stage number output of the optimum boost stage number detection circuit.

Another feature of the present invention is that a boosted output of a charge pump booster circuit and a drive voltage generation circuit, preferably a load fluctuation detection circuit to which a load current detection voltage from a liquid crystal drive voltage generation circuit is input, An optimum booster stage number detection circuit having an input voltage of the charge pump type booster circuit and a voltage corresponding to the drive voltage from the drive voltage generation circuit as an input, and the booster stage number output of the optimum boost stage number detection circuit is detected as the load variation. A charge pump type power supply circuit having a boost stage number setting circuit for setting the number of boost stages of the charge pump type boost circuit according to the output of the circuit.

Here, the load current detection voltage may be supplied to the load variation detection circuit from the gate of the drive transistor of the drive voltage generation circuit. Alternatively, a resistor may be provided between the boosted output and the source of the driving transistor of the drive voltage generation circuit, and the load current detection voltage may be supplied to the load variation detection circuit from between the source and the resistor.

Another feature of the present invention is that the voltage input to the charge pump type booster circuit at the period of the booster clock input to the booster stage number setting circuit is applied to the booster capacitor connected to the output terminal of the charge pump type booster circuit. A liquid crystal drive charge pump system power supply circuit that drives a liquid crystal driver with a liquid crystal drive voltage to which a drive voltage stabilization circuit is connected from a drive voltage generation circuit that outputs boosted output by boosting A load fluctuation detection circuit for detecting a load fluctuation by comparing a boosted output of a charge pump type booster circuit and a load fluctuation detection voltage created by a drive voltage generation circuit; and an input voltage of the charge pump type booster circuit and the drive voltage generation circuit It has an optimal booster stage number detection circuit that detects the optimal booster stage number by comparing the liquid crystal drive voltage from In charge pump power supply circuit for driving liquid crystal having a booster stages setting circuit for controlling the boosting stages of the charge pump booster circuit according to the output of the boosting stages output the load variation detecting circuit of the circuit.

[0013]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings. 1 is a circuit diagram showing a charge pump power supply circuit according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing a charge pump power supply circuit according to a second embodiment of the present invention. FIG. 3 is a circuit diagram showing a charge pump type power supply circuit according to a third embodiment of the present invention. The charge pump type power supply circuit of these embodiments is a charge pump type power supply circuit for driving a liquid crystal.

First, in the circuit diagram showing the charge pump type power supply circuit of the first embodiment, V _CC inputted to the charge pump type booster circuit 1 at the cycle of the boosting clock CK inputted to the boost stage number setting circuit 9. The boosted output HV _CC is output by boosting the voltage to the boosting capacitor Ch connected to the output terminal of the charge pump type booster circuit 1, and the drive voltage is stabilized from the liquid crystal drive voltage generation circuit 4 using the boosted output HV _CC as a power source. In a liquid crystal drive charge pump type power supply circuit for driving a load RL of a liquid crystal driver with a liquid crystal drive voltage V _O to which a drive capacitor C _O is connected, a reference voltage 3 is applied to a negative feedback terminal and resistors R1 and R2 are applied to a positive feedback terminal. an error AMP intersection is connected to the output gate of the error AMP, source boosted output HV _CC, P for driving the drain connected to the resistor R3 consists of a h transistor Q1, the drain and the liquid crystal drive voltage V _O from the intersection of the resistor R3 of the driving Pch transistor Q1, a 1 / 2V _O voltage connection from the intersection of the resistors R2 R3 optimum booster stage number detection circuit 8 , The load variation detection voltage VA from the drive voltage generation circuit 4 output from the intersection of the output of the error AMP and the gate and the boosted output HV _{CC of the} charge pump type booster circuit 1 are compared, and the liquid crystal drive voltage V _{O is changed} to the liquid crystal driver RL. Load fluctuation consumed by the load fluctuation detection circuit 7 is detected, and the detection result D1
~ D4 is output to the boost stage number setting circuit 9.

On the other hand, the input voltage V _{CC of the} charge pump type booster circuit 1 and the 1/2 V _O voltage output from the intersection of the resistors R2 and R3 in the drive voltage generation circuit 4 are input to the optimum booster stage number detection circuit 8. Then, the optimum booster stage number for generating the liquid crystal drive voltage V _O is detected, and the detection results B1 to B5 are output to the booster stage number setting circuit 9.

Further, the booster stage number setting circuit 9 switches SW1 to SW25 to the charge pump type booster circuit 1 at the cycle of the booster clock CK input to the booster stage number setting circuit 9 according to the detection result from the optimum booster stage number detection circuit 8. Control and set the number of boosting stages.

Next, the operation of the charge pump type power supply circuit shown in FIG. 1 will be described. In FIG. 1, the V _CC voltage input to the charge pump type booster circuit 1 at the cycle of the booster clock CK input to the booster stage number setting circuit 9 is supplied to the booster capacitor Ch connected to the output terminal of the charge pump type booster circuit 1. A boosted output HV _CC is output by boosting.

The operation of the charge pump type booster circuit will be described with reference to FIGS. FIG. 14 shows a commonly used charge pump type booster circuit having a boosting capacity of 9 times. Assuming that the high period of the boosting clock CK input to the boosting stage number setting circuit 9 is the charging period, as shown in FIG. 15, SW2, 3, 5, 6, 8,
9, 11, 12, 14, 15, 17, 18, 20, 2
1, 23 and 24 are turned on to charge the capacitors C1 to C8 with the V _CC voltage.

Next, assuming that the Low period of the boosting clock CK is the boosting period, as shown in FIG.
Turn on 7,10,13,16,19,22,25, C
The charges charged in the capacitors 1 to C8 are discharged to the boost capacitor Ch, and the voltage H across the boost capacitor Ch is increased.
Increase V _CC .

Normally, the charge to the boost capacitor Ch is not boosted by one charge / discharge, and the boost clock CK is performed several tens of times.
It is necessary to charge and discharge by inputting.

When boosting by a factor of 5, boosting clock C
The high period of K is SW1 as shown in FIG.
1, 12, 14, 15, 17, 18, 20, 21, 21
3, 24 are turned on, the capacitors C1 to C3 are not charged, and the capacitors C4 to C8 are charged with the V _CC voltage,
During the Low period of the boosting clock CK, SW11, 13, 16, 19, 22, 25 are turned on as shown in FIG.
Then, the charges charged in the capacitors C4 to C8 are discharged to the boosting capacitor Ch to charge the boosting capacitor Ch.

The liquid crystal drive voltage generation circuit 4 has a boosted HV.
A liquid crystal drive voltage V _O that drives the load RL of the liquid crystal driver by amplifying the reference voltage 3 with R1 to R3 using the _CC voltage as a power supply.
And a 1 / 2V _O voltage to be supplied to the optimum booster stage number detection circuit 8 is generated. Here, when the reference voltage 3 is VREF, the liquid crystal drive voltage V _O is determined by V _O = VREF × (R1 + R2 + R3) / R1. A drive voltage stabilizing capacitor C _O and a load RL of the liquid crystal drive driver are connected to the liquid crystal drive voltage V _O end. On the other hand, 1 / supplied to the optimum booster stage number setting circuit 8
The 2V _O voltage is determined by 1 / 2V _O = VREF × (R1 + R2) / R1, and when R2 = R3-R1 is set, V _O = VREF × (R1 + R2 + R3) / R1 = VRE
F × 2 × R3 / R1 1 / 2V _O = VREF × (R1 + R2) / R1 = VRE
F × R3 / R1 and the 1 / 2V _O voltage becomes 1/2 of the liquid crystal drive voltage V _O.

Next, the optimum booster stage number setting circuit 8 of the present invention will be described with reference to FIG. In the optimum booster stage number setting circuit 8, a voltage equivalent to ½ V _CC is created by dividing the V _CC which is the input voltage to the charge pump type booster circuit 1 by resistance division, and with this voltage as a reference, 3/2 V _CC , 4/2 V _CC , 5 /
A voltage equivalent to 2V _CC , 6 / 2V _CC , and 7 / 2V _CC is created.

Here, R6 = R5, R8 = 2 × R7, R9
= R10 = R11 = R12 = R7, 1 / 2V_CC= V_CC× R5 / (R5 + R6) = V_CC× 1 /
Two 3 / 2V_CC= 1/2 x V_CC× (R7 + R8) / R7 = V
_CC× 3/2 4 / 2V_CC= 1/2 x V_CC× (R7 + R8 + R9) / R
7 = V_CC× 4/2 5 / 2V_CC= 1/2 x V_CCX (R7 + R8 + R9 + R1
0) / R7 = V_CC× 5/2 6 / 2V_CC= 1/2 x V_CCX (R7 + R8 + R9 + R1
0 + R11) / R7 = V _CC× 6/2 7 / 2V_CC= 1/2 x V_CCX (R7 + R8 + R9 + R1
0 + R11 + R12) / R7 = V_CC× 7/2 And created with each of these voltages and drive voltage generation circuit 4
1 / 2V, which is equivalent to 1/2 of the liquid crystal drive voltage_O And ratio
If the comparison results are B1, B2, B3, B4, B5,
1 / 2V_CCVoltage and 3 / 2V_CC4 / 2V_CC5/2
V_CC, 6 / 2V_CC, 7 / 2V_CCDepending on the voltage, 1 / 2V_O <3 / 2V_CCHour = V_O <3V_CCTime: B1 =
H, B2 = H, B3 = H, B4 = H, B5 = H 3 / 2V_CC≤ 1 / 2V_O <4 / 2V_CCHour = 3V_CC≤ V_O 
<4V_CCTime: B1 = L, B2 = H, B3 = H, B4 =
H, B5 = H 4 / 2V_CC≤ 1 / 2V_O <5 / 2V_CCHour = 4V_CC≤ V_O 
<5V_CCTime: B1 = L, B2 = L, B3 = H, B4 =
H, B5 = H 5 / 2V_CC≤ 1 / 2V_O <6 / 2V_CCHour = 5V_CC≤ V_O 
<6V_CCTime: B1 = L, B2 = L, B3 = L, B4 =
H, B5 = H 6 / 2V_CC≤ 1 / 2V_O <7 / 2V_CCHour = 6V_CC≤ V_O 
<7V_CCTime: B1 = L, B2 = L, B3 = L, B4 =
L, B5 = H 7 / 2V_CC≤ 1 / 2V_O Hour = 7V_CC≤ V_O Time: B1 =
L, B2 = L, B3 = L, B4 = L, B5 = L Becomes

Here, 1 / 2V _O voltage and 3 / 2V _CC , 4
Hysteresis is provided in each comparator that compares the / 2V _CC , 5 / 2V _CC , 6 / 2V _CC , and 7 / 2V _CC voltages so that the number of boosting stages does not change even if the V _CC voltage or the drive voltage V _O changes slightly. That is also effective. This B1, B2, B3,
Boosting patterns P1 and P according to the output results of B4 and B5
2, P3, P4, P5, P6 and boosting modes D1, D2, D3, D4 from the maximum boosting stage number to the optimum boosting stage number are set as shown in FIG. That is, V _CC = 3v, drive voltage V
Assuming that _O = 12v, V _O = 4V _CC , so the boosting pattern P3 is selected from the table of FIG. 5, and the optimal boosting stage number D4 is 5 times = 5 × 3v = 15v, and the optimal boosting stage number is 5 times. It means that it is detected.

Similarly, V _CC = 2v, 3v, 4v, 5v, V
FIG. 6 shows a boosting pattern when _O = 10 v, 12 v, and 15 v. The voltage shown in parentheses in FIG. 6 is a voltage value when the V _CC voltage is boosted. It can be seen from D4 in FIG. 6 that the optimum number of boosting stages at each input voltage is set. As a result, even if the V _CC voltage input to the charge pump type booster circuit 1 changes, the optimum number of boosting stages is set, excessive boosting is not performed, power consumption is reduced, and the charge pump type The breakdown voltage of the booster circuit can be protected.

Next, the load fluctuation detecting circuit 7 of the present invention will be described with reference to FIG. Driving Pch transistor Q1
The output voltage HV _CC of the charge pump type booster circuit 1 is divided by resistance in accordance with the characteristics of V1, V2, and V3 voltage, and the gate voltage VA of the drive Pch transistor Q1 in the drive voltage generation circuit 4 is compared. Then, assuming that the results are E1, E2, and E3, respectively, V1, V2, and V3 voltages and VA
Depending on the relationship with the voltage, V1 ≦ VA: E1 = H, E2 = H, E3 = H V2 ≦ VA <V1: E1 = L, E2 = H, E3 = H V3 ≦ VA <V2: E1 = L, When E2 = L, E3 = H VA <V3: E1 = L, E2 = L, E3 = L. Here, a hysteresis is provided in each comparator that compares the V1, V2, V3 voltage with the VA voltage, and even if the VA voltage or the boosted output HV _CC slightly changes, the comparison results E1, E2,
It is also effective to prevent the logic of E3 from changing.
Depending on the output results of the comparison results E1, E2, E3, the boosting modes D1, D2, D3, D4 are set to E1 = H, E2 = H, E3 = H: D1 = L, D2 =
L, D3 = L, D4 = H E1 = L, E2 = H, E3 = H: D1 = L, D2 =
L, D3 = H, D4 = L E1 = L, E2 = L, E3 = H: D1 = L, D2 =
H, D3 = L, D4 = L E1 = L, E2 = L, E3 = L: D1 = H, D2 =
It is set by a combination of E1, E2, E3 such as L, D3 = L, D4 = L. FIG. 9 shows this as a table. The boosting modes D1, D2, D3, D4 set here are boosting modes D1, D2, D in FIG. 5 detected by the optimum boosting stage number setting circuit 8.
Equivalent to 3, D4.

Next, the booster stage number setting circuit 9 will be described with reference to FIG. 10, the detection results B1 to B5 of the optimum booster stage number setting circuit 8 and the booster clock CK input to the booster stage number setting circuit 9 are combined to obtain the booster stage number corresponding to the optimum booster stage number detection result shown in FIG. In this way, after connecting to the switches D1 to D4 that switch according to the detection results E1 to E3 from the load variation detection circuit 7 to pass the level shift LS, the control of SW1 to SW25 is performed.
Here, SW1 to SW25 to be turned on according to each number of boosting stages
Is shown in FIG. For example, when 1 / 2V _O <3 / 2V _CC = V _O <3V _CC : B1 =
When H, B2 = H, B3 = H, B4 = H, B5 = H and E1 = H, E2 = H, E3 = H: DI = L, D2 =
When L, D3 = L, D4 = H, the number of boosting stages is 3 so that charge / discharge is performed at three stages SW17, 18, 20, 2 when the boosting clock CK is High.
1, 23 and 24 are turned on and V _{CC is} applied to each capacitor of C6 to C8.
The voltage is charged. When the boost clock CK is Low, S
When W17, 19, 22, and 25 are turned on, the electric charges charged in the capacitors C6 to C8 are discharged to the boosting capacitor Ch to charge the boosting capacitor Ch. As a result, the boost capacitor Ch is charged with three times the charge of the V _CC voltage, and the boost output HV _CC outputs a voltage of 3 V _CC .

Further, 3 / 2V _CC ≤1 / 2V _O <4 / 2V
_CC at the time _{= 3V CC ≦ V O <4V} CC at the time: B1 = L, B2 = H ,
B3 = H, B4 = H, B5 = H and E1 = H, E2 =
When H, E3 = H: D1 = L, D2 = L, D3 = L, D4
When the boosting clock CK is high, SW14, 15, 1
7,18,20,21,23,24 turn on, C5 ~ C
Each capacitor of 8 is charged with the V _CC voltage. SW14, 16, 19, 22, 25 when boosting clock CK is Low
Is turned on, the electric charges charged in the capacitors C5 to C8 are discharged to the boosting capacitor Ch, and the boosting capacitor Ch is charged. As a result, the boost capacitor Ch has V _CC
4 times the voltage is charged and the boosted output HV _CC is 4 V _CC
Is output.

Next, the operation when the power is turned on will be described.
FIG. 19 shows the rising characteristics of the boosted output HV _CC and the drive voltage V _O when the power is turned on. When the power is turned on, the drive voltage V _O increases the load current required to charge the drive voltage stabilizing capacitor 5, so the gate voltage V _O of the drive Pch transistor in the drive voltage generation circuit 4 is increased.
A has a potential equal to or lower than the V3 voltage. After that, since the load current decreases as the drive voltage V _O rises, the VA voltage rises and then stabilizes. Since the V1, V2, and V3 voltages are resistance divisions of the boosted output HVcc, they rise following HVcc.

As a result of comparing the VA voltage with the V1, V2, and V3 voltages, the period of T1 is VA <V3, and E1, E2, E
3 becomes Low output. Similarly, during the period from T1 to T2, V3 ≦ VA <V2, and E1, E2, and E3 are respectively
Low, Low, High output, V2 ≤ VA <V1 during the period from T2 to T3, E1, E2, E3 become Low, High, High output respectively, and V1 ≤ VA during the period after T3, E1, E2, E3. Are High, High, and High output, respectively. As a result, as shown in FIG. 9, the boosting modes in the periods T1, T2, T3, and T4 are set to D1, D2, D3, and D4, respectively. On the other hand, since the 3 / 2V _{CC to} 7 / 2V _CC voltage generating circuit in the optimum boost stage number setting circuit 8 uses HV _CC as a power source, the waveforms of 3 / 2V _{CC to} 7 / 2V _CC are shown in FIG.
Increases to follow the HV _CC and so on. Further, when the relationship between the liquid crystal drive voltage V _O and V _CC is V _O = 5V _CC , FIG.
Therefore, the boosting pattern P4 is selected.

From the above results, during the period of T1, VA <V
3 o'clock: E1 = L, E2 = L, E3 = L, then D1 = H and
5V_CC≤V_O <6V_CCTime: B1 = L, B2 = L, B3 =
L, B4 = H, B5 = H, and the number of boosting stages is 9 from FIG.
Double. Similarly, the period of T2-T1 is D2 = 8 times, T2
3-D2 = 7 times during the period T2, D4 = after the period T3
Since the charge pump type booster circuit is boosted by 6 times,
Boost output HV_CCRises faster and, as a result, the liquid crystal
Drive voltage V_O The rising time T3 of is shortened. Also, the liquid
Crystal drive voltage V _O When there is no load on the stable state,
Boosted output HV of charge pump booster circuit 1_CCIs the liquid
Crystal drive voltage V_O Is set to the minimum booster stage number D4 that can output
Therefore, the power consumption during idling can be reduced. Well
In addition, V that is the reference power source of the charge pump type booster circuit_CC
Even if the voltage increases or decreases, the drive voltage V_O Minimum boost that can output
Set to the number of steps.

Next, the case where the load on the liquid crystal drive voltage V _O is increased will be described. FIG. 20 shows a waveform when the load on the liquid crystal drive voltage V _O increases. LCD drive voltage V _O
The load current of the load RL of the liquid crystal drive driver connected to is supplied from the boosted output HV _CC of the charge pump type booster circuit through the drive Pch transistor in the drive voltage generation circuit 4, and therefore, to the liquid crystal drive voltage V _O. When the load increases, the boosted output HV _CC decreases due to the output impedance of the charge pump type booster circuit, and at the same time, the gate voltage V of the driving Pch transistor, which is the load current detection voltage, decreases.
A decreases. In the load change detection circuit 7, V is V during the period of T5.
Since 1 <VA, the boost mode D4 is selected, and during the period of T6, V2 <VA <V1, and therefore the boost mode D3 is selected. At the same time as the load current of the load RL of the liquid crystal drive driver disappears, the VA voltage rises and V1 <VA, so T7.
During the period of, the boost mode D4 is selected. As described above, the load change detection circuit 7 detects that the gate voltage VA of the driving Pch transistor has dropped, and the boost stage number setting circuit controls so as to increase the boost stage number of the charge pump type boost circuit. As a result, the number of boosting stages of the charge pump type booster circuit is increased, and the boosted output HV is increased.
_CC rises, and the drive voltage V _O is output stably.

Next, a charge pump type power supply circuit according to a second embodiment of the present invention will be described with reference to FIG.

In the first embodiment, the load current detection voltage is supplied to the drive Pch transistor Q1 in the drive voltage generation circuit 4.
2 is supplied to the load change detection circuit 7 from the gate voltage VA, the boosted output HV is supplied in the second embodiment shown in FIG.
_A resistor R4 is inserted between the _CC and the source of the driving Pch transistor, and the voltage between the source and the resistor of the driving Pch transistor is supplied to the load variation detection circuit 7 as a load current detection voltage. The operations of the charge pump type booster circuit 1, the optimum booster stage number detection circuit 8, and the booster stage number setting circuit 9 are the same as those in the first embodiment.

Next, the load fluctuation detecting circuit 7 of the present invention will be described with reference to FIG. Drive voltage generation circuit 4 and V1, V2, and V3 voltages created by resistance-dividing output voltage HV _CC of charge pump type booster circuit 1 according to load current characteristics.
The source voltage VA of the driving Pch transistor Q1 is compared with each other, and assuming that the results are E1, E2, and E3, respectively, depending on the relationship between the V1, V2, and V3 voltages and the VA voltage, when V1 ≦ VA: E1 = H, E2 = H, E3 = H When V2 ≦ VA <V1: E1 = L, E2 = H, E3 = H V3 ≦ VA <V2: E1 = L, E2 = L, E3 = H VA <V3: E1 = L, E2 = L, E3 = L. Here, each comparator for comparing the V1, V2, and V3 voltages with the VA voltage is provided with hysteresis to provide the VA voltage,
Even if the high-voltage output HV _CC fluctuates to some extent, the comparison results E1, E2,
It is also effective to prevent the logic of E3 from changing.
Depending on the output results of the comparison results E1, E2, E3, the boosting modes D1, D2, D3, D4 are set to E1 = H, E2 = H, E3 = H: D1 = L, D2 =
L, D3 = L, D4 = H E1 = L, E2 = H, E3 = H: D1 = L, D2 =
L, D3 = H, D4 = L E1 = L, E2 = L, E3 = H: D1 = L, D2 = H,
D3 = L, D4 = L E1 = L, E2 = L, E3 = L: D1 = H, D2 = L, D
Set as a combination of E1, E2, and E3 such as 3 = L, D4 = L. FIG. 9 shows this as a table. The boosting modes D1, D2, D3, D4 set here correspond to D1, D2, D3, D4 in FIG. 5 detected by the optimum boosting stage number setting circuit 8.

The operation when the power is turned on and the operation when the load on the liquid crystal drive voltage V _O is increased are the same as those in the first embodiment. As a result, the boosted output HV _CC rises quickly when the power is turned on, and as a result, the rise time of the liquid crystal drive voltage V _O is shortened. Further, in a stable state where there is no load on the liquid crystal drive voltage V _O , the boosted output HV _CC of the charge pump type booster circuit 1 is set to the minimum number of boosting stages D4 capable of outputting the liquid crystal drive voltage V _O , so idling. Power consumption can be reduced. Further, even if the V _CC voltage, which is the reference power supply of the charge pump type booster circuit, increases or decreases, it is set to the minimum number of boosting stages that can output the drive voltage V _O.

Next, a charge pump type power supply circuit according to a third embodiment of the present invention will be described with reference to FIG.

In the third embodiment, the load fluctuation detecting circuit 7 in the first embodiment is deleted, and the charge pump type boosting circuit 1 and the optimum boosting stage number detecting circuit 8 are provided.
The operation of is similar to that of the first embodiment. Since the load variation detection circuit 7 is deleted, the detection result E of the load variation detection circuit 7
The booster stage number setting circuit 10 in which 1 to E3 are eliminated will be described with reference to FIGS. 11 and 12.

In FIG. 11, the optimum boosting stage number setting circuit 8
Detection results B1 to B5 and the boosting clock CK input to the boosting stage number setting circuit 9 are combined so that the boosting stage number can be varied from 3 to 8 times in accordance with the optimum boosting stage number detection result shown in FIG. , SW1 to SW25 are controlled after passing through the level shift LS. FIG. 13 shows SW1 to SW25 that are turned on in accordance with each number of boosting stages.

For example, when 1 / 2V _O <3 / 2V _CC = V _O
<3 V _CC : B1 = H, B2 = H, B3 = H, B4 =
When H, B5 = H, and B1 = H, the boosting clock CK is high so that charging / discharging is performed in three boosting stages.
17,18,20,21,23,24 turn on, C6 ~
Each capacitor of C8 is charged with the V _CC voltage. SW17, 19, 22, 25 is ON when boosting clock CK is Low
Then, the electric charges charged in the capacitors C6 to C8 are discharged to the boosting capacitor Ch to charge the boosting capacitor Ch. As a result, the boost capacitor Ch is charged with three times the charge of the V _CC voltage, and the boost output HV _CC outputs a voltage of 3 V _CC . Also, when 3 / 2V _CC ≤1 / 2V _O <4 / 2V _CC = 3V _CC ≤V _O
<4V _CC : B1 = L, B2 = H, B3 = H, B4 =
When H and B5 = H, the number of boosting stages is four, so that when the boosting clock CK is High, SW14, 15, 17,
18, 20, 21, 23, and 24 are turned on, and the capacitors C5 to C8 are charged with the V _CC voltage. Boost clock C
SW14,16,19,22,25 is O when K is Low
Then, the electric charges charged in the capacitors C5 to C8 are discharged to the boosting capacitor Ch to charge the boosting capacitor Ch. As a result, the boost capacitor Ch is charged with four times the V _CC voltage, and the boost output HV _CC outputs a voltage of 4 V _CC . Further, FIG. 12 shows that the number of boosting stages can be varied from 3 to 8 times according to the detection results B1 to B5 of the optimum boosting stage number setting circuit 8, and after passing through the level shift LS, the control of SW1 to SW25 is performed. To do.

For example, when 1 / 2V _O <3 / 2V _CC = V _O
<3 V _CC : B1 = H, B2 = H, B3 = H, B4 =
When H and B5 = H, the number of boosting stages is four, so that when the boosting clock CK is High, SW14 and SW1 are charged and discharged.
5, 17, 18, 20, 21, 23, 24 are turned on and C5
Each capacitor of C8 is charged with the V _CC voltage. When the boosting clock CK is Low, 14, 16, 19, 22, 25
Is turned on, the electric charges charged in the capacitors C5 to C8 are discharged to the boosting capacitor Ch, and the boosting capacitor Ch is
To charge. As a result, the boost capacitor Ch has V
Charge 4 times as high as _CC voltage and 4V for boosted output HV _CC
CC voltage is output.

Also, 3 / 2V _CC ≦ 1 / 2V _O <4 / 2V
_CC time _{= 3V CC ≦ V O <4V} CC when: B1 = L, B2 = H , B
When 3 = H, B4 = H, B5 = H, the number of boosting stages is 5, so that the boosting clock CK is high, SW11, 12, 14, 15, 17, 17, 18, 20,
21, 23 and 24 are turned on, and the respective capacitors C4 to C8 are charged with the V _CC voltage. When the boosting clock CK is Low, SW11, 13, 16, 19, 22, 25 are turned on and C
The charges charged in the capacitors 4 to C8 are discharged to the boost capacitor Ch to charge the boost capacitor Ch.

As a result, the boost capacitor Ch is charged with five times the V _CC voltage, and the boost output HV _CC outputs a voltage of 5 V _CC . From the above results, the minimum number of boosting stages that can output the drive voltage V _O is set even if the V _CC voltage serving as the reference power source of the charge pump type booster circuit increases or decreases.

[0045]

As described above, the first effect of the present invention is that the optimum number of boosting stages is set even if the Vcc voltage input to the charge pump type booster circuit fluctuates. That is, it is possible to reduce power consumption by eliminating boosting.

The second effect is that it is possible to protect the charge pump type booster circuit from breakdown voltage without performing excessive boosting.

A third effect is that since the number of boosting stages can be increased when the power is turned on, the rising period of the drive voltage can be shortened.

The fourth effect is to detect that the boosted output voltage has dropped even if the load has increased and increase the number of boosting stages.
Since the boosted output voltage is increased, the output of the reference power amplifier circuit
Vo does not change.

[Brief description of drawings]

FIG. 1 is a diagram showing a charge pump type power supply circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a charge pump type power supply circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a charge pump type power supply circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram showing an embodiment of the optimum booster stage number detection circuit of the present invention.

FIG. 5 is a diagram showing an example of the optimum boosting stage number detection result of the present invention.

[FIG. 6] V _CC voltage and V of the optimum boost stage number detection result of the present invention
It is a figure which shows the specific example at the time of changing _O voltage.

FIG. 7 is a diagram showing an embodiment of a load change detection circuit of the present invention.

FIG. 8 is a diagram showing another embodiment of the load change detection circuit of the present invention.

FIG. 9 is a diagram showing an example of a load variation detection result of the present invention.

FIG. 10 is a diagram showing one embodiment of a boost stage number setting circuit of the present invention.

FIG. 11 is a diagram showing another embodiment of the boost stage number setting circuit of the present invention.

FIG. 12 is a diagram showing another embodiment of the boost stage number setting circuit of the present invention.

FIG. 13 is a diagram showing a switch operating state at each boost in the charge pump booster circuit.

FIG. 14 is a diagram showing an example of a charge pump type booster circuit.

FIG. 15 is a diagram showing a switch operation at the time of 9 times charge in a charge pump type booster circuit.

FIG. 16 is a diagram showing a switch operation at the time of boosting by a factor of 9 in a charge pump type booster circuit.

FIG. 17 is a diagram showing a switch operation at the time of 5-fold charging in the charge pump type booster circuit.

FIG. 18 is a diagram showing a switch operation at the time of boosting 5 times in the charge pump type booster circuit.

FIG. 19 is a diagram showing a rising characteristic when the power is turned on in the first embodiment.

FIG. 20 is a diagram showing a load variation characteristic according to the first embodiment.

FIG. 21 is a diagram illustrating a conventional liquid crystal driving charge pump type power supply circuit.

FIG. 22 is a diagram showing a rising characteristic when the power is turned on in the conventional technique.

FIG. 23 is a diagram showing load variation characteristics in the conventional technique.

[Explanation of symbols]

1 charge pump type booster circuit 2 booster capacitor Ch 3 reference voltage 4 liquid crystal drive voltage generation circuit 5 drive voltage stabilizing capacitor C _O 6 load RL 7 load fluctuation detection circuit 8 optimum booster stage number detection circuit 9 booster stage number setting circuit 10 booster stage number Setting circuit

Claims (7)

[Claims] 1. An optimum booster stage number detection circuit that receives an input voltage of a charge pump type booster circuit and a voltage corresponding to a drive voltage from a drive voltage generation circuit as an input, and outputs the booster stage number output of the optimum booster stage number detection circuit. Accordingly, the charge pump type power supply circuit is provided with a boosting stage number setting circuit for setting the number of boosting stages of the charge pump type boosting circuit. 2. The charge pump type power supply circuit according to claim 1, wherein the drive voltage generation circuit is a liquid crystal drive voltage generation circuit. 3. A load fluctuation detection circuit which receives a boosted output of a charge pump type booster circuit and a load current detection voltage from a drive voltage generation circuit, and an input voltage of the charge pump type booster circuit and the drive voltage generation circuit. An optimum booster stage number detection circuit that receives a voltage corresponding to the drive voltage of the input circuit, and outputs the booster stage number output of the optimum booster stage number detection circuit according to the output of the load change detection circuit. A charge pump type power supply circuit having a boosting stage number setting circuit for setting the number of stages. 4. The charge pump type power supply circuit according to claim 3, wherein the drive voltage generation circuit is a liquid crystal drive voltage generation circuit. 5. The charge pump type power supply circuit according to claim 3, wherein a load current detection voltage is supplied to the load variation detection circuit from a gate of a drive transistor of the drive voltage generation circuit. 6. A resistor is provided between the boosted output and a source of a drive transistor of the drive voltage generation circuit, and a load current detection voltage is supplied to the load variation detection circuit from between the source and the resistor. The charge pump power supply circuit according to claim 3. 7. A boosted output is obtained by boosting a voltage input to a charge pump type booster circuit at a cycle of a booster clock input to a boost stage number setting circuit to a booster capacitor connected to an output terminal of the charge pump type booster circuit. In the charge pump system power supply circuit for driving liquid crystal, which drives the liquid crystal driver with the liquid crystal drive voltage to which the drive voltage stabilizing circuit is connected from the drive voltage generation circuit which outputs The load fluctuation detection circuit that detects the load fluctuation by comparing the boosted output of and the load fluctuation detection voltage created by the drive voltage generation circuit, the input voltage of the charge pump type booster circuit and the liquid crystal drive voltage from the drive voltage generation circuit. An optimal boost stage number detection circuit for comparing and detecting the optimal boost stage number is provided, and the boost stage number output of the optimal boost stage number detection circuit A charge pump type power supply circuit for driving a liquid crystal device, comprising: a step-up stage number setting circuit for controlling the number of step-up stages of the charge pump type step-up circuit according to the output of the load change detection circuit.