TWI840818B - Method for reworking semiconductor device - Google Patents

Abstract

The present application provides a method for reworking a failed hard mask layer on a via opening in a dielectric layer, including removing the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; and forming a mask layer on the top hard mask layer.

Description

Semiconductor component reworking method

This application claims priority to U.S. Patent Application Nos. 17/709,569 and 17/709,821 (i.e., the priority date is March 31, 2022), the contents of which are incorporated herein by reference in their entirety.

This disclosure relates to a method for reworking a semiconductor device.

Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is constantly shrinking to meet the growing demand for computing power. However, various problems arise in the process of shrinking size, and these problems are increasing. Therefore, challenges remain in achieving improved quality, yield, performance and reliability, as well as reduced complexity.

The above "prior art" description is only to provide background technology, and does not admit that the above "prior art" description discloses the subject matter of this disclosure, does not constitute the prior art of this disclosure, and any description of the above "prior art" should not be regarded as any part of this case.

One aspect of the present disclosure provides a method for preparing a semiconductor device, comprising providing a substrate; forming a dielectric layer on the substrate; forming a through hole opening in the dielectric layer using the first mask layer as a mask; forming an unqualified hard mask layer to fill the through hole opening; forming a second mask layer on the unqualified hard mask layer; and removing the second mask layer and the unqualified hard mask layer. Forming a bottom filling layer to fill the through hole opening; forming a top hard mask layer on the bottom filling layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a through hole in the through hole opening and forming a conductor in the trench opening.

Another aspect of the present disclosure provides a method for preparing a semiconductor device, comprising providing a substrate; forming a dielectric layer on the substrate; forming a through hole opening in the dielectric layer using a first mask layer as a mask; forming an unqualified hard mask layer to fill the through hole opening; forming a second mask layer on the unqualified hard mask layer; removing the second mask layer; performing a recoating process to remove the unqualified hard mask layer; The bottom filling layer is formed into a bottom filling layer; a top hard mask layer is formed on the bottom filling layer; a third mask layer is formed on the top hard mask layer; the top hard mask layer is patterned using the third mask layer as a mask; a trench opening is formed in the dielectric layer using the top hard mask layer as a mask; and a through hole is formed in the through hole opening and a conductor is formed in the trench opening.

Another aspect of the present disclosure provides a method for reworking a semiconductor device. The reworking method includes: removing a defective hard mask layer from a through hole opening in a dielectric layer; forming a bottom filling layer to fill the through hole opening; forming a top hard mask layer on the bottom filling layer; and forming a mask layer on the top hard mask layer.

Another aspect of the present disclosure provides a method for reworking a semiconductor device. The method includes: performing a recoating process to transform a non-conforming hard mask layer on a through hole opening in a dielectric layer into a bottom fill layer; forming a top hard mask layer on the bottom fill layer; and forming a mask layer on the top hard mask layer.

Due to the design of the semiconductor device preparation method disclosed in the present invention, by adopting a bottom filling layer or a bottom filling layer, the expansion of the through hole opening and/or the damage to the through hole opening profile can be reduced or avoided. Therefore, the yield and/or reliability of the semiconductor device can be improved.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

1A: Semiconductor components

1B: Semiconductor components

10: Preparation method

30: Preparation method

101: Base

103: Etch stop layer

105: Dielectric layer

107:Through hole

109: Conductor

201: Bottom filling layer

203: Bottom filling layer

205: Top hard mask layer

205O:Hard mask opening

401: First mask layer

403: Second mask layer

405: The third mask layer

501: Unqualified hard mask layer

501R: Groove

503: Conductive material layer

EVO: Expanded through-hole opening

S11: Step

S13: Step

S15: Step

S17: Step

S19: Step

S21: Step

S23: Step

S31: Step

S33: Step

S35: Step

S37: Step

S39: Step

S41: Step

S43: Step

S45: Step

T1:Thickness

T2: Thickness

T3:Thickness

T4:Thickness

T5:Thickness

T6:Thickness

TO: channel opening

VO: Through hole opening

Z: Direction

When referring to the embodiments and the drawings together with the scope of the patent application, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

FIG1 is a flow chart illustrating a method for preparing a semiconductor device according to an embodiment of the present disclosure.

Figures 2 to 12 are cross-sectional views illustrating the preparation process of a semiconductor device according to an embodiment of the present disclosure.

FIG13 is a flow chart illustrating a method for preparing a semiconductor device according to another embodiment of the present disclosure.

Figures 14 to 24 are cross-sectional views illustrating the preparation process of a semiconductor device according to another embodiment of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are examples and are not meant to be limiting. For example, in the following description, a first feature formed on a second feature may include an embodiment in which the first and second features are directly in contact with each other, and may also include an embodiment in which an additional feature may be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the disclosure may repeatedly reference numbers and/or letters in various embodiments. This repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms, such as "below", "below", "below", "above", "above", etc., may be used here to describe the relationship of an element or feature to another element or features shown in the figure for ease of description. Spatially relative terms are intended to include different orientations of the element in use or operation, as well as the orientation described in the figure. The element may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptors used here may also be interpreted accordingly.

It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly connected to or coupled to the other element or layer, or intervening elements or layers may be present.

It should be understood that although various elements are described herein with the terms first, second, etc., these elements should not be limited by these terms. Unless otherwise specified, these terms are only used to distinguish one element from another. Thus, for example, the first element, first component, or first part discussed below could be referred to as the second element, second component, or second part without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, the use of terms such as "same", "equal", "planar" or "coplanar" in reference to orientation, layout, position, shape, size, quantity or other measures herein does not necessarily mean exactly the same orientation, layout, position, shape, size, quantity or other measures, but rather means nearly the same orientation, layout, position, shape, size, quantity or other measures within an acceptable range of variation that may occur, such as due to manufacturing processes. The term "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same", "substantially equal" or "substantially planar" may be exactly the same, equal or planar, or they may be the same, equal or planar within an acceptable range of variation that may occur, such as due to manufacturing processes.

In this disclosure, semiconductor components generally refer to components that can function by utilizing semiconductor properties. Optoelectronic components, light-emitting display components, semiconductor circuits, and electronic components are all included in the scope of semiconductor components.

It should be noted that in the description of the present disclosure, up (or above) corresponds to the direction of the arrow in direction Z, and down (or below) corresponds to the opposite direction of the arrow in direction Z.

It should be noted that the terms "formation", "formed" and "to form" may refer to and include any method of creating, constructing, patterning, implanting or depositing elements, dopants or materials. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, lithography, dry etching and wet etching.

It should be noted that in the description of the present disclosure, functions or steps indicated herein may occur in a different order than indicated in the figures. For example, two figures shown in succession may in fact be executed substantially simultaneously, or may sometimes be executed in the reverse order, depending on the functions or steps involved.

FIG1 is a flow chart illustrating a method 10 for preparing a semiconductor device 1A according to an embodiment of the present disclosure. FIG2 to FIG12 are cross-sectional views illustrating a process for preparing a semiconductor device 1A according to an embodiment of the present disclosure.

Referring to FIGS. 1 to 3 , in step S11, a substrate 101 may be provided, an etch stop layer 103 may be formed on the substrate 101, a dielectric layer 105 may be formed on the etch stop layer 103, and a through hole opening VO may be formed to expose the etch stop layer 103.

Referring to FIG. 2 , substrate 101 may include a bulk semiconductor substrate entirely composed of at least one semiconductor material, a plurality of component units (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and a plurality of conductive features (not shown for clarity). The manufacturing technology of the bulk semiconductor substrate may include, for example, elementary semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors; or combinations thereof.

In some embodiments, the substrate 101 may include a semiconductor structure on an insulator, which includes, from bottom to top, a processing substrate, an insulator layer, and a topmost semiconductor material layer. The manufacturing techniques for the processing substrate and the topmost semiconductor material layer may include the same materials as the above-mentioned bulk semiconductor substrate. The insulator layer may be a crystalline or amorphous dielectric material, such as an oxide and/or a nitride. For example, the insulator layer may be a dielectric oxide, such as silicon oxide. For another example, the insulator layer may be a dielectric nitride, such as silicon nitride or boron nitride. For another example, the insulator layer may include a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The thickness of the insulator layer can be between 10 nanometers and 200 nanometers.

It should be noted that the term "about" modifies the amount of an ingredient, composition, or reactant employed to refer to variations in numerical amounts that may occur, for example, through typical measurements and liquid handling procedures used to make concentrates or solutions. In addition, variations may occur due to inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used to make compositions or perform methods, etc. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. However, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Referring to FIG. 2 , a plurality of element units may be formed on a bulk semiconductor substrate or the topmost semiconductor material layer. Some portions of the plurality of element units may be formed in a bulk semiconductor substrate or the topmost semiconductor material layer. The plurality of element units may be transistors, such as complementary metal oxide semiconductor transistors, metal oxide semiconductor field effect transistors, fin field effect transistors, etc., or a combination thereof.

2 , a plurality of dielectric layers may be formed on a bulk semiconductor substrate or the topmost semiconductor material layer and cover a plurality of device units. In some embodiments, the manufacturing techniques of the plurality of dielectric layers may include, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorinated silicate glass, low-k (dielectric constant) dielectric materials, etc., or combinations thereof. The dielectric constant of the low-k dielectric material may be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k dielectric material may be less than 2.0. The manufacturing techniques of the plurality of dielectric layers may include deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, or similar processes. The deposition process may be followed by a planarization process to remove excess material and provide a substantially flat surface for subsequent process steps.

2, the plurality of conductive features may include interconnect layers and conductive vias. The interconnect layers may be separated from each other and may be horizontally disposed in the plurality of dielectric layers along the Z direction. The conductive vias may connect adjacent interconnect layers, and adjacent component units and interconnect layers along the Z direction. In some embodiments, the conductive vias may improve heat dissipation and provide structural support. In some embodiments, the manufacturing technology of the plurality of conductive features may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminums, or combinations thereof. During the process of forming the plurality of dielectric layers, a plurality of conductive features may be formed.

In some embodiments, a plurality of component units and a plurality of conductive features may together configure a functional unit in substrate 101. In the description of the present disclosure, a functional unit generally refers to a circuit associated with a function that has been divided into an independent unit. In some embodiments, a functional unit may generally be a highly complex circuit, such as a processor core, a memory controller, or an accelerator unit. In other embodiments, the complexity and function of the functional unit may be more or less complex.

2, an etch stop layer 103 may be formed on a substrate 101. The manufacturing technique of the etch stop layer 103 may include a dielectric material preferably having an etch selectivity different from that of the uppermost layer (e.g., a dielectric layer) of the substrate 101. For example, the manufacturing technique of the etch stop layer 103 may include silicon carbide, silicon oxycarbide, or a similar material, and may be deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition. In the present embodiment, the manufacturing technique of the etch stop layer 103 includes silicon nitride. In some embodiments, the thickness T1 of the etch stop layer 103 may be between about 30 nanometers and about 40 nanometers, or about 35 nanometers.

2, the dielectric layer 105 may be formed on the etch stop layer 103, and the fabrication technology may include, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-on low-k dielectric layer, chemical vapor deposition low-k dielectric layer, or a combination thereof. In some embodiments, the dielectric layer 105 may include a self-planarizing material, such as spin-on glass or a spin-on low-k dielectric material, such as SiLK ^™ . The use of a self-planarizing dielectric material may avoid the need to perform a subsequent planarization step. In some embodiments, the dielectric layer 105 may be formed using a deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process such as chemical mechanical polishing may be performed to provide a substantially flat surface for subsequent process steps. In this embodiment, the dielectric layer 105 may be formed using silicon dioxide.

Referring to FIG. 2 , a first mask layer 401 may be formed on the dielectric layer 105. The first mask layer 401 may be, for example, a photoresist layer. The first mask layer 401 may be patterned to define the location of the through hole opening VO.

3 , a through hole etching process may be performed to remove a portion of the dielectric layer 105 and simultaneously form a through hole opening VO. The etching rate of the dielectric layer 105 in the through hole etching process may be faster than the etching rate of the etch stop layer 103 in the through hole etching process. For example, in the through hole etching process, the etching rate ratio of the dielectric layer 105 to the etch stop layer 103 may be between about 100:1 and about 1.05:1. For another example, in the through hole etching process, the etching rate ratio of the dielectric layer 105 to the etch stop layer 103 may be between about 100:1 and about 10:1. A portion of the etch stop layer 103 may be exposed through the dielectric layer 105.

Referring to FIG. 1 and FIG. 4 , in step S13 , an unqualified hard mask layer 501 may be formed to fill the through hole opening VO, and a second mask layer 403 may be formed on the unqualified hard mask layer 501 .

4 , the non-conforming hard mask layer 501 may be formed by a fabrication technique including, for example, spin coating or other suitable process to fill the via opening VO. In some embodiments, the fabrication technique of the non-conforming hard mask layer 501 may include a material having a slightly faster etch rate (relative to the material of the dielectric layer 105). In some embodiments, the non-conforming hard mask layer 501 may be, for example, AR 40 antireflective agent commercially provided by Rohm and Haas Electronic Materials (Phoenix, Ariz.). In some embodiments, the thickness T2 of the non-conforming hard mask layer 501 measured from the top surface of the dielectric layer 105 may be between about 30 nanometers and about 50 nanometers. In some embodiments, the manufacturing technology of the unqualified hard mask layer 501 may include, for example, silicon nitride, silicon oxynitride, or silicon nitride oxide.

It should be noted that the unqualified hard mask layer 501 is, for example, an unqualified hard mask layer 501 having a size that does not meet the specification, an unqualified hard mask layer 501 that produces pattern deviation, or an unqualified hard mask layer 501 including defects, such as the groove 501R just above the through hole opening VO shown in FIG. 4. The unqualified hard mask layer 501 may have an adverse effect on the yield and reliability of the resulting semiconductor device 1A. Therefore, the unqualified hard mask layer 501 needs to be further processed to avoid or reduce this effect.

Referring to FIG. 4 , a second mask layer 403 may be formed on the unqualified hard mask layer 501. In some embodiments, the thickness T3 of the second mask layer 403 may be between about 180 nanometers and about 220 nanometers. The second mask layer 403 may include a pattern of a trench opening TO (as shown in FIG. 9 ).

Referring to Figures 1, 5 and 6, in step S15, the second mask layer 403 and the unqualified hard mask layer 501 can be removed.

Referring to FIG. 5 , the removal technique of the second mask layer 403 and the unqualified hard mask layer 501 may include, for example, an ashing process, an etching process, other suitable processes or a combination thereof. A cleaning process may be optionally performed to remove any residues formed during the removal of the second mask layer 403 and the unqualified hard mask layer 501.

Referring to FIG. 1 , FIG. 6 and FIG. 7 , in step S17 , a bottom filling layer 201 may be formed to fill the through hole opening VO, a top hard mask layer 205 may be formed on the bottom filling layer 201 , and a third mask layer 405 may be formed on the top hard mask layer 205 .

6, the bottom filling layer 201 may be formed by, for example, spin coating, chemical vapor deposition or other suitable deposition processes to fill the through hole opening VO. In some embodiments, the bottom filling layer 201 may be formed by, for example, silicon carbide, silicon oxycarbide or similar materials. In some embodiments, the bottom filling layer 201 may be formed by a material having a slightly faster etching rate (relative to the material of the dielectric layer 105). In some embodiments, the bottom filling layer 201 may include carbon and hydrogen. In some embodiments, the bottom filling layer 201 may include carbon, hydrogen and oxygen. In some embodiments, the bottom filling layer 201 may include carbon, hydrogen and fluorine. In some embodiments, the bottom fill layer 201 can be a carbon film. The term "carbon film" is used herein to describe a material whose mass is mainly carbon, whose structure is mainly defined by carbon atoms, or whose physical and chemical properties are dominated by its carbon content. The term "carbon film" is meant to exclude materials that are mixtures or compounds that only include carbon, such as dielectric materials such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polysilicon.

In some embodiments, the thickness T4 of the bottom fill layer 201 measured from the top surface of the dielectric layer 105 may be between about 180 nanometers and about 220 nanometers.

When low-k materials are used for dielectric layers (e.g., dielectric layer 105), it is difficult to produce features with little to no surface defects or feature deformation. It has been observed that low-k dielectric materials are generally porous and are easily scratched and damaged during processing, thereby causing defects to form on their surfaces. In addition, low-k materials are generally brittle and may deform during conventional grinding processes. One solution to limit or reduce surface defects and deformation is to deposit a hard mask layer on the exposed low-k material before patterning and etching feature definition on the low-k material. The hard mask layer can resist damage and deformation. The hard mask layer can also protect the underlying low-k material during subsequent material deposition and planarization or material removal processes, such as chemical mechanical polishing or etching, thereby reducing defect formation and feature deformation. The hard mask layer can then be removed by a subsequent planarization process before subsequent processing.

7 , a top hard mask layer 205 may be formed on the bottom fill layer 201. In some embodiments, a thickness T5 of the top hard mask layer 205 may be between about 10 nm and about 100 nm, or between about 10 nm and about 50 nm. In some embodiments, the manufacturing technology of the top hard mask layer 205 may include, for example, silicon, silicon germanium, tetraethyl orthosilicate, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon carbide, etc., or a combination thereof. The manufacturing technology of the top hard mask layer 205 may include a deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, etc. The process temperature for forming the top hard mask layer 205 may be less than 400°C. In some embodiments, the manufacturing technology of the top hard mask layer 205 may include, for example, metal nitrides such as titanium nitride and tantalum nitride.

Alternatively, in some embodiments, the manufacturing technology of the top hard mask layer 205 may include, for example, boron nitride, silicon nitride, boron nitride phosphorus, silicon boron nitride carbon, or similar materials. The manufacturing technology of the top hard mask layer 205 may include a film forming process and a treatment process. In detail, in the film forming process, a first precursor may be introduced on the bottom filling layer 201, and the precursor may be a boron-based precursor to form a boron-based layer. Subsequently, in the treatment process, a second precursor may be introduced, which may be a nitrogen-based precursor, to react with the boron-based layer to convert the boron-based layer into the top hard mask layer 205. In some embodiments, the first precursor may be, for example, an alkyl-substituted derivative of diborane, cycloborane, or cycloborane. In some embodiments, the second precursor can be, for example, ammonia or hydrazine.

During patterning of the third mask layer 405, the top hard mask layer 205 may act as an anti-reflective coating to improve the quality of image transmission from the photomask (not shown) to the top hard mask layer 205.

7 , the third mask layer 405 may be formed on the top hard mask layer 205 by a manufacturing technique including a lithography process. The third mask layer 405 may include a pattern of trench openings TO. In some embodiments, the third mask layer 405 may be a photoresist, such as commercially available photoresist OCG895i, Epic ^™ 2210 ArF photoresist, or other suitable photoresists.

The process including removing the second mask layer 403 and the unqualified hard mask layer 501, forming the bottom filling layer 201, forming the mask top hard mask layer 205, and forming the third mask layer 405 (including patterning the third mask layer 405) can be called a rework process of the unqualified hard mask layer 501, which is used to avoid the unqualified hard mask layer 501 from adversely affecting the produced semiconductor device 1A.

The conventional rework process may include problems such as damage to the sidewall of the through hole opening VO and damage to the profile of the through hole opening VO. In contrast, by using the bottom filling layer 201, damage to the sidewall of the through hole opening VO and damage to the profile of the through hole opening VO can be reduced or avoided. Therefore, the yield and reliability of the produced semiconductor element 1A can be improved.

Referring to FIG. 1 , FIG. 8 and FIG. 9 , in step S19 , a trench opening TO can be formed in the dielectric layer 105 .

8 , a hard mask etching process may be performed to remove a portion of the top hard mask layer 205, and the pattern of the third mask layer 405 may be transferred to the top hard mask layer 205 to form a hard mask opening 205O along the top hard mask layer 205. The etching rate of the top hard mask layer 205 of the hard mask etching process may be faster than the etching rate of the bottom filling layer 201 of the hard mask etching process. For example, during the hard mask etching process, the etching rate ratio of the top hard mask layer 205 to the bottom filling layer 201 may be between about 100:1 and about 1.05:1. For another example, during the hard mask etching process, the etching rate ratio of the top hard mask layer 205 to the bottom fill layer 201 may be between about 100:1 and about 10:1. A portion of the bottom fill layer 201 may be exposed through the hard mask opening 205O.

9 , a trench etching process may be performed using the top hard mask layer 205 and/or the third mask layer 405 as masks to remove a portion of the dielectric layer 105 and the bottom filling layer 201. In some embodiments, during the trench etching process, an etching rate ratio of the dielectric layer 105 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. During the trench etching process, an etching rate ratio of the bottom filling layer 201 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. After the trench etching process, the trench opening TO can be formed in the dielectric layer 105. It should be noted that at the current stage, the etch stop layer 103 can still be covered by the bottom filling layer 201 remaining in the via opening VO.

In some embodiments, the third mask layer 405 may be removed before forming the trench opening TO. In some embodiments, the third mask layer 405 may be removed after the trench etching process for forming the trench opening TO. The removal of the third mask layer 405 may be achieved by, for example, an ashing process or other applicable processes.

Referring to FIG. 1 and FIG. 10 , in step S21, a punching etching process may be performed to form an extended through hole opening EVO to expose the substrate 101.

10 , the punch etching process may remove the bottom filling layer 201 remaining in the via opening VO and the portion of the etch stop layer 103 exposed through the via opening VO. In some embodiments, during the punch etching process, the etching rate ratio of the bottom filling layer 201 to the dielectric layer 105 may be between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. In some embodiments, during the punch etching process, the etching rate ratio of the etch stop layer 103 to the substrate 101 may be between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. After the punch etching process, the via opening VO may be expanded to form an extended via opening EVO along the dielectric layer 105 and the etch stop layer 103. A portion of the substrate 101 may be exposed through the extended via opening EVO.

After the trench etching process and/or the punch etching process, some etching residues may remain (not shown for clarity). The etching residues may be residual material on the inner surface of the trench opening TO after the trench etching process, residual material on the inner surface of the extended through hole opening EVO, or residual material after the ashing process of the third mask layer 405. The etching residues may have different compositions, depending on the material to be etched or ashed.

In some embodiments, a pre-cleaning process and a cleaning process may be used sequentially to remove the above-mentioned etching residues.

During the pre-cleaning process, the intermediate semiconductor component shown in FIG. 10 may be rotated at a speed between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. The pre-cleaning liquid may be sprayed onto the intermediate semiconductor component to cover the entire front side of the intermediate semiconductor component. While the pre-cleaning liquid is sprayed onto the front side of the intermediate semiconductor component, water or other suitable solution may be sprayed onto the back side of the intermediate semiconductor component to clean the back side of the intermediate semiconductor component.

In some embodiments, the pre-cleaning solution may include a chelating agent, a buffer, a fluorinated amine, a surfactant, or a solvent. In some embodiments, the fluorinated amine and the surfactant may be selective.

Generally, chelating agents may also be referred to as complexing agents or clamping agents. Chelating agents may have negatively charged ions, called ligands, that bind to free metal ions to form a complex that remains soluble. Chelating agents may be used to remove metal ions from intermediate semiconductor components. Without being bound by any particular theory, chelating agents may also reduce or prevent corrosion of the bottom conductive layer (of the substrate 101) exposed through the extended via opening EVO.

In some embodiments, the chelating agent of the pre-cleaning solution may include ethylenediaminetetraacetic acid, polyacrylates, carbonates, phosphonates, gluconates, N,N'-bis(2-hydroxyphenyl)ethylenediaminediacetic acid, trinitrosohexacetic acid, deferoxamine B, N,N ' , N" -tris [2-(N-hydroxycarbonyl)ethyl]-1,3,5-benzamide, and/or ethylenediaminedioxohydroxyphenylacetic acid. In some embodiments, the concentration of the chelating agent may be between about 0.001 mg/L and about 300 mg/L, or between about 0.01 mg/L and about 3 mg/L. In some embodiments, in addition, the concentration of the chelating agent may be between 1 ppm and about 400 ppm of the pre-cleaning solution, or preferably between about 40 ppm of the pre-cleaning solution.

The etchant in the pre-cleaning solution can be used to reduce or avoid metal corrosion during the subsequent cleaning process. In some embodiments, the etchant may include an aliphatic alcohol compound having at least one hydroxyl group in the molecule. The number of carbon atoms constituting the alcohol compound is not less than 2, and one carbon atom bonded to the hydroxyl group and another carbon atom bonded to the hydroxyl group are continuously bonded to each other. For example, the etchant may be 2-hydroxyethanol and/or thioglycerol. In some embodiments, the etchant concentration in the pre-cleaning solution may be between about 0.0001% and about 10% (by weight), or between about 0.001% and about 1% (by weight). When the concentration is too low, the corrosion inhibition effect may be limited to an unsatisfactory level. However, too high a concentration may not necessarily further enhance the corrosion inhibition effect, and may make it difficult to handle due to the unique odor of hydroxyl compounds.

In addition, in some embodiments, the buffer of the pre-cleaning solution may include aromatic hydrocarbon compounds, such as benzotriazole and/or 5-methylbenzimidazole. In addition, in some embodiments, the buffer of the pre-cleaning solution may include uric acid, adenine, caffeine and/or purine. In addition, in some embodiments, the buffer of the pre-cleaning solution may include glyoxylic acid. Due to the presence of glyoxylic acid, it is a reducing substance. Even if the metal material is exposed during the pre-cleaning process, the redox potential of the pre-cleaning solution is controlled by adjusting the concentration of glyoxylic acid therein, and the electron transfer between the pre-cleaning solution and the exposed metal material is controlled to prevent the metal material from being corroded. In addition, in some embodiments, the buffer of the pre-cleaning solution may include 2-hydroxyethanol, thioglycerol, benzotriazole, 5-methylbenzimidazole, uric acid, adenine, caffeine, purine and/or glyoxylic acid.

In some embodiments, the amine fluoride of the pre-cleaning solution may include methylamine hydrogen fluoride, ethylamine hydrogen fluoride, propylamine hydrogen fluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, ethanolamine hydrogen fluoride, methylethanolamine hydrogen fluoride, dimethylethanolamine hydrogen fluoride and/or triethylenediamine hydrogen fluoride. The amine fluoride can be used to remove etching residues.

In some embodiments, the concentration of the amine fluoride in the pre-cleaning solution can be determined according to the composition of the etching residues. For example, the concentration of the amine fluoride can be between about 0.1 mass % and about 5 mass % of the entire pre-cleaning solution composition, or between about 0.2 mass % and about 3 mass % of the entire pre-cleaning solution composition. By setting the concentration of the amine fluoride within such a range, it can be ensured that the amine fluoride in the pre-cleaning solution can remove the etching residues, while preventing the amine fluoride from corroding the underlying metal material exposed through the extended via opening EVO, and inhibiting the etching of the underlying dielectric layer exposed through the extended via opening EVO. That is, if the concentration of fluorinated amine in the pre-cleaning solution is too low, the ability to remove residues is low, and if the concentration is too high, the metal material may be corroded, and the exposed dielectric layer may be etched or structurally changed.

The purpose of a surfactant may be to prevent particles from being reattached or re-deposited on the intermediate semiconductor component after being detached from the intermediate semiconductor component. Preventing the reattachment of particles is important because allowing particles to reattach will increase the overall process time. The purpose of a surfactant may also include imparting affinity to a water repellent material layer. Generally speaking, surfactants are long carbon hydrogen chains that usually contain a hydrophilic (polar water soluble group) and a hydrophobic group (non-polar water insoluble group). The surfactant attaches to the front side of the particles and the intermediate semiconductor component with its non-polar group. Therefore, the polar group of the surfactant will be away from the wafer, away from the particles, and pointed toward the pre-cleaning solution covering the front side of the intermediate semiconductor component. Because of this, the particles in the solution bound by the surfactant will be electrostatically repelled from the front side of the intermediate semiconductor element, because the polar groups of the surfactant are present on both the particles and the front side of the intermediate semiconductor element.

In some embodiments, the surfactant of the pre-cleaning liquid may include non-ionic, anionic, or a mixture of non-ionic and anionic compounds. Non-ionic means that the polar end of the surfactant has an electrostatic charge instead of an ionic charge, and anionic means that the polar end of the surfactant has a negative ionic charge. The non-ionic surfactant may be, for example, polyoxyethylene butylphenyl ether, and the anionic surfactant may be, for example, polyoxyethylene alkylphenyl sulfate. In some embodiments, the concentration of the surfactant of the pre-cleaning liquid may be between about 1 ppm and about 100 ppm. In some embodiments, the concentration of the non-ionic surfactant in the pre-cleaning liquid may be about 30 ppm, and the concentration of the anionic surfactant in the pre-cleaning liquid may be about 30 ppm. In some embodiments, the concentration of the surfactant in the pre-cleaning solution can be between 0.0001 mass % and 10 mass % of the entire composition of the pre-cleaning solution, or between about 0.001 mass % and about 5 mass % of the entire composition of the pre-cleaning solution. By setting the concentration within such a range, it can be ensured that the wettability of the front surface of the intermediate semiconductor element is commensurate with the concentration of the surfactant.

In some embodiments, the solvent of the pre-cleaning solution may be deionized water.

In some embodiments, the front side of the middle semiconductor element shown in FIG. 10 may be covered (or soaked) with a pre-cleaning liquid for about 2 minutes. Next, the middle semiconductor element may be rinsed with deionized water to remove the pre-cleaning liquid.

In some embodiments, a drying process may be performed after the pre-cleaning process. The drying process may include spinning at about 100 rpm to about 6000 rpm, or about 3000 rpm for about 20 seconds, and using an air flow to dry the intermediate semiconductor components. In some embodiments, nitrogen or isopropyl alcohol may be used to promote the drying process. In some embodiments, the drying process may be optional. That is, the cleaning process may be performed directly after rinsing with the pre-cleaning solution.

In some embodiments, the cleaning process may include three stages, and an inter-stage rinse is performed between each stage. In detail, during the first stage of the cleaning process, after a pre-cleaning process (or a drying process), a first cleaning liquid may be applied to the intermediate semiconductor element. The first cleaning liquid may be rinsed by a first inter-stage rinse. During the second stage of the cleaning process, a second cleaning liquid may be applied to the intermediate semiconductor element, and then the second cleaning liquid may be rinsed by a second inter-stage rinse. During the third stage of the cleaning process, a third cleaning liquid may be applied to the intermediate semiconductor element and then rinsed by a post-stage rinse.

In some embodiments, during the first stage of the cleaning process, the pre-cleaned intermediate semiconductor component can be rotated at a speed between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. The first cleaning liquid can be sprayed onto the intermediate semiconductor component to cover the entire front side of the intermediate semiconductor component. While applying the first cleaning liquid to the front side of the intermediate semiconductor component, water or other suitable solution can be applied to the back side of the intermediate semiconductor component to clean the back side of the intermediate semiconductor component.

In some embodiments, the first cleaning solution may include dilute hydrofluoric acid. The concentration of the first cleaning solution may be between about 5 parts deionized water to 1 part hydrofluoric acid to about 1000 parts deionized water to 1 part hydrofluoric acid, about 300 parts deionized water to 1 part hydrofluoric acid, or about 50 parts deionized water to 1 part hydrofluoric acid. Typically, the front side of the intermediate semiconductor component may be exposed to the first cleaning solution for a time sufficient to etch the sacrificial oxide (typically about 50 angstroms to 200 angstroms) or the native oxide (typically about 10 angstroms). In some embodiments, the process time of the first stage of the cleaning process may be between about 1 minute and about 5 minutes.

In some embodiments, the first cleaning solution may also include fluorine compounds, organic acid salts and/or glyoxylic acid.

Fluorine compounds may be included in the first cleaning solution as a component for removing etching residues. Examples of fluorine compounds may include hydrofluoric acid and ammonium or amine fluorides, such as ammonium fluoride, ammonium hydrogen fluoride, methylamine hydrogen fluoride, ethylamine hydrogen fluoride, propylamine hydrogen fluoride, tetramethyl ammonium fluoride, tetraethyl ammonium fluoride, ethanolamine hydrogen fluoride, methylethanolamine ammonium fluoride, dimethylethanolamine hydrogen fluoride, and triethylenediamine hydrogen fluoride. In some embodiments, the concentration of the fluorine compound in the first cleaning solution may be determined according to the composition of the etching residues. For example, the concentration of the fluorine compound may be between about 0.1 mass % and about 5 mass % of the entire composition of the first cleaning solution, or between about 0.2 mass % and about 3 mass % of the entire composition of the first cleaning solution.

The organic acid salt may include, for example, ammonium oxalate, ammonium tartrate, ammonium citrate, and ammonium acetate. The organic acid salt may be used as a pH adjuster or buffer in the first cleaning solution. The concentration of the organic acid salt may be between about 0.1 mass % and about 10 mass % of the entire composition of the first cleaning solution, or between about 0.3 mass % and about 5 mass % of the entire composition of the first cleaning solution.

The glyoxylic acid contained in the first cleaning solution can act as a buffer.

In some embodiments, the first cleaning solution may also include an anti-corrosion agent removing component. Examples of anti-corrosion agent removing components include tetramethylammonium hydroxide and/or monomethanolamine.

A first inter-stage rinse may be performed after the first stage of the cleaning process. During the first inter-stage rinse, the intermediate semiconductor components after the first stage of the cleaning process may be rotated between about 10 rpm and about 1000 rpm while being rinsed with deionized water. In some embodiments, the rinse temperature may be between about 19°C and about 23°C. In some embodiments, the process time of the first inter-stage rinse may be between about 20 seconds and about 50 seconds, or about 30 seconds.

In some embodiments, the deionized water used for rinsing between the first stages can be oxidized or ozonated by dissolving oxygen or ozone gas before rinsing the intermediate semiconductor components. Dissolved oxygen or ozone can be added to the deionized water at a concentration greater than 1 ppm as an oxidant. For example, the concentration of dissolved oxygen or ozone can be between about 1 ppm and about 200 ppm, or between about 2 ppm and about 20 ppm. For another example, the deionized water can be saturated with dissolved oxygen or ozone. In addition, hydrogen peroxide can be added to the deionized water at a concentration greater than 100 ppm as an oxidant. Regardless of which oxidant is used, its oxidation potential should be sufficient to oxidize the most corrosion-resistant metal (noble metal) in the solution. Copper (Cu ²⁺ ) has a standard reduction potential of 0.3 V and is generally the most corrosion-resistant metal currently available. Therefore, a standard reduction potential greater than 0.5 V is required. Oxygen or ozone will dissolve the metal ions and prevent precipitation by oxidizing the metal ions in solution. This will make the first interstage rinse more effective to reduce process time.

In some embodiments, the deionized water used for the first interstage rinse may have carbon dioxide dissolved therein to dissipate static electricity that builds up in the deionized water. Static electricity that builds up in the deionized water may come from the rotation of the intermediate semiconductor components. The dissolved carbon dioxide may also make the deionized water more acidic, thereby reducing any metal contamination. In some embodiments, carbon dioxide may be dissolved into the deionized water in an amount sufficient to dissipate static electricity. For example, the amount of carbon dioxide dissolved into the deionized water may be sufficient to reduce the resistivity of the deionized water to less than 5 megohm.cm.

In some embodiments, isopropyl alcohol, or any other liquid with a lower surface tension than deionized water, may be added to the deionized water used for the first interstage rinsing. The isopropyl alcohol may help spread the deionized water on the front side of the intermediate semiconductor component, thereby allowing chemicals to be removed more quickly. The isopropyl alcohol may also help spin the rinse liquid off the intermediate semiconductor component during the spinning process. Additionally, during the rinsing, isopropyl alcohol vapor may be blown onto the front side of the intermediate semiconductor component to assist in the first interstage rinsing.

In some embodiments, the deionized water used to remove the pre-rinse solution can have similar treatment to the deionized water used during the first interstage rinse.

In some embodiments, during the second stage of the cleaning process, the intermediate semiconductor component after being rinsed during the first stage can be rotated at a speed between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. The second cleaning liquid can be sprayed onto the intermediate semiconductor component to cover the entire front side of the intermediate semiconductor component. While applying the second cleaning liquid to the front side of the intermediate semiconductor component, water or other suitable solution can be applied to the back side of the intermediate semiconductor component to clean the back side of the intermediate semiconductor component.

In some embodiments, the second cleaning solution may be an alkaline solution, including, for example, aqueous solutions of inorganic compounds, such as sodium hydroxide, potassium hydroxide and ammonium hydroxide, and aqueous solutions of organic compounds, such as tetramethylammonium hydroxide and choline. The second cleaning solution may also include hydrogen peroxide. The purpose of ammonium hydroxide and hydrogen peroxide in the second cleaning solution is to remove particles and residual organic contaminants on the front side of the intermediate semiconductor element.

For example, in this embodiment, the second cleaning solution may include ammonium hydroxide, hydrogen peroxide and water. The concentrations of ammonium hydroxide, hydrogen peroxide and water may exist in dilution ratio definitions between 5/1/1 and 1000/1/1, respectively. In some embodiments, the ratio of ammonium hydroxide/hydrogen peroxide may vary between 0.05/1 and 5/1. In some embodiments, hydrogen peroxide is not used at all. The ammonium hydroxide in the second cleaning solution will come from a 28-29% w/w (mass percent concentration) ammonia solution. The hydrogen peroxide in the second cleaning solution will be a 31-32% w/w solution of hydrogen peroxide to water. Due to the effects of ammonium hydroxide and hydrogen peroxide, the pH value of the second cleaning solution may be between 9 and 12, or between 10 and 11.

In some embodiments, the second cleaning solution may further include a chelating agent. The chelating agent of the second cleaning solution may have a compound and concentration similar to that of the chelating agent in the pre-cleaning solution, and its description is not repeated here.

In some embodiments, the second cleaning solution may further include a surfactant. The surfactant in the second cleaning solution may have a compound and concentration similar to that of the surfactant in the pre-cleaning solution, and its description is not repeated here.

In some embodiments, the second cleaning liquid may further include dissolved hydrogen. The dissolved hydrogen in the second cleaning liquid may provide cavitation (bubbles) to the second cleaning liquid. Providing cavitation to the second cleaning liquid may enhance the cleaning process. In some embodiments, the concentration of dissolved hydrogen may be between about 0.01 mg/L and about 5 mg/L, or between about 0.1 mg/L and about 5 mg/L. In some embodiments, other suitable cavitating gases may also be used, such as nitrogen, helium, argon, or oxygen. For example, dissolved oxygen at a concentration between 1 mg/L and 20 mg/L may be used in the second cleaning liquid.

In some embodiments, the process time of the second stage of the cleaning process may be between about 30 seconds and about 100 seconds, between about 30 seconds and about 90 seconds, or between about 30 seconds and about 60 seconds. In some embodiments, the temperature of the second cleaning solution may be between about 40°C and about 85°C.

The second inter-stage rinse can be performed after the second stage of the cleaning process. The second inter-stage rinse can be performed using a procedure similar to the first inter-stage rinse, and will not be repeated here.

In some embodiments, during the third stage of the cleaning process, the intermediate semiconductor element rinsed during the second stage can be rotated at a speed between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. The third cleaning liquid can be sprayed onto the intermediate semiconductor element to cover the entire front side of the intermediate semiconductor element. While the third cleaning liquid is applied to the front side of the intermediate semiconductor element, water or other suitable solution can be applied to the back side of the intermediate semiconductor element to clean the back side of the intermediate semiconductor element.

In some embodiments, the third cleaning solution may be an acidic solution including, for example, aqueous solutions of inorganic acids such as hydrochloric acid, hydrofluoric acid, sulfuric acid and nitric acid, and aqueous solutions of organic acids such as oxalic acid, citric acid, malonic acid, apple acid, fumaric acid and maleic acid. In some embodiments, the third cleaning solution may also include hydrogen peroxide. The concentration of the acidic solution may be between about 0.001% and about 10% (by weight), or between about 0.01% and about 5% (by weight). When the concentration is too low, a sufficient cleaning effect may not be obtained. When the concentration is too high, metal corrosion of the cleaning equipment or other related equipment may occur.

After the third stage of the cleaning process, a post-stage rinse can be performed. The post-stage rinse can be performed using a procedure similar to the first inter-stage rinse, and its description will not be repeated here.

In some embodiments, the second and third phases of the cleaning process may be optional. In other words, only the first phase of the cleaning process may be performed. In some embodiments, the third phase of the cleaning process may be optional. In other words, only the first and second phases of the cleaning process may be performed.

Referring to FIG. 1 , FIG. 11 and FIG. 12 , in step S23 , a through hole 107 may be formed in the extended through hole opening EVO, and a conductor 109 may be formed in the trench opening TO.

Referring to FIG. 11 , a layer of conductive material 503 may be formed to completely fill the extended via opening EVO and the trench opening TO. The conductive material may be, for example, copper. The manufacturing technology of the conductive material layer 503 may include, for example, chemical vapor deposition, physical vapor deposition, sputtering or other applicable deposition processes.

Referring to FIG. 12 , a planarization process, such as chemical mechanical polishing, may be performed until the top surface of the dielectric layer 105 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. After the planarization process, the conductive material layer 503 may become a via 107 in the extended via opening EVO and a conductor 109 in the trench opening TO. The substrate 101, the first etch stop layer 103, the dielectric layer 105, the via 107, and the conductor 109 together configure the semiconductor device 1A.

FIG. 13 is a flow chart illustrating a method 30 for preparing a semiconductor device 1B according to another embodiment of the present disclosure.

Figures 14 to 24 are cross-sectional views illustrating the preparation process of a semiconductor device 1B according to another embodiment of the present disclosure.

Referring to FIGS. 13 to 15 , in step S31, a substrate 101 may be provided, an etch stop layer 103 may be formed on the substrate 101, a dielectric layer 105 may be formed on the etch stop layer 103, and a through hole opening VO may be formed to expose the etch stop layer 103.

Referring to FIG. 14 , a process similar to that shown in FIG. 2 may be used to form the substrate 101, the etch stop layer 103, the dielectric layer 105 and the first mask layer 401, and the description thereof will not be repeated here.

Referring to FIG. 15 , a process similar to that shown in FIG. 3 may be used to form a through hole opening VO along the dielectric layer 105 and expose the etch stop layer 103, and the description thereof will not be repeated here.

Referring to FIG. 13 and FIG. 16 , in step S33 , an unqualified hard mask layer 501 may be formed to fill the through hole opening VO, and a second mask layer 403 may be formed on the unqualified hard mask layer 501 .

Referring to FIG. 16 , a procedure similar to that shown in FIG. 4 can be used to form the unqualified hard mask layer 501 and the second mask layer 403 , and the description thereof will not be repeated here.

Referring to Figures 13 and 17, in step S35, the second mask layer 403 can be removed.

Referring to FIG. 17 , the second mask layer 403 may be selectively removed. The removal technique of the second mask layer 403 may include, for example, an ashing process or an applicable etching process. In some embodiments, during the removal of the second mask layer 403, the etching rate ratio of the second mask layer 403 to the unqualified hard mask layer 501 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1.

Referring to FIG. 13 and FIG. 18 , in step S37 , the unqualified hard mask layer 501 can be transformed into the bottom fill layer 203 through a recoating process.

Referring to FIG. 18 , in some embodiments, the recoating process may be, for example, a spin-on process, chemical vapor deposition, physical vapor deposition, sputtering, or other suitable deposition processes. The recoating process may repair defects (e.g., grooves 501R) of the unqualified hard mask layer 501. After the recoating process, the unqualified hard mask layer 501 may become the bottom fill layer 203. In some embodiments, the thickness T6 of the bottom fill layer 203 may be between about 180 nanometers and about 220 nanometers. The manufacturing technology of the bottom fill layer 203 may include the same material as the unqualified hard mask layer 501, and its description is not repeated here. In some embodiments, a planarization process, such as chemical mechanical polishing or other suitable process, may be performed to provide a substantially flat surface for subsequent process steps. In some embodiments, the planarization process may be omitted.

In practice, removing the unqualified hard mask layer 501 may enlarge the through hole opening VO and/or damage the profile of the through hole opening VO. In this embodiment, recoating is used to repair the unqualified hard mask layer 501 instead of removing it, which can reduce or avoid the expansion of the through hole opening VO or the damage of the profile of the through hole opening VO.

Referring to FIG. 13 and FIG. 19 , in step S39 , a top hard mask layer 205 may be formed on the bottom fill layer 203 , and a third mask layer 405 may be formed on the top hard mask layer 205 .

Referring to FIG. 19 , the top hard mask layer 205 and the third mask layer 405 can be formed by a process similar to that shown in FIG. 7 , and the description thereof will not be repeated here.

The process includes removing the third mask layer 405, the bottom filling layer 203 of the manufacturing technology is a re-coating process, forming the top hard mask layer 205, and forming the third mask layer 405 (including patterning the third mask layer 405), which can be called a re-processing process of the unqualified hard mask layer 501. The process is used to avoid the unqualified hard mask layer 501 from adversely affecting the produced semiconductor device 1B.

Referring to FIG. 13 , FIG. 20 and FIG. 21 , in step S41 , a trench opening TO can be formed in the dielectric layer 105 .

Referring to FIG. 20 , a hard mask opening 205O may be formed using a procedure similar to that shown in FIG. 8 , and its description is not repeated here. A portion of the bottom fill layer 203 is exposed by the hard mask opening 205O.

21 , a trench etching process may be performed using the top hard mask layer 205 and/or the third mask layer 405 as masks to remove portions of the dielectric layer 105 and the bottom fill layer 203. In some embodiments, during the trench etching process, an etching rate ratio of the dielectric layer 105 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. During the trench etching process, an etching rate ratio of the bottom fill layer 203 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. After the trench etching process, the trench opening TO can be formed in the dielectric layer 105. It should be noted that at the current stage, the etch stop layer 103 can still be covered by the remaining bottom fill layer 203 in the via opening VO.

Referring to FIG. 13 and FIG. 22 , in step S43 , a punching etching process may be performed to form an extended through hole opening EVO to expose the substrate 101 .

22 , the punch etching process may remove the bottom fill layer 203 remaining in the via opening VO and the portion of the etch stop layer 103 exposed through the via opening VO. In some embodiments, during the punch etching process, the etch rate ratio of the bottom fill layer 203 to the dielectric layer 105 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. In some embodiments, during the punch etching process, the etch rate ratio of the etch stop layer 103 to the substrate 101 may be between about 100:1 and about 1.05:1 or between about 100:1 and about 10:1. After the punch etching process, the via opening VO may be extended to the extended via opening EVO along the dielectric layer 105 and the etch stop layer 103. A portion of the substrate 101 may be exposed through the extended via opening EVO.

In some embodiments, a procedure similar to that shown in FIG. 10 may be used to perform a pre-cleaning treatment and a cleaning process on the intermediate semiconductor element shown in FIG. 22, and the description thereof will not be repeated here.

Referring to FIG. 13 , FIG. 23 and FIG. 24 , in step S45 , a through hole 107 may be formed in the extended through hole opening EVO, and a conductor 109 may be formed in the trench opening TO.

Referring to FIG. 23 and FIG. 24 , a process similar to that shown in FIG. 11 and FIG. 12 can be used to form the through hole 107 and the conductor 109 , and the description thereof will not be repeated here. The substrate 101 , the first etch stop layer 103 , the dielectric layer 105 , the through hole 107 and the conductor 109 together configure the semiconductor device 1B .

One aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming a dielectric layer on the substrate; forming a through hole opening in the dielectric layer using the first mask layer as a mask; forming an unqualified hard mask layer to fill the through hole opening; forming a second mask layer on the unqualified hard mask layer; and removing the second mask layer and the unqualified hard mask layer. Forming a bottom filling layer to fill the through hole opening; forming a top hard mask layer on the bottom filling layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a through hole in the through hole opening and forming a conductor in the trench opening.

Another aspect of the present disclosure provides a method for preparing a semiconductor device, comprising providing a substrate; forming a dielectric layer on the substrate; forming a through hole opening in the dielectric layer using a first mask layer as a mask; forming an unqualified hard mask layer to fill the through hole opening; forming a second mask layer on the unqualified hard mask layer; removing the second mask layer; performing a recoating process to remove the unqualified hard mask layer; The bottom filling layer is formed into a bottom filling layer; a top hard mask layer is formed on the bottom filling layer; a third mask layer is formed on the top hard mask layer; the top hard mask layer is patterned using the third mask layer as a mask; a trench opening is formed in the dielectric layer using the top hard mask layer as a mask; and a through hole is formed in the through hole opening and a conductor is formed in the trench opening.

Another aspect of the present disclosure provides a defective hard mask layer disposed on a through hole opening in a dielectric layer, and a reworking method thereof includes removing the defective hard mask layer; forming a bottom filling layer to fill the through hole opening; forming a top hard mask layer on the bottom filling layer; and forming a mask layer on the top hard mask layer.

Another aspect of the present disclosure provides a defective hard mask layer disposed on a through hole opening in a dielectric layer, and a reworking method thereof includes performing a recoating process to transform the defective hard mask layer into a bottom fill layer; forming a top hard mask layer on the bottom fill layer; and forming a mask layer on the top hard mask layer.

Due to the design of the semiconductor device preparation method disclosed in the present invention, by adopting a bottom filling layer or a bottom filling layer, the expansion of the through hole opening and/or the damage to the through hole opening profile can be reduced or avoided. Therefore, the yield and/or reliability of the semiconductor device can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined by the scope of the patent application. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacturing, material compositions, means, methods and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

1A: Semiconductor components

101: Base

103: Etch stop layer

105: Dielectric layer

107:Through hole

109: Conductor

EVO: Expanded through-hole opening

Claims (10)

A rework method includes: removing a defective hard mask layer from a via opening in a dielectric layer; forming a bottom fill layer to fill the via opening; forming a top hard mask layer on the bottom fill layer; and forming a mask layer on the top hard mask layer. A rework method as described in claim 1, wherein the bottom fill layer and the unqualified hard mask layer include different materials. A rework method as described in claim 2, wherein the thickness of the unqualified hard mask layer is different from the thickness of the bottom fill layer. A rework method as described in claim 3, wherein the thickness of the unqualified hard mask layer is between about 30 nanometers and about 50 nanometers. A reworking method as described in claim 4, wherein the thickness of the bottom fill layer is between about 180 nanometers and about 220 nanometers. A rework method includes: performing a recoating process to convert a non-conforming hard mask layer on a through hole opening in a dielectric layer into a bottom fill layer; forming a top hard mask layer on the bottom fill layer; and forming a mask layer on the top hard mask layer. A rework method as described in claim 6, wherein the bottom fill layer and the unqualified hard mask layer include the same material. A rework method as described in claim 6, wherein the thickness of the unqualified hard mask layer is different from the thickness of the bottom fill layer. The rework method as described in claim 8, wherein the thickness of the unqualified hard mask layer is between about 30 nanometers and about 50 nanometers. A reworking method as described in claim 9, wherein the thickness of the bottom fill layer is between about 180 nanometers and about 220 nanometers.

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