TW202341292A - Method for reworking semiconductor device - Google Patents

Abstract

The present application provides a method for reworking a failed hard mask layer on a via opening in a dielectric layer, including removing the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; and forming a mask layer on the top hard mask layer.

Description

Reworking methods for semiconductor components

This application claims priority to U.S. Patent Application Nos. 17/709,569 and 17/709,821 (that is, the priority date is "March 31, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method of remanufacturing semiconductor components.

Semiconductor components are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are continuously shrinking in size to meet growing demands for computing power. However, various problems arise during the downsizing process, and such problems are increasing. Therefore, challenges remain in achieving improvements in quality, throughput, performance and reliability, and in reducing complexity.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming a dielectric layer on the substrate; using the first mask layer as a mask to form a through hole in the dielectric layer opening; forming an unqualified hard mask layer to fill the through hole; forming a second mask layer on the unqualified hard mask layer; removing the second mask layer and the unqualified hard mask layer. Form an underfill layer to fill the via opening; form a top hard mask layer on the underfill layer; form a third mask layer on the top hard mask layer; use the third mask layer as Patterning the top hard mask layer for masking; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via hole in the via opening and A trench is formed in the trench opening.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, which includes providing a substrate; forming a dielectric layer on the substrate; using a first mask layer as a mask to form a via in the dielectric layer. hole opening; forming an unqualified hard mask layer to fill the through hole opening; forming a second mask layer on the unqualified hard mask layer; removing the second mask layer; performing a recoating process to The unqualified hard mask layer becomes a bottom filling layer; a top hard mask layer is formed on the bottom filling layer; a third mask layer is formed on the top hard mask layer; the third mask layer is used as Patterning the top hard mask layer for masking; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via hole in the via opening and A trench is formed in the trench opening.

Another aspect of the present disclosure provides a method of remanufacturing semiconductor devices. The rework method includes: removing a defective hard mask layer from a via opening in a dielectric layer; forming an underfill layer to fill the via opening; forming a top hard mask on the underfill layer layer; and forming a mask layer on the top hard mask layer.

Another aspect of the present disclosure provides a method of remanufacturing semiconductor devices. The reworking method includes: performing a recoating process to convert an unqualified hard mask layer on a via opening in a dielectric layer into an underfill layer; forming a top hard mask layer on the underfill layer; and forming a mask layer on the top hard mask layer.

Due to the design of the semiconductor device manufacturing method of the present disclosure, by using an underfill layer or an underfill layer, the expansion of the via opening and/or the damage to the profile of the via opening can be reduced or avoided. Therefore, the yield and/or reliability of the semiconductor device can be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are just examples and are not meant to be limiting. For example, in the following description, the first feature formed on the second feature may include an embodiment in which the first and second features are formed in direct contact, or may include an embodiment in which additional features may be formed between the first and second features. For example, the first and second features may not be in direct contact. Additionally, reference numbers and/or letters may be repeated in various embodiments of this disclosure. This repetition is for simplicity and clarity and does not by itself determine the relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms, such as "under", "below", "below", "on", "above", etc., for convenience of description, may be used here to describe one element or feature relative to another as shown in the figure ( some) elements or characteristics. Spatially relative terms are intended to encompass various orientations of elements in use or operation, as well as the orientation depicted in the figures. The element may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that when an element or layer is referred to as being "connected" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer, or intervening elements or layers may be present. layer.

It will be understood that, although the terms first, second, etc. are used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are only used to distinguish one element from another. Thus, for example, a first element, element or section discussed below could be termed a second element, element or section without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, terms such as "same", "equal", "planar" or "coplanar" are used herein when referring to orientation, layout, location, shape, size, quantity or other measures, and not necessarily means exactly the same orientation, layout, position, shape, size, quantity or other measures, but means almost the same orientation, layout, position within acceptable variations that may occur, for example due to the manufacturing process , shape, size, quantity or other measures. The term "substantially" may be used here to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially planar" may be exactly the same, equal, or planar, or they may be the same, equal, or planar within acceptable variations. , such as changes that may occur due to the manufacturing process.

In this disclosure, semiconductor components generally refer to components that utilize semiconductor characteristics to function. Optoelectronic components, light-emitting display components, semiconductor circuits and electronic components are all included in the category of semiconductor components.

It should be noted that in the description of the present disclosure, upper (or upper) corresponds to the direction of the arrow of direction Z, and lower (or lower) corresponds to the opposite direction of the arrow of direction Z.

It should be noted that the terms "form", "formed" and "to form" may refer to and include any method of creating, building, patterning, implanting or depositing elements, dopants or materials. Examples of formation methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, lithography, dry etching, and wet etching .

It should be noted that in the description of the present disclosure, the functions or steps noted herein may occur out of the order noted in the figures. For example, two numbers displayed in succession may in fact be executed substantially simultaneously, or may sometimes be executed in reverse order, depending on the functions or steps involved.

FIG. 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. 2 to 12 are cross-sectional views illustrating the manufacturing process of the semiconductor device 1A according to one embodiment of the present disclosure.

Referring to FIGS. 1 to 3 , in step S11 , a substrate 101 may be provided, an etching stop layer 103 may be formed on the substrate 101 , a dielectric layer 105 may be formed on the etching stop layer 103 , and a via opening VO may be formed to expose Etch stop layer 103.

Referring to FIG. 2 , the substrate 101 may include a bulk semiconductor substrate composed entirely of at least one semiconductor material, a plurality of component units (not shown for the sake of clarity), and a plurality of dielectric layers (not shown for the sake of clarity). ) and a plurality of conductive features (not shown for clarity). The manufacturing technology of the bulk semiconductor substrate may include, for example, elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and antimony Indium, or other III-V compound semiconductors or II-VI compound semiconductors; or combinations thereof.

In some embodiments, substrate 101 may include a semiconductor-on-insulator structure that includes, from bottom to top, a processing substrate, an insulator layer, and an uppermost semiconductor material layer. The fabrication techniques for the handle substrate and uppermost semiconductor material layer may include the same materials as the bulk semiconductor substrate described above. The insulator layer may be a crystalline or amorphous dielectric material, such as oxide and/or nitride. For example, the insulator layer may be a dielectric oxide such as silicon oxide. As another example, the insulator layer may be a dielectric nitride, such as silicon nitride or boron nitride. As another example, the insulator layer may include a stack of dielectric oxide and dielectric nitride, such as silicon oxide and silicon nitride or boron nitride, in any order. The thickness of the insulator layer can be between 10 nanometers and 200 nanometers.

It should be noted that the term "about" modifies the amount of an ingredient, composition, or reactant employed to refer to changes in the numerical amount that may occur, for example, through typical measurement and liquid handling procedures used to make concentrates or solutions. In addition, variations may arise from inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the compositions or perform the methods. In one aspect, the term "about" means within 10% of the reported value. On the other hand, the term "about" means within 5% of the reported value. However, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

Referring to FIG. 2 , a plurality of element units may be formed on a bulk semiconductor substrate or an uppermost semiconductor material layer. Portions of the plurality of component units may be formed in a bulk semiconductor substrate or an uppermost layer of semiconductor material. The plurality of element units may be transistors, such as complementary metal oxide semiconductor transistors, metal oxide semiconductor field effect transistors, fin field effect transistors, etc., or combinations thereof.

Referring to FIG. 2 , a plurality of dielectric layers may be formed on a bulk semiconductor substrate or an uppermost semiconductor material layer, and cover a plurality of component units. In some embodiments, the manufacturing technology of the plurality of dielectric layers may include, for example, silicon oxide, borophosphate glass, undoped silicate glass, fluorosilicate glass, low-k (dielectric constant ) dielectric materials, etc., or combinations thereof. The dielectric constant of low-k dielectric materials can be less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k dielectric material may be less than 2.0. The manufacturing technology of the plurality of dielectric layers may include a deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, or similar processes. The deposition process may be followed by a planarization process to remove excess material and provide a substantially flat surface for subsequent process steps.

Referring to Figure 2, the plurality of conductive features may include interconnect layers and conductive vias. The interconnection layers can be separated from each other and can be horizontally disposed in a plurality of dielectric layers along the Z direction. Conductive vias can connect adjacent interconnect layers, as well as adjacent component units and interconnect layers along the Z direction. In some embodiments, conductive vias may improve heat dissipation and may provide structural support. In some embodiments, fabrication techniques for the plurality of conductive features may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), Metal nitrides (eg titanium nitride), transition metal aluminides, or combinations thereof. During the process of forming a plurality of dielectric layers, a plurality of conductive features may be formed.

In some embodiments, a plurality of element units and a plurality of conductive features may jointly configure functional units in the substrate 101 . In the description of this disclosure, a functional unit generally refers to a function-related circuit that has been divided into an independent unit. In some embodiments, functional units may typically be highly complex circuits such as processor cores, memory controllers, or accelerator units. In other embodiments, the complexity and functionality of the functional units may be more complex or less complex.

Referring to FIG. 2 , an etch stop layer 103 may be formed on the substrate 101 . The fabrication technique of the etch stop layer 103 may include preferably being made of a dielectric material having a different etch selectivity than the uppermost layer (eg, dielectric layer) of the substrate 101 . For example, the fabrication technology of the etch stop layer 103 may include silicon carbide, silicon oxycarbide or similar materials, and may be deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition. In this embodiment, the manufacturing technology of the etching stop layer 103 includes silicon nitride. In some embodiments, the thickness T1 of the etch stop layer 103 may be between about 30 nanometers and about 40 nanometers, or about 35 nanometers.

Referring to FIG. 2 , dielectric layer 105 may be formed on etch stop layer 103 , and fabrication techniques may include, for example, silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate Glass, spin-on low-k dielectric layer, chemical vapor deposited low-k dielectric layer, or combinations thereof. In some embodiments, dielectric layer 105 may include a self-planarizing material such as spin glass or a spin low-k dielectric material such as SiLK™. The use of self-planarizing dielectric materials avoids the need for subsequent planarization steps. In some embodiments, the manufacturing technology of the dielectric layer 105 may include a deposition process, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent process steps. In this embodiment, the manufacturing technology of the dielectric layer 105 includes silicon dioxide.

Referring to FIG. 2 , a first mask layer 401 may be formed on the dielectric layer 105 . The first mask layer 401 may be, for example, a photoresist layer. The first mask layer 401 may be patterned to define the location of the via opening VO.

Referring to FIG. 3 , a via etching process may be performed to remove a portion of the dielectric layer 105 and simultaneously form the via opening VO. The etching rate of the dielectric layer 105 during the via etching process may be faster than the etching rate of the etch stop layer 103 during the via etching process. For example, during the via etching process, the etch rate ratio of the dielectric layer 105 to the etch stop layer 103 may be between about 100:1 and about 1.05:1. For another example, in the via etching process, the etching rate ratio of the dielectric layer 105 and the etching stop layer 103 may be between about 100:1 and about 10:1. A portion of the etch stop layer 103 may be exposed through the dielectric layer 105 .

Referring to FIGS. 1 and 4 , in step S13 , a defective hard mask layer 501 may be formed to fill the via opening VO, and a second mask layer 403 may be formed on the defective hard mask layer 501 .

Referring to FIG. 4 , the defective hard mask layer 501 can be filled with the via opening VO by manufacturing techniques including, for example, spin coating or other suitable processes. In some embodiments, the fabrication technique of the failed hard mask layer 501 may include a material with a slightly faster etch rate (relative to the material of the dielectric layer 105 ). In some embodiments, the off-spec hard mask layer 501 may be, for example, AR 40 antireflective agent commercially available from Rohm and Haas Electronic Materials (Phoenix, Ariz.). In some embodiments, the thickness T2 of the failed hard mask layer 501 measured from the top surface of the dielectric layer 105 may be between about 30 nanometers and about 50 nanometers. In some embodiments, the fabrication technology of the failed hard mask layer 501 may include, for example, silicon nitride, silicon oxynitride, or silicon nitride oxide.

It should be noted that the defective hard mask layer 501 is, for example, a defective hard mask layer 501 that is out of specification, a defective hard mask layer 501 that produces pattern deviation, or a defective hard mask layer that includes defects. 501, a groove 501R directly above the via opening VO as shown in Figure 4. Substandard hard mask layer 501 may adversely affect the yield and reliability of the resulting semiconductor device 1A. Therefore, the failed hard mask layer 501 requires further processing to avoid or mitigate this effect.

Referring to FIG. 4 , a second mask layer 403 may be formed on the defective hard mask layer 501 . In some embodiments, the thickness T3 of the second mask layer 403 may be between about 180 nanometers and about 220 nanometers. The second mask layer 403 may include a pattern of trench openings TO (as shown in FIG. 9 ).

Referring to Figures 1, 5 and 6, in step S15, the second mask layer 403 and the unqualified hard mask layer 501 can be removed.

Referring to FIG. 5 , the removal technology of the second mask layer 403 and the unqualified hard mask layer 501 may include, for example, an ashing process, an etching process, other suitable processes, or a combination thereof. A cleaning process may optionally be performed to remove any residue formed during removal of the second mask layer 403 and the failed hard mask layer 501 .

Referring to FIGS. 1, 6 and 7, in step S17, an underfill layer 201 may be formed to fill the via opening VO, a top hard mask layer 205 may be formed on the underfill layer 201, and a top hard mask layer 205 may be formed on the underfill layer 201. A third mask layer 405 is formed on 205.

Referring to FIG. 6 , the manufacturing technology of the underfill layer 201 may include, for example, spin coating, chemical vapor deposition or other suitable deposition processes to fill the via opening VO. In some embodiments, the fabrication technology of the underfill layer 201 may include, for example, silicon carbide, silicon oxycarbide, or similar materials. In some embodiments, the fabrication technique of underfill layer 201 may include a material with a slightly faster etch rate (relative to the material of dielectric layer 105 ). In some embodiments, underfill layer 201 may contain carbon and hydrogen. In some embodiments, underfill layer 201 may include carbon, hydrogen, and oxygen. In some embodiments, underfill layer 201 may include carbon, hydrogen, and fluorine. In some embodiments, underfill layer 201 may be a carbon film. The term "carbon film" is used here to describe a material whose mass is primarily carbon, whose structure is defined primarily by carbon atoms, or whose physical and chemical properties are dominated by its carbon content. The term "carbon film" is meant to exclude materials that consist solely of mixtures or compounds of carbon, such as dielectric materials such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polycrystalline silicon.

In some embodiments, the thickness T4 of the underfill layer 201 measured from the top surface of the dielectric layer 105 may be between about 180 nanometers and about 220 nanometers.

When low-k materials are used for dielectric layers, such as dielectric layer 105, it is difficult to create features with few surface defects or feature deformations. It has been observed that low-k dielectric materials are usually porous and are easily scratched and damaged during the manufacturing process, thus causing defects to form on their surfaces. Additionally, low-k materials are often brittle and may deform during conventional grinding processes. One solution to limit or reduce surface defects and deformations is to deposit a hard mask layer over the exposed low-k material before patterning and etching feature definition into the low-k material. Hard mask layers resist damage and distortion. The hard mask layer also protects the underlying low-k material during subsequent material deposition and planarization or material removal processes, such as chemical mechanical polishing techniques or etching techniques, thereby reducing defect formation and feature distortion. The hard mask layer can then be removed by a subsequent planarization process before subsequent processes.

Referring to FIG. 7 , a top hard mask layer 205 may be formed on the underfill layer 201 . In some embodiments, the thickness T5 of the top hard mask layer 205 may be between about 10 nanometers and about 100 nanometers, or between about 10 nanometers and about 50 nanometers. In some embodiments, the manufacturing technology of the top hard mask layer 205 may include, for example, silicon, silicon germanium, tetraethyl orthosilicate, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon carbide, etc., or its combination. The manufacturing technology of the top hard mask layer 205 may include deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, etc. The process temperature for forming the top hard mask layer 205 can be lower than 400°C. In some embodiments, the fabrication technology of the top hard mask layer 205 may include, for example, metal nitrides such as titanium nitride and tantalum nitride.

Alternatively, in some embodiments, the fabrication technology of the top hard mask layer 205 may include, for example, boron nitride, silicon nitride, boron phosphorus nitride, boron nitride silicon carbon, or similar materials. The manufacturing technology of the top hard mask layer 205 may include a film forming process and a processing process. In detail, during the film formation process, a first precursor may be introduced on the underfill layer 201, and the precursor may be a boron-based precursor to form a boron-based layer. Subsequently, during the processing process, a second precursor, which may be a nitrogen-based precursor, may be introduced to react with the boron-based layer to turn the boron-based layer into the top hard mask layer 205 . In some embodiments, the first precursor may be, for example, diborane, borazine, or an alkyl substituted derivative of borazane. In some embodiments, the second precursor may be, for example, ammonia or hydrazine.

During patterning of the third mask layer 405, the top hard mask layer 205 may act as an anti-reflective coating to improve the quality of image transmission from the photomask (not shown) to the top hard mask layer 205.

Referring to FIG. 7 , the third mask layer 405 may be formed on the top hard mask layer 205 by a manufacturing technology including a photolithography process. The third mask layer 405 may include a pattern of trench openings TO. In some embodiments, the third mask layer 405 may be a photoresist, such as commercially available photoresist OCG895i, Epic™ 2210 ArF photoresist, or other suitable photoresist.

It includes removing the second mask layer 403 and the unqualified hard mask layer 501, forming the bottom filling layer 201, forming the mask top hard mask layer 205, and forming the third mask layer 405 (including removing the third mask layer 405 The process of determining the pattern) can be called a rework process of the unqualified hard mask layer 501. This process is used to avoid the adverse effects of the unqualified hard mask layer 501 on the produced semiconductor device 1A.

The conventional rework process may include problems such as damage to the side wall of the through hole opening VO and damage to the contour of the through hole opening VO. On the contrary, by using the underfill layer 201, the sidewall damage of the via opening VO and the contour damage of the via opening VO can be reduced or avoided. Therefore, the yield and reliability of the produced semiconductor element 1A can be improved.

Referring to FIGS. 1 , 8 and 9 , in step S19 , a trench opening TO may be formed in the dielectric layer 105 .

Referring to FIG. 8 , a hard mask etch process may be performed to remove portions of the top hard mask layer 205 , and the pattern of the third mask layer 405 may be transferred to the top hard mask layer 205 to be formed along the top hard mask layer 205 Hard mask opening 205O. The etch rate of the top hard mask layer 205 of the hard mask etch process may be faster than the etch rate of the underfill layer 201 of the hard mask etch process. For example, during the hard mask etch process, the etch rate ratio of the top hard mask layer 205 to the underfill layer 201 may be between about 100:1 and about 1.05:1. As another example, during the hard mask etching process, the etch rate ratio of the top hard mask layer 205 to the underfill layer 201 may be between about 100:1 and about 10:1. A portion of underfill layer 201 may be exposed through hard mask opening 205O.

Referring to FIG. 9 , a trench etching process may be performed using the top hard mask layer 205 and/or the third mask layer 405 as a mask to remove portions of the dielectric layer 105 and the underfill layer 201 . In some embodiments, during the trench etch process, the etch rate ratio of the dielectric layer 105 to the top hard mask layer 205 may be between about 100:1 to about 1.05:1 or between about 100:1 to about 10 :1 between. During the trench etch process, the etch rate ratio of the underfill layer 201 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. After the trench etching process, trench openings TO may be formed in the dielectric layer 105 . It should be noted that at the current stage, the etch stop layer 103 may still be covered by the remaining underfill layer 201 in the via opening VO.

In some embodiments, the third mask layer 405 may be removed before forming the trench opening TO. In some embodiments, the third mask layer 405 may be removed after the trench etching process used to form the trench opening TO. The third mask layer 405 can be removed by, for example, an ashing process or other suitable processes.

Referring to FIGS. 1 and 10 , in step S21 , a punching etching process may be performed to form an extended via opening EVO to expose the substrate 101 .

Referring to FIG. 10 , the punching etching process can remove the remaining underfill layer 201 in the via opening VO and the portion of the etch stop layer 103 exposed through the via opening VO. In some embodiments, during the punch etching process, the etch rate ratio of the underfill layer 201 to the dielectric layer 105 may be between about 100:1 and about 1.05:1, or between about 100:1 and about 10 :1 between. In some embodiments, during the punch etching process, the etch rate ratio of the etch stop layer 103 to the substrate 101 may be between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. . After the punch etching process, the via opening VO may be expanded to form an expanded via opening EVO along the dielectric layer 105 and the etch stop layer 103 . A portion of the substrate 101 may be exposed through the expanded via opening EVO.

After the trench etch process and/or punch etch process, some etch residue may be left behind (not shown for clarity). The etching residue may be residual material on the inner surface of the trench opening TO after the trench etching process, residual material on the inner surface of the extended via opening EVO, or residual material after the ashing process of the third mask layer 405 . Etch residues can have different compositions, depending on the material being etched or ashed.

In some embodiments, a pre-cleaning process and a cleaning process can be used sequentially to remove the etching residue.

During the pre-cleaning process, the intermediate semiconductor element shown in FIG. 10 may be rotated at a speed between about 10 rpm and about 2000 rpm, or between about 100 rpm and 1000 rpm. The pre-cleaning liquid can be sprayed onto the intermediate semiconductor element to cover the entire front surface of the intermediate semiconductor element. While the pre-cleaning liquid is sprayed on the front side of the middle semiconductor element, water or other suitable solutions can be sprayed on the back side of the middle semiconductor element to clean the back side of the middle semiconductor element.

In some embodiments, the pre-cleaning fluid may include chelating agents, corrosion inhibitors, amine fluorides, surfactants, or solvents. In some embodiments, the amine fluoride and surfactant may be optional.

Often, chelating agents may also be called complexing agents or clamping agents. Chelating agents can have negatively charged ions, called ligands, that combine with free metal ions to form combined complexes that remain soluble. Chelating agents can be used to remove metal ions from intermediate semiconductor components. Without being bound by any particular theory, the chelating agent may also reduce or prevent corrosion of the bottom conductive layer (of substrate 101) exposed through the extended via opening EVO.

In some embodiments, the chelating agent of the pre-cleaning solution may include ethylenediaminetetraacetic acid, polyacrylate, carbonate, phosphonate, gluconate, N,N'-bis(2-hydroxyphenyl)ethylene glycol Aminodiacetic acid, trinitrosohexaacetic acid, deferoxamine B, N,N′,N″-tris[2-(N-hydroxycarbonyl)ethyl]-1,3,5-benzamide, and/ or ethylenediaminedioxyhydroxyphenylacetic acid. In some embodiments, the concentration of the chelating agent can be between about 0.001 mg/L and about 300 mg/L, or between about 0.01 mg/L and about 3 mg/L. In some embodiments, in addition, the concentration of the chelating agent may be between 1 ppm and about 400 ppm of the pre-cleaning liquid, or preferably between about 40 ppm of the pre-cleaning liquid.

Corrosion inhibitors in pre-cleaning solutions can be used to reduce or avoid metal corrosion during subsequent cleaning processes. In some embodiments, the corrosion inhibitor may include an aliphatic alcohol compound having at least one thiol group in the molecule. The number of carbon atoms constituting the alcohol compound is not less than 2, and one carbon atom bonded to the mercapto group and the other carbon atom bonded to the hydroxyl group are continuously bonded to each other. For example, the corrosion inhibitor may be 2-mercaptoethanol and/or thioglycerol. In some embodiments, the corrosion inhibitor concentration in the pre-cleaning solution may be between about 0.0001% and about 10% by weight, or between about 0.001% and about 1% by weight. When the concentration is too low, the corrosion inhibition effect may be limited to an unsatisfactory level. Too high a concentration may not necessarily further improve the corrosion inhibition effect, and may make it difficult to handle due to the unique odor of sulfhydryl-containing compounds.

In addition, in some embodiments, the corrosion inhibitor of the pre-cleaning solution may include aromatic hydrocarbon compounds, such as benzotriazole and/or 5-methylbenzimidazole. In addition, in some embodiments, the corrosion inhibitor of the pre-cleaning solution may include uric acid, adenine, caffeine and/or purine. Additionally, in some embodiments, the corrosion inhibitor of the pre-cleaning solution may include glyoxylic acid. Due to the presence of glyoxylic acid, which is a reducing substance, even if the metal material is exposed during the pre-cleaning process, the redox potential of the pre-cleaning solution is controlled by adjusting the concentration of glyoxylic acid. The electron transfer between metal materials is controlled to prevent corrosion of metal materials. In addition, in some embodiments, the corrosion inhibitor of the pre-cleaning solution may include 2-mercaptoethanol, thioglycerol, benzotriazole, 5-methylbenzimidazole, uric acid, adenine, caffeine, purine and/or or glyoxylic acid.

In some embodiments, the amine fluoride in the pre-cleaning solution may include methylamine hydrogen fluoride, ethylamine hydrogen fluoride, propylamine hydrogen fluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, ethanolamine hydrogen fluoride, methylethanolamine hydrogen fluoride, dimethyl ethanolamine hydrogen fluoride and/or triethylenediamine hydrogen fluoride. Amine fluoride can be used to remove etching residues.

In some embodiments, the concentration of amine fluoride in the pre-cleaning solution can be determined based on the composition of the etching residue. For example, the concentration of the amine fluoride may be between about 0.1 mass % and about 5 mass % of the entire pre-cleaning liquid composition, or between about 0.2 mass % and about 3 mass % of the entire pre-cleaning liquid composition. By setting the concentration of amine fluoride within such a range, it can be ensured that the amine fluoride in the pre-cleaning solution can remove etching residues, while preventing the amine fluoride from corroding the underlying metal material exposed through the expanded via opening EVO, and Suppresses etching of the underlying dielectric layer exposed through the extended via opening EVO. That is to say, if the concentration of amine fluoride in the pre-cleaning solution is too low, the ability to remove residues will be very low. If the concentration is too high, the metal material may be corroded, and the exposed dielectric layer may be etched or structured. change.

The purpose of the surfactant may be to prevent particles from reattaching or redepositing on the intermediate semiconductor element after being detached from the intermediate semiconductor element. Preventing particle re-attachment is important because allowing particles to re-attach increases the overall process time. The purpose of the surfactant may also include imparting affinity to the layer of water-repellent material. Generally speaking, surfactants are long hydrocarbon chains, usually containing a hydrophilic (polar water-soluble group) and a hydrophobic group (non-polar water-insoluble group). The surfactant attaches its non-polar groups to the front side of the particles and the intermediate semiconductor element. Therefore, the polar groups of the surfactant will be directed away from the wafer, away from the particles, towards the pre-clean fluid covering the front side of the intermediate semiconductor component. Because of this, surfactant-bound particles in solution will be electrostatically repelled from the front face of the intermediate semiconductor element because both the particles and the front face of the intermediate semiconductor element have the polar groups of the surfactant.

In some embodiments, the surfactant of the pre-cleaning solution may include nonionic, anionic, or a mixture of nonionic and anionic compounds. Nonionic means that the polar end of the surfactant has an electrostatic rather than ionic charge, and anionic means that the polar end of the surfactant has a negative ionic charge. The nonionic surfactant may be, for example, polyoxyethylene butyl phenyl ether, and the anionic surfactant may be, for example, polyoxyethylene alkylphenyl sulfate. In some embodiments, the surfactant concentration of the pre-cleaning liquid may be between about 1 ppm and about 100 ppm. In some embodiments, the concentration of the nonionic surfactant in the pre-cleaning liquid may be about 30 ppm, and the concentration of the anionic surfactant in the pre-cleaning liquid may be about 30 ppm. In some embodiments, the concentration of the surfactant of the pre-cleaning liquid may be between 0.0001 mass % and 10 mass % of the entire composition of the pre-cleaning liquid, or between about 0.001 mass % and about 5 mass % of the entire composition of the pre-cleaning liquid. between mass %. By setting the concentration within such a range, it is possible to ensure that the wettability of the front surface of the intermediate semiconductor element is commensurate with the concentration of the surfactant.

In some embodiments, the solvent of the pre-cleaning solution may be deionized water.

In some embodiments, the front surface of the middle semiconductor element shown in FIG. 10 may be covered (or soaked) in the pre-cleaning liquid for about 2 minutes. Next, the intermediate semiconductor element may be rinsed with deionized water to remove the pre-cleaning liquid.

In some embodiments, a drying process may be performed after the pre-cleaning process. The drying process may include rotating between about 100 rpm and about 6000 rpm, or about 3000 rpm for about 20 seconds, and using an air flow to dry the intermediate semiconductor device. In some embodiments, nitrogen or isopropyl alcohol may be used to facilitate the drying process. In some embodiments, the drying process may be optional. In other words, the cleaning process can be executed directly after flushing with the pre-cleaning liquid.

In some embodiments, the cleaning process may include three stages, with interstage rinsing performed between each stage. In detail, during the first stage of the cleaning process, the first cleaning liquid may be applied to the intermediate semiconductor element after the pre-cleaning process (or drying process). The first cleaning liquid may be rinsed by the first inter-stage rinse. During the second stage of the cleaning process, a second cleaning fluid may be applied to the intermediate semiconductor device, and the second cleaning fluid may then be rinsed by a second inter-stage rinse. During the third stage of the cleaning process, a third cleaning liquid may be applied to the intermediate semiconductor device and then rinsed by a post-stage rinse.

In some embodiments, during the first stage of the cleaning process, the pre-cleaned intermediate semiconductor device may be cleaned between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. rotate at the desired speed. The first cleaning liquid may be sprayed onto the middle semiconductor element to cover the entire front surface of the middle semiconductor element. While the first cleaning liquid is applied to the front side of the middle semiconductor element, water or other suitable solution may be applied to the back side of the middle semiconductor element to clean the back side of the middle semiconductor element.

In some embodiments, the first cleaning solution may include dilute hydrofluoric acid. The concentration of the first cleaning solution can be between about 5 parts deionized water to 1 part hydrofluoric acid to about 1000 parts deionized water to 1 part hydrofluoric acid, about 300 parts deionized water to 1 part hydrofluoric acid, or About 50 parts deionized water to 1 part hydrofluoric acid. Typically, the front side of the intermediate semiconductor element may be exposed to the first cleaning solution for a time sufficient to etch the sacrificial oxide (typically about 50 angstroms to 200 angstroms) or the native oxide (typically about 10 angstroms). In some embodiments, the process time of the first stage of the cleaning process may be between about 1 minute and about 5 minutes.

In some embodiments, the first cleaning solution may further include fluorine compounds, organic acid salts, and/or glyoxylic acid.

The fluorine compound may be included in the first cleaning liquid as a component for removing etching residues. Examples of the fluorine compound may include hydrofluoric acid and ammonium or amine fluoride, such as ammonium fluoride, ammonium bifluoride, methylamine hydrogen fluoride, ethylamine hydrogen fluoride, propylamine hydrogen fluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, Ethanolamine hydrogen fluoride, methylethanolamine ammonium fluoride, dimethylethanolamine hydrogen fluoride, and triethylenediamine hydrogen fluoride. In some embodiments, the concentration of the fluorine compound in the first cleaning solution may be determined according to the composition of the etching residue. For example, the concentration of the fluorine compound may be between about 0.1 mass % and about 5 mass % of the entire composition of the first cleaning liquid, or between about 0.2 mass % and about 3 mass % of the entire composition of the first cleaning liquid.

Organic acid salts may include, for example, ammonium oxalate, ammonium tartrate, ammonium citrate, and ammonium acetate. The organic acid salt can be used as a pH adjuster or buffer in the first cleaning solution. The concentration of the organic acid salt may be between about 0.1 mass % and about 10 mass % of the entire composition of the first cleaning liquid, or between about 0.3 mass % and about 5 mass % of the entire composition of the first cleaning liquid.

The glyoxylic acid contained in the first cleaning solution can be used as a corrosion inhibitor.

In some embodiments, the first cleaning solution may further include a resist removal component. Examples of resist removal components include tetramethylammonium hydroxide and/or monocarbinolamine.

The first inter-stage rinse can be performed after the first stage of the cleaning process. During the first inter-stage rinse, the intermediate semiconductor component after the first stage of the cleaning process may be rotated between about 10 rpm and about 1000 rpm while being rinsed with deionized water. In some embodiments, the rinse temperature can be between about 19°C and about 23°C. In some embodiments, the process time of the first inter-stage rinse may be between about 20 seconds and about 50 seconds, or about 30 seconds.

In some embodiments, the deionized water used for the first interstage rinse may be oxidized or ozonated by dissolved oxygen or ozone gas before rinsing the intermediate semiconductor components. Dissolved oxygen or ozone can be added to deionized water at a concentration greater than 1 ppm as an oxidizing agent. For example, the concentration of dissolved oxygen or ozone may be between about 1 ppm and about 200 ppm, or between about 2 ppm and about 20 ppm. As another example, deionized water can be saturated with dissolved oxygen or ozone. In addition, hydrogen peroxide with a concentration greater than 100 ppm can be added to deionized water as an oxidizing agent. Regardless of which oxidant is used, its oxidation potential should be sufficient to oxidize the most corrosion-resistant metal in the solution (noble metal). Copper (Cu ²⁺ ) has a standard reduction potential of 0.3V and is generally the most corrosion-resistant metal available. Therefore, a standard reduction potential greater than 0.5V is required. Oxygen or ozone will dissolve metal ions and prevent precipitation by oxidizing the metal ions in the solution. This will make the first interstage rinse more efficient to reduce process time.

In some embodiments, the deionized water used for the first interstage rinse may have carbon dioxide dissolved therein to dissipate accumulated static electricity in the deionized water. The static electricity that accumulates in deionized water may come from the rotation of the intermediate semiconductor element. Dissolved carbon dioxide also makes deionized water more acidic, thus reducing any metal contamination. In some embodiments, carbon dioxide can be dissolved into deionized water in an amount sufficient to dissipate static electricity. For example, the amount of carbon dioxide dissolved into the deionized water may be sufficient to reduce the resistivity of the deionized water to less than 5 Megohm∙cm.

In some embodiments, isopropanol may be added to the deionized water used for the first interstage rinse, or any other liquid with a lower surface tension than deionized water. The isopropyl alcohol helps spread the deionized water on the front side of the intermediate semiconductor component, thus allowing the chemicals to be removed faster. Isopropyl alcohol also helps the rinse solution spin off the intermediate semiconductor components during the spin process. In addition, during rinsing, isopropyl alcohol vapor can be blown to the front side of the intermediate semiconductor component to assist in the first inter-stage rinsing.

In some embodiments, the deionized water used to remove the pre-wash liquid may have a similar treatment to the deionized water used during the first interstage rinse.

In some embodiments, during the second stage of the cleaning process, the intermediate semiconductor device after rinsing between the first stages may be cleaned between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. Rotate at speeds between /min. The second cleaning liquid may be sprayed onto the middle semiconductor element to cover the entire front surface of the middle semiconductor element. While the second cleaning liquid is applied to the front side of the middle semiconductor element, water or other suitable solution may be applied to the back side of the middle semiconductor element to clean the back side of the middle semiconductor element.

In some embodiments, the second cleaning solution may be an alkaline solution, including, for example, aqueous solutions of inorganic compounds, such as sodium hydroxide, potassium hydroxide, and ammonium hydroxide, and aqueous solutions of organic compounds, such as tetramethylammonium hydroxide. with choline. The second cleaning solution may also include hydrogen peroxide. The purpose of the ammonium hydroxide and hydrogen peroxide in the second cleaning solution is to remove particles and residual organic pollutants on the front surface of the intermediate semiconductor element.

For example, in this embodiment, the second cleaning liquid may include ammonium hydroxide, hydrogen peroxide and water. The concentrations of ammonium hydroxide, hydrogen peroxide and water can exist in dilution ratio definitions between 5/1/1 and 1000/1/1 respectively. In some embodiments, the ammonium hydroxide/hydrogen peroxide ratio can vary between 0.05/1 and 5/1. In some embodiments, no hydrogen peroxide is used at all. The ammonium hydroxide in the second cleaning solution will come from a 28-29% w/w (mass percent concentration) ammonia solution. The hydrogen peroxide in the second cleaning solution will be a 31-32% w/w solution of hydrogen peroxide in water. Due to the action of ammonium hydroxide and hydrogen peroxide, the pH value of the second cleaning solution can be between 9 and 12, or between 10 and 11.

In some embodiments, the second cleaning solution may also include a chelating agent. The chelating agent in the second cleaning liquid may have a similar compound and concentration to the chelating agent in the pre-cleaning liquid, and its description will not be repeated here.

In some embodiments, the second cleaning solution may also include a surfactant. The surfactant in the second cleaning liquid may have a similar compound and concentration to the surfactant in the pre-cleaning liquid, and its description will not be repeated here.

In some embodiments, the second cleaning liquid may also include dissolved hydrogen. Dissolved hydrogen in the second cleaning liquid can provide cavitation (generation of bubbles) to the second cleaning liquid. Providing cavitation to the second cleaning fluid enhances the cleaning process. In some embodiments, the concentration of dissolved hydrogen can be between about 0.01 mg/L and about 5 mg/L, or between about 0.1 mg/L and about 5 mg/L. In some embodiments, other suitable cavitation gases such as nitrogen, helium, argon, or oxygen may also be used. For example, dissolved oxygen with a concentration between 1 mg/L and 20 mg/L can be used in the second cleaning solution.

In some embodiments, the process time of the second stage of the cleaning process may be between about 30 seconds and about 100 seconds, between about 30 seconds and about 90 seconds, or between about 30 seconds and about 60 seconds. In some embodiments, the temperature of the second cleaning liquid may be between about 40°C and about 85°C.

The second interstage rinse can be performed after the second stage of the cleaning process. The second inter-stage rinse can be performed using a procedure similar to the first inter-stage rinse, and the description will not be repeated here.

In some embodiments, during the third stage of the cleaning process, the intermediate semiconductor device after rinsing between the second stages may be cleaned between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. Rotate at speeds between /min. The third cleaning liquid can be sprayed onto the middle semiconductor element to cover the entire front surface of the middle semiconductor element. While the third cleaning liquid is applied to the front side of the middle semiconductor element, water or other suitable solution may be applied to the back side of the middle semiconductor element to clean the back side of the middle semiconductor element.

In some embodiments, the third cleaning solution may be an acidic solution including, for example, aqueous solutions of inorganic acids such as hydrochloric acid, hydrofluoric acid, sulfuric acid, and nitric acid, as well as oxalic acid, citric acid, malonic acid, malic acid, fumaric acid, and Aqueous solutions of organic acids such as maleic acid. In some embodiments, the third cleaning solution may further include hydrogen peroxide. The concentration of the acidic solution may be between about 0.001% and about 10% by weight, or between about 0.01% and about 5% by weight. When the concentration is too low, sufficient cleaning effects may not be obtained. When concentrations are too high, metal corrosion of cleaning equipment or other related equipment may occur.

After the third stage of the cleaning process, a post-stage rinse can be performed. The post-stage rinse can be performed with a procedure similar to the first inter-stage rinse, the description of which will not be repeated here.

In some embodiments, the second and third stages of the cleaning process may be optional. In other words, only the first stage of the cleaning process can be performed. In some embodiments, the third stage of the cleaning process may be optional. In other words, only the first and second stages of the cleaning process can be performed.

Referring to FIGS. 1 , 11 and 12 , in step S23 , the via hole 107 may be formed in the expanded via hole opening EVO, and the trench 109 may be formed in the trench opening TO.

Referring to FIG. 11 , a layer of conductive material 503 may be formed to completely fill the extended via opening EVO and the trench opening TO. The conductive material may be, for example, copper. The manufacturing technology of the conductive material layer 503 may include, for example, chemical vapor deposition, physical vapor deposition, sputtering or other suitable deposition processes.

Referring to FIG. 8 , a planarization process, such as chemical mechanical polishing, may be performed until the top surface of dielectric layer 105 is exposed to remove excess material and provide a substantially planar surface for subsequent process steps. After the planarization process, the conductive material layer 503 may become the via 107 in the expanded via opening EVO and the trench 109 in the trench TO. The substrate 101, the first etching stop layer 103, the dielectric layer 105, the via 107 and the trench 109 jointly configure the semiconductor device 1A.

FIG. 13 is a flow chart illustrating a method 30 for manufacturing a semiconductor device 1B according to another embodiment of the present disclosure.

14 to 24 are cross-sectional views illustrating the manufacturing process of the semiconductor device 1B according to another embodiment of the present disclosure.

Referring to FIGS. 13 to 15 , in step S31 , a substrate 101 may be provided, an etching stop layer 103 may be formed on the substrate 101 , a dielectric layer 105 may be formed on the etching stop layer 103 , and a via opening VO may be formed to expose Etch stop layer 103.

Referring to FIG. 14 , a process similar to that shown in FIG. 2 may be used to form the substrate 101 , the etching stop layer 103 , the dielectric layer 105 and the first mask layer 401 , and their description will not be repeated here.

Referring to FIG. 15 , a procedure similar to that shown in FIG. 3 may be used to form the via opening VO along the dielectric layer 105 and expose the etch stop layer 103 , the description of which will not be repeated here.

Referring to FIGS. 13 and 16 , in step S33 , a defective hard mask layer 501 may be formed to fill the via opening VO, and a second mask layer 403 may be formed on the defective hard mask layer 501 .

Referring to FIG. 16 , a procedure similar to that shown in FIG. 4 may be used to form the failed hard mask layer 501 and the second mask layer 403 , the description of which will not be repeated here.

Referring to FIG. 13 and FIG. 17 , in step S35 , the second mask layer 403 may be removed.

Referring to FIG. 17 , the second mask layer 403 may be selectively removed. The removal technique of the second mask layer 403 may include, for example, an ashing process or an appropriate etching process. In some embodiments, during removal of the second mask layer 403, the etch rate ratio of the second mask layer 403 to the failed hard mask layer 501 may be between about 100:1 and about 1.05:1 or between about Between 100:1 and about 10:1.

Referring to FIGS. 13 and 18 , in step S37 , the unqualified hard mask layer 501 can be transformed into the underfill layer 203 through a recoating process.

Referring to FIG. 18 , in some embodiments, the recoating process may be, for example, a spin coating process, chemical vapor deposition, physical vapor deposition, sputtering, or other suitable deposition processes. The recoating process can repair defects of the failed hard mask layer 501 (eg, grooves 501R). After the recoat process, the failed hard mask layer 501 may become the underfill layer 203. In some embodiments, the thickness T6 of the underfill layer 203 may be between about 180 nanometers and about 220 nanometers. The manufacturing technology of the underfill layer 203 may include the same material as the failed hard mask layer 501, and its description will not be repeated here. In some embodiments, a planarization process, such as chemical mechanical polishing or other suitable processes, may be performed to provide a substantially planar surface for subsequent process steps. In some embodiments, the planarization process may be omitted.

Conventionally, removing the unqualified hard mask layer 501 may enlarge the via opening VO and/or damage the profile of the via opening VO. In this embodiment, using recoating to repair the defective hard mask layer 501 instead of removing it can reduce or avoid the expansion of the via opening VO or the damage to the profile of the via opening VO.

Referring to FIGS. 13 and 19 , in step S39 , a top hard mask layer 205 may be formed on the bottom filling layer 203 , and a third mask layer 405 may be formed on the top hard mask layer 205 .

Referring to FIG. 19 , a process similar to that shown in FIG. 7 may be used to form the top hard mask layer 205 and the third mask layer 405 , and the description thereof will not be repeated here.

Including removing the third mask layer 405, the manufacturing technology is to recoat the bottom filling layer 203 of the process, forming the top hard mask layer 205, and forming the third mask layer 405 (including patterning the third mask layer 405). This process is called a reworking process of the defective hard mask layer 501 , and is used to avoid the adverse effects of the defective hard mask layer 501 on the produced semiconductor device 1B.

Referring to FIG. 13 , FIG. 20 and FIG. 21 , in step S41 , a trench opening TO may be formed in the dielectric layer 105 .

Referring to FIG. 20 , a process similar to that shown in FIG. 8 may be used to form the hard mask opening 205O, and the description thereof will not be repeated here. A portion of underfill layer 203 is exposed by hard mask opening 205O.

Referring to FIG. 21 , the top hard mask layer 205 and/or the third mask layer 405 can be used as a mask to perform a trench etching process to remove part of the dielectric layer 105 and the underfill layer 203 . In some embodiments, during the trench etch process, the etch rate ratio of the dielectric layer 105 to the top hard mask layer 205 may be between about 100:1 to about 1.05:1 or between about 100:1 to about 10 :1 between. During the trench etch process, the etch rate ratio of the bottom fill layer 203 to the top hard mask layer 205 may be between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. After the trench etching process, trench openings TO may be formed in the dielectric layer 105 . It should be noted that at the current stage, the etch stop layer 103 may still be covered in the channel opening VO by the remaining underfill layer 203 .

Referring to FIGS. 13 and 22 , in step S43 , a punching etching process may be performed to form an extended via opening EVO to expose the substrate 101 .

Referring to FIG. 22 , the punching etching process can remove the remaining underfill layer 203 in the via opening VO and the portion of the etch stop layer 103 exposed through the via opening VO. In some embodiments, during the punch etching process, the etch rate ratio of the underfill layer 203 to the dielectric layer 105 may be between about 100:1 to about 1.05:1 or about 100:1 to about 10:1 between. In some embodiments, during the punch etching process, the etch rate ratio of the etch stop layer 103 to the substrate 101 may be between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. between. After the punch etching process, the via opening VO may be expanded along the dielectric layer 105 and the etch stop layer 103 to expand the via opening EVO. A portion of the substrate 101 may be exposed through the expanded via opening EVO.

In some embodiments, a procedure similar to that shown in FIG. 10 may be used to perform a pre-cleaning process and a cleaning process on the intermediate semiconductor device shown in FIG. 22 , and the description thereof will not be repeated here.

Referring to FIGS. 13 , 23 and 24 , in step S45 , the via hole 107 may be formed in the expanded via hole opening EVO, and the trench 109 may be formed in the trench opening TO.

Referring to FIGS. 23 and 24 , a process similar to that shown in FIGS. 11 and 12 can be used to form the through hole 107 and the trench 109 , and the description thereof will not be repeated here. The substrate 101, the first etching stop layer 103, the dielectric layer 105, the via 107 and the trench 109 jointly configure the semiconductor device 1B.

One aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate; forming a dielectric layer on the substrate; using the first mask layer as a mask to form a through hole in the dielectric layer opening; forming an unqualified hard mask layer to fill the through hole; forming a second mask layer on the unqualified hard mask layer; removing the second mask layer and the unqualified hard mask layer. Form an underfill layer to fill the via opening; form a top hard mask layer on the underfill layer; form a third mask layer on the top hard mask layer; use the third mask layer as Patterning the top hard mask layer for masking; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via hole in the via opening and A trench is formed in the trench opening.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, which includes providing a substrate; forming a dielectric layer on the substrate; using a first mask layer as a mask to form a via in the dielectric layer. hole opening; forming an unqualified hard mask layer to fill the through hole opening; forming a second mask layer on the unqualified hard mask layer; removing the second mask layer; performing a recoating process to The unqualified hard mask layer becomes a bottom filling layer; a top hard mask layer is formed on the bottom filling layer; a third mask layer is formed on the top hard mask layer; the third mask layer is used as Patterning the top hard mask layer for masking; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via hole in the via opening and A trench is formed in the trench opening.

Another aspect of the present disclosure provides a defective hard mask layer disposed on a via opening in a dielectric layer. The reworking method includes removing the defective hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; and forming a mask layer on the top hard mask layer.

Another aspect of the present disclosure provides a defective hard mask layer disposed over a via opening in a dielectric layer. The reworking method includes performing a recoat process to convert the defective hard mask layer into an underfill. layer; forming a top hard mask layer on the bottom fill layer; and forming a mask layer on the top hard mask layer.

Due to the design of the semiconductor device manufacturing method of the present disclosure, by using an underfill layer or an underfill layer, the expansion of the via opening and/or the damage to the profile of the via opening can be reduced or avoided. Therefore, the yield and/or reliability of the semiconductor device can be improved.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and may be substituted for many of the processes described above with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, etc. can be used in accordance with the disclosure to have the same function or achieve substantially the same results as the corresponding embodiments described herein. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1A: Semiconductor components 1B:Semiconductor components 10:Preparation method 30:Preparation method 101: Base 103: Etch stop layer 105: Dielectric layer 107:Through hole 109:Ditch 201: Bottom filling layer 203: Bottom filling layer 205: Top hard mask layer 205O: Hard mask opening 401: First mask layer 403: Second mask layer 405: The third mask layer 501: Unqualified hard mask layer 501R: Groove 503: Conductive material layer EVO: Extended Via Opening S11: Steps S13: Steps S15: Steps S17: Steps S19: Steps S21: Steps S23: Steps S31: Steps S33: Steps S35: Steps S37: Steps S39: Steps S41: Steps S43: Steps S45: Steps T1:Thickness T2:Thickness T3:Thickness T4:Thickness T5:Thickness T6:Thickness TO: ditch opening VO: Through hole opening Z: direction

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 2 to 12 are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG. 13 is a flow chart illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. 14 to 24 are cross-sectional views illustrating a manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

1A: Semiconductor components

101: Base

103: Etch stop layer

105: Dielectric layer

107:Through hole

109:Ditch

EVO: Extended Via Opening

Claims (10)

A rework method that includes: removing a failed hard mask layer from a via opening in a dielectric layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; and A mask layer is formed on the top hard mask layer. The reworking method of claim 1, wherein the underfill layer and the failed hard mask layer include different materials. The reworking method of claim 2, wherein the thickness of the unqualified hard mask layer is different from the thickness of the underfill layer. The reworking method of claim 3, wherein the thickness of the defective hard mask layer is between about 30 nanometers and about 50 nanometers. The reworking method of claim 4, wherein the thickness of the underfill layer is between about 180 nanometers and about 220 nanometers. A rework method that includes: Performing a recoating process to convert a failed hard mask layer over a via opening in a dielectric layer into an underfill layer; forming a top hard mask layer on the underfill layer; and A mask layer is formed on the top hard mask layer. The reworking method of claim 6, wherein the underfill layer and the failed hard mask layer include the same material. The reworking method as claimed in the claim, wherein the thickness of the defective hard mask layer is different from the thickness of the underfill layer. The reworking method of claim 8, wherein the thickness of the failed hard mask layer is between about 30 nanometers and about 50 nanometers. The reworking method of claim 9, wherein the thickness of the underfill layer is between about 180 nanometers and about 220 nanometers.

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