TWI836975B - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A chip package structure includes a lead frame, at least one chip and a protective layer. The lead frame includes at least one die pad and a plurality of lead pads surrounding the die pad. The die pad is a singular metal structure having no metal leads attached to it to maintain its stability, there are also no leads in between the lead pads to ensure a high lead pad density and high number of lead pads. The chip is disposed on the die pad of the lead frame, and electrically connected to the lead pads of the lead frame. The protective layer at least covers the lead frame and exposes the first etched surface and the second etched surface.

Description

Chip packaging structure and manufacturing method thereof

The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof.

In recent years, with the rapid development of electronic technology, the emergence of high-tech electronic industries has made electronic products with better functions more user-friendly and better functions constantly introduced, and the design is trending towards light, thin, short and small. In terms of semiconductor packaging technology, the Quad Flat Package (QFP) or Quad Flat Non-leaded Package (QFN) of the quad flat package series has a shorter signal transmission path and a relatively faster signal transmission speed, so it is one of the mainstream packaging types.

Generally speaking, the lead frame used in the QFN package structure is made by etching a metal sheet to form a chip carrier and multiple pin pads. Due to the thickness limit of the metal sheet, the fan-out line width is larger, and the various parts of the overall structure, such as the chip carrier and multiple pin pads, need to be connected, resulting in a significant reduction in the total number of pin pads.

The present invention provides a chip packaging structure and a manufacturing method thereof. The manufacturing process is simple, and the number of connection pins on the chip can be greatly increased and the manufacturing cost can be reduced.

The chip packaging structure of the present invention includes a lead frame, at least one chip and a protective layer. The lead frame includes at least one chip seat and a plurality of pin pads surrounding the chip seat. The chip seat is a single metal structure, and its edges and corners are not connected to metal wires to maintain its stability, and there are no wires passing between the pin pads, so as to achieve a high pin pad density and a high number of pins on the pin pads. The chip is arranged on the chip seat of the lead frame and is electrically connected to the pin pads of the lead frame. The protective layer at least covers the lead frame and exposes the first etching surface and the second etching surface.

In one embodiment of the present invention, the protective layer is a packaging colloid that covers the lead frame and the chip.

In one embodiment of the present invention, the wafer base has at least one inner surface and at least one outer surface facing each other. The wafer is directly disposed on the inner surface, and the outer surface is a first etching surface.

In one embodiment of the present invention, the chip package structure further includes a plurality of bonding wires electrically connecting the chip and the lead pads.

In an embodiment of the present invention, the above chip packaging structure further includes a plurality of solder balls. The lead frame further includes multiple lines connecting the pin pads. Solder balls are disposed between a surface of each trace and an active surface of the chip. The chip is electrically connected to the pin pad through solder balls. The protective layer covers a back surface of the chip relative to the active surface.

In an embodiment of the present invention, the above-mentioned chip packaging structure further includes an adhesive disposed between the chip and the circuit and covering the solder balls and the circuit.

In an embodiment of the present invention, the above-mentioned protective layer is a solder resist green paint.

In an embodiment of the present invention, the above chip packaging structure further includes a plurality of solder balls. The lead frame further includes multiple lines connecting the pin pads. Solder balls are disposed between a surface of each trace and an active surface of the chip. The chip is electrically connected to the pin pad through solder balls. In an embodiment of the present invention, the above-mentioned chip packaging structure further includes an adhesive disposed between the chip and the circuit and covering the solder balls and the circuit. A back surface of the chip relative to the active surface is exposed to the protective layer and the primer.

The manufacturing method of the chip packaging structure of the present invention includes the following steps. A metal material is electroplated to form a carrier. The carrier includes at least one chip seat, a plurality of pin pads surrounding the chip seat, and a plurality of connection portions connecting the chip seat and the pin pads. At least one chip is arranged on the chip seat of the carrier and is electrically connected to the pin pad of the carrier. After arranging the chip on the chip seat of the carrier, a protective layer is formed to cover the chip, the chip seat and the pin pads, and etching is used to remove part of the chip seat and part of each pin pad connection part of the carrier, and Form a lead frame.

In one embodiment of the present invention, the step of electroplating a metal material to form a carrier includes: providing a substrate, a stainless steel layer and a metal layer. The stainless steel layer is located on the substrate and conformally covers the substrate. The metal layer is formed on the stainless steel layer and conformally covers the stainless steel layer. A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer is used as a plating mask to electroplating a metal material on the metal layer exposed by the patterned photoresist layer. The patterned photoresist layer and the metal layer, stainless steel layer and substrate thereunder are removed to form a carrier.

In one embodiment of the present invention, the step of placing the chip on the chip holder of the carrier and electrically connecting the chip to the pin pads of the carrier includes: attaching the carrier to a table with an adhesive layer, placing the chip on the chip holder of the carrier, and forming a plurality of bonding wires to electrically connect the chip and the pin pads.

In one embodiment of the present invention, after the above-mentioned removal of the connection portion of the carrier, part of the chip holder and part of each pin pad, a protective layer is formed. The protective layer is an encapsulant, and the protective layer covers the carrier and the chip.

In one embodiment of the present invention, the wafer base has at least one inner surface and at least one outer surface facing each other. The wafer is directly disposed on the inner surface, and the outer surface is a first etching surface.

In one embodiment of the present invention, the above-mentioned step of electroplating a metal material to form a carrier includes: providing a base material and a first metal layer, and the first metal layer is formed on the base material. Part of the first metal layer is removed to form at least one first groove and a plurality of second grooves that expose part of the substrate. A stainless steel layer and a second metal layer are formed. The stainless steel layer is located on the first metal layer and the base material and conformally covers the first metal layer, the inner wall of the first groove and the inner wall of the second groove. The second metal layer is formed on the stainless steel layer and conformally covers the stainless steel layer to form the connection portion of this structure. Electroplating metal material on the second metal layer. The metal material filled in the first groove defines a chip seat, and the metal material filled in the second groove defines a pin pad, which is connected to the pin pad and disposed in the first groove and the second groove. The metal material outside the groove defines a plurality of circuits, and the metal material connecting the circuits to the chip holder and the second metal layer below defines a connection portion. The stainless steel layer, the first metal layer below and the substrate are separated from the interface between the second metal layer and the stainless steel layer below to form a carrier.

In one embodiment of the present invention, the step of arranging the chip on the chip seat of the carrier and electrically connecting it to the lead pads of the carrier includes forming a plurality of solder balls on the chip. Arrange the wafer on the wafer holder of the carrier. The solder ball is located between the first surface and an active surface of the chip. The chip is electrically connected to the pin pad through solder balls.

In one embodiment of the present invention, after the chip is arranged on the chip base of the carrier and before the protective layer is formed, a primer is formed between the chip and the circuit to cover the solder balls and the circuit.

In one embodiment of the present invention, the connection portion of the carrier, a portion of the chip base and a portion of each lead pad are removed before forming a protective layer, and the protective layer is a packaging glue body that covers the lead frame, the chip and the bottom glue.

In one embodiment of the present invention, after the connection portion of the carrier, part of the chip base and part of each lead pad are removed to form a lead frame, a protective layer is formed to cover the bottom of the lead frame and expose the first etching surface and the second etching surface. The protective layer is a solder mask green paint and is connected to the primer.

Based on the above, in the chip package structure and the manufacturing method of the present invention, the carrier is formed by electroplating metal materials, and after the chip is arranged on the chip seat of the carrier, the connection part of the carrier is removed to form a lead frame. In the prior art, the lead frame is formed by etching a metal sheet. In order to maintain the connectivity of its structure, the chip seat and each inner ring pin pad need to pass through the outer ring pin pad to the outermost ring annular connection ring through the extra wiring. The number of the outer ring pin pads is reduced, thereby reducing the application range of the chip. The chip packaging structure and the manufacturing method thereof of the present invention achieve the connectivity of the carrier through the connecting portion, and do not require the chip seat to be connected to the external ring with a wire, nor do they require the inner layer pin pads to pass through the wires between the outer layer pin pads, thereby increasing the number of outer layer pin pads and thus expanding the application range of the chip.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

FIG. 1A to FIG. 1G are cross-sectional schematic diagrams of a method for manufacturing a chip package structure according to an embodiment of the present invention. Regarding the method for manufacturing the chip package structure of the present embodiment, first, please refer to FIG. 1A, and provide a substrate 10, a stainless steel layer 12, and a metal layer 14. The stainless steel layer 12 is located on the substrate 10 and conformally covers the substrate 10. The metal layer 14 is formed on the stainless steel layer 12 and conformally covers the stainless steel layer 12. Here, the substrate 10 can be, for example, a core substrate, which is composed of a sheet-like fiberglass resin base and copper foils disposed on opposite sides of the sheet-like fiberglass resin base, and can be regarded as a hard board, but is not limited to this.

1B, a patterned photoresist layer 16 is formed on the metal layer 14, wherein the patterned photoresist layer 16 exposes a portion of the metal layer 14. In one embodiment, the thickness of the patterned photoresist layer 16 is, for example, 56 micrometers, but is not limited thereto.

Next, referring to FIG. 1C , the patterned photoresist layer 16 is used as a plating mask to electroplate a metal material M on the metal layer 14 exposed by the patterned photoresist layer 16 .

Next, please refer to FIG. 1C, FIG. 1D and FIG. 1E at the same time, remove the patterned photoresist layer 16, and attach it to the carrier 110 through, for example, ultraviolet tape, and separate the stainless steel layer 12 and the metal layer 14 by a soft transfer plate, and remove the substrate 10 and the stainless steel layer 12 thereon, so that the carrier 110 is formed. At this time, the carrier 110 includes at least one chip seat (two chip seats 112a are schematically shown), a plurality of lead pads 114a surrounding the chip seat 112a, and a plurality of connecting portions 116a connecting the chip seat 112a and the lead pads 114a. At this point, the step of using the electroplated metal material M to form the carrier 110 has been completed. It should be noted that since the removed substrate 10 is not cut, it can be reused, which can effectively reduce the manufacturing cost.

Next, please refer to FIG. 1E again, the carrier 110 is attached to the table top 20 having an adhesive layer 22 . In one embodiment, the table 20 is a platform used by a packaging factory for mass production, but it is not limited to this.

1F, at least one chip (two chips 120a are schematically shown) is placed on the chip seat 112a of the carrier 110, and a plurality of bonding lines 130a are formed to electrically connect the chip 120a and the pin pads of the carrier 110. 114a. Here, the back side of the chip 120a can directly contact the chip holder 112a or be fixed on the wafer holder 112a through a die attach film (DAF). In short, in this embodiment, the active surface of the chip 120a and the pin pads 114a of the carrier 110 are electrically connected through bonding wires 130a. In one embodiment, the length of the bonding line 130a may be, for example, 3 mm, but is not limited thereto.

Afterwards, please refer to FIG. 1F again, a protective layer 140a is formed to at least cover the carrier 110. Here, the protective layer 140a is, for example, an encapsulant, wherein the protective layer 140a covers the carrier 110, the chip 120a and the bonding wire 130a.

Finally, please refer to FIG. 1F and FIG. 1G at the same time, the table 20, the adhesive layer 22, the connecting portion 116a of the carrier 110, a portion of the chip base 112a, and a portion of each pin pad 114a are removed to form a lead frame 110a. Here, for example, the table 20 and the adhesive layer 22 thereon are removed by disassembling the board, and the method of removing the connecting portion 116a of the carrier 110, a portion of the chip base 112a, and a portion of each pin pad 114a is, for example, etching. At this time, the lead frame 110a includes the chip base 112a and the pin pads 114a surrounding the chip base 112a, which means that the lead frame 110a of this embodiment does not have a trace. The wafer base 112a has an inner surface S1 and an outer surface (i.e., a first etched surface S2) opposite to each other, wherein the wafer 120a can be directly disposed on the inner surface S1. In an embodiment not shown, the first etched surface S2 of the wafer base 112a and the second etched surface 115a of the lead pad 114a can also be subjected to a surface treatment to form a surface treatment layer (e.g., tin) thereon to prevent oxidation of the first etched surface S2 of the wafer base 112a and the second etched surface 115a of the lead pad 114a. Since the connection portion 116a of the carrier 110 is removed after the protective layer 140a is formed in this embodiment, the overall structure can have a better supporting force, which can improve the structural reliability of the overall structure. At this point, the manufacturing of the QFN type chip package structure 100a has been completed.

In one embodiment, when the length of the bonding line 130a is, for example, 3 mm, the size of the pin pad 114a is, for example, 0.23 mm×0.4 mm, and the distance between the die base 112a and the pin pad 114a is 0.5 mm. At that time, in a 5X6 matrix, when the area is 5 mm X 5 mm, there can be 341 pin pads; when the area is 10 mm That is, this embodiment can be used with high-density chips.

Structurally, please refer to FIG. 1G again. In this embodiment, the chip package structure 100a includes a lead frame 110a, a chip 120a, and a protective layer 140a. The lead frame 110a includes a chip base 112a and pin pads 114a surrounding the chip base 112a. The chip base 112a has a first etched surface S2, and each pin pad 114a has a second etched surface 115a. The chip base 112a is a single metal structure, and there are no metal wires connected to its edges and corners to maintain its stability. There are no wires passing between the pin pads 114a, so as to achieve a high pin pad density and a high number of pin pads. The chip 120a is disposed on the chip base 112a of the lead frame 110a and is electrically connected to the lead pad 114a of the lead frame 110a. The protective layer 140a at least covers the lead frame 110a and exposes the first etched surface S2 and the second etched surface 115a.

More specifically, the chip base 112a of the present embodiment has an inner surface S1 and an outer surface (i.e., a first etched surface S2) facing each other, wherein the chip 120a can be directly disposed on the inner surface S1. Furthermore, the chip package structure 100a of the present embodiment further includes a bonding wire 130a electrically connected to the chip 120a and the lead pad 114a. In addition, the protective layer 140a of the present embodiment is embodied as a packaging gel, covering the lead frame 110a, the chip 120a and the bonding wire 130a.

In this embodiment, the carrier 110 is formed by electroplating the metal material M, and after the chip 120a is placed on the chip seat 112a of the carrier 110, the connecting portion 116a of the carrier 110 is removed to form the lead frame 110a. Compared with the prior art of etching metal sheets to form a lead frame, the chip packaging structure 100a and its manufacturing method of this embodiment have a simple manufacturing process, which can effectively significantly increase the number of pin pads and reduce manufacturing costs. cost.

It should be noted that the following embodiments use the component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

2A to 2G are schematic cross-sectional views of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. Regarding the manufacturing method of the chip packaging structure of this embodiment, first, please refer to FIG. 2A to provide a base material 30 and a first metal layer 40 , wherein the first metal layer 40 is formed on the base material 30 . Here, the substrate 30 can be, for example, a core substrate, which is composed of a sheet-shaped fiberglass resin substrate and copper foils disposed on opposite sides of the sheet-shaped fiberglass resin substrate, and can be regarded as a hard substrate. board, but not limited to this. The thickness of the first metal layer 40 is, for example, 60 microns, where the first metal layer 40 is, for example, a copper layer. It should be noted that this embodiment only schematically illustrates a single-sided process. In another embodiment, a double-sided process may also be adopted based on process requirements, which still falls within the scope of the present invention.

Next, please refer to FIG. 2B to remove part of the first metal layer 40 to form at least one first groove (schematically showing one first groove 42 ) and a plurality of second grooves that expose part of the base material 30 . slot 44. Here, the method of removing part of the first metal layer 40 is, for example, etching.

Next, referring to FIG. 2B , a stainless steel layer 50 and a second metal layer 60 are formed. The stainless steel layer 50 is located on the first metal layer 40 and the substrate 30 and conformally covers the first metal layer 40, the inner wall of the first groove 42, and the inner wall of the second groove 44. The second metal layer 60 is formed on the stainless steel layer 50 and conformally covers the stainless steel layer 50.

Next, please refer to FIG. 2C , a metal material 70 is electroplated on the second metal layer 60, wherein the metal material 70 filled in the first groove 42 can define the chip base 112b, and the metal material 70 filled in the second groove 44 can define the lead pad 114b. The metal material 70 connected to the lead pad 114b and arranged outside the first groove 42 and the second groove 44 can define a plurality of lines 118b. The metal material 70 connecting the line 118b and the chip base 112b and the second metal layer 60 thereunder define a connecting portion 116b. At this time, the chip base 112b is connected to the lead pad 114b through the connecting portion 116b and the line 118b. In one embodiment, the thickness of the metal material 70 is, for example, 70 microns, but is not limited thereto. In an embodiment not shown, the chip base 112b, the lead pads 114b and the circuits 118b may also be surface treated to form a surface treatment layer thereon to prevent oxidation.

Next, please refer to FIG. 2D , an ultraviolet tape is attached to the structure of FIG. 2C , and the stainless steel layer 50 and the second metal layer 60 are separated by a soft transfer plate, and the stainless steel layer 50 , the first metal layer 40 and the substrate 30 are removed, thereby forming a carrier 110 ′.

Next, please refer to FIG. 2E. This rotating plate structure is placed on a conventional table 20 of the packaging manufacturer. The adhesive layer 22 on the upper surface has adhesive properties so that the chip holder 112b and the pin pad 114b can be tightly connected to the table 20. Next, a plurality of solder balls 150b are formed on the chip 120b. The chip 120b is disposed on the chip seat 112b of the carrier 110', wherein the solder ball 150b is located between a surface 119b of each trace 118b and an active surface 121b of the chip 120b. The chip 120b is electrically connected to the pin pad 114b through the solder ball 150b and the circuit 118b. At this time, the chip 120b is not in direct contact with the chip holder 112b. However, the chip 112b still has a thermal conductive function and can transfer the heat energy generated by the chip 120b to the chip holder 112b through the solder ball 150b and the circuit 118b, and then to the outside for heat dissipation. Next, an undercoat 160b is formed in the gaps between the chip 120b and the circuit 118b, between the chip 120b and the chip seat 112b, and between the circuits 118b to cover the solder ball 150b, the circuit 118b and the carrier 110' relatively adjacent to the chip 120b. of the front.

Afterwards, please refer to FIG. 2E and FIG. 2F at the same time. Micro-etching is used to remove the connection portion 116b of the carrier 110', part of the chip seat 112b and part of each pin pad 114b from the back side of the carrier 110' to form a Leadframe 110b. At this time, the chip holder 112b has a first etching surface S2', and each pin pad 114b has a second etching surface 115b.

Finally, referring to FIG. 2G , a protective layer 140b is formed to at least cover the lead frame 110b and expose the first etched surface S2′ and the second etched surface 115b. Here, the connection portion 116b of the carrier 110′, a portion of the chip base 112b, and a portion of each lead pad 114b are removed before forming the protective layer 140b, and the protective layer 140b is embodied as a packaging glue body and covers the lead frame 110b, the chip 120b, and the bottom glue 160b. Here, the periphery of the protective layer 140b is aligned with the periphery of the bottom glue 160b and the periphery of the lead frame 110b. At this point, the manufacture of the chip package structure 100b of the quad flat no external lead (QFN) type has been completed.

Structurally, please refer to FIG. 2G . In this embodiment, the chip package structure 100b includes a lead frame 110b, a chip 120b, and a protective layer 140b. The lead frame 110b includes a chip base 112b, a pin pad 114b surrounding the chip base 112b, and a line 118b connecting the pin pad 114b and connecting the pin pad 114b and the chip base 112b. The chip base 112b has a first etched surface S2′, and each pin pad 114b has a second etched surface 115b. The chip 120b is disposed on the chip base 112b of the lead frame 110b and is electrically connected to the pin pad 114b of the lead frame 110b. The protection layer 140b at least covers the lead frame 110b and exposes the first etched surface S2' and the second etched surface 115b.

More specifically, in this embodiment, the chip holder 112b and the pin pads 114b are located on the same plane, and the line 118b, such as a fan-out line, is located above the chip holder 112b and the pin pads 114b and the orthographic projection is incomplete. overlap. Chip package structure 100b also includes solder balls 150b. Solder ball 150b is disposed between surface 119b of each trace 118b and active surface 121b of die 120b. The chip 120b is electrically connected to the pin pad 114b through the solder ball 150b. The protective layer 140b covers the back surface 123b of the wafer 120b relative to the active surface 121b. In addition, the chip packaging structure 100b also includes an undercoat 160b, which is disposed between the chip 120b and the circuit 118b and covers the solder ball 150b and the circuit 118b.

In this embodiment, the carrier 110' is formed by electroplating the metal material 70, and after the chip 120b is placed on the chip seat 112b of the carrier 110', the connecting portion 116b of the carrier 110' is removed to form the lead frame 110b. . Compared with the prior art of etching metal sheets to form a lead frame, the chip packaging structure 100a and its manufacturing method of this embodiment have a simple manufacturing process and can effectively significantly increase the number of pin pads 114b on the chip. Just below 120b and below and outside of chip 120b. Since the lead frame 110b is formed by electroplating, the line width/line spacing of the lines 118b of the lead frame 110b can be, for example, 35 microns/35 microns, which can increase the number of fan-out rows of the pin pads 114b.

FIG. 2H is a schematic cross-sectional view of a chip packaging structure according to an embodiment of the present invention. Please refer to FIG. 2G and FIG. 2H at the same time. The chip packaging structure 100c of this embodiment is similar to the chip packaging structure 100b in FIG. 2G. The main difference between the two is that in this embodiment, the protective layer 140c is embodied as a Solder resist green paint, and the protective layer 140c is connected to the primer 160b. Here, the back surface 123b of the chip 120b relative to the active surface 121b is exposed to the protective layer 140b and the base glue 160b. This structure can reduce the thickness of the packaged product and achieve the goal of being light, thin and compact.

To sum up, in the chip packaging structure and its manufacturing method of the present invention, the carrier is formed by electroplating metal materials, and after the chip is placed on the chip seat of the carrier, the connecting portion of the carrier is removed, and Form a leadframe. Compared with the prior art of etching metal sheets to form lead frames, the chip packaging structure and its manufacturing method of the present invention have a simple manufacturing process and can greatly increase the density and row number of pin pads, so that the Use higher chip pin count.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10, 30: substrate 12, 50: stainless steel layer 14: metal layer 16: patterned photoresist layer 20: countertop 22: adhesive layer 40: first metal layer 42: first groove 44: second groove 60: second metal layer 70, M: metal material 100a: chip packaging structure 110, 110': carrier 110a, 110b: lead frame 112a, 112b: chip holder 114a, 114b: lead pad 115a, 115b: second etched surface 116a, 116b: connection part 118b: circuit 119b: surface 120a, 120b: chip 121b: active surface 123b: back surface 130a: wire bonding 140a, 140b, 140c: protective layer 141a, 141b: bottom surface 150b: solder ball 160b: bottom glue S1: inner surface S2, S2’: first etched surface

Figures 1A to 1G are schematic cross-sectional views of a method for manufacturing a chip packaging structure according to an embodiment of the present invention. Figures 2A to 2G are schematic cross-sectional views of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. Figure 2H is a schematic cross-sectional view of a chip packaging structure according to an embodiment of the present invention.

20: Countertop

22: Adhesive layer

110b: Conductor frame

112b: chip holder

114b: Pin pad

115b: Second etching surface

118b:line

119b: Surface

120b: chip

121b: Active surface

150b: Solder ball

160b: Base glue

S2’: first etched surface

Claims (19)

A chip packaging structure includes: A lead frame includes at least one chip holder and a plurality of pin pads surrounding the at least one wafer holder, wherein the at least one wafer holder has at least a first etched surface, and each of the pin pads has a second etched surface On the surface, the at least one chip holder is a single metal structure, with no metal wires connected to its edges and corners to maintain its stability, and no wires passing between the pin pads; At least one chip is disposed on the at least one chip seat of the lead frame and is electrically connected to the pin pads of the lead frame; and A protective layer covers at least the lead frame and exposes the at least one first etched surface and the second etched surface. The chip packaging structure of claim 1, wherein the protective layer is a packaging colloid covering the lead frame and the at least one chip. The chip packaging structure of claim 2, wherein the at least one chip holder has at least one inner surface and at least one outer surface opposite to each other, the at least one chip is directly disposed on the at least one inner surface, and the at least one outer surface The surface is the at least one first etching surface. The chip packaging structure as described in claim 2 further includes: A plurality of bonding wires are electrically connected to the at least one chip and the pin pads. The chip packaging structure as described in claim 2 further includes: A plurality of solder balls, the lead frame further includes a plurality of circuits connected to the pin pads, the solder balls are arranged between a surface of each circuit and an active surface of the at least one chip, the at least one chip The solder balls are electrically connected to the pin pads, and the protective layer covers a back surface of the at least one chip relative to the active surface. The chip packaging structure as described in claim 5 further includes: An undercoat is disposed between the at least one chip and the circuits, and covers the solder balls and the circuits. The chip packaging structure of claim 1, wherein the protective layer is a solder resist green paint. The chip packaging structure as described in claim 7 further includes: A plurality of solder balls, the lead frame further includes a plurality of circuits connected to the pin pads, the solder balls are arranged between a surface of each circuit and an active surface of the at least one chip, and the at least one The chip is electrically connected to the pin pads through the solder balls. The chip package structure as described in claim 8 further includes: A primer, disposed between the at least one chip and the circuits, and covering the solder balls and the circuits, wherein a back surface of the at least one chip relative to the active surface is exposed outside the protective layer and the primer. A method for manufacturing a chip packaging structure, including: Electroplating a metal material to form a carrier, the carrier including at least one chip seat, a plurality of pin pads surrounding the at least one chip seat, and a plurality of connection portions connecting the at least one chip seat and the pin pads; disposing at least one chip on the at least one chip holder of the carrier and electrically connecting with the pin pads of the carrier; After disposing the at least one chip on the at least one chip holder of the carrier, removing the connection portions of the carrier, part of the at least one chip holder and part of each of the pin pads to form a lead frame, wherein The at least one die pad has at least a first etched surface, and each of the pin pads has a second etched surface; and A protective layer is formed to cover at least the lead frame and expose the at least one first etched surface and the second etched surface. The manufacturing method of the chip packaging structure as described in claim 10, wherein the step of electroplating the metal material to form the carrier includes: Providing a substrate, a stainless steel layer and a metal layer, the stainless steel layer is located on the substrate and conformally covers the substrate, and the metal layer is formed on the stainless steel layer and conformally covers the stainless steel layer; Forming a patterned photoresist layer on the metal layer; Using the patterned photoresist layer as a plating mask, electroplating the metal material on the metal layer exposed by the patterned photoresist layer; and Removing the patterned photoresist layer and the metal layer, the stainless steel layer and the substrate thereunder to form the carrier. The manufacturing method of the chip package structure as described in claim 10, wherein the step of configuring the at least one chip on the at least one chip seat of the carrier and electrically connecting the at least one chip to the pin pads of the carrier includes: Attaching the carrier to a table having an adhesive layer; Configuring the at least one chip on the at least one chip seat of the carrier; and Forming a plurality of bonding wires to electrically connect the at least one chip and the pin pads. The manufacturing method of a chip packaging structure as claimed in claim 11, wherein after removing the connection portions of the carrier, part of the at least one chip seat and part of each of the pin pads and forming the protective layer, the protective layer is An encapsulating colloid is provided, and the protective layer covers the carrier and the at least one chip. A method for manufacturing a chip packaging structure as described in claim 13, wherein the at least one chip seat has at least one inner surface and at least one outer surface opposite to each other, the at least one chip is directly configured on the at least one inner surface, and the at least one outer surface is the at least one first etching surface. The manufacturing method of the chip packaging structure as described in claim 10, wherein the step of electroplating the metal material to form the carrier includes: Providing a substrate and a first metal layer, the first metal layer is formed on the substrate; Removing a portion of the first metal layer to form at least one first groove and a plurality of second grooves that expose a portion of the substrate; Forming a stainless steel layer and a second metal layer, the stainless steel layer is located on the first metal layer and the substrate and conformally covers the first metal layer, the inner wall of the at least one first groove and the inner walls of the second grooves, and the second metal layer is formed on the stainless steel layer and conformally covers the stainless steel layer; Electroplating the metal material on the second metal layer, the metal material filled in the at least one first groove defines the at least one chip seat, and the metal material filled in the second grooves defines the lead pads, the metal material connecting the lead pads and arranged outside the at least one first groove and the second grooves defines a plurality of circuits, and the metal material connecting the circuits and the at least one chip seat and the second metal layer thereunder defines the connecting parts; and Separating the stainless steel layer from the first metal layer thereunder and the substrate from the interface between the second metal layer and the stainless steel layer thereunder to form the carrier. The manufacturing method of the chip package structure as described in claim 15, wherein the step of configuring the at least one chip on the at least one chip seat of the carrier and electrically connecting it to the pin pads of the carrier includes: forming a plurality of solder balls on the at least one chip; and configuring the at least one chip on the at least one chip seat of the carrier, the solder balls being located between a surface of each of the circuits and an active surface of the at least one chip, and the at least one chip being electrically connected to the pin pads through the solder balls. The manufacturing method of the chip packaging structure as described in claim 16 further includes: After arranging the at least one chip on the at least one chip seat of the carrier and before forming the protective layer, an undercoat is formed between the at least one chip and the circuits to cover the solder balls and the circuits. some lines. The manufacturing method of a chip packaging structure as claimed in claim 17, wherein the connection portions of the carrier, part of the at least one chip seat and part of each of the pin pads are removed before forming the protective layer, and the protective layer It is a packaging colloid that covers the lead frame, the at least one chip and the base glue. The manufacturing method of a chip packaging structure as claimed in claim 17, wherein the connecting portions of the carrier, part of the at least one chip seat and part of each of the pin pads are removed to form a protective layer after forming the lead frame. Cover the bottom of the lead frame and expose the at least one first etched surface and the second etched surface, and the protective layer is a solder resist green paint, and the protective layer is connected to the primer.

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