TWI831526B - Bandgap reference circuit and method of generating reference voltage and reference current simultaneously - Google Patents

Abstract

The present disclosure provides a bandgap reference circuit including a common circuit, a current compensation circuit, a voltage locking circuit, and a current mirror circuit. The common circuit includes a first resistor, a second resistor, and a first transistor in series connected from an output terminal. The output terminal is used to output a reference circuit. A first branch of the current mirror circuit is connected with the output terminal, and used to provide a parallel current. A second branch of the current mirror circuit is used to output a reference current. The current compensation circuit is used to make a current generated in the current compensation circuit have an opposite temperature coefficient to a current generated in the common circuit. The voltage locking circuit is used to make a voltage difference between two ends of the second resistor have an opposite temperature coefficient to a voltage at the emitter of the first transistor. The present disclosure also provides a method of generating a reference voltage and a reference current simultaneously.

Description

Band difference reference circuit and method of generating reference voltage and reference current simultaneously

This case relates to the field of bandgap reference circuits, especially to bandgap reference circuits and methods that simultaneously generate reference voltages and reference currents.

Conventional band difference reference circuits usually need to provide temperature-independent reference voltages and reference currents. However, these circuits can usually only generate reference voltages or reference currents independently, but cannot generate reference voltages and reference currents at the same time. Therefore, they are usually Separate circuits for generating reference voltages and circuits for generating reference currents will double the number of components, thereby increasing energy consumption.

On the one hand, this case provides a band difference reference circuit, including: a common circuit, the common circuit includes a first resistor, a second resistor and a first transistor connected in series from an output end, and the base of the first transistor and The collector is grounded, the emitter of the first transistor and the second resistor are connected to the current compensation terminal, the second resistor and the first resistor are connected to the voltage locking terminal, and the output terminal is used to output a reference voltage; current compensation circuit, including one end connected to the output terminal and a ground terminal; voltage locking circuit, including one end connected to the output terminal and a ground terminal; and a current mirror circuit, the first branch of the current mirror circuit The second branch of the current mirror circuit is used to output a reference current. The parallel current is equal to the common circuit, the current compensation circuit and the voltage lock. The sum of the currents of the circuit; the reference current is equal to or proportional to the parallel current; wherein the current compensation circuit also includes an end connected to the current compensation end, and the current compensation circuit is used to make The current generated on the current compensation circuit and the current generated on the common circuit has an opposite temperature coefficient; the voltage locking circuit also includes an end connected to the voltage locking terminal, the voltage locking circuit is used to make the voltage difference across the second resistor and the emitter of the first transistor Voltage has opposite temperature coefficients.

The band difference reference circuit provided in the embodiment of this case can make the voltage difference between the two ends of the second resistor on the common circuit and the voltage of the emitter of the first transistor have the opposite effect by setting up a common circuit and setting up a voltage locking circuit to connect to the common circuit. temperature coefficient, so that the reference voltage output by the common circuit at the output end is a voltage that offsets the temperature coefficient. By configuring the current compensation circuit to be connected to the common circuit, the current generated on the current compensation circuit and the current generated on the common circuit can have opposite temperature coefficients, so that the parallel current passing through the output end is a current that has offset the temperature coefficient. By setting up a current mirror circuit, the same current as the first branch of the current mirror circuit can be output on the second branch of the current mirror circuit, that is, a reference current can be output. Therefore, the band difference reference circuit of this embodiment can simultaneously output a reference voltage and a reference current that offset the temperature coefficient by setting up a common circuit. Compared with the conventional circuit, it saves the number of components, reduces energy consumption and cost.

In one embodiment, the current compensation circuit includes a metal oxide half field effect transistor, a third resistor and a first amplifier. The drain of the metal oxide half field effect transistor is connected to the output end. The metal oxide half field effect transistor is connected to the output terminal. The source of the effect transistor is connected to one end of the third resistor and the negative input end of the first amplifier, and the gate of the metal oxide half field effect transistor is connected to the output end of the first amplifier; The other end of the third resistor is grounded; the positive input end of the first amplifier is connected to the current compensation end; the voltage lock end includes a fourth resistor, a second transistor and a second amplifier, and the fourth resistor One end is connected to the output end, and the other end of the fourth resistor is connected to the negative input end of the second amplifier and the emitter of the second transistor; the base and collector of the second transistor Ground; the positive input terminal of the second amplifier is connected to the voltage lock terminal.

In one embodiment, the band difference reference circuit further includes an adjustment circuit for adjusting the resistance values of the first resistor, the second resistor, the third resistor and the fourth resistor.

In one embodiment, the reference voltage is expressed as: V _REF =V _BE1 +△V _BE2,1 (1+R1/R2); where V _BE1 is the voltage of the emitter of the first transistor, △V _BE2,1 is the voltage difference across the second resistor, R1 is the resistance of the first resistor, and R2 is the resistance of the second resistor.

In one embodiment, the reference current is expressed as: I _REF =nI _P =n[V _BE1 /R3+(1+R1/R4)(△V _BE2,1 /R2)]; where _IP is passed by the The parallel current at the output end, n is the ratio between the reference current and the parallel current and is a positive number, V _BE1 is the voltage of the emitter of the first transistor, R3 is the resistance of the third resistor, R1 is the resistance of the first resistor, R4 is the resistance of the fourth resistor, ΔV _BE2,1 is the voltage difference across the second resistor, and R2 is the resistance of the second resistor.

In one embodiment, the resistance values of the first resistor and the fourth resistor are equal, and the reference current is expressed as: I _REF =nI _P =n[V _BE1 /R3+2(ΔV _BE2,1 / R2)]; where _IP is the parallel current passing through the output terminal, n is the ratio between the reference current and the parallel current and is a positive number, V _BE1 is the voltage of the emitter of the first transistor, R3 is the resistance of the third resistor, ΔV _BE2,1 is the voltage difference across the second resistor, and R2 is the resistance of the second resistor.

On the other hand, the embodiment of the present case provides a method for generating a reference voltage and a reference current at the same time, including: providing a common circuit, the common circuit including a first resistor, a second resistor and a first transistor connected in series from an output end. The base and collector of the first transistor are grounded, the emitter of the first transistor and the second resistor are connected to the current compensation terminal, and the second resistor and the first resistor are connected to a voltage locking terminal; a voltage locking circuit is provided, the voltage locking circuit includes an end connected to the output terminal, a ground terminal and an end connected to the voltage locking end; a current compensation circuit is provided, the current compensation circuit includes the The end connected to the output end, the ground end and the end connected to the current compensation end; lock the voltage of the voltage lock end so that the voltage difference between the two ends of the second resistor is equal to the voltage of the emitter of the first transistor having an opposite temperature coefficient; outputting a reference voltage at the output terminal; generating a current having an opposite temperature coefficient to the current on the common circuit on the current compensation circuit; and providing a current mirror circuit to convert the current The first branch of the mirror circuit is connected to the output terminal, and a reference current is output in the second branch of the current mirror circuit.

The method of generating a reference voltage and a reference current at the same time provided by the embodiment of this case provides a common circuit and sets a voltage locking circuit to connect to the common circuit, so that the voltage difference across the second resistor on the common circuit can be matched with the radiation of the first transistor. pole voltages have opposite temperature coefficients, causing the common The reference voltage output by the circuit at the output terminal is a voltage that offsets the temperature coefficient. By providing a current compensation circuit connected to the common circuit, the current generated on the current compensation circuit and the current generated on the common circuit can have opposite temperature coefficients, so that the parallel current passing through the output end is a current that has offset the temperature coefficient. By setting up a current mirror circuit, the same current as the first branch of the current mirror circuit can be output on the second branch of the current mirror circuit, that is, a reference current can be output. Therefore, the band difference reference circuit of this embodiment can simultaneously output a reference voltage and a reference current that offset the temperature coefficient by setting up a common circuit. Compared with the conventional circuit, it saves the number of components, reduces energy consumption and cost.

In one embodiment, providing a current compensation circuit includes providing a metal oxide half field effect transistor, a third resistor and a first amplifier. The drain of the metal oxide half field effect transistor is connected to the output terminal. The metal oxide half field effect transistor is connected to the output terminal. The source of the effect transistor is connected to one end of the third resistor and the negative input end of the first amplifier, and the gate of the metal oxide half field effect transistor is connected to the output end of the first amplifier; The other end of the third resistor is grounded; the positive input terminal of the first amplifier is connected to the current compensation terminal; and providing the voltage locking circuit includes providing a fourth resistor, a second transistor and a second amplifier, the fourth resistor One end of the fourth resistor is connected to the output end, and the other end of the fourth resistor is connected to the negative input end of the second amplifier and the emitter of the second transistor; the base and collector of the second transistor The positive input terminal of the second amplifier is connected to the voltage lock terminal.

In one embodiment, the reference voltage is expressed as: V _BEF =V _BE1 + △V _BE2,1 (1+R1/R2); where V _BE1 is the voltage of the emitter of the first transistor, △V _BE2,1 is the voltage difference across the second resistor, R1 is the resistance of the first resistor, R2 is the resistance of the second resistor; and outputting the reference voltage at the output terminal includes: adjusting the The resistance values of the first resistor and the second resistor are such that the reference voltage is a voltage with zero temperature coefficient.

In one embodiment, the reference current is expressed as: I _REF =nI _P =n[V _BE1 /R3+(1+R1/R4)(ΔV _BE2,1 /R2)]; where I _P is passed by the The parallel current at the output end, n is the ratio between the reference current and the parallel current and is a positive number, V _BE1 is the voltage of the emitter of the first transistor, R3 is the resistance of the third resistor, R1 is the resistance of the first resistor, R4 is the resistance of the fourth resistor, ΔV _BE2,1 is the voltage difference across the second resistor, R2 is the resistance of the second resistor; and Outputting the reference current in the second branch of the current mirror circuit includes: adjusting the resistance values of the first resistor, the second resistor, the third resistor and the fourth resistor, so that the reference current is A current with zero temperature coefficient.

In one embodiment, the resistance values of the first resistor and the fourth resistor are equal, and the reference current is expressed as: I _REF =nI _P =n[V _BE1 /R3+2(ΔV _BE2,1 / R2)]; where _IP is the parallel current passing through the output terminal, n is the ratio between the reference current and the parallel current and is a positive number, V _BE1 is the voltage of the emitter of the first transistor, R3 is the resistance of the third resistor, △V _BE2,1 is the voltage difference across the second resistor, R2 is the resistance of the second resistor; and in the second branch of the current mirror circuit Outputting the reference current includes: adjusting the resistance values of the second resistor and the third resistor so that the reference current is a current with zero temperature coefficient.

100: Band difference reference circuit

1: Current mirror circuit

10:The first branch

11:Public circuit

13: Current compensation circuit

15: Voltage lock circuit

30:Second branch

R1: first resistor

R2: second resistor

R3: The third resistor

R4: The fourth resistor

Q1: The first transistor

Q2: Second transistor

OP1: first amplifier

OP2: Second amplifier

M1, M2, M3: metal oxide half field effect transistor

V ₁ , V ₄ : endpoints

V ₂ : Current compensation terminal

V ₃ : voltage lock terminal

V _DD : power supply voltage terminal

P: output terminal

V _REF : reference voltage

_IP : Parallel current

I _REF : reference current

I _PTAT : Common current

I _CTAT : first current

I ₂ : second current

S1, S2, S3, S4, S5, S6, S7: steps

Figure 1 is a schematic diagram of a band difference reference circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a band difference reference circuit according to an embodiment of the present invention.

FIG. 3 is a flow chart of a method for generating a reference voltage and a reference current simultaneously according to an embodiment of the present invention.

The technical solutions in the embodiments of this case will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this case. Obviously, the described embodiments are part of the embodiments of this case, rather than all of the embodiments.

Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by a person skilled in the art belonging to the subject matter. The terms used in the description of this case are only for the purpose of describing specific embodiments and are not intended to limit this case.

In order to further elaborate on the technical means and effects adopted by the present invention to achieve the intended purpose, the case is described in detail below in conjunction with the accompanying drawings and preferred embodiments.

This embodiment provides a band difference reference circuit. Please refer to FIGS. 1 and 2 together. The band difference reference circuit 100 includes a common circuit 11 , a current compensation circuit 13 , a voltage locking circuit 15 and a current mirror circuit 1 . Among them, the common circuit 11 includes a first resistor R1, a second resistor R2 and a first transistor Q1 connected in series from an output terminal P. The first resistor R1 and the second resistor R2 are connected to the voltage locking terminal V ₃ . The base and collector of the crystal Q1 are grounded, the emitter of the first transistor Q1 and the second resistor R2 are connected to the current compensation terminal V ₂ , and the output terminal P is used to output the reference voltage _VREF . The current compensation circuit 13 includes one end connected to the output terminal P and a ground terminal. The voltage lock circuit 15 includes one end connected to the output terminal P and a ground terminal. The first branch 10 of the current mirror circuit 1 is connected to the output terminal P to provide a parallel current _IP . The second branch 30 of the current mirror circuit 1 is used to output the reference current I _REF . The parallel current _IP is equal to the current of the common circuit 11 and The reference current I _REF , the sum of the currents of the compensation circuit 13 and the voltage locking circuit 15, may be equal to the parallel current _IP or proportional to the parallel current _IP . For example, the ratio between the reference current I _REF and the parallel current _IP can be 0.8, 1, 1.5, 2, 4, etc.

In this embodiment, the current compensation circuit 13 is also connected to the current compensation terminal V ₂ with the common circuit 11, so that the first current I _CTAT generated on the current compensation circuit 13 and the common current I _PTAT generated on the common circuit 11 have the same relationship. Opposite temperature coefficient. For example, the common current I _PTAT has a positive temperature coefficient and the first current I _CTAT has a negative temperature coefficient. The voltage locking circuit 15 is also connected to the voltage locking terminal V ₃ with the common circuit 11 for making the voltage difference across the second resistor R2 and the voltage of the emitter of the first transistor Q1 have an opposite temperature coefficient. For example, the voltage difference across the second resistor R2 has a positive temperature coefficient, and the voltage at the emitter of the first transistor Q1 has a negative temperature coefficient.

In this embodiment, the current mirror circuit 1 includes a power supply voltage terminal V _DD as a power supply. The first branch 10 includes a metal oxide half field effect transistor M1. The source of the metal oxide half field effect transistor M1 is connected to the power supply voltage terminal V _DD. connection, the drain is connected to the common circuit 11, the current compensation circuit 13 and the voltage locking circuit 15 that are commonly connected to the output terminal P to provide a parallel current _IP flowing through the output terminal P. The second branch 30 includes a metal oxide semi-field effect transistor M2. The source of the metal oxide semi-field effect transistor M2 is connected to the power supply voltage terminal V _DD , and the drain is used to output the reference current I _REF . The gates of the metal oxide half field effect transistor M1 and the metal oxide half field effect transistor M2 of the current mirror circuit 1 are connected to each other. In the current mirror circuit 1, the parallel current _IP on the first branch 10 is proportional to the reference current I _REF on the second branch 30. Specifically, the ratio between the parallel current _IP and the reference current I _REF is related to the metal oxide half field effect transistor M1 and the metal oxide half field effect transistor M2. For example, when the MOSFET M1 and the MOSFET M2 are the same, the parallel current _IP is equal to the reference current I _REF .

In this embodiment, the current compensation circuit 13 includes a third resistor R3 and a first amplifier OP1. One end of the third resistor R3 is grounded, and the other end is connected to the negative input end of the first amplifier OP1 (denoted as endpoint V ₁ ). The positive input terminal of the first amplifier OP1 is connected to the current compensation terminal _V2 . The current compensation terminal _V2 is located between the second resistor R2 and the first transistor Q1.

In this embodiment, the current compensation circuit 13 further includes a metal oxide semiconductor field effect transistor M3. The source of the MOSFET M3 is connected to the third resistor R3, the negative input terminal of the first amplifier OP1 is connected to the end point V ₁ , the drain is connected to the output terminal P, and the gate is connected to the output terminal of the first amplifier OP1 , that is, the first amplifier OP1 is also used to control the bias voltage of the metal oxide semiconductor field effect transistor M3.

In this embodiment, the voltage locking circuit 15 includes a second transistor Q2 and a second amplifier OP2. The base and collector of the second transistor Q2 are grounded, and the emitter and the negative input terminal of the second amplifier OP2 are connected to the terminal V ₄ . The positive input terminal of the second amplifier OP2 is connected to the voltage locking terminal _V3 for making the voltage of the voltage locking terminal _V3 equal to the voltage of the emitter of the second transistor Q2. The voltage locking terminal _V3 is located between the first resistor R1 and between the second resistor R2. The voltage locking circuit 15 also includes a fourth resistor R4. One end of the fourth resistor R4, the emitter of the second transistor Q2, and the negative input end of the second amplifier OP2 are connected to the terminal V ₄ . The other end of the fourth resistor R4 Connect to output terminal P. The output terminal of the second amplifier OP2 is connected to the gates of the metal oxide semiconductor field effect transistor M1 and the metal oxide semiconductor field effect transistor M2 to control the bias voltage of the first branch 10 and the second branch 30 .

In this embodiment, both the second transistor Q2 and the first transistor Q1 are negative temperature coefficient components. That is, the equivalent resistance of the first transistor Q1 and the second transistor Q2 will decrease as the temperature increases. Therefore, the voltage at the emitter of the second transistor Q2 (denoted as V _BE2 ) and the voltage at the emitter of the first transistor Q1 (denoted as V _BE1 ) both have negative temperature coefficients. In this embodiment, the second transistor Q2 and the first transistor Q1 may also include a plurality of transistors of the same type, but the first transistor Q1 and the second transistor Q2 include different numbers of transistors (for example, the number ratio is 8:1), there is no restriction on this in this case.

In this embodiment, the positive input terminal of the second amplifier OP2 is connected to the voltage locking terminal V ₃ between the first resistor R1 and the second resistor R2, and the negative input terminal is connected to the emitter of the second transistor Q2 (denoted as Endpoint V ₄ ), due to the effect of a virtual short circuit, the voltages at the voltage locking end V ₃ and the end point V ₄ are equal. Because on the common circuit 11, from the voltage locking terminal _V3 to the ground terminal, it passes through the second resistor R2 and the first transistor Q1 in sequence, while on the voltage locking circuit 15, from the terminal _V4 to the grounding terminal, it only passes through the second resistor R2 and the first transistor Q1. Crystal Q2, when the voltage is the same, the current flowing through the first transistor Q1 and the current density flowing through the second transistor Q2 are different, and the first transistor Q1 and the second transistor Q2 have the same temperature coefficient. In the case of , the voltage difference applied to the second resistor R2 (equivalent to the voltage difference between the emitters of the second transistor Q2 and the first transistor Q1, recorded as △V _BE2,1 ) has the same value as the first The voltage V _BE1 at the emitter terminal of transistor Q1 has an opposite temperature coefficient.

In this embodiment, the common circuit 11 is used to output the reference voltage V _REF , and can be determined by the voltage V _BE1 at the emitter end of the first transistor Q1 , the voltage difference ΔV _BE2,1 across the second resistor R2 , and the first resistor R1 , the second resistor R2 determines the reference voltage _VREF . Specifically, the reference voltage V _REF can be expressed as: V _REF =V _BE1 +△V _BE2,1 (1+R1/R2); (1) where V _BE1 is the voltage of the emitter of the first transistor Q1, △ V _BE2,1 is the voltage difference across the second resistor R2, R1 is the resistance of the first resistor R1, and R2 is the resistance of the second resistor R2. Specifically, the reference voltage V _REF output at the output terminal P is the sum of the voltages applied to the three components of the first resistor R1, the second resistor R2, and the first transistor Q1, where, due to the The base and collector are grounded, so the voltage applied to the first transistor Q1 is V _BE1 , and the voltage applied to the second resistor R2 is △V _BE2,1 . At this time, the current through the second resistor R2 can be expressed as △V _BE2,1 /R2, then the voltage on the first resistor R1 connected in series with the second resistor R2 can be expressed as (△V _BE2,1 /R2)*R1, so the first resistor R1 and the second resistor R2 The sum of the voltages across resistor R2 is △V _BE2,1 (1+R1/R2).

In this embodiment, since V _BE1 and △V _BE2,1 have opposite temperature coefficients, formula (1) can be used to adjust the resistance values of the first resistor R1 and the second resistor R2 to make the output terminal P output The reference voltage V _REF has zero temperature coefficient (that is, the effect of the temperature coefficient is canceled). Specifically, the first transistor Q1 is a PNP bipolar transistor. When its base and collector are grounded, the voltage V _BE1 at its emitter has a negative temperature coefficient, that is, the value of the voltage V _BE1 will change with the temperature. rises and falls. The voltage difference ΔV _BE2,1 applied across the second resistor R2 has a positive temperature coefficient opposite to the voltage V _BE1 , that is, the value of the voltage ΔV _BE2,1 will increase as the temperature increases. Since the voltage difference ΔV _BE2,1 applied across the second resistor R2 has a positive temperature coefficient, the resulting common current I _PTAT flowing through the second resistor R2 also has a positive temperature coefficient. The two resistors R2 are connected in series, so the common current I _PTAT also flows through the first resistor R1, so that the voltage difference applied across the first resistor R1 also has a positive temperature coefficient. By adjusting the resistance values of the first resistor R1 and the second resistor R2, the temperature coefficient of the reference voltage V _REF output at the output terminal P can be adjusted, so that the reference voltage V _REF is not affected by temperature, that is, the reference voltage V REF Voltage V _REF has zero temperature coefficient.

The band difference reference circuit 100 provided in the embodiment of this case is provided by setting a common circuit 11 and a voltage locking circuit 15, and connecting the negative input terminal of the second amplifier OP2 in the voltage locking circuit 15 to the end point V ₄ and the positive input terminal At the voltage locking terminal V ₃ , the virtual short-circuit effect of the second amplifier OP2 can be used to lock the voltage of the voltage locking terminal V ₃ and the end point V ₄ , and by connecting the voltage locking terminal V ₃ to the first resistor R1 and the first resistor R1 in sequence. The emitter of a transistor Q1 is connected to the emitter of the second transistor Q2 at the end point _V4 , and the base and collector of the first transistor Q1 and the base and collector of the second transistor Q2 are grounded. , different current densities flowing through the first transistor Q1 and the second transistor Q2 can be utilized, so that the voltage difference applied across the second resistor R2 has a temperature coefficient opposite to the voltage on the emitter of the first transistor Q1. Then, by adjusting the resistance values of the first resistor R1 and the second resistor R2, the output terminal P can output the reference voltage _VREF with zero temperature coefficient.

In this embodiment, due to the virtual short circuit effect, the voltage at the end point V ₁ is equal to the voltage at the current compensation terminal V ₂ , and the voltage at the current compensation terminal V ₂ is the voltage V _BE1 of the emitter of the first transistor Q1 , the voltage V _BE1 has the characteristic of negative temperature coefficient, so the voltage at the end point V ₁ also has the characteristic of negative temperature coefficient. Since the voltage at the terminal V ₁ acts on the third resistor R3, the first current I _CTAT flowing through the third resistor R3 has the same negative temperature coefficient as the voltage V _BE1 , that is, as the temperature increases, the first current I CTAT The value of a current I _CTAT will decrease accordingly. On the other hand, the common current I _PTAT on the common circuit 11 has a positive temperature coefficient. Therefore, the currents on the common circuit 11 and the current compensation circuit 13 have opposite temperature coefficients.

In this embodiment, the current compensation circuit 13, the voltage locking circuit 15 and the common circuit 11 are all connected to the output terminal P, so the parallel current IP passing through the output terminal _P is the sum of the currents of the three circuits, and the common circuit The common current I _PTAT on 11 and the first current I _CTAT on the current compensation circuit 13 have opposite temperature coefficients. For example, the common current I _PTAT has a positive temperature coefficient, while the first current I _CTAT has a negative temperature coefficient. Therefore, the parallel current _IP includes the common current I _PTAT and the first current I _CTAT with opposite temperature coefficients, so that the temperature coefficient of the parallel current _IP can be adjusted by adjusting the values of the common current I _PTAT and the first current I _CTAT , thus becoming The current has a zero temperature coefficient, so that the reference current I _REF output from the second branch 30 of the current mirror circuit 1 is also a current with a zero temperature coefficient.

In this embodiment, the second branch 30 of the current mirror circuit 1 is used to copy the parallel current _IP to generate the reference current I _REF . Specifically, the reference current I _REF can be expressed as: I _REF =nI _P =n[I _CTAT +I _PTAT +I ₂ ]=n[V _BE1 /R3+△V _BE2,1 /R2+I ₂ ]; (2 ) Among them, R3 is the resistance of the third resistor R3, n is the ratio between the reference current I _REF and the parallel current _IP , V _BE1 /R3 is the current on the current compensation circuit 13, △V _BE2,1 /R2 is The current on the common circuit 11, _I2, is the current on the voltage lock circuit 15. In addition, n can be any positive number, such as: 0.8, 1, 1.5, 2, 4, etc. Since the currents on the common circuit 11, the current compensation circuit 13 and the voltage locking circuit 15 all have a certain temperature coefficient, and the temperature coefficients of the currents on the common circuit 11 and the current compensation circuit 13 are opposite, the parallel current _IP can be adjusted by adjusting each The temperature coefficient of the current on one branch is used to achieve zero temperature coefficient.

In one embodiment, the second current I ₂ on the voltage lock circuit 15 can be adjusted by the resistance values of the first resistor R1 and the fourth resistor R4. In this case, the quantity ratio of the second transistor Q2 and the first transistor Q1 can be changed according to the resistance value ratio of the first resistor R1 and the fourth resistor R4, so that the second current I ₂ and the common current I _PTAT associated. That is: I ₂ =(R1/R4)I _PTAT ; (3) The reference current can be expressed as: I _REF =nI _P =n[I _CTAT +I _PTAT +I ₂ ]=n[V _BE1 /R3+(1 +R1/R4)(△V _BE2,1 /R2)]; (4) In other words, in such an embodiment, the first resistor R1, the second resistor R2, the third resistor R3 and the third resistor can be adjusted. The resistance of the four resistors R4 makes the parallel current _IP have a zero temperature coefficient (that is, canceling the influence of the temperature coefficient). And it has high flexibility in circuit design to meet various application needs. For example, under low current requirements, the resistance of the fourth resistor R4 can be increased, and the ratio of the second transistor Q2 to the first transistor Q1 can be correspondingly reduced.

It can be seen that by setting the resistance between the fourth resistor R4 and the first resistor R1 (along with setting the quantitative ratio between the first transistor Q1 and the second transistor Q2), the voltage locking circuit 15 can be The value of the second current I ₂ is associated with the value of the common current I _PTAT on the common circuit 11 , so that the reference current I _REF can be completely determined by the parameters of each component, and can then be adjusted by adjusting the first resistor R1 and the second resistor R1 . The resistor R2, the third resistor R3 and the fourth resistor R4 are used to obtain the reference current I _REF with zero temperature coefficient.

In another embodiment, the resistance of the fourth resistor R4 and the resistance of the first resistor R1 may also be substantially equal, so that the second current I ₂ on the voltage locking circuit 15 and the common current I _PTAT on the common circuit 11 The current values are essentially the same. Specifically, since the common circuit 11 and the voltage lock circuit 15 are both connected from the output terminal P to the ground terminal, when the voltages of the voltage lock terminal V ₃ and the end point V ₄ are equal, the first resistor R1 and the fourth resistor R4 are affected by The cross-voltage is also the same. Therefore, when the resistance value of the first resistor R1 is the same as the resistance value of the fourth resistor R4, the common current I _PTAT on the common circuit 11 and the second current I ₂ on the voltage locking circuit 15 are also the same and have the same temperature coefficient. , the reference current I _REF at this time can be expressed as: I _REF =nI _P =n[I _CTAT +2I _PTAT ]=n[V _BE1 /R3+2(△V _BE2,1 /R2)]; (5) It can be seen that the reference current I _REF includes V _BE1 and ΔV _BE2,1 with opposite temperature coefficients, as well as R2 and R3 as variables. Therefore, formula (5) can be used to adjust the resistance values of the second resistor R2 and the third resistor R3 so that the reference current I _REF has a zero temperature coefficient (that is, the influence of the temperature coefficient is offset).

The band difference reference circuit 100 provided in the embodiment of this case is provided by setting a common circuit 11 and a current compensation circuit 13, and connecting the positive input terminal of the first amplifier OP1 of the current compensation circuit 13 to the current compensation terminal V ₂ and the negative input terminal At the end point V ₁ , the end point V ₁ and the current compensation terminal V ₂ can be made to have the same voltage, so that the temperature coefficient of the voltage difference across the third resistor R3 is the same as the temperature coefficient of the voltage of the emitter of the first transistor Q1 Similarly, the first current I _CTAT of the current compensation circuit 13 has an opposite temperature coefficient to the common current I _PTAT of the common circuit, and finally the sum of the currents of the common circuit 11, the current compensation circuit 13 and the voltage locking circuit 15 cancels Temperature coefficient of parallel current _IP . On the other hand, by setting the resistance of the fourth resistor R4 to be equal to the resistance of the first resistor R1, the second current I2 on the voltage locking circuit 15 can be equal to the common current I _PTAT , thus simplifying the calculation process and obtaining Parallel current _IP with zero temperature coefficient. By setting the current mirror circuit 1, the second branch 30 can be made to output a reference current I _REF that is equal to or proportional to the parallel current _IP , that is, a reference current I _REF with zero temperature coefficient.

In this embodiment, the band difference reference circuit also includes an adjustment circuit (not shown) for adjusting the resistance values of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4. Reference voltage V _REF and reference current I _REF . Specifically, it can be known from formulas (1) and (2) that the temperature coefficients of the reference voltage V _REF and the reference current I _REF output by the band difference reference circuit 100 are determined by the characteristics of the first transistor Q1 and the second transistor Q2 and The resistance values of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are determined together. Although the resistance values of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are set, The value can offset the effect of the temperature coefficient, but the resistors themselves will still drift during the manufacturing process, so the circuit needs to be adjusted to compensate. Among them, the resistance of the fourth resistor R4 is related to the first resistor R1. Specifically, the resistance of the fourth resistor R4 is substantially equal to or in a certain proportion to the resistance of the first resistor R1. Therefore, when adjusting the first resistor R1 When the resistance value is , the resistance value of the fourth resistor R4 needs to be adjusted synchronously to ensure the corresponding relationship with the first resistor R1 .

In this embodiment, the adjustment circuit may include a plurality of resistor strings. Each resistor string is connected in parallel with the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4. Each resistor string includes a plurality of resistors arranged in parallel. Each branch includes a resistor and a switch. By controlling the opening and closing of the switches on the plurality of branches, the resistances of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 can be adjusted. value. In other embodiments, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 can also be directly set as resistors with adjustable resistance values, and the first resistor R1, the second resistor R2 The third resistor R3 and the fourth resistor R4 are respectively connected to the adjustment circuit. The adjustment circuit can adjust the resistance value of each resistor by issuing instructions.

The band difference reference circuit 100 provided in the embodiment of this case is configured by setting the negative input terminal of the second amplifier OP2 to be connected to the terminal V ₄ , the positive input terminal to be connected to the voltage locking terminal V ₃ , and the negative input terminal of the first amplifier OP1 to be connected to At the terminal V ₁ , the positive input terminal is connected to the current compensation terminal V ₂ , and the voltage V BE1 on the emitter of the first transistor Q1 can also be made smaller than the voltage on the emitter of the second transistor Q2 , that is, the voltage V _BE1 on the emitter of the first transistor Q1 is applied to the terminal V 1 . The voltage difference across the three resistors R3 is reduced, which is beneficial to reducing the power consumption of the current compensation circuit 13 . For example, after adjusting the resistance values of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor _R4 , the voltage at the current compensation terminal V ₂ is about 10% smaller, so the resistance of the third resistor R3 can also be relatively reduced by about 10%, and the power consumption of the first current I _CTAT on the current compensation circuit 13 is reduced by about 20%. Thereby, the overall power consumption of the band difference reference circuit 100 is reduced.

To sum up, the band difference reference circuit 100 provided in the embodiment of this case is by connecting the common circuit 11, the current compensation circuit 13 and the voltage locking circuit 15 to the output terminal P, and connecting the current compensation circuit 13 to the common circuit 11 The current compensation terminal V ₂ on the voltage locking circuit 15 is connected to the voltage locking terminal V ₃ on the common circuit 11. The reference voltage V _REF and the reference current I _REF with zero temperature coefficient can be simultaneously output through one circuit, which improves the general performance. While being practical, it reduces the number of components, which is beneficial to improving space utilization and reducing energy consumption.

The embodiment of this case also provides a method of generating a reference voltage and a reference current at the same time. The method of generating a reference voltage and a reference current at the same time can be exemplarily applied to the above-mentioned band difference reference circuit 100. Please refer to Figure 3, which includes: Step S1: Provide a common circuit 11. The common circuit 11 includes a first resistor R1, a second resistor R2 and a first transistor Q1 connected in series from an output terminal P. The base and collector of the first transistor Q1 are grounded. The emitter of a transistor Q1 and the second resistor R2 are connected to the current compensation terminal V ₂ , and the second resistor R2 and the first resistor R1 are connected to the voltage locking terminal V ₃ ; Step S2: Provide a voltage locking circuit 15 and a voltage locking circuit 15 It includes one end connected to the output terminal P, a ground terminal and an end connected to the voltage locking terminal _V3 ; Step S3: Provide a current compensation circuit 13. The current compensation circuit 13 includes an end connected to the output terminal P, a ground terminal and a current compensation circuit. One end connected to terminal V ₂ ; Step S4: Lock the voltage of terminal V ₃ so that the voltage difference across the second resistor R2 and the voltage of the emitter of the first transistor Q1 have an opposite temperature coefficient; Step S5: At the output The terminal P outputs the reference voltage _VREF ; Step S6: Generate a current with an opposite temperature coefficient to the current on the common circuit 11 on the current compensation circuit 13; Step S7: Provide a current mirror circuit 1, and connect the current mirror circuit 1 to One branch 10 is connected to the output terminal P, and the second branch 30 of the current mirror circuit 1 outputs the reference current I _REF .

In this embodiment, step S2 also includes: providing a second transistor Q2 and a second amplifier OP2, grounding the base and collector of the second transistor Q2, and connecting the negative input terminal of the second amplifier OP2 with the second The emitter of the transistor Q2 is connected, and the positive input terminal of the second amplifier OP2 is connected to the voltage locking terminal V ₃ .

In this embodiment, step S2 also includes: providing a fourth resistor R4, connecting one end of the fourth resistor R4 to the output terminal P, and connecting the other end of the fourth resistor R4 to the negative input terminal of the second amplifier OP2 and the second The emitter of the transistor Q2 is connected; the base and collector of the second transistor Q2 are connected to ground; and the positive input terminal of the second amplifier OP2 is connected to the voltage locking terminal V ₃ .

In this embodiment, step S3 also includes: providing a metal oxide half field effect transistor M3, a third resistor R3 and a first amplifier OP1, connecting the drain of the metal oxide half field effect transistor M3 to the output terminal P, and connecting the metal oxide half field effect transistor M3 with the output terminal P. The source of the half field effect transistor M3 is connected to one end of the third resistor R3 and the negative input end of the first amplifier OP1, and the gate of the metal oxide half field effect transistor M3 is connected to the output end of the first amplifier OP1; The other end of the resistor R3 is connected to ground; and the positive input terminal of the first amplifier OP1 is connected to the current compensation terminal V ₂ .

In this embodiment, the reference voltage V _REF output in step S5 can be expressed as: V _REF =V _BE1 +△V _BE2,1 (1+R1/R2); where V _BE1 is the voltage of the first transistor Q1 The emitter voltage, △V _BE2,1 is the voltage difference across the second resistor R2, R1 is the resistance of the first resistor R1, R2 is the resistance of the second resistor R2, through the second resistor The current of R2 can be expressed as △V _BE2,1 /R2, then the voltage on the first resistor R1 connected in series with the second resistor R2 can be expressed as (△V _BE2,1 /R2)*R1, so the first resistor R1 The sum of the voltage on the second resistor R2 is △V _BE2,1 (1+R1/R2).

In one embodiment, step S5 further includes: adjusting the resistance values of the first resistor R1 and the second resistor R2 so that the reference voltage V _REF is a voltage with zero temperature coefficient.

In this embodiment, the reference current I _REF output in step S7 can be expressed as: I _REF =nI _P =n[V _BE1 /R3+(1+R1/R4)(ΔV _BE2,1 /R2)]; where _IP is the parallel current passing through the output terminal P, n is the ratio between the reference current I _REF and the parallel current _IP , and n is a positive number (for example: 0.8, 1, 1.5, 2, 4, etc.), V _BE1 is the voltage of the emitter of the first transistor Q1, R3 is the resistance of the third resistor R3, R1 is the resistance of the first resistor R1, R4 is the resistance of the fourth resistor R4, △V _BE2,1 is the resistance of the second resistor R3. The voltage difference between the two ends of the resistor R2, R2 is the resistance of the second resistor R2, V _BE1 /R3 is the current on the current compensation circuit 13, △V _BE2,1 /R2 is the current on the common circuit 11.

In this embodiment, step S7 also includes: setting a metal oxide half field effect transistor M1 in the first branch 10 and setting a metal oxide half field effect transistor M2 in the second branch 30; The source is connected to the power supply voltage terminal V _DD , and the drain of the metal oxide half field effect transistor M1 is connected to the output terminal P; the source of the metal oxide half field effect transistor M2 is connected to the power supply voltage terminal V _DD , and the metal oxide half field effect transistor M1 is connected to the drain. The drain output reference current I _REF of the oxygen half field effect transistor M2; connect the gates of the metal oxygen half field effect transistor M1 and the metal oxygen half field effect transistor M2 to each other; connect the output end of the second amplifier OP2 with the metal oxygen half field effect transistor M2. The gates of the half field effect transistor M1 and the metal oxide half field effect transistor M2 are connected together to control the bias voltages of the first branch 10 and the second branch 30 .

In one embodiment, step S7 further includes: adjusting the resistance values of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 so that the reference current I _REF is a current with zero temperature coefficient.

In another embodiment, the resistance of the first resistor R1 may be substantially equal to the resistance of the fourth resistor R4. In this case, the reference current I _REF may be simply expressed as: I _REF =nI _P =n[V _BE1 /R3+ 2(ΔV _BE2,1 /R2)]; in this embodiment, step S7 also includes: adjusting the resistance values of the second resistor R2 and the third resistor R3 so that the reference current I _REF is a current with zero temperature coefficient.

The method provided by the embodiment of this case is to generate a reference voltage and a reference current at the same time by connecting a common circuit, a current compensation circuit, a voltage locking circuit and a current mirror circuit to the output end, and connecting the current compensation circuit to the current on the common circuit. At the compensation end, the voltage locking circuit is connected to the voltage locking end on the public circuit. It can simultaneously output the reference voltage V _REF and the reference current I _REF with zero temperature coefficient through one circuit, which improves the versatility and reduces the cost of the components. Quantity, which helps improve space utilization and reduce energy consumption.

Those of ordinary skill in the art should realize that the above embodiments are only used to illustrate the present invention and are not used to limit the present invention. As long as they are within the scope of the essential spirit of the present invention, appropriate changes can be made to the above embodiments. and changes are within the scope of protection claimed by the present invention.

1: Current mirror circuit

11:Public circuit

13: Current compensation circuit

15: Voltage lock circuit

V ₂ : Current compensation terminal

V ₃ : voltage lock terminal

P: output terminal

V _REF : reference voltage

_IP : Parallel current

I _REF : reference current

I _PTAT : Common current

I _CTAT : first current

I ₂ : second current

Claims (9)

A band difference reference circuit is improved in that it includes: a common circuit, the common circuit includes a first resistor, a second resistor and a first transistor connected in series from an output end, and the base of the first transistor and The collector is grounded, the emitter of the first transistor and the second resistor are connected to the current compensation terminal, the second resistor and the first resistor are connected to the voltage locking terminal, and the output terminal is used to output a reference voltage; current compensation circuit, including one end connected to the output terminal and a ground terminal; voltage locking circuit, including one end connected to the output terminal and a ground terminal; and a current mirror circuit, the first branch of the current mirror circuit The second branch of the current mirror circuit is used to output a reference current. The parallel current is equal to the common circuit, the current compensation circuit and the voltage lock. The sum of the currents of the circuit; the reference current is equal to or proportional to the parallel current; wherein the current compensation circuit also includes an end connected to the current compensation end, and the current compensation circuit is used to make The current generated on the current compensation circuit and the current generated on the common circuit have opposite temperature coefficients; the voltage locking circuit also includes an end connected to the voltage locking terminal, and the voltage locking circuit is used to enable the The voltage difference across the second resistor and the voltage of the emitter of the first transistor have an opposite temperature coefficient; wherein, the reference voltage is expressed as: V _REF =V _BE1 +△V _BE2,1 (1+R1/ R2); where V _BE1 is the voltage of the emitter of the first transistor, △V _BE2,1 is the voltage difference across the second resistor, R1 is the resistance of the first resistor, and R2 is the The resistance of the second resistor. The band difference reference circuit of claim 1, wherein the current compensation circuit includes a metal oxide half field effect transistor, a third resistor and a first amplifier, and the drain electrode of the metal oxide half field effect transistor is connected to the output terminal is connected, the source electrode of the metal oxide half field effect transistor is connected to one end of the third resistor and the negative input end of the first amplifier, and the gate electrode of the metal oxide half field effect transistor is connected to the first The output end of the amplifier is connected; the other end of the third resistor is connected to ground; the positive input end of the first amplifier is connected to the current compensation end; The voltage lock circuit includes a fourth resistor, a second transistor and a second amplifier. One end of the fourth resistor is connected to the output end, and the other end of the fourth resistor is connected to the negative input of the second amplifier. The terminal is connected to the emitter of the second transistor; the base and collector of the second transistor are grounded; the positive input terminal of the second amplifier is connected to the voltage lock terminal. The band difference reference circuit according to claim 2, further comprising an adjustment circuit for adjusting the resistance values of the first resistor, the second resistor, the third resistor and the fourth resistor. The band difference reference circuit as described in request item 3, wherein the reference current is expressed as: I _REF =nI _P =n[V _BE1 /R3+(1+R1/R4)(△V _BE2,1 /R2)] ; Where _IP is the parallel current passing through the output terminal, n is the ratio between the reference current and the parallel current and is a positive number, V _BE1 is the voltage of the emitter of the first transistor, and R3 is the The resistance of the third resistor, R1 is the resistance of the first resistor, R4 is the resistance of the fourth resistor, △V _BE2,1 is the voltage difference across the second resistor, R2 is the The resistance of the second resistor. The band difference reference circuit as described in claim 3, wherein the resistance values of the first resistor and the fourth resistor are equal, and the reference current is expressed as: I _REF =nI _P =n[V _BE1 /R3+ 2(△V _BE2,1 /R2)]; where _IP is the parallel current passing through the output terminal, n is the ratio between the reference current and the parallel current and is a positive number, V _BE1 is the first The voltage of the emitter of the transistor, R3 is the resistance of the third resistor, ΔV _BE2,1 is the voltage difference across the second resistor, and R2 is the resistance of the second resistor. A method for generating a reference voltage and a reference current at the same time. An improvement thereof includes: providing a common circuit. The common circuit includes a first resistor, a second resistor and a first transistor connected in series from an output end. The base and collector of a transistor are grounded, the emitter of the first transistor and the second resistor are connected to the current compensation terminal, and the second resistor and the first resistor are connected to the voltage locking terminal. ; Provide a voltage locking circuit, the voltage locking circuit includes an end connected to the output end, a ground end and an end connected to the voltage locking end; Provide a current compensation circuit, the current compensation circuit includes an end connected to the output end One end of the connection, the ground end and the end connected to the current compensation end; lock the voltage of the voltage locking end so that the voltage difference across the second resistor and the voltage of the emitter of the first transistor have an opposite temperature coefficient; outputting a reference voltage at the output terminal; generating a current with an opposite temperature coefficient to the current on the common circuit on the current compensation circuit; and providing a current mirror circuit, which converts the current mirror circuit to The first branch is connected to the output terminal, and a reference current is output in the second branch of the current mirror circuit; where the reference voltage is expressed as: V _REF =V _BE1 +△V _BE2,1 (1+ R1/R2); where V _BE1 is the voltage of the emitter of the first transistor, △V _BE2,1 is the voltage difference across the second resistor, R1 is the resistance of the first resistor, and R2 is the resistance of the second resistor; and outputting a reference voltage at the output end includes: adjusting the resistance of the first resistor and the second resistor so that the reference voltage is a voltage with zero temperature coefficient. The method of simultaneously generating a reference voltage and a reference current as described in claim 6, wherein providing the current compensation circuit includes providing a metal oxide half field effect transistor, a third resistor and a first amplifier, and the drain of the metal oxide half field effect transistor The electrode of the metal oxide half field effect transistor is connected to the output end, the source electrode of the metal oxide half field effect transistor is connected to one end of the third resistor and the negative input end of the first amplifier, and the gate electrode of the metal oxide half field effect transistor is connected to the output end of the first amplifier; the other end of the third resistor is grounded; the positive input end of the first amplifier is connected to the current compensation end; and providing a voltage locking circuit includes providing a fourth resistor, a third Two transistors and a second amplifier, one end of the fourth resistor is connected to the output end, and the other end of the fourth resistor is connected to the negative input end of the second amplifier and the emitter of the second transistor. Connection; the base and collector of the second transistor are grounded; the positive input terminal of the second amplifier is connected to the voltage lock terminal. The method of generating a reference voltage and a reference current simultaneously as described in claim 7, wherein the reference current is expressed as: I _REF =nI _P =n[V _BE1 /R3+(1+R1/R4)(△V _{BE2, 1} /R2)]; where _IP is the parallel current passing through the output terminal, n is the ratio between the reference current and the parallel current and is a positive number, and V _BE1 is the emitter of the first transistor. voltage, R3 is the resistance of the third resistor, R1 is the resistance of the first resistor, R4 is the resistance of the fourth resistor, △V _BE2,1 is the voltage difference across the second resistor , R2 is the resistance of the second resistor; and outputting the reference current in the second branch of the current mirror circuit includes: adjusting the first resistor, the second resistor, the third resistor and the The resistance of the fourth resistor is such that the reference current is a current with zero temperature coefficient. The method for generating a reference voltage and a reference current at the same time as described in claim 7, wherein the resistance values of the first resistor and the fourth resistor are substantially equal, and the reference current is expressed as: I _REF =nI _P = n[V _BE1 /R3+2(△V _BE2,1 /R2)]; where _IP is the parallel current passing through the output terminal, n is the ratio between the reference current and the parallel current and is a positive number, V _BE1 is the voltage of the emitter of the first transistor, R3 is the resistance of the third resistor, △V _BE2,1 is the voltage difference across the second resistor, R2 is the resistance of the second resistor. resistance; and outputting a reference current in the second branch of the current mirror circuit includes: adjusting the resistance of the second resistor and the third resistor so that the reference current is a current with zero temperature coefficient.

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