TWI830182B - 處理高電阻率基底的方法以及高電阻率基底 - Google Patents
處理高電阻率基底的方法以及高電阻率基底 Download PDFInfo
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Abstract
本發明揭露一種處理高電阻率基底以實現靜電夾持的方法以及一種高電阻率基底。底面植入有降低電阻率的物質。通過這種方式,可大大降低基底的底面的電阻率。在一些實施例中,為了植入底面,將塗層施加到頂面。在施加塗層之後,翻轉基底以使得前表面接觸卡盤的頂面。隨後將離子植入到所暴露底面中以產生低電阻率層。底面附近的低電阻率層的電阻率在植入之後可小於1000歐姆公分。一旦已植入底面,就可常規地處理基底。稍後可通過晶圓背側薄化工藝來去除低電阻率層。
Description
本揭露的實施例涉及一種用於改進的基底處置的方法,且特定來說,涉及一種用於改進的高電阻率基底處理的方法。
本申請要求2021年4月9日提交的美國專利申請第17/226,277號的優先權,其揭露內容以全文引用的方式併入本文中。
使用多個工藝製造基底以產生半導體裝置。在許多這些工藝中,將基底夾持到表面以使得基底在整個工藝中保持靜止。
可使用機械夾持實現這一夾持,其中基底實體地附接到卡盤。儘管有效,但機械夾持可導致污染、工藝均勻性較差、有用晶圓面積減少或因背側氣體壓力而損壞基底。替代地,可使用靜電力將基底夾持到卡盤。電場產生於卡盤內。這些電場導致基底中的電子牽引到基底的底面,在那裏其受卡盤中的正電荷吸引。這一吸引用於將基底夾持到卡盤。
靜電夾持極為有效且降低基底受污染或損壞的可能性。然而,這一技術依賴於基底具有相當低電阻率的事實。這允許電子在基底內自由移動,從而產生靜電夾持力。
具有高電阻率的基底,例如高電阻率矽、碳化矽以及砷化鎵,不產生與矽基底相同的夾持力。實際上,在一個測試中,當矽基底安置在卡盤上時,靜電卡盤中產生的電流是未填充卡盤情況下的三倍。相比而言,當高電阻率基底安置在卡盤上時,卡盤中產生的電流幾乎與未填充卡盤時相同。
因為這一點,這些高電阻率基底難以進行處理。舉例來說,在低壓下施加背側氣體可導致基底變得未夾持。同時,低卡盤力將限制在一些情況下用於晶圓冷卻的高壓背側氣體的使用。此外,這些基底可能易受由於無法將累積電荷消散到卡盤而造成的損壞。
因此,處理高電阻率基底以使其可靜電夾持到卡盤的方法將為有益的。另外,如果這一方法不會對產量產生不利影響或引入許多額外的製造工藝,那麼其將是有利的。
揭露一種修改高電阻率基底以使得基底可靜電夾持到卡盤的方法。底面植入有降低電阻率的物質。通過這種方式,可大大降低基底的底面的電阻率。在一些實施例中,為了植入底面,將塗層施加到頂面。在施加塗層之後,翻轉基底以使得前表面接觸卡盤的頂面。隨後將離子植入到所暴露底面中以產生低電阻率層。底面附近的低電阻率層的電阻率在植入之後可小於1000歐姆公分。一旦已植入底面,就可常規地處理基底。稍後可通過晶圓背側薄化工藝去除低電阻率層,而在一些實施例中,將對層進行電鍍或金屬化以形成垂直晶體管的電極。
根據一個實施例,揭露一種處理高電阻率基底以實現靜電夾持的方法。方法包括:將塗層施加到高電阻率基底的頂面;將離子植入到高電阻率基底的底面中以形成低電阻率層;去除塗層,使得高電阻率基底包括其底面附近的低電阻率層,所述高電阻率基底可夾持到靜電卡盤。在一些實施例中,塗層為低電阻率材料,使得在植入離子之前翻轉高電阻率基底,以使得塗層與靜電卡盤的頂面接觸且塗層允許將高電阻率基底夾持到靜電卡盤。在某些實施例中,塗層包括非晶碳或氧化鈦。在某些實施例中,離子將低電阻率層的電阻率相對於高電阻率基底的電阻率降低至少五個數量級。在一些實施例中,離子將低電阻率層的電阻率降低到小於1000歐姆公分。在某些實施例中,離子將低電阻率層的電阻率降低到小於100歐姆公分。在一些實施例中,高電阻率基底包括GaAs基底,且離子包括矽。在某些實施例中,高電阻率基底包括SiC基底,且離子包括磷、鋁或硼。在一些實施例中,高電阻率基底包括高電阻率矽基底,且離子包括磷或硼。在某些實施例中,植入是使用非零傾斜角執行的。在一些實施例中,植入離子使得離子的峰值濃度出現在小於500奈米的深度處。在某些實施例中,稍後去除低電阻率層。在某些實施例中,稍後對低電阻率層進行電鍍或金屬化以形成電極。
根據另一實施例,揭露一種處理高電阻率基底以實現靜電夾持的方法,其中高電阻率基底包括安置在頂面上的具有低電阻率的犧牲層。方法包括:將離子植入到高電阻率基底的底面中,其中翻轉高電阻率基底,使得犧牲層與靜電卡盤的頂面接觸且犧牲層允許將高電阻率基底夾持到靜電卡盤;其中在植入之後,高電阻率基底包括其底面附近的低電阻率層,所述高電阻率基底可夾持到靜電卡盤。在某些實施例中,離子將低電阻率層的電阻率相對於高電阻率基底的電阻率降低至少五個數量級。在一些實施例中,離子將低電阻率層的電阻率降低到小於1000歐姆公分。在某些實施例中,離子將低電阻率層的電阻率降低到小於100歐姆公分。在某些實施例中,植入是使用非零傾斜角執行的。在一些實施例中,植入離子使得離子的峰值濃度出現在小於500奈米的深度處。在某些實施例中,高電阻率基底包括GaAs基底、SiC基底或高電阻率矽基底,且離子包括矽、磷、鋁或硼。
根據另一實施例,揭露一種適用於靜電夾持的高電阻率基底。高電阻率基底包括安置在基底內的低電阻率層,其中低電阻率層包括降低電阻率的物質,且其中低電阻率層的電阻率為1000歐姆公分或小於1000歐姆公分。在某些實施例中,降低電阻率的物質的峰值濃度設置在2奈米與2微米之間的深度處。
如上所述,由於產生的夾持力較弱,所以使用帶有靜電卡盤的高電阻率基底可能存在問題。為了解決這個問題,揭露一種提高處置這些高電阻率基底的能力的方法,且更特定來說,揭露一種提高利用具有靜電卡盤的這些高電阻率基底的能力的方法。
圖1A到圖1F繪示高電阻率基底,因為將這一方法應用於所述基底。圖2示出繪示這一方法中涉及的工藝的流程圖。
方法開始於高電阻率基底100,如圖1A中和圖2的方框200中所繪示。高電阻率基底100可為砷化鎵(gallium arsenide;GaAs)、碳化矽(silicon carbide;SiC)、高電阻率矽(high resistivity silicon;Hi-Res Si)或其它高電阻率基底。將高電阻率基底定義為具有等於或大於1E4歐姆公分的電阻率的基底。在一些實施例中,高電阻率基底可具有等於或大於1E8的電阻率。在某些實施例中,在任何其它製造工藝之前執行本文中所描述的方法。在一些實施例中,可在利用靜電夾持的第一工藝之前將高電阻率基底插入到製造工藝流程中。高電阻率基底100的厚度不受這一實施例限制且可達到數微米厚。
接下來,將塗層110施加到高電阻率基底100的頂面101,如方框210和圖1B中所繪示。這一塗層110可具有例如小於1000歐姆公分的低電阻率。在某些實施例中,塗層110的電阻率可小於300歐姆公分。塗層110可為非晶碳(amorphous carbon;a-C)、氧化鈦(titanium oxide;TiO
x)或另一合適的材料。在某些實施例中,由於易於應用而選擇塗層110。在某些實施例中,可通過旋塗、化學氣相沉積(chemical vapor deposition;CVD)、物理氣相沉積(physical vapor deposition;PVD)、原子層沉積(atomic layer deposition;ALD)或其他合適的方法施加塗層110。這一塗層110的厚度不受本揭露限制,因為稍後將去除塗層。因此,塗層110可具有在2奈米與5微米之間的厚度。
接下來,如方框220和圖1C中所繪示,翻轉高電阻率基底100,使得帶有塗層110的頂面101與卡盤的頂面接觸。應注意,由於塗層110由低電阻率材料製成,因此可使用靜電卡盤。靜電卡盤的靜電力由於塗層110而能夠夾持高電阻率基底。
接下來,如方框230和圖1D中所繪示,執行離子植入工藝以便將離子120植入到高電阻率基底100的所暴露底面中。使用將降低高電阻率基底100的電阻率的物質(也稱為降低電阻率的物質)的離子120來執行離子植入工藝。舉例來說,對於SiC基底,降低電阻率的物質可為鋁、硼、磷或另一合適的物質。對於Hi-Res Si基底,降低電阻率的物質可為硼、磷或另一合適的物質。對於GaAs基底,降低電阻率的物質可為矽或另一合適的物質。
可選擇離子植入工藝的能量,使得植入區的厚度在例如2奈米與5微米之間。在某些實施例中,厚度可在2奈米與500奈米之間。對於GaAs基底,這一能量可在5千電子伏特與10兆電子伏特之間。當然,也可使用其他厚度,這取決於高電阻率基底的整體厚度。
離子植入工藝的劑量可為充足的,使得植入區成為具有小於1000歐姆公分的電阻率的低電阻率層。在某些實施例中,劑量可使得低電阻率層130的電阻率變成100歐姆公分或小於100歐姆公分。對於GaAs基底,劑量可在1E13原子/平方公分與1E18原子/平方公分之間,或在某些實施例中,在1E14原子/平方公分與1E16原子/平方公分之間。GaAs基底可具有1E8歐姆公分到1E10歐姆公分的電阻率。因此,離子植入工藝將高電阻率基底的植入部分的電阻率降低大於五個數量級,且可將電阻率降低六個或大於六個數量級。可針對SiC、高電阻率以及其它高電阻率基底執行使用合適的物質的類似植入工藝。
在某些實施例中,可使用非零傾斜角執行離子植入工藝以使溝道最小化。圖1D繪示用於植入離子120的非零傾斜角(θ)。這一非零傾斜角可在1°與60°之間。在其它實施例中,可不採用非零傾斜角。
舉例來說,在一個測試中,將矽離子以45°傾斜角(相對於定義為0°的垂直植入)植入到GaAs基底中。離子的能量為30千電子伏特且劑量在1E14原子/平方公分與1E15原子/平方公分之間。所得低電阻率層130的厚度小於100奈米,且在某些實施例中,峰值濃度(Rp)在大約50奈米的深度處。
因此,可使用淺植入產生低電阻率層130,使得離子濃度接近基底的底面。峰值濃度可設置在2奈米與2微米之間的深度處,這取決於基底的厚度。在某些實施例中,峰值濃度可位於小於500奈米的深度處。在一些實施例中,峰值濃度可位於小於250奈米的深度處。在一些實施例中,峰值濃度可位於小於1000奈米的深度處。
如方框240和圖1E中所繪示,在離子植入工藝之後,可再次翻轉高電阻率基底100,使得帶有低電阻率層130的底面102可與卡盤的頂面接觸。暴露塗層110。
接下來,如方框250和圖1F中所繪示,可去除塗層110。在某些實施例中,可使用反應性離子刻蝕(reactive ion etch;RIE)工藝、濕法清潔工藝、機械拋光、化學機械拋光或其它薄膜去除工藝來去除塗層110。在其它實施例中,在塗層110包括非晶碳的情況下,可採用氧灰化工藝。
因此,在去除塗層110之後,帶有在其底面附近安置的低電阻率層130的高電阻率基底100準備好進行進一步處理。應注意,除在底面附近包含低電阻率層130以外,高電阻率基底未改變。低電阻率層130可具有2奈米到3微米的厚度。在某些實施例中,低電阻率層130的厚度可小於1微米厚。在一些實施例中,厚度可小於500奈米。在一些實施例中,厚度可小於250奈米。在一些實施例中,厚度可小於100奈米。
在某些實施例中,如方框260中所繪示,在離子植入工藝之後執行退火工藝以修復低電阻率層130中的任何損壞。然而,在某些實施例中,在正常處理期間,高電阻率基底可稍後經受退火工藝。在這些實施例中,有可能取消繪示於方框260中的專用退火工藝。可出於這一目的使用多種退火工藝,例如鍋爐(300℃到100℃,10分鐘到60分鐘)、快速熱退火(1050℃到1200℃且5秒到20秒)或激光退火工藝(>1000℃,幾十納秒)。
接下來,可根據現有製造工藝處理高電阻率基底100,如方框270中所繪示。舉例來說,可製造高電阻率基底100以形成晶體管、功率裝置、光學裝置、太陽能電池、傳感器或其他組件。在高電阻率基底100的底面102附近包含低電阻率層130允許使用常規靜電卡盤來夾持高電阻率基底100。
在高電阻率基底100的製造完成之後,處理低電阻率層130,如方框280中所繪示。在一個實施例中,使用常規晶圓薄化技術去除低電阻率層130。在其它實施例中,例如形成垂直晶體管的實施例中,可對低電阻率層130進行電鍍或金屬化以形成一個或多個電極。
儘管圖1A到圖1F和圖2繪示一種修改高電阻率基底以允許其與靜電卡盤一起使用的方法,但也可能使用其它方法。
舉例來說,在某些實施例中,高電阻率基底最初可具有犧牲頂部層。在圖案化工藝期間將帶有低電阻率的這一犧牲層用作硬罩幕或傳輸層。這一犧牲頂部層可充當上文所描述的塗層,且可在背側離子植入工藝期間用於夾持以形成低電阻率層130。
在這一情形下,圖2的方框210可為任選的。另外,繪示於方框250中的塗層的去除也可為任選的。換句話說,犧牲層可充當上文所描述的塗層。
因此,本揭露描述處理高電阻率基底以實現靜電夾持的若干方法。此外,還揭露一種能夠靜電夾持的高電阻率基底。高電阻率基底包括安置在基底內的低電阻率層。這一低電阻率層可使用降低電阻率的物質的離子植入來產生且可具有1000歐姆公分或小於1000歐姆公分的電阻率。在一些實施例中,低電阻率層可具有100歐姆公分或小於100歐姆公分的電阻率。另外,降低電阻率的物質(Rp)的峰值濃度可設置在2奈米與2微米之間的深度處。
本申請中的上述實施例可具有許多優點。如上文所描述,無法使用靜電力恰當地夾持高電阻率基底。通過在高電阻率基底的底面附近添加低電阻率層,這些基底可像傳統的矽基底一樣夾持,而不需要修改靜電卡盤。
另外,通過結合低電阻率層,在處理期間積聚在高電阻率基底上的電荷可消散到卡盤。這降低了損壞的可能性。
最後,基底夾持和脫開夾持(declamp)的RC時間常數可建模如下:
其中ρ
卡盤為卡盤的介電層的電阻率,d
卡盤為介電層的厚度,ρ
晶圓為基底的電阻率,d
晶圓為基底的厚度,且間隙為卡盤與基底之間的間隙的厚度。對於具有1E8歐姆公分或大於1E8歐姆公分的ρ
晶圓的高電阻率基底,分子的第二項支配可大於100秒的RC常數。通過添加電阻率比基底低至少五個數量級的低電阻率層,RC常數可降低到小於0.5秒。
本揭露不限於本文中所描述的具體實施例的範圍。實際上,除了本文中所描述的那些修改之外,本揭露的其它各種實施例和修改對於本領域的技術人員將從前述描述和附圖中變得顯而易見。因此,這類其它實施例和修改意圖屬於本揭露的範圍。另外,儘管已出於特定目的在特定環境下在特定實施方案的上下文中描述了本揭露,但本領域的一般技術人員將認識到其有用性不限於此,並且出於任何數目個目的,本揭露可以有利地在任何數目個環境中實施。因此,應考慮到如本文中所描述的本揭露的整個廣度和精神來解釋上文闡述的申請專利範圍。
100:高電阻率基底
101:頂面
102:底面
110:塗層
120:離子
130:低電阻率層
200、210、220、230、240、250、260、270、280:方框
θ:非零傾斜角
為了更好地理解本揭露,參考附圖,其以引用的方式併入本文中且其中:
圖1A到圖1F繪示正在處理中的高電阻率基底。
圖2為繪示根據一個實施例的高電阻率基底所經歷工藝的流程圖。
200、210、220、230、240、250、260、270、280:方框
Claims (18)
- 一種處理高電阻率基底以實現靜電夾持的方法,包括:將塗層塗佈到所述高電阻率基底的頂面,其中所述高電阻率基底的電阻率大於1000歐姆公分;將離子植入到所述高電阻率基底的底面中以形成低電阻率層,其中所述低電阻率層的電阻率小於1000歐姆公分;去除所述塗層,使得所述高電阻率基底包括其底面附近的所述低電阻率層,所述高電阻率基底能夠被夾持到靜電卡盤。
- 如請求項1所述的方法,其中所述塗層為低電阻率材料,使得在植入所述離子之前翻轉所述高電阻率基底,以使得所述塗層與所述靜電卡盤的頂面接觸且所述塗層使所述高電阻率基底夾持到所述靜電卡盤。
- 如請求項1所述的方法,其中所述塗層包括非晶碳或氧化鈦。
- 如請求項1所述的方法,其中所述離子將所述低電阻率層的電阻率相對於所述高電阻率基底的電阻率降低至少五個數量級。
- 如請求項1所述的方法,其中所述離子將所述低電阻率層的所述電阻率降低到小於100歐姆公分。
- 如請求項1所述的方法,其中所述高電阻率基底包括砷化鎵基底、碳化矽基底或高電阻率矽基底,且所述離子包括矽、磷、鋁或硼。
- 如請求項1所述的方法,其中植入是使用非零傾斜角執行的。
- 如請求項1所述的方法,其中植入所述離子使得離子的峰值濃度出現在小於500奈米的深度處。
- 如請求項1所述的方法,其中稍後去除所述低電阻率層。
- 如請求項1所述的方法,其中稍後對所述低電阻率層進行電鍍或金屬化以形成電極。
- 一種處理高電阻率基底以實現靜電夾持的方法,其中所述高電阻率基底包括安置在頂面上的具有低電阻率的犧牲層,所述方法包括:將離子植入到所述高電阻率基底的底面中,其中所述高電阻率基底的電阻率大於1000歐姆公分,且翻轉所述高電阻率基底,使得所述犧牲層與靜電卡盤的頂面接觸且所述犧牲層使所述高電阻率基底夾持到所述靜電卡盤;其中在植入之後,所述高電阻率基底包括其底面附近的低電阻率層,所述低電阻率層的電阻率小於1000歐姆公分,所述高電阻率基底能夠被夾持到所述靜電卡盤。
- 如請求項11所述的方法,其中所述離子將所述低電阻率層的電阻率相對於所述高電阻率基底的電阻率降低至少五個數量級。
- 如請求項11所述的方法,其中所述離子將所述低電阻率層的所述電阻率降低到小於100歐姆公分。
- 如請求項11所述的處理高電阻率基底的方法,其中植入是使用非零傾斜角執行的。
- 如請求項11所述的方法,其中植入所述離子使得離子的峰值濃度出現在小於500奈米的深度處。
- 如請求項11所述的方法,其中所述高電阻率基底包括砷化鎵基底、碳化矽基底或高電阻率矽基底,且所述離子包括矽、磷、鋁或硼。
- 一種用於靜電夾持的高電阻率基底,包括安置在所述高電阻率基底內的低電阻率層,其中所述低電阻率層包括降低電阻率的物質,其中所述高電阻率基底的電阻率大於1000歐姆公分,且所述低電阻率層的電阻率為1000歐姆公分或小於1000歐姆公分。
- 如請求項17所述的高電阻率基底,其中所述降低電阻率的物質的峰值濃度設置在2奈米與2微米之間的深度處。
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US8956979B2 (en) | 2011-11-17 | 2015-02-17 | Skyworks Solutions, Inc. | Systems and methods for improving front-side process uniformity by back-side metallization |
WO2013094665A1 (ja) | 2011-12-22 | 2013-06-27 | 信越化学工業株式会社 | 複合基板 |
KR101895128B1 (ko) * | 2016-12-19 | 2018-09-04 | 주식회사 야스 | 바이폴라 대전 처리에 의한 기판 척킹 방법 및 시스템 |
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2021
- 2021-04-09 US US17/226,277 patent/US11594441B2/en active Active
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2022
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- 2022-03-15 JP JP2023561300A patent/JP2024513882A/ja active Pending
- 2022-03-15 KR KR1020237038545A patent/KR20230169234A/ko unknown
- 2022-03-15 WO PCT/US2022/020337 patent/WO2022216416A1/en active Application Filing
- 2022-03-25 TW TW111111397A patent/TWI830182B/zh active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20100093161A1 (en) * | 2007-03-29 | 2010-04-15 | Osamu Kusumoto | Method for manufacturing semiconductor device |
TW200947604A (en) * | 2008-02-11 | 2009-11-16 | Applied Materials Inc | High efficiency electro-static chucks for semiconductor wafer processing |
CN105103273A (zh) * | 2013-04-26 | 2015-11-25 | 古河电气工业株式会社 | 半导体晶片保护用粘接带 |
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JP2024513882A (ja) | 2024-03-27 |
US11594441B2 (en) | 2023-02-28 |
CN117223086A (zh) | 2023-12-12 |
KR20230169234A (ko) | 2023-12-15 |
WO2022216416A1 (en) | 2022-10-13 |
TW202305868A (zh) | 2023-02-01 |
US20220328337A1 (en) | 2022-10-13 |
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