TWI825870B - Electronic package structure and manufacturing method thereof - Google Patents

Electronic package structure and manufacturing method thereof Download PDF

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TWI825870B
TWI825870B TW111127679A TW111127679A TWI825870B TW I825870 B TWI825870 B TW I825870B TW 111127679 A TW111127679 A TW 111127679A TW 111127679 A TW111127679 A TW 111127679A TW I825870 B TWI825870 B TW I825870B
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conductive
substrate
layer
interposer
coaxial
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TW111127679A
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TW202335558A (en
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王金勝
譚瑞敏
林文禹
王擇威
陳君合
馬光華
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欣興電子股份有限公司
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Priority to US17/902,902 priority Critical patent/US20230268257A1/en
Priority to US18/338,273 priority patent/US20230335506A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

An electronic package structure and manufacturing method thereof are provided. The electronic package structure includes an interposer, a circuit board, a chip and a circuit structure. The interposer includes an interposer substrate and a coaxial conductive element. The interposer substrate includes a cavity. The coaxial conductive element is located in the interposer substrate. The coaxial conductive element includes a first conductive structure, a second conductive structure and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is disposed between the first conductive structure and the second conductive structure. The circuit board is disposed on a bottom surface of the interposer substrate and electrically connects with the coaxial conductive element. The chip is disposed within the cavity and is located on the circuit board to electrically connect with the circuit board. The circuit structure is disposed on an upper surface of the interposer substrate and electrically connects with the coaxial conductive element.

Description

電子封裝結構及其製造方法Electronic packaging structure and manufacturing method

本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種電子封裝結構及其製造方法。 The present invention relates to a packaging structure and a manufacturing method thereof, and in particular, to an electronic packaging structure and a manufacturing method thereof.

隨著科技進步，電子產品的功能越來越豐富，天線(antenna)結構與晶片封裝結構的整合有助於電子產品微型化及輕量化的需求。一般來說，對於現行的具有天線結構的晶片封裝結構來說，通常是將晶片設置於電路基板上，並覆蓋膜封材料於晶片上，以形成晶片封裝結構。而天線結構則設置於晶片封裝結構上，並透過晶片封裝結構中貫穿膜封材料的導電柱或導電球使天線結構與電路基板電性連接。然而，上述封裝結構無法有效防止射頻(radio frequency)訊號於傳輸過程中發散，且具有較大的體積。 With the advancement of science and technology, electronic products are becoming more and more functional. The integration of antenna structures and chip packaging structures contributes to the demand for miniaturization and lightweighting of electronic products. Generally speaking, for the current chip packaging structure with an antenna structure, the chip is usually placed on a circuit substrate and a film sealing material is covered on the chip to form the chip packaging structure. The antenna structure is disposed on the chip packaging structure, and is electrically connected to the circuit substrate through conductive pillars or conductive balls penetrating the film sealing material in the chip packaging structure. However, the above-mentioned packaging structure cannot effectively prevent radio frequency (radio frequency) signals from diverging during transmission, and has a large volume.

本發明提供一種電子封裝結構及其製造方法，可降低訊號損耗，並且有助於電子封裝結構的微型化。 The present invention provides an electronic packaging structure and a manufacturing method thereof, which can reduce signal loss and contribute to the miniaturization of the electronic packaging structure.

本發明的電子封裝結構包括中介層、電路基板、晶片以及線路結構。中介層包括中介層基板以及同軸導電件。中介層基板具有上表面及相對於上表面的下表面，其中中介層基板包括空腔。同軸導電件位於中介層基板中。同軸導電件包括第一導電結構、第二導電結構以及第一絕緣結構。第二導電結構環繞第一導電結構。第一絕緣結構設置於第一導電結構與第二導電結構之間。電路基板設置於中介層基板的下表面上，並與同軸導電件電性連接。晶片設置於空腔中且位於電路基板上，以與電路基板電性連接。線路結構設置於中介層基板的上表面上，並與同軸導電件電性連接。 The electronic packaging structure of the present invention includes an interposer, a circuit substrate, a chip and a circuit structure. The interposer includes an interposer substrate and coaxial conductive parts. The interposer substrate has an upper surface and a lower surface relative to the upper surface, wherein the interposer substrate includes a cavity. Coaxial conductive elements are located in the interposer substrate. The coaxial conductive member includes a first conductive structure, a second conductive structure and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is disposed between the first conductive structure and the second conductive structure. The circuit substrate is disposed on the lower surface of the interposer substrate and is electrically connected to the coaxial conductive component. The chip is disposed in the cavity and located on the circuit substrate to be electrically connected to the circuit substrate. The circuit structure is disposed on the upper surface of the interposer substrate and is electrically connected to the coaxial conductive component.

在本發明的一實施例中，上述的中介層基板的材質包括導電材料。 In an embodiment of the present invention, the interposer substrate is made of a conductive material.

在本發明的一實施例中，上述的電子封裝結構還包括熱界面材料，設置於晶片的背面並與中介層基板接觸。 In one embodiment of the present invention, the above-mentioned electronic packaging structure further includes a thermal interface material disposed on the back side of the chip and in contact with the interposer substrate.

在本發明的一實施例中，上述的線路結構包括第一核心層、第一天線層、第二天線層以及多個接墊。第一核心層具有第一表面及與第一表面相對的第二表面，其中第二表面面向中介層。第一天線層設置在第一表面上。第二天線層設置在第二表面上。多個接墊設置在第二表面上且對應於同軸導電件。 In an embodiment of the present invention, the above circuit structure includes a first core layer, a first antenna layer, a second antenna layer and a plurality of contact pads. The first core layer has a first surface and a second surface opposite to the first surface, wherein the second surface faces the interposer. The first antenna layer is disposed on the first surface. The second antenna layer is disposed on the second surface. A plurality of contact pads are disposed on the second surface and correspond to the coaxial conductive members.

在本發明的一實施例中，上述的多個接墊包括第一接墊以及第二接墊。第一接墊對應於同軸導電件的第一導電結構。第二接墊對應於同軸導電件的第二導電結構，其中第二接墊為環 形。 In an embodiment of the present invention, the plurality of pads include a first pad and a second pad. The first pad corresponds to the first conductive structure of the coaxial conductive member. The second pad corresponds to the second conductive structure of the coaxial conductive member, wherein the second pad is a ring shape.

在本發明的一實施例中，上述的多個接墊包括第一接墊以及多個第二接墊。第一接墊對應於同軸導電件的第一導電結構。多個第二接墊對應於同軸導電件的第二導電結構，其中多個第二接墊環繞第一接墊。 In an embodiment of the present invention, the plurality of pads include a first pad and a plurality of second pads. The first pad corresponds to the first conductive structure of the coaxial conductive member. The plurality of second pads correspond to the second conductive structure of the coaxial conductive member, wherein the plurality of second pads surround the first pad.

在本發明的一實施例中，上述的電子封裝結構還包括第一導電連接件，設置於線路結構的多個接墊與同軸導電件之間。 In an embodiment of the present invention, the above-mentioned electronic packaging structure further includes a first conductive connection member disposed between a plurality of pads of the circuit structure and the coaxial conductive member.

在本發明的一實施例中，上述的電子封裝結構還包括第一黏著層，設置於中介層與線路結構之間。 In an embodiment of the present invention, the above-mentioned electronic packaging structure further includes a first adhesive layer disposed between the interposer layer and the circuit structure.

在本發明的一實施例中，上述的電路基板包括對應於同軸導電件的多個接墊。電子封裝結構還包括第二導電連接件，設置於電路基板與同軸導電件之間。 In an embodiment of the present invention, the above-mentioned circuit substrate includes a plurality of pads corresponding to coaxial conductive elements. The electronic packaging structure also includes a second conductive connection member disposed between the circuit substrate and the coaxial conductive member.

在本發明的一實施例中，上述的同軸導電件的第一導電結構適於傳輸訊號，第二導電結構適於接地或與電源連接。 In an embodiment of the present invention, the first conductive structure of the above-mentioned coaxial conductive member is suitable for transmitting signals, and the second conductive structure is suitable for grounding or connecting to a power source.

本發明的電子封裝結構的製造方法包括以下步驟。提供電路基板。設置晶片於電路基板上。提供中介層，其包括中介層基板以及同軸導電件。中介層基板具有上表面及相對於上表面的下表面，其中中介層基板包括空腔。同軸導電件位於中介層基板中。同軸導電件包括第一導電結構、第二導電結構以及第一絕緣結構。第二導電結構環繞第一導電結構。第一絕緣結構設置於第一導電結構與第二導電結構之間。然後，提供線路結構，於第一溫度下，將線路結構壓合於中介層基板的上表面上。形成空腔於 中介層基板的下表面。於第二溫度下，接合電路基板於中介層基板的下表面上，並使晶片設置於空腔中。 The manufacturing method of the electronic packaging structure of the present invention includes the following steps. Provide circuit board. Place the chip on the circuit substrate. An interposer is provided, which includes an interposer substrate and a coaxial conductive member. The interposer substrate has an upper surface and a lower surface relative to the upper surface, wherein the interposer substrate includes a cavity. Coaxial conductive elements are located in the interposer substrate. The coaxial conductive member includes a first conductive structure, a second conductive structure and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is disposed between the first conductive structure and the second conductive structure. Then, a circuit structure is provided, and the circuit structure is pressed onto the upper surface of the interposer substrate at a first temperature. form a cavity in The lower surface of the interposer substrate. At the second temperature, the circuit substrate is bonded to the lower surface of the interposer substrate, and the chip is placed in the cavity.

在本發明的一實施例中，上述的中介層的形成步驟包括提供核心基板，核心基板具有第一側及相對於第一側的第二側。形成第一貫通孔於核心基板中。填充絕緣材料於第一貫通孔中。形成第二貫通孔於絕緣材料中，以形成第一絕緣結構。形成第一導電材料層於核心基板的第一側與第二側上及第二貫通孔中。圖案化第一導電材料層，以暴露出部分第一絕緣結構。 In an embodiment of the present invention, the above step of forming the interposer includes providing a core substrate having a first side and a second side opposite to the first side. A first through hole is formed in the core substrate. Fill the first through hole with insulating material. A second through hole is formed in the insulating material to form a first insulating structure. A first conductive material layer is formed on the first side and the second side of the core substrate and in the second through hole. The first conductive material layer is patterned to expose a portion of the first insulating structure.

在本發明的一實施例中，上述的第一貫通孔的孔徑在250μm至450μm之間，第二貫通孔的孔徑在50μm至100μm之間。 In an embodiment of the present invention, the diameter of the first through hole is between 250 μm and 450 μm, and the diameter of the second through hole is between 50 μm and 100 μm.

在本發明的一實施例中，上述的中介層的形成步驟包括提供核心基板，核心基板具有第一側及相對於第一側的第二側。形成環形凹槽於核心基板的第一側上，其中環形凹槽不貫穿核心基板的第二側。填充絕緣材料於環形凹槽中，以形成第一絕緣結構。自核心基板的第二側移除部分核心基板直到第一絕緣結構被暴露出。形成第一導電材料層於核心基板的第一側及第二側上。圖案化第一導電材料層，以暴露出部分第一絕緣結構。 In an embodiment of the present invention, the above step of forming the interposer includes providing a core substrate having a first side and a second side opposite to the first side. An annular groove is formed on the first side of the core substrate, wherein the annular groove does not penetrate the second side of the core substrate. Fill the annular groove with insulating material to form a first insulating structure. A portion of the core substrate is removed from the second side of the core substrate until the first insulating structure is exposed. A first conductive material layer is formed on the first side and the second side of the core substrate. The first conductive material layer is patterned to expose a portion of the first insulating structure.

在本發明的一實施例中，上述的製造方法還包括形成第一黏著材料層於中介層基板的上表面上，其中第一黏著材料層為半固化狀態。形成多個通孔於第一黏著材料層中，以暴露出部分同軸導電件。形成第一導電連接材料於多個通孔中。 In an embodiment of the present invention, the above-mentioned manufacturing method further includes forming a first adhesive material layer on the upper surface of the interposer substrate, wherein the first adhesive material layer is in a semi-cured state. A plurality of through holes are formed in the first adhesive material layer to expose part of the coaxial conductive member. Form first conductive connection material in the plurality of through holes.

在本發明的一實施例中，上述的第一導電連接材料包括 銅膠、銀膠或暫態液相燒結膠。 In an embodiment of the present invention, the above-mentioned first conductive connection material includes Copper glue, silver glue or transient liquid phase sintering glue.

在本發明的一實施例中，上述的將線路結構壓合於中介層基板的上表面上的步驟包括於第一溫度下，壓合線路結構與中介層基板以使線路結構的多個接墊與第一導電連接材料對應連接，並固化第一黏著材料層。 In an embodiment of the present invention, the above-mentioned step of laminating the circuit structure on the upper surface of the interposer substrate includes laminating the circuit structure and the interposer substrate at a first temperature so that the plurality of pads of the circuit structure Correspondingly connect with the first conductive connection material, and solidify the first adhesive material layer.

在本發明的一實施例中，上述的接合電路基板於中介層基板的下表面上的步驟包括形成阻焊層於中介層基板的下表面上，其中阻焊層包括多個通孔，以暴露出部分同軸導電件。形成第二導電連接材料於多個通孔中。透過第二導電連接材料對應接合同軸導電件與電路基板的多個接墊。 In one embodiment of the present invention, the step of bonding the circuit substrate to the lower surface of the interposer substrate includes forming a solder resist layer on the lower surface of the interposer substrate, wherein the solder resist layer includes a plurality of through holes to expose Take out some coaxial conductive parts. Second conductive connection materials are formed in the plurality of through holes. The coaxial conductive component and the plurality of pads of the circuit substrate are correspondingly connected through the second conductive connection material.

在本發明的一實施例中，上述的第二導電連接材料包括錫膏或焊球。 In an embodiment of the present invention, the above-mentioned second conductive connection material includes solder paste or solder balls.

在本發明的一實施例中，上述的第一溫度在180℃至220℃之間，第二溫度在250℃至270℃之間。 In an embodiment of the present invention, the above-mentioned first temperature is between 180°C and 220°C, and the second temperature is between 250°C and 270°C.

基於上述，本發明的電子封裝結構可整合電路基板、中介層以及線路結構於一封裝結構中，且晶片設置於中介層的空腔中，使空間得以有效的被利用，進而有利於電子封裝結構的微型化，並且由於中介層由導電材料構成，有助於提升晶片的散熱能力。此外，由於中介層包括用以電性連接線路結構及電路基板的同軸導電件，可降低線路結構所接收或發出的射頻訊號在傳輸過程中的訊號損耗，並可屏蔽電磁干擾訊號，以提升訊號的完整性。 Based on the above, the electronic packaging structure of the present invention can integrate the circuit substrate, interposer and circuit structure into a package structure, and the chip is arranged in the cavity of the interposer, so that the space can be effectively utilized, which is beneficial to the electronic packaging structure. Miniaturization, and because the interposer is made of conductive materials, it helps to improve the heat dissipation capacity of the chip. In addition, because the interposer layer includes coaxial conductive elements that are used to electrically connect the circuit structure and the circuit substrate, it can reduce the signal loss during the transmission process of the radio frequency signals received or emitted by the circuit structure, and can shield electromagnetic interference signals to improve the signal of integrity.

10,20:電子封裝結構 10,20: Electronic packaging structure

100:電路基板 100:Circuit substrate

100’,200’:結構 100’, 200’: structure

101:核心基板 101:Core substrate

102:絕緣層 102:Insulation layer

110:線路層 110: Line layer

112,114:接墊 112,114: Pad

120:阻焊層 120: Solder mask

130:晶片 130:Chip

130a:主動面 130a: Active side

130b:背面 130b: Back

132:接點 132:Contact

140:底膠 140: Primer

150:熱界面材料 150: Thermal interface materials

200:中介層 200: Intermediary layer

201,201’:核心基板 201,201’: Core substrate

201a,201a’:第一側 201a, 201a’: first side

201b,201b’:第二側 201b,201b’: second side

202,202’:第一導電材料層 202,202’: first conductive material layer

203,203’:第一導電層 203,203’: first conductive layer

205:中介層基板 205:Interposer substrate

205a:上表面 205a: Upper surface

205b:下表面 205b: Lower surface

210:同軸導電件 210: Coaxial conductive parts

211:絕緣材料 211:Insulating materials

212:第一絕緣結構 212: First insulation structure

214:第一導電結構 214: First conductive structure

214a:第一接墊部分 214a: First pad part

214b:第一導電柱部分 214b: First conductive pillar part

216:第二導電結構 216: Second conductive structure

216a:第二接墊部分 216a: Second pad part

216b:第二導電柱部分 216b: Second conductive pillar part

220:第一黏著層 220: First adhesive layer

220’:第一黏著材料層 220’: First adhesive material layer

222:離型膜 222: Release film

230,232:空腔 230,232:Cavity

230a,230b,232a,232b:側壁 230a, 230b, 232a, 232b: side wall

230c:底面 230c: Bottom surface

240:第一導電連接件 240: First conductive connector

240a:中間導電連接件 240a: Intermediate conductive connector

240b:周邊導電連接件 240b: Peripheral conductive connectors

240’:第一導電連接材料 240’: First conductive connection material

260:阻焊層 260: Solder mask

270:第二導電連接件 270: Second conductive connector

270’:第二導電連接材料 270’: Second conductive connection material

300:線路結構 300: Line structure

301:第一核心層 301: First core layer

301a:第一表面 301a: First surface

301b:第二表面 301b: Second surface

302,303:絕緣層 302,303: Insulation layer

305:導電柱 305:Conductive pillar

311,313:導電層 311,313: Conductive layer

312:第一天線層 312: First antenna layer

314:第二天線層 314: Second antenna layer

316:接墊 316: Pad

316a:第一接墊 316a: first pad

316b,316b’:第二接墊 316b, 316b’: second pad

320:阻焊層 320: Solder mask

A1,R1,R2:區域 A1,R1,R2:Area

CV1,CV2:導通孔 CV1, CV2: via holes

OP1,OP2,OP3:開口 OP1, OP2, OP3: opening

P:部分 P:part

PR:圖案化光阻層 PR: Patterned photoresist layer

T:環形凹槽 T: Annular groove

TH1:第一貫通孔 TH1: First through hole

TH2:第二貫通孔 TH2: Second through hole

V1,V1a,V1b,V1a’,V1b’,V2,V3:通孔 V1, V1a, V1b, V1a’, V1b’, V2, V3: through holes

d1,d2:孔徑 d1, d2: aperture

d3,d4:直徑 d3,d4: diameter

d5:距離 d5: distance

d6:外徑 d6:Outer diameter

d7:寬度 d7:width

圖1是依照本發明的一實施例的一種電子封裝結構的剖視示意圖。 FIG. 1 is a schematic cross-sectional view of an electronic packaging structure according to an embodiment of the present invention.

圖2是圖1的電子封裝結構的一種上視示意圖。 FIG. 2 is a schematic top view of the electronic packaging structure of FIG. 1 .

圖3是依照本發明的另一實施例的一種電子封裝結構的剖視示意圖。 FIG. 3 is a schematic cross-sectional view of an electronic packaging structure according to another embodiment of the present invention.

圖4A至圖4C是依照本發明的一實施例的一種晶片設置於電路基板的製造流程的剖視示意圖。 4A to 4C are schematic cross-sectional views of a manufacturing process of placing a chip on a circuit substrate according to an embodiment of the present invention.

圖5A至圖5F是依照本發明的一實施例的一種包含同軸導電件的中介層的製造流程的剖視示意圖。 5A to 5F are schematic cross-sectional views of a manufacturing process of an interposer including coaxial conductive elements according to an embodiment of the present invention.

圖6A至圖6F是依照本發明的另一實施例的一種包含同軸導電件的中介層的製造流程的剖視示意圖。 6A to 6F are schematic cross-sectional views of a manufacturing process of an interposer including coaxial conductive elements according to another embodiment of the present invention.

圖7A至圖7D是依照本發明的一實施例的一種第一導電連接件的製造流程的剖視示意圖。 7A to 7D are schematic cross-sectional views of a manufacturing process of a first conductive connector according to an embodiment of the present invention.

圖8A至圖8B是圖7B的區域R1的一種局部上視示意圖。 8A to 8B are a partial top view of the region R1 of FIG. 7B.

圖9A至圖9C是依照本發明的一實施例的一種線路結構的示意圖。 9A to 9C are schematic diagrams of a circuit structure according to an embodiment of the present invention.

圖10A至圖10E是依照本發明的一實施例的一種電子封裝結構的製造流程的剖視示意圖。 10A to 10E are schematic cross-sectional views of a manufacturing process of an electronic packaging structure according to an embodiment of the present invention.

下文列舉實施例並配合所附圖式來進行詳細地說明，但所提供的實施例並非用以限制本發明所涵蓋的範圍。此外，圖式僅以說明為目的，並未依照原尺寸作圖。為了方便理解，下述說明中相同的元件將以相同的符號標示來說明。 Examples are listed below and described in detail with reference to the accompanying drawings. However, the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to original size. To facilitate understanding, the same components in the following description will be identified with the same symbols.

此外，關於文中所使用「包含」、「包括」、「具有」等等用語，均為開放性的用語，也就是指「包括但不限於」。 In addition, the terms "including", "including", "having", etc. used in the article are all open terms, which means "including but not limited to".

應當理解，儘管術語「第一」、「第二」、「第三」等在本文中可以用於描述各種元件、部件、區域、層及/或部分，但是這些元件、部件、區域、及/或部分不應受這些術語的限制。這些術語僅用於將一個元件、部件、區域、層或部分與另一個元件、部件、區域、層或部分區分開。因此，下面討論的「第一元件」、「部件」、「區域」、「層」、或「部分」可以被稱為第二元件、部件、區域、層或部分而不脫離本文的教導。 It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

本文中所提到的方向用語，例如：「上」、「下」、「前」、「後」、「左」、「右」等，僅是參考附圖的方向。因此，使用的方向用語是用來說明，而並非用來限制本發明。 The directional terms mentioned in this article, such as "up", "down", "front", "back", "left", "right", etc., are only for reference to the directions in the accompanying drawings. Accordingly, the directional terms used are illustrative and not limiting of the invention.

在附圖中，各圖式繪示的是特定實施例中所使用的方法、結構及/或材料的通常性特徵。然而，這些圖式不應被解釋為界定或限制由這些實施例所涵蓋的範圍或性質。舉例來說，為了清楚起見，各膜層、區域及/或結構的相對尺寸、厚度及位置可能縮小或放大。 In the drawings, each figure illustrates the general features of methods, structures, and/or materials used in particular embodiments. However, these drawings should not be interpreted as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.

在下述實施例中，相同或相似的元件將採用相同或相似 的標號，且將省略其贅述。此外，不同實施例中的特徵在沒有衝突的情況下可相互組合，且依本說明書或申請專利範圍所作之簡單的等效變化與修飾，皆仍屬本專利涵蓋的範圍內。 In the following embodiments, the same or similar elements will be used. label, and its detailed description will be omitted. In addition, features in different embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made in accordance with this specification or the scope of the patent application are still within the scope of this patent.

圖1是依照本發明的一實施例的一種電子封裝結構的剖視示意圖。圖2是圖1的電子封裝結構的一種上視示意圖。為了清楚示意，圖2僅繪示晶片130、第一導電連接件240及第一黏著層220並省略繪示其他構件，省略的部分可參考圖1加以理解。 FIG. 1 is a schematic cross-sectional view of an electronic packaging structure according to an embodiment of the present invention. FIG. 2 is a schematic top view of the electronic packaging structure of FIG. 1 . For clarity of illustration, FIG. 2 only shows the chip 130, the first conductive connector 240 and the first adhesive layer 220 and omits other components. The omitted parts can be understood with reference to FIG. 1 .

請參照圖1與圖2，電子封裝結構10包括電路基板100、中介層200、晶片130以及線路結構300。中介層200包括中介層基板205以及同軸導電件210。中介層基板205具有上表面205a及相對於上表面205a的下表面205b，且中介層基板205包括空腔230。同軸導電件210位於中介層基板205中。同軸導電件210包括第一導電結構214、第二導電結構216以及第一絕緣結構212。第二導電結構216環繞第一導電結構214。第一絕緣結構212設置於第一導電結構214與第二導電結構216之間。電路基板100設置於中介層基板205的下表面205b上，並與同軸導電件210電性連接。晶片130設置於空腔230中且位於電路基板100上，以與電路基板100電性連接。線路結構300設置於中介層基板205的上表面205a上，並與同軸導電件210電性連接。 Referring to FIGS. 1 and 2 , the electronic packaging structure 10 includes a circuit substrate 100 , an interposer 200 , a chip 130 and a circuit structure 300 . The interposer 200 includes an interposer substrate 205 and a coaxial conductive member 210 . The interposer substrate 205 has an upper surface 205a and a lower surface 205b opposite to the upper surface 205a, and the interposer substrate 205 includes a cavity 230. The coaxial conductive member 210 is located in the interposer substrate 205 . The coaxial conductive member 210 includes a first conductive structure 214 , a second conductive structure 216 and a first insulating structure 212 . The second conductive structure 216 surrounds the first conductive structure 214 . The first insulating structure 212 is disposed between the first conductive structure 214 and the second conductive structure 216 . The circuit substrate 100 is disposed on the lower surface 205b of the interposer substrate 205 and is electrically connected to the coaxial conductive member 210. The chip 130 is disposed in the cavity 230 and located on the circuit substrate 100 to be electrically connected to the circuit substrate 100 . The circuit structure 300 is disposed on the upper surface 205a of the interposer substrate 205 and is electrically connected to the coaxial conductive member 210.

由於晶片130可設置於中介層200的空腔230中，可有效利用空間，進而減小電子封裝結構10的體積。由於中介層200包括同軸導電件210以電性連接線路結構300及電路基板100，可 降低線路結構300所接收或發出的射頻訊號在傳輸過程中的訊號損耗，並可屏蔽電磁干擾訊號，以提升訊號的完整性。 Since the chip 130 can be disposed in the cavity 230 of the interposer 200 , space can be effectively utilized, thereby reducing the volume of the electronic packaging structure 10 . Since the interposer 200 includes the coaxial conductive member 210 to electrically connect the circuit structure 300 and the circuit substrate 100, it can The signal loss during the transmission process of the radio frequency signals received or sent by the line structure 300 is reduced, and electromagnetic interference signals can be shielded to improve signal integrity.

在一些實施例中，中介層基板205的材質可為導電材料，較佳地可以是導電且導熱的材料，例如銅、鋁或其他合適的金屬材料或上述材料的合金。如此一來，同軸導電件210可由部分中介層基板205構成，且中介層基板205具有散熱能力。 In some embodiments, the material of the interposer substrate 205 can be a conductive material, preferably an electrically conductive and thermally conductive material, such as copper, aluminum or other suitable metal materials or alloys of the above materials. In this way, the coaxial conductive member 210 can be formed by part of the interposer substrate 205, and the interposer substrate 205 has heat dissipation capability.

在一些實施例中，空腔230為自下表面205b向上表面205a凹下的凹陷，空腔230可由中介層基板205的側壁230a、230b及底面230c構成。也就是說，空腔230不貫穿中介層基板205，但本發明不以此為限。在其他實施例中，空腔230可貫穿中介層基板205。 In some embodiments, the cavity 230 is a depression that is concave from the lower surface 205b to the upper surface 205a. The cavity 230 may be formed by the sidewalls 230a, 230b and the bottom surface 230c of the interposer substrate 205. That is to say, the cavity 230 does not penetrate the interposer substrate 205, but the present invention is not limited thereto. In other embodiments, cavity 230 may extend through interposer substrate 205 .

在一些實施例中，空腔230的尺寸(例如長、寬、高)至少大於晶片130的尺寸，以使晶片130可容納於空腔230中。 In some embodiments, the dimensions (eg, length, width, height) of the cavity 230 are at least larger than the dimensions of the wafer 130 so that the wafer 130 can be accommodated in the cavity 230 .

在一些實施例中，線路結構300包括第一核心層301、第一天線層312、第二天線層314以及多個接墊316。第一核心層301具有第一表面301a及與第一表面301a相對的第二表面301b，其中第二表面301b面向中介層200。第一天線層312設置在第一表面301a上。第二天線層314與多個接墊316設置在第二表面301b上。多個接墊316可包括第一接墊316a及第二接墊316b。第一接墊316a對應於同軸導電件210的第一導電結構214，多個第二接墊316b對應於同軸導電件210的第二導電結構216。 In some embodiments, the circuit structure 300 includes a first core layer 301 , a first antenna layer 312 , a second antenna layer 314 and a plurality of pads 316 . The first core layer 301 has a first surface 301a and a second surface 301b opposite to the first surface 301a, wherein the second surface 301b faces the interposer 200. The first antenna layer 312 is provided on the first surface 301a. The second antenna layer 314 and the plurality of contact pads 316 are disposed on the second surface 301b. The plurality of pads 316 may include a first pad 316a and a second pad 316b. The first pad 316a corresponds to the first conductive structure 214 of the coaxial conductive component 210, and the plurality of second pads 316b corresponds to the second conductive structure 216 of the coaxial conductive component 210.

在一些實施例中，第一導電連接件240可設置於線路結 構300的多個接墊316與同軸導電件210之間，以使接墊316與同軸導電件210電性連接。在一些實施例中，第一導電連接件240的材料可包括銅、銀、銅合金、銅錫合金、錫鉍合金或其他合適材料，本發明不以此為限。 In some embodiments, the first conductive connection 240 may be disposed at the circuit junction. between the plurality of pads 316 of the structure 300 and the coaxial conductive member 210, so that the pads 316 and the coaxial conductive member 210 are electrically connected. In some embodiments, the material of the first conductive connection member 240 may include copper, silver, copper alloy, copper-tin alloy, tin-bismuth alloy or other suitable materials, but the present invention is not limited thereto.

在一些實施例中，由俯視觀之，如圖2所示，對應於同軸導電件210的第一導電連接件240的排列圖案可與線路結構300的多個接墊316的排列(可參考後述圖9B、9C及其相關內容)對應。也就是說，第一導電連接件240可以包括與第一接墊316a對應的中間導電連接件240a，以及與第二接墊316b對應的周邊導電連接件240b。在一些實施例中，第二接墊316b為環形接墊，因此周邊導電連接件240b可以對應地為環形而環繞中間導電連接件240a。在其他實施例中，第二接墊316b包括多個環繞第一接墊316a的接墊，因此周邊導電連接件240b可以對應地為多個周邊導電連接件240b’，並環繞中間導電連接件240a。 In some embodiments, viewed from a top view, as shown in FIG. 2 , the arrangement pattern of the first conductive connecting members 240 corresponding to the coaxial conductive members 210 may be the same as the arrangement of the plurality of pads 316 of the circuit structure 300 (please refer to the following description). Figures 9B, 9C and related contents) correspond. That is, the first conductive connection 240 may include a middle conductive connection 240a corresponding to the first pad 316a, and a peripheral conductive connection 240b corresponding to the second pad 316b. In some embodiments, the second pad 316b is an annular pad, so the peripheral conductive connector 240b can be correspondingly annular and surround the middle conductive connector 240a. In other embodiments, the second pad 316b includes a plurality of pads surrounding the first pad 316a, so the peripheral conductive connector 240b may be a plurality of peripheral conductive connectors 240b' and surround the middle conductive connector 240a. .

圖2中雖繪示電子封裝結構10包括兩種對應於同軸導電件210的第一導電連接件240的排列圖案，但並非用以限定本發明。電子封裝結構10的第一導電連接件240可以包括一種或多種對應於同軸導電件210的排列圖案。 Although FIG. 2 shows that the electronic package structure 10 includes two arrangement patterns of the first conductive connecting members 240 corresponding to the coaxial conductive members 210, this is not intended to limit the present invention. The first conductive connection member 240 of the electronic package structure 10 may include one or more arrangement patterns corresponding to the coaxial conductive members 210 .

在一些實施例中，同軸導電件210可設置於晶片130的周圍，但本發明不以此為限。圖1、2中雖繪示同軸導電件210對稱設置於晶片130的兩側，但並非用以限定本發明，同軸導電件210的位置及數量可依據實際需求調整。 In some embodiments, the coaxial conductive member 210 may be disposed around the chip 130, but the invention is not limited thereto. Although the coaxial conductive members 210 are shown symmetrically disposed on both sides of the chip 130 in FIGS. 1 and 2 , this is not intended to limit the present invention. The position and number of the coaxial conductive members 210 can be adjusted according to actual needs.

在一些實施例中，電子封裝結構10還包括第一黏著層220。第一黏著層220設置於中介層200與線路結構300之間，以利中介層200與線路結構300的接合。 In some embodiments, the electronic packaging structure 10 further includes a first adhesive layer 220 . The first adhesive layer 220 is disposed between the interposer layer 200 and the circuit structure 300 to facilitate the bonding of the interposer layer 200 and the circuit structure 300 .

在一些實施例中，電路基板100可以是印刷電路板(PCB)、柔性印刷電路板(FPC)或其他合適電路板。舉例來說，電路基板100包括多個交替堆疊的絕緣層及線路層(詳細內容可參考後述圖4A的相關內容)。在一些實施例中，電路基板100包括對應於晶片130的接墊112以及對應於同軸導電件210的接墊114。 In some embodiments, circuit substrate 100 may be a printed circuit board (PCB), flexible printed circuit board (FPC), or other suitable circuit board. For example, the circuit substrate 100 includes a plurality of alternately stacked insulation layers and circuit layers (for details, please refer to the relevant content of FIG. 4A described later). In some embodiments, the circuit substrate 100 includes pads 112 corresponding to the wafer 130 and pads 114 corresponding to the coaxial conductive members 210 .

在一些實施例中，晶片130具有主動面130a及相對於主動面130a的背面130b。晶片130的主動面130a面向電路基板100，並與電路基板100電性連接。 In some embodiments, the wafer 130 has an active side 130a and a backside 130b opposite the active side 130a. The active surface 130a of the chip 130 faces the circuit substrate 100 and is electrically connected to the circuit substrate 100.

在一些實施例中，電子封裝結構10還包括熱界面材料150設置於晶片130的背面130b並與空腔230的底面230c接觸。如此一來，晶片130可透過熱界面材料150散熱，並可進一步將熱傳導至中介層基板205，以使電子封裝結構10的散熱能力提升。 In some embodiments, the electronic packaging structure 10 further includes a thermal interface material 150 disposed on the backside 130b of the chip 130 and in contact with the bottom surface 230c of the cavity 230. In this way, the chip 130 can dissipate heat through the thermal interface material 150 and further conduct the heat to the interposer substrate 205 to improve the heat dissipation capability of the electronic packaging structure 10 .

在一些實施例中，電子封裝結構10還包括第二導電連接件270，其可設置於電路基板100與同軸導電件210之間。舉例來說，第二導電連接件270可設置於電路基板100的接墊114與同軸導電件210之間，以使接墊114與同軸導電件210電性連接。在一些實施例中，第二導電連接件270的材料可包括錫、銅錫合金、無鉛合金或其他合適材料，本發明不以此為限。 In some embodiments, the electronic package structure 10 further includes a second conductive connection member 270 , which may be disposed between the circuit substrate 100 and the coaxial conductive member 210 . For example, the second conductive connection member 270 may be disposed between the pad 114 of the circuit substrate 100 and the coaxial conductive member 210 so that the contact pad 114 and the coaxial conductive member 210 are electrically connected. In some embodiments, the material of the second conductive connection member 270 may include tin, copper-tin alloy, lead-free alloy or other suitable materials, but the present invention is not limited thereto.

在一些實施例中，同軸導電件210的第一導電結構214適於傳輸訊號，第二導電結構216適於接地或與電源連接。也就是說，電路基板100對應於第一導電結構214的接墊114可為訊號接墊，電路基板100對應於第二導電結構216的接墊114可為接地接墊或電源接墊。 In some embodiments, the first conductive structure 214 of the coaxial conductive member 210 is suitable for transmitting signals, and the second conductive structure 216 is suitable for grounding or connecting to a power source. That is to say, the pads 114 of the circuit substrate 100 corresponding to the first conductive structure 214 can be signal pads, and the pads 114 of the circuit substrate 100 corresponding to the second conductive structure 216 can be ground pads or power pads.

圖3是依照本發明的另一實施例的一種電子封裝結構的剖視示意圖。在此必須說明的是，圖3的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 3 is a schematic cross-sectional view of an electronic packaging structure according to another embodiment of the present invention. It must be noted here that the embodiment of FIG. 3 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

請參照圖3，圖3的電子封裝結構20與圖1的電子封裝結構10的主要差異在於：電子封裝結構20的中介層基板205包括空腔232，空腔232貫穿中介層基板205。也就是說，空腔232由中介層基板205的側壁232a、232b構成，但不具有底面，因而空腔232可暴露出第一黏著層220的表面。 Please refer to FIG. 3 . The main difference between the electronic packaging structure 20 of FIG. 3 and the electronic packaging structure 10 of FIG. 1 is that the interposer substrate 205 of the electronic packaging structure 20 includes a cavity 232 , and the cavity 232 penetrates the interposer substrate 205 . That is to say, the cavity 232 is formed by the sidewalls 232a and 232b of the interposer substrate 205 but does not have a bottom surface, so the cavity 232 can expose the surface of the first adhesive layer 220 .

在本實施例中，晶片130的背面130b並未設置熱界面材料，但並非用以限定本發明，熱界面材料可依實際需求設置。 In this embodiment, the thermal interface material is not provided on the backside 130b of the chip 130, but this is not intended to limit the present invention. The thermal interface material can be provided according to actual requirements.

圖4A至圖4C是依照本發明的一實施例的一種晶片設置於電路基板的製造流程的剖視示意圖。在此必須說明的是，圖4A至圖4C的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在 此不贅述。 4A to 4C are schematic cross-sectional views of a manufacturing process of placing a chip on a circuit substrate according to an embodiment of the present invention. It must be noted here that the embodiments of FIGS. 4A to 4C follow the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, please refer to the foregoing embodiments. No need to go into details.

請參照圖4A，提供電路基板100。舉例來說，電路基板100可包括核心基板101以及交替堆疊於核心基板101兩側的絕緣層102與線路層110。線路層110的最頂層可包括多個接墊112、114，接墊112可以是作為後續與晶片130的接點對應連接的接墊，接墊114可以是作為後續與同軸導電件210對應連接的接墊。 Referring to FIG. 4A , a circuit substrate 100 is provided. For example, the circuit substrate 100 may include a core substrate 101 and insulating layers 102 and circuit layers 110 alternately stacked on both sides of the core substrate 101 . The topmost layer of the circuit layer 110 may include a plurality of pads 112 and 114. The pad 112 may be a pad that is subsequently connected to the contact point of the chip 130. The pad 114 may be a pad that is subsequently connected to the coaxial conductive member 210. Pad.

應理解，圖4A僅示意性的繪示兩層絕緣層102及四層線路層110於核心基板101上，但並非用以限定本發明，絕緣層及線路層的數量及線路層的佈線設計可依實際需求調整。此外，雖然本發明的核心層中並未繪示任何導通孔，但並非用以限定本發明，其可依實際需求設置導通孔於核心層中。 It should be understood that FIG. 4A only schematically illustrates two layers of insulation layers 102 and four layers of circuit layers 110 on the core substrate 101, but is not intended to limit the present invention. The number of insulation layers and circuit layers and the wiring design of the circuit layers can be Adjust according to actual needs. In addition, although no via holes are shown in the core layer of the present invention, this is not intended to limit the present invention, and via holes can be provided in the core layer according to actual needs.

請參照圖4B，形成阻焊層120於電路基板100的兩側上。阻焊層120具有多個開口OP1以暴露出電路基板100最外側的部分線路層110。舉例來說，接墊112、114被開口OP1暴露出，以利於後續與其他構件的連接。阻焊層120的材料可以為防焊材料(例如綠漆)、感光型介電材料或其他合適材料。 Referring to FIG. 4B , a solder resist layer 120 is formed on both sides of the circuit substrate 100 . The solder resist layer 120 has a plurality of openings OP1 to expose the outermost portion of the circuit layer 110 of the circuit substrate 100 . For example, the pads 112 and 114 are exposed by the opening OP1 to facilitate subsequent connection with other components. The material of the solder resist layer 120 may be a solder resist material (such as green paint), a photosensitive dielectric material, or other suitable materials.

請參照圖4C，設置晶片130於電路基板100上。舉例來說，晶片130的主動面130a上可包括多個接點132，接點132與電路基板100的接墊112對應，使晶片130設置於電路基板100上且電性連接。 Referring to FIG. 4C , the chip 130 is placed on the circuit substrate 100 . For example, the active surface 130a of the chip 130 may include a plurality of contacts 132 corresponding to the pads 112 of the circuit substrate 100, so that the chip 130 is disposed on the circuit substrate 100 and electrically connected.

在一些實施例中，在晶片130的接點132與電路基板100的接墊112對應連接前，可於暴露出接墊112的開口OP1中設置 底膠140，再進行後續接合，以提升晶片130與電路基板100的接合強度，其中底膠140的材料例如為環氧樹脂焊錫膏(epoxy solder paste)或其他合適材料。在其他實施例中，底膠140的材料也可以是環氧樹脂助焊劑(epoxy flux)、環氧樹脂膠(epoxy glue)或其他合適材料，並可在晶片130的接點132與電路基板100的接墊112對應連接之後，設置底膠140於晶片130與電路基板100之間。在又一些其他實施例中，可不設置底膠140，直接將晶片130的接點132與電路基板100的接墊112對應接合。 In some embodiments, before the contacts 132 of the chip 130 are connected to the pads 112 of the circuit substrate 100, they may be disposed in the openings OP1 exposing the pads 112. The primer 140 is then used for subsequent bonding to enhance the bonding strength between the chip 130 and the circuit substrate 100 . The material of the primer 140 is, for example, epoxy solder paste or other suitable materials. In other embodiments, the material of the primer 140 can also be epoxy flux, epoxy glue or other suitable materials, and can be used between the contact 132 of the chip 130 and the circuit substrate 100 After the corresponding pads 112 are connected, the primer 140 is disposed between the chip 130 and the circuit substrate 100 . In some other embodiments, the base glue 140 may not be provided, and the contacts 132 of the chip 130 and the contact pads 112 of the circuit substrate 100 may be directly connected to each other.

在一些實施例中，底膠140可設置於晶片130與電路基板100之間的空間，以橫向覆蓋部分接點132的側壁，或者完全覆蓋接點132的側壁。 In some embodiments, the primer 140 may be disposed in the space between the chip 130 and the circuit substrate 100 to laterally cover part of the sidewalls of the contacts 132 or completely cover the sidewalls of the contacts 132 .

在一些實施例中，可設置熱界面材料150於晶片130的背面130b上，但本發明不以此為限。 In some embodiments, the thermal interface material 150 can be disposed on the backside 130b of the chip 130, but the invention is not limited thereto.

經過上述製程後可大致上完成包含晶片130的電路基板100的結構100’的製作。 After the above process, the fabrication of the structure 100' of the circuit substrate 100 including the wafer 130 can be substantially completed.

圖5A至圖5F是依照本發明的一實施例的一種包含同軸導電件的中介層基板的製造流程的剖視示意圖。在此必須說明的是，圖5A至圖5F的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 5A to 5F are schematic cross-sectional views of a manufacturing process of an interposer substrate including coaxial conductive elements according to an embodiment of the present invention. It must be noted here that the embodiments of FIGS. 5A to 5F follow the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

請參照圖5A，提供核心基板201。舉例來說，核心基板 201包括具有第一側201a與相對於第一側201a的第二側201b。核心基板201例如可為銅板、鋁板、合金板或其他合適的導電材料。核心基板201的厚度可以在150μm至250μm之間。 Referring to FIG. 5A, a core substrate 201 is provided. For example, the core substrate 201 includes a first side 201a and a second side 201b opposite the first side 201a. The core substrate 201 may be, for example, a copper plate, an aluminum plate, an alloy plate or other suitable conductive materials. The thickness of the core substrate 201 may be between 150 μm and 250 μm.

請參照圖5B，形成第一貫通孔TH1於核心基板201中。舉例來說，可透過機械鑽孔或蝕刻等方式，於核心基板201中形成貫穿核心基板201的第一貫通孔TH1。第一貫通孔TH1的孔徑d1可以在250μm至450μm之間。 Referring to FIG. 5B , a first through hole TH1 is formed in the core substrate 201 . For example, the first through hole TH1 penetrating the core substrate 201 can be formed in the core substrate 201 through mechanical drilling or etching. The pore diameter d1 of the first through hole TH1 may be between 250 μm and 450 μm.

請參照圖5C，填充絕緣材料211於第一貫通孔TH1中。絕緣材料211例如可以是環氧樹脂、聚酯樹脂、聚醯亞胺或其他合適的絕緣材料。 Referring to FIG. 5C , the insulating material 211 is filled in the first through hole TH1. The insulating material 211 may be, for example, epoxy resin, polyester resin, polyimide or other suitable insulating materials.

請參照圖5D，形成第二貫通孔TH2於絕緣材料211中，以形成第一絕緣結構212。舉例來說，可透過機械鑽孔或雷射等方式，於絕緣材料211的中心處形成第二貫通孔TH2。也就是說，第二貫通孔TH2與第一貫通孔TH1(標示於圖5B)基本上具有相同的軸心。第二貫通孔TH2的孔徑d2可以在50μm至100μm之間。由於第二貫通孔TH2的形成，絕緣材料211有部分被移除而成為第一絕緣結構212。第一絕緣結構212為空心圓柱，也就是說，若以俯視觀之，第一絕緣結構212的形狀為環形。 Referring to FIG. 5D , a second through hole TH2 is formed in the insulating material 211 to form the first insulating structure 212 . For example, the second through hole TH2 can be formed in the center of the insulating material 211 through mechanical drilling or laser. That is to say, the second through hole TH2 and the first through hole TH1 (marked in FIG. 5B ) basically have the same axis center. The pore diameter d2 of the second through hole TH2 may be between 50 μm and 100 μm. Due to the formation of the second through hole TH2, part of the insulating material 211 is removed to form the first insulating structure 212. The first insulation structure 212 is a hollow cylinder, that is to say, when viewed from above, the shape of the first insulation structure 212 is an annular shape.

請參照圖5E，形成第一導電材料層202於核心基板201的第一側201a與第二側201b上及第二貫通孔TH2(標示於圖5D)中。舉例來說，可透過電鍍或沉積製程，將導電材料(例如銅、鋁或其他合適的導電材料或上述材料的合金)形成於核心基板201的 第一側201a及第二側201b上，並填入第二貫通孔TH2中，以形成第一導電材料層202。在一些實施例中，第一導電材料層202可填滿於第二貫通孔TH2中。 Referring to FIG. 5E , a first conductive material layer 202 is formed on the first side 201 a and the second side 201 b of the core substrate 201 and in the second through hole TH2 (marked in FIG. 5D ). For example, a conductive material (such as copper, aluminum or other suitable conductive materials or alloys of the above materials) can be formed on the core substrate 201 through an electroplating or deposition process. on the first side 201a and the second side 201b, and fill the second through hole TH2 to form the first conductive material layer 202. In some embodiments, the first conductive material layer 202 may be filled in the second through hole TH2.

在一些實施例中，第一導電材料層202與核心基板201的材質為相同，因此第一導電材料層202與核心基板201之間可能不存在界面，但為了使製造流程清楚，圖5E、5F以虛線將第一導電材料層202與核心基板201區分。 In some embodiments, the first conductive material layer 202 and the core substrate 201 are made of the same material, so there may be no interface between the first conductive material layer 202 and the core substrate 201. However, in order to make the manufacturing process clear, Figures 5E and 5F The first conductive material layer 202 is distinguished from the core substrate 201 by a dotted line.

請參照圖5F，圖案化第一導電材料層202，以暴露出部分第一絕緣結構212。舉例來說，可透過蝕刻的方式，圖案化第一導電材料層202，以移除部分覆蓋第一絕緣結構212的第一導電材料層202，而形成開口OP2於第一導電層203中。也就是說，開口OP2可暴露出第一絕緣結構212，而第一導電層203覆蓋於核心基板201的第一側201a與第二側201b上及填充於第二貫通孔TH2(標示於圖5D)中。第一絕緣結構212、部分第一導電層203及部分核心基板201可構成同軸導電件210。詳細而言，同軸導電件210可包括第一導電結構214、第二導電結構216以及第一絕緣結構212。第一導電結構214可包括第一導電柱部分214b及位於第一導電柱部分214b兩端的第一接墊部分214a。第一接墊部分214a設置於第一側201a與第二側201b上並與第二貫通孔TH2重疊，第一導電柱部分214b位於第二貫通孔TH2中，以電性連接其兩端的第一接墊部分214a。也就是說，部分第一導電層203可構成第一接墊部分214a及第一導電柱部分214b。在一些實施例中，第一 接墊部分214a的直徑可以大於第一導電柱部分214b的直徑，例如第一接墊部分214a的直徑d3可以在75μm至175μm之間，第一導電柱部分214b的直徑d4可以在50μm至100μm之間。 Referring to FIG. 5F , the first conductive material layer 202 is patterned to expose part of the first insulating structure 212 . For example, the first conductive material layer 202 can be patterned by etching to remove part of the first conductive material layer 202 covering the first insulating structure 212 to form the opening OP2 in the first conductive layer 203 . That is to say, the opening OP2 can expose the first insulating structure 212, and the first conductive layer 203 covers the first side 201a and the second side 201b of the core substrate 201 and fills the second through hole TH2 (marked in FIG. 5D )middle. The first insulating structure 212 , part of the first conductive layer 203 and part of the core substrate 201 may form the coaxial conductive member 210 . In detail, the coaxial conductive member 210 may include a first conductive structure 214 , a second conductive structure 216 and a first insulating structure 212 . The first conductive structure 214 may include a first conductive pillar portion 214b and first pad portions 214a located at both ends of the first conductive pillar portion 214b. The first pad portion 214a is disposed on the first side 201a and the second side 201b and overlaps the second through hole TH2. The first conductive pillar portion 214b is located in the second through hole TH2 to electrically connect the first conductive post portion 214b at both ends. Pad portion 214a. That is to say, part of the first conductive layer 203 may form the first pad portion 214a and the first conductive pillar portion 214b. In some embodiments, the first The diameter of the pad portion 214a may be larger than the diameter of the first conductive pillar portion 214b. For example, the diameter d3 of the first pad portion 214a may be between 75 μm and 175 μm, and the diameter d4 of the first conductive pillar part 214b may be between 50 μm and 100 μm. between.

第二導電結構216環繞第一導電結構214。第二導電結構216可包括第二導電柱部分216b及位於第二導電柱部分216b兩端的第二接墊部分216a。第二接墊部分216a設置於第一側201a與第二側201b上並環繞第一接墊部分214a，開口OP2將第一接墊部分214a與將第二接墊部分216a分離，也就是說，第二接墊部分216a不與第一接墊部分214a連接。第二導電柱部分216b連接其兩端的第二接墊部分216a，且環繞第一導電柱部分214b。第一絕緣結構212設置於第一導電結構214與第二導電結構216之間，以使第一導電結構214與第二導電結構216電性分離。在本實施例中，第二接墊部分216a可由部分第一導電層203構成，第二導電柱部分216b可由部分核心基板201構成。 The second conductive structure 216 surrounds the first conductive structure 214 . The second conductive structure 216 may include a second conductive pillar portion 216b and a second pad portion 216a located at both ends of the second conductive pillar portion 216b. The second pad portion 216a is disposed on the first side 201a and the second side 201b and surrounds the first pad portion 214a. The opening OP2 separates the first pad portion 214a from the second pad portion 216a, that is, The second pad portion 216a is not connected to the first pad portion 214a. The second conductive pillar portion 216b is connected to the second pad portions 216a at both ends thereof and surrounds the first conductive pillar portion 214b. The first insulating structure 212 is disposed between the first conductive structure 214 and the second conductive structure 216 to electrically separate the first conductive structure 214 and the second conductive structure 216 . In this embodiment, the second pad portion 216a may be formed by a portion of the first conductive layer 203, and the second conductive pillar portion 216b may be formed by a portion of the core substrate 201.

在一些實施例中，核心基板201與第一導電層203可構成中介層基板205。換句話說，部分中介層基板205可構成同軸導電件210的第一導電結構214及第二導電結構216。 In some embodiments, the core substrate 201 and the first conductive layer 203 may constitute the interposer substrate 205 . In other words, part of the interposer substrate 205 may form the first conductive structure 214 and the second conductive structure 216 of the coaxial conductive member 210 .

經過上述製程後可大致上完成包含同軸導電件210的中介層200的製作。 After the above process, the production of the interposer 200 including the coaxial conductive member 210 can be substantially completed.

圖6A至圖6F是依照本發明的另一實施例的一種包含同軸導電件的中介層基板的製造流程的剖視示意圖。在此必須說明的是，圖6A至圖6F的實施例沿用圖5A至圖5F的實施例的元件 標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 6A to 6F are schematic cross-sectional views of a manufacturing process of an interposer substrate including coaxial conductive elements according to another embodiment of the present invention. It must be noted here that the embodiment of FIGS. 6A to 6F uses the elements of the embodiment of FIGS. 5A to 5F Labels and part of the content, the same or similar labels are used to represent the same or similar components, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

請參照圖6A，提供核心基板201’，核心基板201’具有第一側201a’與相對於第一側201a’的第二側201b’。核心基板201’例如可為銅板、鋁板、合金板或其他合適的導電材料。核心基板201’的厚度可以在150μm至250μm之間。 Referring to Figure 6A, a core substrate 201' is provided. The core substrate 201' has a first side 201a' and a second side 201b' opposite to the first side 201a'. The core substrate 201' may be, for example, a copper plate, an aluminum plate, an alloy plate or other suitable conductive materials. The thickness of the core substrate 201' may be between 150 μm and 250 μm.

請參照圖6B，形成環形凹槽T於核心基板201’的第一側201a’上，其中環形凹槽T不貫穿核心基板201’的第二側201b’。舉例來說，可以透過蝕刻的方式，於核心基板201’的第一側201a’上蝕刻出環形凹槽T，如圖6B的區域A1所示，區域A1為環形凹槽T的上視示意圖。核心基板201’被環形凹槽T環繞的部分P基本上與環形凹槽T具有相同軸心。 Referring to Figure 6B, an annular groove T is formed on the first side 201a' of the core substrate 201', wherein the annular groove T does not penetrate the second side 201b' of the core substrate 201'. For example, an annular groove T can be etched on the first side 201a' of the core substrate 201' through etching, as shown in the area A1 of FIG. 6B. The area A1 is a top view of the annular groove T. The portion P of the core substrate 201' surrounded by the annular groove T has substantially the same axis as the annular groove T.

在一些實施例中，環形凹槽T的底面至第二側201b’的距離d5可以在50μm至100μm之間，但本發明不以此為限。在一些實施例中，環形凹槽T的外徑d6可以在250μm至450μm之間，但本發明不以此為限。在一些實施例中，環形凹槽T的寬度d7可以在100μm至175μm之間，但本發明不以此為限。 In some embodiments, the distance d5 from the bottom surface of the annular groove T to the second side 201b' may be between 50 μm and 100 μm, but the present invention is not limited thereto. In some embodiments, the outer diameter d6 of the annular groove T may be between 250 μm and 450 μm, but the present invention is not limited thereto. In some embodiments, the width d7 of the annular groove T may be between 100 μm and 175 μm, but the present invention is not limited thereto.

請參照圖6C，填充絕緣材料於環形凹槽T中，以形成第一絕緣結構212。 Referring to FIG. 6C , insulating material is filled in the annular groove T to form the first insulating structure 212 .

請參照圖6D，自核心基板201’的第二側201b’移除部分核心基板201’直到第一絕緣結構212被暴露出。舉例來說，可透 過蝕刻、機械研磨等方式移除部分核心基板201’，而使核心基板201’的第二側201b’與第一絕緣結構212的底面齊平。 Referring to Figure 6D, a portion of the core substrate 201' is removed from the second side 201b' of the core substrate 201' until the first insulation structure 212 is exposed. For example, it can be Part of the core substrate 201' is removed by over-etching, mechanical grinding, etc., so that the second side 201b' of the core substrate 201' is flush with the bottom surface of the first insulation structure 212.

請參照圖6E，形成第一導電材料層202’於核心基板201’的第一側201a’及第二側201b’上。舉例來說，可透過電鍍或沉積製程，將導電材料(例如銅、鋁或其他合適的導電材料或上述材料的合金)形成於核心基板201’的第一側201a’及第二側201b’上，並覆蓋第一絕緣結構212，以形成第一導電材料層202’。在一些實施例中，第一導電材料層202’與核心基板201’的材質為相同，因此第一導電材料層202’與核心基板201’之間可能不存在界面，但為了使製造流程清楚，圖6E、6F中以虛線將第一導電材料層202’與核心基板201’區分。 Referring to FIG. 6E, a first conductive material layer 202' is formed on the first side 201a' and the second side 201b' of the core substrate 201'. For example, a conductive material (such as copper, aluminum or other suitable conductive materials or alloys of the above materials) can be formed on the first side 201a' and the second side 201b' of the core substrate 201' through an electroplating or deposition process. , and cover the first insulating structure 212 to form the first conductive material layer 202'. In some embodiments, the first conductive material layer 202' and the core substrate 201' are made of the same material, so there may be no interface between the first conductive material layer 202' and the core substrate 201'. However, in order to make the manufacturing process clear, In FIGS. 6E and 6F , the first conductive material layer 202 ′ is distinguished from the core substrate 201 ′ by a dotted line.

請參照圖6F，圖案化第一導電材料層202’，以暴露出部分第一絕緣結構212。舉例來說，可透過蝕刻的方式，圖案化第一導電材料層202’，以移除部分覆蓋第一絕緣結構212的第一導電材料層202’，而形成開口OP3於第一導電層203’中。也就是說，開口OP3可暴露出第一絕緣結構212，而第一導電層203’覆蓋於核心基板201’的第一側201a’與第二側201b’上。第一絕緣結構212、部分第一導電層203’及部分核心基板201’可構成同軸導電件210。詳細而言，同軸導電件210可包括第一導電結構214、第二導電結構216以及第一絕緣結構212。第一導電結構214可包括第一導電柱部分214b及位於第一導電柱部分214b兩端的第一接墊部分214a。第一接墊部分214a設置於第一側201a’與第二側201b’上並 與被環形凹槽T(標示於圖6B)環繞的部分P(標示於圖6B)重疊，第一導電柱部分214b由被環形凹槽T(標示於圖6B)環繞的部分P構成，以電性連接其兩端的第一接墊部分214a。也就是說，部分第一導電層203’可構成第一接墊部分214a，核心基板201’可構成第一導電柱部分214b。 Referring to FIG. 6F, the first conductive material layer 202' is patterned to expose a portion of the first insulating structure 212. For example, the first conductive material layer 202' can be patterned by etching to remove part of the first conductive material layer 202' covering the first insulating structure 212, thereby forming the opening OP3 in the first conductive layer 203'. middle. That is to say, the opening OP3 can expose the first insulation structure 212, and the first conductive layer 203' covers the first side 201a' and the second side 201b' of the core substrate 201'. The first insulating structure 212, part of the first conductive layer 203' and part of the core substrate 201' may form the coaxial conductive member 210. In detail, the coaxial conductive member 210 may include a first conductive structure 214 , a second conductive structure 216 and a first insulating structure 212 . The first conductive structure 214 may include a first conductive pillar portion 214b and first pad portions 214a located at both ends of the first conductive pillar portion 214b. The first pad portion 214a is disposed on the first side 201a' and the second side 201b'. Overlapping the portion P (marked in FIG. 6B ) surrounded by the annular groove T (marked in FIG. 6B ), the first conductive pillar portion 214 b is composed of the portion P surrounded by the annular groove T (marked in FIG. 6B ) to electrically The first pad portion 214a is electrically connected to both ends thereof. That is to say, part of the first conductive layer 203' may constitute the first pad part 214a, and the core substrate 201' may constitute the first conductive pillar part 214b.

第二導電結構216環繞第一導電結構214。第二導電結構216可包括第二導電柱部分216b及位於第二導電柱部分216b兩端的第二接墊部分216a。第二接墊部分216a設置於第一側201a’與第二側201b’上並環繞第一接墊部分214a，開口OP3將第一接墊部分214a與將第二接墊部分216a分離，也就是說，第二接墊部分216a不與第一接墊部分214a連接。第二導電柱部分216b連接其兩端的第二接墊部分216a，且環繞第一導電柱部分214b。第一絕緣結構212設置於第一導電結構214與第二導電結構216之間，以使第一導電結構214與第二導電結構216電性分離。在本實施例中，第二接墊部分216a可由部分第一導電層203’構成，第二導電柱部分216b可由部分核心基板201’構成。 The second conductive structure 216 surrounds the first conductive structure 214 . The second conductive structure 216 may include a second conductive pillar portion 216b and a second pad portion 216a located at both ends of the second conductive pillar portion 216b. The second pad portion 216a is disposed on the first side 201a' and the second side 201b' and surrounds the first pad portion 214a. The opening OP3 separates the first pad portion 214a from the second pad portion 216a, that is, That is, the second pad portion 216a is not connected to the first pad portion 214a. The second conductive pillar portion 216b is connected to the second pad portions 216a at both ends thereof and surrounds the first conductive pillar portion 214b. The first insulating structure 212 is disposed between the first conductive structure 214 and the second conductive structure 216 to electrically separate the first conductive structure 214 and the second conductive structure 216 . In this embodiment, the second pad portion 216a may be formed by a portion of the first conductive layer 203', and the second conductive pillar portion 216b may be formed by a portion of the core substrate 201'.

在一些實施例中，核心基板201’與第一導電層203’可構成中介層基板205。換句話說，部分中介層基板205可構成同軸導電件210的第一導電結構214及第二導電結構216。 In some embodiments, the core substrate 201' and the first conductive layer 203' may constitute the interposer substrate 205. In other words, part of the interposer substrate 205 may form the first conductive structure 214 and the second conductive structure 216 of the coaxial conductive member 210 .

經過上述製程後可大致上完成包含同軸導電件210的中介層200的製作。 After the above process, the production of the interposer 200 including the coaxial conductive member 210 can be substantially completed.

圖7A至圖7D是依照本發明的一實施例的一種第一導電 連接件的製造流程的剖視示意圖。圖8A至圖8B是圖7B的區域R1的一種局部上視示意圖。在此必須說明的是，圖7A至圖7D的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 7A to 7D are a first conductive circuit according to an embodiment of the present invention. Schematic cross-section of the connector manufacturing process. 8A to 8B are a partial top view of the region R1 of FIG. 7B. It must be noted here that the embodiments of FIGS. 7A to 7D follow the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

請參照圖7A，形成第一黏著材料層220’於中介層200的一側上。舉例來說，中介層200可以是由圖5A至圖5F製作的包含同軸導電件210的中介層200或是由圖6A至圖6F製作的包含同軸導電件210的中介層200，相關內容請參考前述，在此不贅述。第一黏著材料層220’可透過層壓(laminate)的方式形成於中介層200的中介層基板205的上表面205a上，以使第一黏著材料層220’覆蓋位於中介層基板205的上表面205a上的第一接墊部分214a、第二接墊部分216a。第一黏著材料層220’可以為半固化狀態，舉例來說，第一黏著材料層220’可包括半固化狀態的樹脂，例如b階段(B-stage)環氧樹脂膠/膠帶、含b階段(B-stage)環氧樹脂的玻璃纖維層(prepreg，PP)或其他合適材料。在一些實施例中，第一黏著材料層220’未與中介層基板205接觸的一側可包括離型膜222，也就是說，第一黏著材料層220’位於中介層基板205與離型膜222之間，但本發明不以此為限。 Referring to FIG. 7A, a first adhesive material layer 220' is formed on one side of the interposer 200. For example, the interposer 200 may be the interposer 200 including the coaxial conductive member 210 made from FIGS. 5A to 5F or the interposer 200 including the coaxial conductive member 210 made from FIGS. 6A to 6F. For related information, please refer to The aforementioned will not be repeated here. The first adhesive material layer 220' may be formed on the upper surface 205a of the interposer substrate 205 of the interposer 200 through lamination, so that the first adhesive material layer 220' covers the upper surface of the interposer substrate 205. The first pad portion 214a and the second pad portion 216a on 205a. The first adhesive material layer 220' may be in a semi-cured state. For example, the first adhesive material layer 220' may include a resin in a semi-cured state, such as b-stage epoxy resin glue/tape, b-stage epoxy resin glue/tape, (B-stage) Glass fiber layer of epoxy resin (prepreg, PP) or other suitable materials. In some embodiments, the side of the first adhesive material layer 220' that is not in contact with the interposer substrate 205 may include a release film 222. That is to say, the first adhesive material layer 220' is located between the interposer substrate 205 and the release film. 222, but the present invention is not limited to this.

請參照圖7B，形成多個通孔V1於第一黏著材料層220’中，以暴露出部分同軸導電件210。舉例來說，可透過雷射鑽孔的方式形成多個通孔V1於第一黏著材料層220’及離型膜222(若有) 中。多個通孔V1可以暴露出同軸導電件210的部分第一接墊部分214a與部分第二接墊部分216a。 Referring to FIG. 7B, a plurality of through holes V1 are formed in the first adhesive material layer 220' to expose part of the coaxial conductive member 210. For example, a plurality of through holes V1 can be formed in the first adhesive material layer 220' and the release film 222 (if any) through laser drilling. middle. The plurality of through holes V1 may expose part of the first pad part 214a and part of the second pad part 216a of the coaxial conductive member 210.

在一些實施例中，以俯視觀之，如圖8A所示，多個通孔V1可包括通孔V1a以及環繞通孔V1a的多個通孔V1b。通孔V1a對應於第一接墊部分214a以暴露出部分第一接墊部分214a，多個通孔V1b對應於第二接墊部分216a以暴露出部分第二接墊部分216a。本實施例中僅示意性的繪示6個環繞通孔V1a的通孔V1b，但並非用以限定本發明，通孔V1b的數量可依據實際需求調整。舉例來說，相鄰的通孔V1b之間的最短距離可以設計為小於或等於所欲傳輸的無線電波波長的1/10。 In some embodiments, viewed from above, as shown in FIG. 8A , the plurality of through holes V1 may include a plurality of through holes V1a and a plurality of through holes V1b surrounding the through holes V1a. The through hole V1a corresponds to the first pad portion 214a to expose a portion of the first pad portion 214a, and the plurality of through holes V1b corresponds to the second pad portion 216a to expose a portion of the second pad portion 216a. This embodiment only schematically illustrates six through holes V1b surrounding the through hole V1a, but this is not intended to limit the present invention. The number of through holes V1b can be adjusted according to actual needs. For example, the shortest distance between adjacent through holes V1b can be designed to be less than or equal to 1/10 of the wavelength of the radio wave to be transmitted.

在其他實施例中，以俯視觀之，如圖8B所示，多個通孔V1可包括通孔V1a’以及環繞通孔V1a’的單一通孔V1b’。通孔V1b’的形狀可對應於第二接墊部分216a設置為環形，以暴露出部分第二接墊部分216a。 In other embodiments, from a top view, as shown in FIG. 8B , the plurality of through holes V1 may include a through hole V1a' and a single through hole V1b' surrounding the through hole V1a'. The shape of the through hole V1b' may be configured as an annular shape corresponding to the second pad portion 216a, so as to expose a portion of the second pad portion 216a.

請參照圖7C及7D，形成第一導電連接材料240’於多個通孔V1中，之後移除離型膜222(若有)。第一導電連接材料240’例如可以是銀膠、銅膠、暫態液相燒結(Transient Liquid Phase Sintering；TLPS)導電膠或其他合適材料。 Referring to Figures 7C and 7D, first conductive connection materials 240' are formed in the plurality of through holes V1, and then the release film 222 (if any) is removed. The first conductive connection material 240' may be, for example, silver glue, copper glue, transient liquid phase sintering (Transient Liquid Phase Sintering; TLPS) conductive glue, or other suitable materials.

經過上述製程後可大致上完成包含同軸導電件210及第一導電連接材料240’的中介層200的結構200’的製作。 After the above process, the structure 200' of the interposer 200 including the coaxial conductive member 210 and the first conductive connection material 240' can be substantially completed.

圖9A至圖9C是依照本發明的一實施例的一種線路結構的示意圖。在此必須說明的是，圖9A至圖9C的實施例沿用圖1 的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 9A to 9C are schematic diagrams of a circuit structure according to an embodiment of the present invention. It must be noted here that the embodiment of FIGS. 9A to 9C follows the same method as that of FIG. 1 Component numbers and part of the content of the embodiments, the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

請參照圖9A至圖9C，線路結構300包括第一核心層301、第一天線層312、第二天線層314以及多個接墊316。第一核心層301具有第一表面301a及與第一表面301a相對的第二表面301b。第一天線層312設置在第一表面301a上。第二天線層314與多個接墊316設置在第二表面301b上，也就是說，第二天線層314與多個接墊316為相同膜層。多個接墊316可與同軸導電件210對應，以便於後續與同軸導電件210的連接。舉例來說，多個接墊316可包括第一接墊316a及第二接墊316b。第一接墊316a對應於同軸導電件210的第一接墊部分214a，第二接墊316b對應於同軸導電件210的第二接墊部分216a。 Referring to FIGS. 9A to 9C , the circuit structure 300 includes a first core layer 301 , a first antenna layer 312 , a second antenna layer 314 and a plurality of pads 316 . The first core layer 301 has a first surface 301a and a second surface 301b opposite to the first surface 301a. The first antenna layer 312 is provided on the first surface 301a. The second antenna layer 314 and the plurality of contact pads 316 are disposed on the second surface 301b. That is to say, the second antenna layer 314 and the plurality of contact pads 316 are the same film layer. The plurality of pads 316 may correspond to the coaxial conductive member 210 to facilitate subsequent connection with the coaxial conductive member 210 . For example, the plurality of pads 316 may include a first pad 316a and a second pad 316b. The first pad 316a corresponds to the first pad portion 214a of the coaxial conductive member 210, and the second pad 316b corresponds to the second pad portion 216a of the coaxial conductive member 210.

在一些實施例中，如圖9B所示，第二接墊316b可為多個第二接墊316b’。多個第二接墊316b’對應於同軸導電件210的第二導電結構216，其中多個第二接墊316b’環繞第一接墊316a。在其他實施例中，如圖9C所示，第二接墊316b可為單一第二接墊316b。第二接墊316b為環形且環繞第一接墊316a，並可對應於同軸導電件210的第二導電結構216。 In some embodiments, as shown in FIG. 9B , the second pad 316b may be a plurality of second pads 316b'. The plurality of second pads 316b' correspond to the second conductive structure 216 of the coaxial conductive member 210, wherein the plurality of second pads 316b' surround the first pad 316a. In other embodiments, as shown in FIG. 9C , the second pad 316b may be a single second pad 316b. The second pad 316b is annular and surrounds the first pad 316a, and may correspond to the second conductive structure 216 of the coaxial conductive member 210.

在一些實施例中，線路結構300還包括導電層311、313以及絕緣層302、303。導電層311、313分別設置於第一核心層301的第一表面301a、第二表面301b上。絕緣層302設置於導電 層311與第一天線層312之間，並具有導通孔CV1設置於絕緣層302中以使導電層311與第一天線層312電性連接。絕緣層303設置於導電層313與第二天線層314之間，並具有導通孔CV2設置於絕緣層303中以使導電層313與第二天線層314或接墊316電性連接。 In some embodiments, the circuit structure 300 further includes conductive layers 311 and 313 and insulating layers 302 and 303. The conductive layers 311 and 313 are respectively provided on the first surface 301a and the second surface 301b of the first core layer 301. The insulating layer 302 is disposed on the conductive A conductive hole CV1 is provided in the insulating layer 302 between the layer 311 and the first antenna layer 312 to electrically connect the conductive layer 311 and the first antenna layer 312 . The insulating layer 303 is disposed between the conductive layer 313 and the second antenna layer 314, and has a via hole CV2 disposed in the insulating layer 303 to electrically connect the conductive layer 313 to the second antenna layer 314 or the pad 316.

在一些實施例中，線路結構300還包括貫穿第一核心層301的導電柱305，以電性連接導電層311與導電層313。導電柱305例如可以是實心金屬柱或是空心金屬柱並有絕緣材料填充於空心金屬柱中，本發明不以此為限。在其他實施例中，線路結構300可不包括貫穿第一核心層301的導電柱。 In some embodiments, the circuit structure 300 further includes conductive pillars 305 penetrating the first core layer 301 to electrically connect the conductive layer 311 and the conductive layer 313 . The conductive pillar 305 may be, for example, a solid metal pillar or a hollow metal pillar with insulating material filled in the hollow metal pillar. The present invention is not limited thereto. In other embodiments, the circuit structure 300 may not include conductive pillars penetrating the first core layer 301 .

應理解，圖9A僅示意性的繪示線路結構300的絕緣層、導電層及天線層，但並非用以限定本發明，絕緣層、導電層及天線層的數量及佈線設計可依實際需求調整。 It should be understood that FIG. 9A only schematically illustrates the insulating layer, conductive layer and antenna layer of the circuit structure 300, but is not used to limit the present invention. The number and wiring design of the insulating layer, conductive layer and antenna layer can be adjusted according to actual needs. .

圖10A至圖10E是依照本發明的一實施例的一種電子封裝結構的製造流程的剖視示意圖。 10A to 10E are schematic cross-sectional views of a manufacturing process of an electronic packaging structure according to an embodiment of the present invention.

請參照圖10A，提供線路結構300。線路結構300例如為前述圖9A所示的線路結構300，相關描述請參考上述內容，在此不贅述。形成阻焊層320於絕緣層302、303的表面上，以覆蓋第一天線層312與第二天線層314。阻焊層320具有多個通孔V2，以暴露出部分接墊316。阻焊層320的材料可以為防焊材料(例如綠漆)、感光型介電材料或其他合適材料。 Referring to Figure 10A, a circuit structure 300 is provided. The circuit structure 300 is, for example, the circuit structure 300 shown in FIG. 9A . For related descriptions, please refer to the above content and will not be described again here. A solder resist layer 320 is formed on the surfaces of the insulating layers 302 and 303 to cover the first antenna layer 312 and the second antenna layer 314. The solder resist layer 320 has a plurality of through holes V2 to expose part of the pads 316 . The material of the solder resist layer 320 may be a solder resist material (eg, green paint), a photosensitive dielectric material, or other suitable materials.

請參照圖10A及圖10B，將線路結構300的多個接墊316 與設置於中介層200的第一導電連接材料240’對應連接。舉例來說，可先將第一導電連接材料240’設置於中介層200上，如前述圖7D所示的結構200’，相關描述請參考上述內容，在此不贅述。然後，將設置於同軸導電件210的第一接墊部分214a上的第一導電連接材料240’對應連接線路結構300的第一接墊316a，將設置於同軸導電件210的第二接墊部分216a上的第一導電連接材料240’對應連接線路結構300的第二接墊316b。 Referring to FIG. 10A and FIG. 10B , the plurality of pads 316 of the circuit structure 300 are Correspondingly connected to the first conductive connection material 240' provided on the interposer 200. For example, the first conductive connection material 240' can be disposed on the interposer 200 first, such as the structure 200' shown in FIG. 7D. For related descriptions, please refer to the above content and will not be repeated here. Then, the first conductive connecting material 240' disposed on the first pad portion 214a of the coaxial conductive member 210 corresponds to the first pad 316a of the connection circuit structure 300, and the first conductive connecting material 240' is disposed on the second pad portion of the coaxial conductive member 210. The first conductive connection material 240' on 216a corresponds to the second pad 316b of the connection circuit structure 300.

然後，於第一溫度下，壓合線路結構300與中介層200，以固化第一黏著材料層220’至C階段(C-stage)，而形成第一黏著層220。第一溫度例如在180℃至220℃之間。 Then, the circuit structure 300 and the interposer layer 200 are pressed together at a first temperature to cure the first adhesive material layer 220' to the C-stage to form the first adhesive layer 220. The first temperature is, for example, between 180°C and 220°C.

在一些實施例中，第一導電連接材料240’可於第一溫度下加熱熔融後，再固化形成第一導電連接件240，以使線路結構300的多個接墊316與對應的同軸導電件210可良好的接合且電性連接。在一些實施例中，若第一導電連接材料240’為暫態液相燒結導電膠，由於其包括金屬焊料粒子(例如銅、錫鉍合金等)，透過加熱可於界面產生液相的金屬粒子的組合，進而固化形成金屬間化合物(intermetallic compound，IMC)，以提升界面的接合力，並具有良好的導電性。 In some embodiments, the first conductive connection material 240' can be heated and melted at a first temperature, and then solidified to form the first conductive connection member 240, so that the plurality of pads 316 of the circuit structure 300 are connected to the corresponding coaxial conductive members. 210 can be well bonded and electrically connected. In some embodiments, if the first conductive connection material 240' is a transient liquid-phase sintered conductive adhesive, since it includes metal solder particles (such as copper, tin-bismuth alloy, etc.), liquid metal particles can be generated at the interface through heating. The combination is then solidified to form an intermetallic compound (IMC) to enhance the bonding strength of the interface and have good electrical conductivity.

請參照圖10C，形成空腔230於中介層基板205的下表面205b，以形成中介層200。舉例來說，可先形成圖案化光阻層PR於中介層基板205的下表面205b上。圖案化光阻層PR覆蓋同軸導電件210，並暴露出部分中介層基板205的下表面205b。然 後，以圖案化光阻層PR為罩幕，蝕刻中介層基板205，以形成空腔230。在本實施例中，空腔230不蝕穿中介層基板205，因此空腔230由中介層基板205的側壁230a、230b及底面230c構成，但本發明不以此為限。在其他實施例中，空腔230可蝕穿中介層基板205，而暴露出第一黏著層220。 Referring to FIG. 10C , a cavity 230 is formed on the lower surface 205b of the interposer substrate 205 to form the interposer 200 . For example, a patterned photoresist layer PR may be formed on the lower surface 205b of the interposer substrate 205 first. The patterned photoresist layer PR covers the coaxial conductive member 210 and exposes part of the lower surface 205b of the interposer substrate 205. Ran Finally, using the patterned photoresist layer PR as a mask, the interposer substrate 205 is etched to form a cavity 230 . In this embodiment, the cavity 230 does not etch through the interposer substrate 205, so the cavity 230 is composed of the sidewalls 230a, 230b and the bottom surface 230c of the interposer substrate 205, but the invention is not limited thereto. In other embodiments, the cavity 230 can be etched through the interposer substrate 205 to expose the first adhesive layer 220 .

請參照圖10D，移除圖案化光阻層PR。形成阻焊層260於中介層基板205的下表面205b上。阻焊層260包括多個通孔V3，以暴露出部分同軸導電件210，例如暴露出同軸導電件210位於下表面205b上的部分第一接墊部分214a及部分第二接墊部分216a。阻焊層260的材料可以為防焊材料(例如綠漆)、感光型介電材料或其他合適材料。 Referring to Figure 10D, the patterned photoresist layer PR is removed. A solder resist layer 260 is formed on the lower surface 205b of the interposer substrate 205. The solder resist layer 260 includes a plurality of through holes V3 to expose part of the coaxial conductive component 210, such as part of the first pad part 214a and part of the second pad part 216a of the coaxial conductive component 210 located on the lower surface 205b. The material of the solder resist layer 260 may be a solder resist material (eg, green paint), a photosensitive dielectric material, or other suitable materials.

請參照圖10E，形成第二導電連接材料270’於多個通孔V3(標示於圖10D)中。第二導電連接材料270’例如可以為錫膏、焊球或其他合適材料。 Referring to FIG. 10E, a second conductive connection material 270' is formed in a plurality of through holes V3 (marked in FIG. 10D). The second conductive connection material 270' may be, for example, solder paste, solder balls, or other suitable materials.

之後，請參照圖1，於第二溫度下，接合電路基板100於中介層基板205的下表面205b上，並使晶片130設置於空腔230中。舉例來說，可先將晶片130設置於電路基板100上，如前述圖4C所示的結構100’，相關描述請參考上述內容，在此不贅述。然後，將晶片130與中介層基板205的空腔230對應，並將第二導電連接材料270’與電路基板100的接墊114對應連接，如此一來，可透過第二導電連接材料270’接合中介層200與結構100’並使其電性連接。在一些實施例中，第二導電連接材料270’可於第 二溫度下進行回焊製程，以形成第二導電連接件270，以提升中介層200與100電路基板的接合強度。在一些實施例中，第二溫度在250℃至270℃之間。 1, at the second temperature, the circuit substrate 100 is bonded to the lower surface 205b of the interposer substrate 205, and the chip 130 is placed in the cavity 230. For example, the chip 130 can be placed on the circuit substrate 100 first, such as the structure 100' shown in FIG. 4C. Please refer to the above content for related description, which will not be described again here. Then, the chip 130 is corresponding to the cavity 230 of the interposer substrate 205, and the second conductive connection material 270' is correspondingly connected to the pad 114 of the circuit substrate 100. In this way, the second conductive connection material 270' can be connected. The interposer 200 is electrically connected to the structure 100'. In some embodiments, the second conductive connection material 270' can be A reflow process is performed at two temperatures to form the second conductive connector 270 to enhance the bonding strength between the interposer 200 and the circuit substrate 100 . In some embodiments, the second temperature is between 250°C and 270°C.

經過上述製程後可大致上完成電子封裝結構10的製作。 After the above process, the production of the electronic packaging structure 10 can be substantially completed.

綜上所述，本發明的電子封裝結構可整合電路基板、中介層以及線路結構於一封裝結構中，且晶片設置於中介層的空腔中，使空間得以有效的被利用，進而有利於電子封裝結構的微型化，並且由於中介層由導電材料構成，有助於提升晶片的散熱能力。此外，由於中介層包括用以電性連接線路結構及電路基板的同軸導電件，可降低線路結構所接收或發出的射頻訊號在傳輸過程中的訊號損耗，並可屏蔽電磁干擾訊號，以提升訊號的完整性。 In summary, the electronic packaging structure of the present invention can integrate the circuit substrate, the interposer and the circuit structure into a package structure, and the chip is disposed in the cavity of the interposer, so that the space can be effectively utilized, which is beneficial to the electronics. The miniaturization of the packaging structure, and because the interposer is made of conductive materials, helps to improve the heat dissipation capacity of the chip. In addition, because the interposer layer includes coaxial conductive elements that are used to electrically connect the circuit structure and the circuit substrate, it can reduce the signal loss during the transmission process of the radio frequency signals received or emitted by the circuit structure, and can shield electromagnetic interference signals to improve the signal of integrity.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10:電子封裝結構 10: Electronic packaging structure

100:電路基板 100:Circuit substrate

112,114:接墊 112,114: Pad

130:晶片 130:Chip

130a:主動面 130a: Active side

130b:背面 130b: Back

150:熱界面材料 150: Thermal interface materials

200:中介層 200: Intermediary layer

205:中介層基板 205:Interposer substrate

205a:上表面 205a: Upper surface

205b:下表面 205b: Lower surface

210:同軸導電件 210: Coaxial conductive parts

212:第一絕緣結構 212: First insulation structure

214:第一導電結構 214: First conductive structure

216:第二導電結構 216: Second conductive structure

220:第一黏著層 220: First adhesive layer

230:空腔 230:Cavity

230a,230b:側壁 230a, 230b: side wall

230c:底面 230c: Bottom surface

240:第一導電連接件 240: First conductive connector

270:第二導電連接件 270: Second conductive connector

300:線路結構 300: Line structure

301:第一核心層 301: First core layer

301a:第一表面 301a: First surface

301b:第二表面 301b: Second surface

312:第一天線層 312: First antenna layer

314:第二天線層 314: Second antenna layer

316:接墊 316: Pad

316a:第一接墊 316a: first pad

316b:第二接墊 316b: Second pad

Claims (20)

一種電子封裝結構，包括： 中介層，包括： 中介層基板，具有上表面及相對於所述上表面的下表面，其中所述中介層基板包括空腔；以及 同軸導電件，位於所述中介層基板中，所述同軸導電件包括： 第一導電結構； 第二導電結構，環繞所述第一導電結構；以及 第一絕緣結構，設置於所述第一導電結構與所述第二導電結構之間； 電路基板，設置於所述中介層基板的所述下表面上，並與所述同軸導電件電性連接； 晶片，設置於所述空腔中且位於所述電路基板上，以與所述電路基板電性連接；以及 線路結構，設置於所述中介層基板的所述上表面上，並與所述同軸導電件電性連接。 An electronic packaging structure including: Intermediary layer, including: an interposer substrate having an upper surface and a lower surface opposite the upper surface, wherein the interposer substrate includes a cavity; and Coaxial conductive parts are located in the interposer substrate, and the coaxial conductive parts include: first conductive structure; a second conductive structure surrounding the first conductive structure; and A first insulating structure is provided between the first conductive structure and the second conductive structure; A circuit substrate is disposed on the lower surface of the interposer substrate and is electrically connected to the coaxial conductive member; A chip is disposed in the cavity and located on the circuit substrate to be electrically connected to the circuit substrate; and A circuit structure is disposed on the upper surface of the interposer substrate and is electrically connected to the coaxial conductive member. 如請求項1所述的電子封裝結構，其中所述中介層基板的材質包括導電材料。The electronic packaging structure of claim 1, wherein the interposer substrate is made of conductive material. 如請求項1所述的電子封裝結構，更包括： 熱界面材料，設置於所述晶片的背面並與所述中介層基板接觸。 The electronic packaging structure as described in claim 1 further includes: Thermal interface material is disposed on the back side of the wafer and in contact with the interposer substrate. 如請求項1所述的電子封裝結構，其中所述線路結構包括： 第一核心層，具有第一表面及與所述第一表面相對的第二表面，其中所述第二表面面向所述中介層； 第一天線層，設置在所述第一表面上； 第二天線層，設置在所述第二表面上；以及 多個接墊，設置在所述第二表面上且對應於所述同軸導電件。 The electronic packaging structure as claimed in claim 1, wherein the circuit structure includes: A first core layer having a first surface and a second surface opposite to the first surface, wherein the second surface faces the interposer; A first antenna layer disposed on the first surface; a second antenna layer disposed on the second surface; and A plurality of contact pads are provided on the second surface and correspond to the coaxial conductive member. 如請求項4所述的電子封裝結構，其中所述多個接墊包括： 第一接墊，對應於所述同軸導電件的所述第一導電結構；以及 第二接墊，對應於所述同軸導電件的所述第二導電結構，其中所述第二接墊為環形。 The electronic packaging structure of claim 4, wherein the plurality of pads include: A first pad corresponding to the first conductive structure of the coaxial conductive member; and The second contact pad corresponds to the second conductive structure of the coaxial conductive member, wherein the second contact pad is annular. 如請求項4所述的電子封裝結構，其中所述多個接墊包括： 第一接墊，對應於所述同軸導電件的所述第一導電結構；以及 多個第二接墊，對應於所述同軸導電件的所述第二導電結構，其中所述多個第二接墊環繞所述第一接墊。 The electronic packaging structure of claim 4, wherein the plurality of pads include: A first pad corresponding to the first conductive structure of the coaxial conductive member; and A plurality of second contact pads corresponds to the second conductive structure of the coaxial conductive member, wherein the plurality of second contact pads surround the first contact pad. 如請求項4所述的電子封裝結構，更包括： 第一導電連接件，設置於所述線路結構的所述多個接墊與所述同軸導電件之間。 The electronic packaging structure as described in claim 4 further includes: The first conductive connection member is disposed between the plurality of pads of the circuit structure and the coaxial conductive member. 如請求項1所述的電子封裝結構，更包括： 第一黏著層，設置於所述中介層與所述線路結構之間。 The electronic packaging structure as described in claim 1 further includes: A first adhesive layer is disposed between the interposer layer and the circuit structure. 如請求項1所述的電子封裝結構，其中所述電路基板包括對應於所述同軸導電件的多個接墊，所述電子封裝結構更包括： 第二導電連接件，設置於所述電路基板與所述同軸導電件之間。 The electronic packaging structure of claim 1, wherein the circuit substrate includes a plurality of pads corresponding to the coaxial conductive members, and the electronic packaging structure further includes: The second conductive connecting member is disposed between the circuit substrate and the coaxial conductive member. 如請求項1所述的電子封裝結構，其中所述同軸導電件的所述第一導電結構適於傳輸訊號，所述第二導電結構適於接地或與電源連接。The electronic packaging structure of claim 1, wherein the first conductive structure of the coaxial conductive member is suitable for transmitting signals, and the second conductive structure is suitable for grounding or connecting to a power source. 一種電子封裝結構的製造方法，包括： 提供電路基板； 設置晶片於所述電路基板上； 提供中介層，所述中介層包括： 中介層基板，具有上表面及相對於所述上表面的下表面；以及 同軸導電件位於所述中介層基板中，其中所述同軸導電件包括： 第一導電結構； 第二導電結構，環繞所述第一導電結構；以及 第一絕緣結構，設置於所述第一導電結構與所述第二導電結構之間； 提供線路結構，於第一溫度下，將線路結構壓合於所述中介層基板的所述上表面上； 形成空腔於所述中介層基板的所述下表面；以及 於第二溫度下，接合所述電路基板於所述中介層基板的所述下表面上，並使所述晶片設置於所述空腔中。 A method for manufacturing an electronic packaging structure, including: Provide circuit substrate; placing a chip on the circuit substrate; An intermediary layer is provided, and the intermediary layer includes: an interposer substrate having an upper surface and a lower surface relative to the upper surface; and Coaxial conductive elements are located in the interposer substrate, wherein the coaxial conductive elements include: first conductive structure; a second conductive structure surrounding the first conductive structure; and A first insulating structure is provided between the first conductive structure and the second conductive structure; Provide a circuit structure, and press the circuit structure onto the upper surface of the interposer substrate at a first temperature; forming a cavity on the lower surface of the interposer substrate; and At the second temperature, the circuit substrate is bonded to the lower surface of the interposer substrate, and the chip is placed in the cavity. 如請求項11所述的製造方法，其中所述中介層的形成步驟包括： 提供核心基板，所述核心基板具有第一側及相對於所述第一側的第二側； 形成第一貫通孔於所述核心基板中； 填充絕緣材料於所述第一貫通孔中； 形成第二貫通孔於所述絕緣材料中，以形成所述第一絕緣結構； 形成第一導電材料層於所述核心基板的所述第一側與所述第二側上及所述第二貫通孔中；以及 圖案化所述第一導電材料層，以暴露出部分所述第一絕緣結構。 The manufacturing method according to claim 11, wherein the forming step of the interposer layer includes: providing a core substrate having a first side and a second side opposite the first side; Forming a first through hole in the core substrate; Filling the first through hole with insulating material; Forming a second through hole in the insulating material to form the first insulating structure; forming a first conductive material layer on the first side and the second side of the core substrate and in the second through hole; and The first conductive material layer is patterned to expose a portion of the first insulating structure. 如請求項12所述的製造方法，其中所述第一貫通孔的孔徑在250μm至450μm之間，所述第二貫通孔的孔徑在50μm至100μm之間。The manufacturing method according to claim 12, wherein the pore diameter of the first through hole is between 250 μm and 450 μm, and the pore diameter of the second through hole is between 50 μm and 100 μm. 如請求項11所述的製造方法，其中所述中介層的形成步驟包括： 提供核心基板，所述核心基板具有第一側及相對於所述第一側的第二側； 形成環形凹槽於所述核心基板的所述第一側上，其中所述環形凹槽不貫穿所述核心基板的所述第二側； 填充絕緣材料於所述環形凹槽中，以形成所述第一絕緣結構； 自所述核心基板的所述第二側移除部分所述核心基板直到所述第一絕緣結構被暴露出； 形成第一導電材料層於所述核心基板的所述第一側及所述第二側上；以及 圖案化所述第一導電材料層，以暴露出部分所述第一絕緣結構。 The manufacturing method according to claim 11, wherein the forming step of the interposer layer includes: providing a core substrate having a first side and a second side opposite the first side; forming an annular groove on the first side of the core substrate, wherein the annular groove does not penetrate the second side of the core substrate; Filling the annular groove with insulating material to form the first insulating structure; removing a portion of the core substrate from the second side of the core substrate until the first insulating structure is exposed; forming a first layer of conductive material on the first side and the second side of the core substrate; and The first conductive material layer is patterned to expose a portion of the first insulating structure. 如請求項11所述的製造方法，更包括： 形成第一黏著材料層於所述中介層基板的所述上表面上，其中所述第一黏著材料層為半固化狀態； 形成多個通孔於所述第一黏著材料層中，以暴露出部分所述同軸導電件； 形成第一導電連接材料於所述多個通孔中。 The manufacturing method as described in claim 11 further includes: Forming a first adhesive material layer on the upper surface of the interposer substrate, wherein the first adhesive material layer is in a semi-cured state; forming a plurality of through holes in the first adhesive material layer to expose part of the coaxial conductive member; Form first conductive connection material in the plurality of through holes. 如請求項15所述的製造方法，其中所述第一導電連接材料包括銅膠、銀膠或暫態液相燒結膠。The manufacturing method according to claim 15, wherein the first conductive connection material includes copper glue, silver glue or transient liquid phase sintering glue. 如請求項15所述的製造方法，其中將線路結構壓合於所述中介層基板的所述上表面上的步驟包括： 於所述第一溫度下，壓合所述線路結構與所述中介層基板以使所述線路結構的多個接墊與所述第一導電連接材料對應連接，並固化第一黏著材料層。 The manufacturing method according to claim 15, wherein the step of laminating the circuit structure onto the upper surface of the interposer substrate includes: At the first temperature, the circuit structure and the interposer substrate are pressed together so that the plurality of pads of the circuit structure are correspondingly connected to the first conductive connection material, and the first adhesive material layer is cured. 如請求項11所述的製造方法，其中接合所述電路基板於所述中介層基板的所述下表面上的步驟包括： 形成阻焊層於所述中介層基板的所述下表面上，其中所述阻焊層包括多個通孔，以暴露出部分所述同軸導電件； 形成第二導電連接材料於所述多個通孔中；以及 透過所述第二導電連接材料對應接合所述同軸導電件與所述電路基板的多個接墊。 The manufacturing method of claim 11, wherein the step of bonding the circuit substrate to the lower surface of the interposer substrate includes: Forming a solder resist layer on the lower surface of the interposer substrate, wherein the solder resist layer includes a plurality of through holes to expose part of the coaxial conductive member; forming a second conductive connection material in the plurality of through holes; and The coaxial conductive member and the plurality of pads of the circuit substrate are correspondingly connected through the second conductive connection material. 如請求項18所述的製造方法，其中所述第二導電連接材料包括錫膏或焊球。The manufacturing method of claim 18, wherein the second conductive connection material includes solder paste or solder balls. 如請求項11所述的製造方法，其中所述第一溫度在180℃至220℃之間，所述第二溫度在250℃至270℃之間。The manufacturing method according to claim 11, wherein the first temperature is between 180°C and 220°C, and the second temperature is between 250°C and 270°C.
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