TWI823617B - Reconfigurable capacity memory and manufacturing method thereof - Google Patents

Abstract

The present disclosure provides a reconfigurable capacity memory and manufacturing method thereof. The reconfigurable capacity memory comprises a first circuit layer, a second circuit layer, a sealing ring and a transmission layer. The sealing ring is disposed on the first circuit layer. The second circuit layer is disposed on the sealing ring in a stack structure. The transmission layer is configured in the sealing ring and protruded from the sealing ring. By way of this stack structure the first circuit layer and the second layer is connected to each other. Therefore, a plurality of first circuit layer and a plurality of second layer may be divided into a single integrated circuit according to the requirement. The purpose of saving manufacturing cost and flexibility may be achieved.

Description

Reconfigurable capacity bandwidth memory structure and manufacturing method thereof

The invention relates to an integrated circuit structure, and in particular to a reconfigurable capacity bandwidth memory structure and a manufacturing method thereof.

A wafer stack structure is currently formed through a Wafer On Wafer (WOW) process. The wafer stack structure includes a substrate, a logic circuit layer and a memory crystal layer. The substrate, the logic circuit layer and The memory crystal layer has a plurality of accommodation cavities between each other. The accommodation cavities respectively correspond to the substrate, the logic circuit layer and the memory crystal layer to form a plurality of integrated circuits, and through the accommodation A metal layer is provided in the cavity so that the substrate, the logic circuit layer and the memory crystal layer are electrically connected to each other. Through the wafer stacking process, the integrated circuits (ICs) can be manufactured at the same time. ), and then divide the integrated circuits from each other to form an integrated circuit.

In order to accurately segment the integrated circuits, a sealing ring (Sealing Ring) is provided on the logic circuit layer and the memory crystal layer respectively. Through the sealing ring, the accommodation cavities are independent and not connected to each other, so as to ensure that the cavities are separated from each other. The integrated circuits are divided into integrated circuits along the sealing ring.

However, in the existing technology, each accommodation cavity is independently disconnected through the sealing ring, resulting in the inability to transmit electrical signals between the integrated circuits. As a result, during subsequent segmentation, the setting of the sealing ring will make it impossible to perform the processing according to user needs. The integrated circuits can be divided flexibly. In addition, if user needs are different, the integrated circuit processes can be carried out independently to form different integrated circuits in response to different needs.

Therefore, it is necessary to further provide better improvement solutions in the existing technology.

In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a reconfigurable capacity bandwidth memory and a manufacturing method thereof. Through the improved structure between the memory crystal and the logic circuit, the memory crystal and the logic circuit can be connected to each other to provide subsequent Each integrated circuit can be electrically connected to save production costs and enable flexible expansion.

The main technical means adopted by the present invention to achieve the above objectives are mainly to make the aforementioned reconfigurable capacity bandwidth memory structure include: a first circuit layer; A sealing member disposed on the first circuit layer; a signal transmission layer disposed within the seal and protruding outward; A second circuit layer is provided on the top of the seal.

Through the above structure, the signal transmission layer is provided on the seal, so that each first circuit layer and each second circuit layer can be connected through the signal transmission layer. In this way, it can be manufactured through a single integrated circuit process. To produce integrated circuits that meet the needs of different users, there is no need to perform integrated circuit manufacturing processes in batches according to different user needs, and the integrated circuits can be subsequently divided according to user needs, and there will be no problem that the signals between the integrated circuits cannot be transmitted to each other. situation to achieve the purpose of saving production costs and flexibly expanding.

Another main technical means adopted by the present invention to achieve the above object is that the manufacturing method of the aforementioned reconfigurable capacity bandwidth memory structure includes: Provide a first circuit layer and a second circuit layer; Stack a plurality of separation layers to form a seal on the first circuit layer and the second circuit layer respectively, and form a signal transmission layer on at least one of the separation layers; and After the sealing member is formed, the second circuit layer is stacked on the first circuit layer through the sealing member.

Through the above-mentioned manufacturing method of the memory structure, the sealing member is disposed between the first circuit layer and the second circuit layer, and the signal transmission layer is protruded in the sealing member, so that the integrated circuits can pass through the The signal transmission layer is electrically connected. In this way, integrated circuits that meet the needs of different users can be manufactured through a single integrated circuit process. There is no need to perform integrated circuit processes in batches according to different user needs, and subsequent integrated circuit processes can be based on user needs. When the integrated circuit is divided, signals between the integrated circuits will not be unable to transmit to each other, so as to achieve the purpose of saving production costs and flexibly expanding.

Regarding the preferred embodiment of the present invention, please refer to Figure 1, in which the present invention provides a reconfigurable capacity bandwidth memory structure 10, which includes a first circuit layer 20 and a sealing ring 30 , a signal transmission layer 31 and a second circuit layer 40, the sealing member 30 is provided on the first circuit layer 20, the signal transmission layer 31 is provided in the sealing member 30 and protrudes outward, the second circuit Layer 40 is provided on top of seal 30 .

In this embodiment, the seal 30 includes a plurality of separation layers, which are vertically stacked from one side of the first circuit layer 20 and one side of the second circuit layer 40 , and each of the separation layers has The signal transmission layer 31 protrudes outward to electrically connect the adjacent first circuit layer 20 and the second circuit layer 40 .

Specifically, the second circuit layer 40 is stacked on top of the first circuit layer 20 , and the separation layers are stacked from one side of the first circuit layer 20 toward the second circuit layer 40 to form the seal 30 And stacked from one side of the second circuit layer 40 toward the first circuit layer 20 to form the seal 30 and vertically connected to the first circuit layer 20 and the second circuit layer 40 respectively. In this embodiment, the sealing member 30 can be in the shape of a closed ring.

In this embodiment, the first circuit layer 20 is a logic circuit layer 20' or a memory crystal layer 40', and the second circuit layer 40 is a logic circuit layer 20' or a memory crystal layer 40'. .

In this embodiment, as shown in Figure 2, when the first circuit layer 20 or the second circuit layer 40 is the logic circuit layer 20', the logic circuit layer 20' further includes a logic circuit 21, the The logic circuit 21 is disposed on one side of the logic circuit layer 20 ′ and within the closed ring of the seal 30 . In this embodiment, the logic circuit 21 includes a Complementary Metal-Oxide-Semiconductor (CMOS) and a Micro Electro Mechanical Systems (MEMS).

In this embodiment, when the first circuit layer 20 or the second circuit layer 40 is the memory crystal layer 40', the memory crystal layer 40' further includes a memory 41, and the memory 41 is configured On one side of the memory crystal layer 40' and within the closed annular shape of the seal 30, it is disposed opposite to the logic circuit 21.

In this embodiment, the reconfigurable capacity bandwidth memory structure 10 further includes a metal pad 50 , and the metal pad 50 is respectively disposed on the logic circuit 21 and the memory 41 .

In this embodiment, the reconfigurable capacity bandwidth memory structure 10 further includes a conductive member 51 , which is disposed between the signal transmission layer 31 and the metal pad 50 and connected with the signal transmission layer 31 And the metal pad 50 is electrically connected, so that the logic circuit 21 and the memory 41 perform signal transmission through the metal pad 50 , the conductive component 51 and the signal transmission layer 31 . In this embodiment, the conductive member 51 includes a plurality of conductive layers that are stacked.

In this embodiment, the length of the signal transmission layer 31 is greater than the length of the separation layers so as to protrude outward from the sealing member 30 .

To further illustrate the application of the present invention, for example, as shown in FIG. 3 is a bottom cross-sectional structural diagram of an integrated circuit 60. When a memory capacity of a memory 41 is 1GB, if the memory required by the user When the body capacity is 2GB, at this time, since each memory 41 can transmit signals to each other through the signal transmission layer 31, cutting can be performed on the scribe line (Scribe Line) including the two memories 41 to form the The integrated circuit 60 allows the user to obtain a memory capacity of 2GB formed by two memories 41. At the same time, the integrated circuit 60 also includes two logic circuits 21 to provide More computing power.

According to the above embodiments and specific application methods, the present invention can further summarize a manufacturing method of a reconfigurable capacity bandwidth memory structure. As shown in Figure 4, the method includes the following steps: Provide a first circuit layer 20 and a second circuit layer 40 (S41); Stack a plurality of separation layers to form a seal 30 on the first circuit layer 20 and the second circuit layer 40 respectively, and form a signal transmission layer on at least one of the separation layers (S42); and After the sealing member is formed, the second circuit layer 40 is stacked on the first circuit layer through the sealing member (S43).

In summary, by disposing the signal transmission layer 31 on the seal 30, the logic circuits 21 and the memories 41 can be connected, so that subsequent integrated circuits can communicate with each other through the signal transmission layer 31. Electrical connection, in this way, integrated circuits that meet the needs of different customers can be manufactured through a single integrated circuit process. There is no need to perform integrated circuit processes in batches according to different user needs, and when users need multiple logic circuits and multiple When two memories form an integrated circuit, the reconfigurable capacity-bandwidth memory structure can be divided according to needs, without the situation that the signals between the integrated circuits cannot be transmitted to each other, so as to save production costs and The purpose of flexible expansion.

10: Reconfigurable capacity bandwidth memory structure 20: First circuit layer 20’: Logic circuit layer 21: Logic circuit 30:Seals 31: Signal transmission layer 40: Second circuit layer 40’: Memory crystal layer 41:Memory 50:Metal pad 51: Conductive parts 60:Integrated circuit

Figure 1 is a structural diagram of the reconfigurable capacity bandwidth memory structure of the present invention; Figure 2 is a structural diagram of a specific embodiment of the reconfigurable capacity bandwidth memory structure of the present invention; Figure 3 is a bottom cross-sectional structural view of the reconfigurable capacity bandwidth memory structure of the present invention; and FIG. 4 is a flow chart of the manufacturing method of the reconfigurable capacity bandwidth memory structure of the present invention.

10: Reconfigurable capacity bandwidth memory structure

20: First circuit layer

30:Seals

31: Signal transmission layer

40: Second circuit layer

50:Metal pad

51: Conductive parts

Claims (10)

A reconfigurable capacity bandwidth memory structure, which includes: a first circuit layer; A sealing member disposed on the first circuit layer; a signal transmission layer disposed within the seal and protruding outward; and A second circuit layer is provided on the top of the seal. The reconfigurable capacity bandwidth memory structure of claim 1, wherein the sealing member is in the shape of a closed ring. The reconfigurable capacity bandwidth memory structure as claimed in claim 2, wherein the first circuit layer is a logic circuit layer or a memory crystal layer, and the second circuit layer is the logic circuit layer or the memory crystal layer. bulk crystal layer. The reconfigurable capacity bandwidth memory structure as described in claim 3, wherein the logic circuit layer includes: A logic circuit is provided on one side of the logic circuit layer and within the closed ring of the seal. The reconfigurable capacity bandwidth memory structure as claimed in claim 4, wherein the memory crystal layer includes: A memory is disposed on one side of the memory crystal layer and within the closed ring of the seal, and is disposed opposite to the logic circuit. The reconfigurable capacity bandwidth memory structure as described in claim 5, wherein the reconfigurable capacity bandwidth memory structure further includes: A metal pad is provided on the logic circuit and the memory respectively. The reconfigurable capacity-bandwidth memory structure as described in claim 6, wherein the reconfigurable capacity-bandwidth memory structure further includes: A conductive component is disposed between the signal transmission layer and the metal pad and is electrically connected to the signal transmission layer and the metal pad. The reconfigurable capacity bandwidth memory structure of claim 7, wherein the seal is formed by stacking a plurality of separation layers. The reconfigurable capacity bandwidth memory structure of claim 8, wherein the length of the signal transmission layer is greater than the length of the separation layers. A method for manufacturing a reconfigurable capacity-bandwidth memory structure, which method includes: Provide a first circuit layer and a second circuit layer; Stack a plurality of separation layers to form a seal on the first circuit layer and the second circuit layer respectively, and form a signal transmission layer on at least one of the separation layers; and After the sealing member is formed, the second circuit layer is stacked on the first circuit layer through the sealing member.

Images