TWI823291B - Protection circuit - Google Patents

Abstract

A protection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor and a second transistor having a first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the pad and the ground terminal and controlled by the trigger circuit. When the transient event occurs on the pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.

Description

protection circuit

The present invention relates to a protection circuit, and in particular to a protection circuit that has high voltage tolerance and can quickly provide a discharge path.

With the development of semiconductor manufacturing processes for integrated circuits, the size of semiconductor components has been reduced to the sub-micron stage to improve the performance and computing speed of integrated circuits. However, shrinking device sizes have made semiconductor devices susceptible to damage by large currents caused by voltage spikes. Therefore, when a large current/voltage occurs in a very short time on the input/output bonding pads coupled to the integrated circuit, a protection circuit that can respond quickly to the large current/voltage and stably provide a discharge path is required. . For example, protection devices or circuits such as electrostatic discharge (ESD) protection circuits and transient voltage suppressors (TVS) can provide discharge paths to protect semiconductor components from damage by large currents. Therefore, the discharge performance (ie, protection capability) of this protection device or circuit is really important.

In view of this, the present invention proposes a protection circuit. The protection circuit is coupled to a bonding pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor and a second transistor having a first conductivity type coupled in series between the bonding pad and a ground terminal. The trigger circuit detects whether a transient event occurs on the bond pad. The discharge circuit is coupled between the bonding pad and the ground terminal and is controlled by the trigger circuit. When a transient event occurs on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the bonding pad and the ground.

In order to make the above-mentioned objects, features and advantages of the present invention more clearly understandable, a preferred embodiment is given below and described in detail with reference to the accompanying drawings.

Figure 1 shows a protection circuit according to an embodiment of the present invention. Referring to Figure 1, in order to explain in detail, Figure 1 not only shows the protection circuit 1, but also shows the bonding pad 12. As shown in FIG. 1 , the protection circuit 1 is coupled to the bonding pad 12 and includes a trigger circuit 10 and a discharge circuit 11 . The trigger circuit 10 and the discharge circuit 11 are both coupled between the bonding pad 12 and the ground terminal GND.

When the protection circuit 1 operates in a normal operating mode, a supply voltage is provided to the bonding pad 12 . At this time, the trigger circuit 10 controls the discharge circuit 11 not to provide any discharge path between the bonding pad 12 and the ground terminal GND. When the protection circuit 1 is not operating in the normal operating mode, the bonding pad 12 does not receive any supply voltage. At this time, the trigger circuit 10 detects whether a transient event occurs on the bonding pad 12 . When detecting whether a transient event occurs on the bonding pad 12, the trigger circuit 10 generates a signal or voltage to control or trigger the discharge circuit 11 to provide a discharge path between the bonding pad 12 and the ground terminal GND.

In this embodiment, the transient event may be an event involving a large voltage or a large current. For example, the transient event may be an electrostatic discharge (ESD) event or a surge event. In one embodiment, the protection circuit 1 may be an electrostatic discharge (Electrostatic Discharge, ESD) protection circuit or a transient voltage suppressor (Transient Voltage Suppressor, TVS).

Figure 2 shows a protection circuit according to another embodiment of the present invention. The protection circuit 1 in Figure 1 can be realized by the protection circuit 1A in Figure 2 . Referring to FIG. 2 , the trigger circuit 10 of the protection circuit 1A may include transistors 20 and 21 and a resistor 22 . The transistors 20 and 21 have the same conductivity type, and each has three electrode terminals, namely a first electrode terminal, a second electrode terminal, and a control electrode terminal. In this embodiment, the transistors 20 and 21 are both implemented by N-type Metal-Oxide-Semiconductor (NMOS) transistors, that is, the conductivity type of the transistors 20 and 21 is N-type. The first electrode terminal, the second electrode terminal, and the control electrode terminal of each of the transistors 20 and 21 are respectively the drain electrode, the source electrode, and the gate electrode of the NMOS transistor. As shown in Figure 2. The drain electrode (first electrode terminal) 200 of the NMOS transistor 20 is coupled to the bonding pad 12 , its source electrode (second electrode terminal) 201 is coupled to the node N20 , and its gate electrode (control electrode terminal) 202 is coupled to the node N21 . The drain 210 of the NMOS transistor 21 is coupled to the node N20, the source 211 of the NMOS transistor 21 is coupled to the ground terminal GND, and the gate 212 of the NMOS transistor 21 is coupled to the node N21. According to the above connection structure, the NMOS transistors 20 and 21 are coupled in series between the bonding pad 12 and the ground terminal GND. The resistor 22 is coupled between the node N21 and the ground terminal GND.

As shown in FIG. 2 , the discharge circuit 11 includes a transistor 23 . The transistor 23 has three electrode terminals, which are a first electrode terminal, a second electrode terminal, and a control electrode terminal. In this embodiment, the transistor 23 is also implemented as an NMOS transistor. The first electrode terminal, the second electrode terminal, and the control electrode terminal of the transistor 23 are the drain electrode, the source electrode, and the gate electrode of the NMOS transistor 23 respectively. The drain 230 of the NMOS transistor 23 is coupled to the bonding pad 12 , the source 231 of the NMOS transistor 23 is coupled to the ground terminal GND, and the gate 232 of the NMOS transistor 23 is coupled to the node N20 . According to the above connection structure, it can be seen that the NMOS transistor 23 is also coupled between the bonding pad 12 and the ground terminal GND.

In the embodiment of the present invention, the withstand voltage of the NMOS transistor 23 is higher than that of the NMOS transistors 20 and 21 . In one example, the NMOS transistors 20 and 23 are high voltage withstand transistors, and the voltage withstand level of the NMOS transistor 23 is higher than that of the NMOS transistor 20 . For example, the NMOS transistor 20 is a transistor with a voltage resistance of 20V (volts), the NMOS transistor 21 is a transistor with a voltage resistance of 5V, and the NMOS transistor 23 is a transistor with a voltage resistance of 24V. However, the present invention does not use This is the limit.

In one embodiment, the NMOS transistors 20 and 23 can be implemented as high-voltage tolerant transistors by increasing the dimensions (eg, thickness, lateral diffusion distance) of the doped regions of their drains.

In one embodiment, the channel width of the NMOS transistors 20 and 21 is approximately several hundred micrometers (um), and the channel width of the NMOS transistor 23 is approximately 100 to 150 kilomicrometers (kum). The resistance value of the resistor 22 is approximately in the range of 1 to 10 kiloohms (kohm).

The detailed operation of the protection circuit 1A will be described below.

Referring to FIG. 3A, when the protection circuit 1A operates in a normal operating mode, a supply voltage VDD is provided to the bonding pad 12. In this embodiment, the supply voltage VDD is, for example, a voltage of 24V. At this time, since the resistor 22 is coupled between the node N21 and the ground terminal GND, the voltage on the node N21 is at a low level relative to the supply voltage VDD, that is, the voltage on the gates 202 and 212 of the NMOS transistors 20 and 21 The voltages are all at a low level. Due to the low level voltage on gates 202 and 212, both NMOS transistors 20 and 21 are turned off. In Figure 3A and subsequent figures, a turned-off transistor will be marked "(OFF)". Since the NMOS transistors 20 and 21 are both turned off, the voltage on the node N20 is at a low level relative to the supply voltage VDD, that is, the voltage on the gate 232 of the NMOS transistor 23 is at a low level, which makes the NMOS transistor 23 is also turned off (OFF).

According to the above, it can be known that in the normal operation mode, all NMOS transistors in the protection circuit 1A coupled between the bonding pad 12 and the ground terminal GND are in the off state. In other words, the protection circuit 1A of this case cuts off any discharge path between the bonding pad 12 and the ground terminal GND. Therefore, in the normal operating mode, the protection circuit 1A will not cause unnecessary leakage current, and avoid unnecessary power consumption caused by the setting of the protection circuit 1A.

Referring to FIG. 3B , when the protection circuit 1A is not in the normal operation mode, the supply voltage VDD is not provided to the bonding pad 12 , that is, the bonding pad 12 is in a floating state, or the voltage of the bonding pad 12 is equal to 0V. When a transient event (eg, an ESD event or a surge event) occurs on bonding pad 12 , the voltage of bonding pad 12 increases momentarily. There is a parasitic capacitance between the drain 200 and the gate 202 of the transistor 20 , which forms an RC circuit with the resistor 22 . Through the coupling effect of the parasitic capacitance between the drain 200 and the gate 202 , the voltage on the node N21 increases instantaneously with the voltage of the bonding pad 12 . At this time, in response to the instantaneous increase in voltage at node N21, NMOS transistors 20 and 21 are turned on instantaneously. In Figure 3B and subsequent figures, the transistor that is turned on will be marked "(ON)".

Due to the conduction of the NMOS transistors 20 and 21, the NMOS transistors 20 and 21 respectively have conduction internal resistances R30 and R31. The conduction internal resistances R30 and R31 form a voltage divider. This voltage divider divides the voltage difference between the bonding pad 12 and the ground terminal GND to generate the trigger voltage V30 on the node N20. The trigger voltage V30 generated through the voltage dividing operation has a high level voltage to turn on the NMOS transistor 23 . Therefore, a discharge path P30 is formed between the bonding pad 12 and the ground terminal GND, so that the charge of a large current accompanying the transient event on the bonding pad 12 is conducted to the ground terminal GND through the discharge path P30.

According to the above, when a transient event occurs on the bonding pad 12, the trigger circuit 10 can quickly generate a high level trigger voltage V30 through the operation of the NMOS transistors 20 and 21 and the resistor 22 to trigger the discharge circuit 11 to provide a discharge path. P30, so that a large amount of charges on the bonding pad 12 can be quickly conducted to the ground terminal GND through the discharge path P30, thereby protecting components in other circuits coupled to the bonding pad 12 from being damaged by large currents.

In the embodiment of FIG. 2 , although not shown in FIG. 2 , the base (bulk) of the NMOS transistor 23 may be connected to its source 231 .

Figure 4 shows a protection circuit according to another embodiment of the present invention. The protection circuit 1 in Figure 1 can be implemented by the protection circuit 1B in Figure 4 . The circuit structure of the protection circuit 1B in Figure 4 is substantially the same as the circuit structure of the protection circuit 1A in Figure 2 . Referring to Figure 4, the difference between the protection circuits 1B and 1A lies in the base (bulk) 233 of the NMOS transistor 23. The base 233 of the NMOS transistor 23 is coupled to the node N21 , that is, the base 233 is coupled to the gates 202 and 212 of the NMOS transistors 20 and 21 .

Since the circuit structure of the protection circuit 1B in Figures 4 and 5 is roughly the same as that of the protection circuit 1A in Figure 2, the operation of the protection circuit 1B is also basically the same as the operation of the protection circuit 1A. Please refer to the above-mentioned description of the protection circuit 1A. Description with Figure 3B. In the following, description of the same operations will be omitted, and only the operation of the NMOS transistor 23 will be specifically described.

Referring to FIG. 4 , the drain 230 , source 231 , and base 233 of the NMOS transistor 23 form a parasitic NPN bipolar junction transistor (BJT) 40 . The drain electrode 230, the source electrode 231, and the base electrode 233 of the NMOS transistor 23 serve as the collector (C), the emitter (E), and the base electrode (B) of the NPN type BJT 40, respectively. When the protection circuit 1B operates in a normal operation mode, the voltage on the node N21 is at a low level relative to the supply voltage VDD. Based on the low level voltage on the node N21 and the source 231 coupled to the ground terminal GND, the NPN BJT 40 is turned off. In the case where the protection circuit 1B is not in the normal operating mode and a transient event occurs on the bonding pad 12, the base-emitter voltage (V _BE ) of the NPN type BJT 40 is greater than 0.7V because the voltage on the node N21 has a high level. , which makes the NPN type BJT 40 conductive. At this time, the charge of the large current accompanying the transient event on the bonding pad 12 is also conducted to the ground terminal GND through the turned-on NPN BJT 40 .

Based on the above, in the protection circuit 1B of FIG. 4, the base 233 of the NMOS transistor 23 is coupled to the node N21. Therefore, when a transient event occurs on the bonding pad 12 , the parasitic NPN BJT 40 can quickly turn on in response to the high level voltage of the node N21 , thereby improving the overall discharge capability of the NMOS transistor 23 .

Figure 6 shows a protection circuit according to another embodiment of the present invention. The protection circuit 1 in Figure 1 can be realized by the protection circuit 1C in Figure 6 . Referring to FIG. 6 , the trigger circuit 10 of the protection circuit 1C may include transistors 60 and 61 and a resistor 62 . The transistors 60 and 61 have the same conductivity type, and each has three electrode terminals, namely a first electrode terminal, a second electrode terminal, and a control electrode terminal. In this embodiment, the transistors 60 and 61 are both implemented as NMOS transistors, that is, the conductivity type of the transistors 60 and 61 is N-type. The first electrode terminal, the second electrode terminal, and the control electrode terminal of each of the transistors 60 and 61 are respectively the drain electrode, the source electrode, and the gate electrode of the NMOS transistor. As shown in Figure 6. The drain 600 of the NMOS transistor 60 is coupled to the bonding pad 12 , and the source 601 of the NMOS transistor 60 is coupled to the node N60 . The drain 610 of the NMOS transistor 61 is coupled to the node N60, the source 611 of the NMOS transistor 61 is coupled to the ground terminal GND, and the gate 612 of the NMOS transistor 61 is coupled to the power terminal T60. According to the above connection structure, it can be seen that the NMOS transistors 60 and 61 are coupled in series between the bonding pad 12 and the ground terminal GND. Resistor 62 is coupled between gate 602 of NMOS transistor 60 and node N60.

As shown in FIG. 6 , the discharge circuit 11 includes a transistor 63 . The transistor 63 has three electrode terminals, which are a first electrode terminal, a second electrode terminal, and a control electrode terminal. In this embodiment, the transistor 63 is also implemented as an NMOS transistor. The first electrode terminal, the second electrode terminal, and the control electrode terminal of the transistor 63 are the drain electrode, the source electrode, and the gate electrode of the NMOS transistor 63 respectively. The drain 630 of the NMOS transistor 63 is coupled to the bonding pad 12 , the source 631 of the NMOS transistor 63 is coupled to the ground terminal GND, and the gate 632 of the NMOS transistor 63 is coupled to the node N60 . According to the above connection structure, it can be seen that the NMOS transistor 63 is also coupled between the bonding pad 12 and the ground terminal GND.

In the embodiment of the present invention, the withstand voltage of the NMOS transistor 63 is higher than that of the NMOS transistors 60 and 61 . In one example, the NMOS transistors 60 and 63 are high-voltage withstand transistors, and the voltage-withstand level of the NMOS transistor 63 is higher than that of the NMOS transistor 60 . For example, the NMOS transistor 60 is a transistor with a withstand voltage of 20V (volts), the NMOS transistor 61 is a transistor with a withstand voltage of 5V, and the NMOS transistor 63 is a transistor with a withstand voltage of 24V.

In one embodiment, the NMOS transistors 60 and 63 can be implemented as high-voltage withstand transistors by increasing the doping region size of their drains (eg, vertical doping depth or lateral diffusion distance). However, the present invention does not Not limited to this.

In one embodiment, the channel width of the NMOS transistors 60 and 61 is approximately several hundred micrometers (um), and the channel width of the NMOS transistor 63 is approximately 100 to 150 kilomicrometers (kum). The resistance value of the resistor 62 is approximately in the range of 1 to 10 kiloohms (kohm).

The detailed operation of the protection circuit 1C will be described below.

Referring to FIG. 7A, when the protection circuit 1C operates in a normal operation mode, a supply voltage VDD is provided to the bonding pad 12, and another supply voltage VCC is provided to the power terminal T60. In this embodiment, the supply voltage VDD is, for example, a voltage of 24V, and the supply voltage VCC is, for example, a voltage of 5V. At this time, since the supply voltage VCC of 5V is provided to the gate 612 of the NMOS transistor 61 through the power terminal T60, the NMOS transistor 61 is always in a conductive state (ON). Through the turned-on NMOS transistor 61, the voltage on the node N60 is at a low level relative to the supply voltage VDD, that is, the voltage on the gate 632 of the NMOS transistor 63 is at a low level. Based on the low level voltage on gate 632, NMOS transistor 63 is turned OFF. In addition, the voltage of the gate 602 is at a low level relative to the supply voltage VDD through the resistor 62 coupled between the gate 602 of the NMOS transistor 60 and the node N60. Based on the low level voltage of gate 602, NMOS transistor 60 is turned off.

According to the above, it can be known that in the normal operation mode, the NMOS transistors 60 and 63 in the protection circuit 1C coupled between the bonding pad 12 and the ground terminal GND are in the off state. In other words, the protection circuit 1C of this case cuts off any discharge path between the bonding pad 12 and the ground terminal GND. Therefore, in the normal operating mode, the protection circuit 1C will not cause unnecessary leakage current, and avoid unnecessary power consumption caused by the setting of the protection circuit 1C.

Referring to FIG. 7B , when the protection circuit 1C is not in the normal operating mode, the supply voltage VDD is not provided to the bonding pad 12 , and the supply voltage VCC is not provided to the power terminal T60 , that is, the bonding pad 12 and/or the power supply. The terminal T60 is in a floating state, or the voltage of the bonding pad 12 and/or the power terminal T60 is equal to 0V. When a transient event (eg, an ESD event or a surge event) occurs on bonding pad 12 , the voltage of bonding pad 12 increases momentarily. There is a parasitic capacitance between the drain 600 and the gate 602 of the transistor 60 , which forms an RC circuit with the resistor 62 . Through the coupling effect of the parasitic capacitance between the drain 600 and the gate 602 , the voltage of the gate 602 of the NMOS transistor 60 increases instantaneously with the voltage of the bonding pad 12 . At this time, in response to the instantaneous increase in the voltage of the gate 602, the NMOS transistor 60 is turned on. In addition, since the power terminal T60 is in a floating state or the voltage of the power terminal T60 is equal to 0V, the NMOS transistor 61 is in a fully conductive state or a weak conduction state (ON).

Due to the conduction of the NMOS transistors 60 and 61, the NMOS transistors 60 and 61 respectively have conduction internal resistances R60 and R61. The conduction internal resistances R60 and R61 form a voltage divider. This voltage divider divides the voltage difference between the bonding pad 12 and the ground terminal GND to generate the trigger voltage V60 on the node N60. The trigger voltage V60 generated through the voltage dividing operation has a high level voltage to turn on the NMOS transistor 63 . Therefore, a discharge path P60 is formed between the bonding pad 12 and the ground terminal GND, so that the charge of a large current accompanying the transient event on the bonding pad 12 is conducted to the ground terminal GND through the discharge path P60.

According to the above, when a transient event occurs on the bonding pad 12, the trigger circuit 10 can quickly generate a high level trigger voltage V60 through the operation of the NMOS transistors 60 and 61 and the resistor 62 to trigger the discharge circuit 11 to provide a discharge path. P60, so that a large amount of charges on the bonding pad 12 can be quickly conducted to the ground terminal GND through the discharge path P60, thereby protecting components in other circuits coupled to the bonding pad 12 from being damaged by large currents.

In the embodiment of FIG. 6 , although not shown in FIG. 6 , the base of the NMOS transistor 63 may be connected to its source 631 .

Figure 8 shows a protection circuit according to another embodiment of the present invention. The protection circuit 1 in Figure 1 can be realized by the protection circuit 1D in Figure 8 . The circuit structure of the protection circuit 1D in Figure 8 is substantially the same as the circuit structure of the protection circuit 1C in Figure 6 . Referring to Figure 8, the difference between the protection circuits 1D and 1C lies in the base (bulk) 633 of the NMOS transistor 63. The base 633 of the NMOS transistor 63 is coupled to the node N60 , that is, the base 633 is coupled to the gate 632 of the NMOS transistor 63 .

Since the circuit structure of the protection circuit 1D in Figure 8 is roughly the same as that of the protection circuit 1C in Figure 6, the operation of the protection circuit 1D is also basically the same as the operation of the protection circuit 1C. Please refer to the above about 7A and 7B. Figure description. In the following, description of the same operations will be omitted, and only the operation of the NMOS transistor 63 will be specifically described.

Referring to FIGS. 8 and 9 , the drain 630 , the source 631 , and the base 633 of the NMOS transistor 63 form a parasitic NPN bipolar junction transistor (BJT) 80 . The drain electrode 630, the source electrode 631, and the base electrode 633 of the NMOS transistor 63 serve as the collector (C), the emitter (E), and the base electrode (B) of the NPN type BJT 80, respectively. When the protection circuit 1D operates in a normal operating mode, the voltage on the node N60 is at a low level relative to the supply voltage VDD. Based on the low level voltage on the node N60 and the source 631 coupled to the ground terminal GND, the NPN BJT 80 is turned off. In the case where the protection circuit 1D is not in the normal operating mode and a transient event occurs on the bonding pad 12, since the trigger voltage V60 on the node N60 has a high level, the base-emitter voltage (V _BE ) of the NPN type BJT 80 is greater than 0.7V, which makes the NPN type BJT 80 conductive. At this time, the charge of the large current accompanying the transient event on the bonding pad 12 is also conducted to the ground terminal GND through the turned-on NPN BJT 80 .

Based on the above, in the protection circuit 1D of FIG. 8, the base 633 of the NMOS transistor 63 is coupled to the node N60. Therefore, when a transient event occurs on the bonding pad 12 , the parasitic NPN BJT 80 can quickly turn on in response to the high level voltage of the node N60 , thereby improving the overall discharge capability of the NMOS transistor 63 .

Figure 10A shows an electronic circuit according to an embodiment of the present invention. Referring to Figure 10A, the electronic device 13A includes a core circuit 100, a bonding pad 12, and the protection circuit 1 shown in Figure 1 of this case. This protection circuit 1 can be implemented by any one of the protection circuits 1A to 1D shown in Figures 2, 4, 6, and 8. In the embodiment of FIG. 10A , the protection circuit 1 is arranged outside the core circuit 100 . When a transient event occurs at the bonding pad 12 , the protection circuit 1 provides or triggers a discharge path between the bonding pad 12 and the ground terminal GND. A large amount of charge on the bonding pad 12 can be quickly conducted to the ground terminal GND through this discharge path, thereby protecting the components or circuits in the core circuit 100 from being damaged by large currents accompanying transient events.

In other embodiments, the protection circuit 1 may be disposed inside the core circuit 100 . As shown in FIG. 10B , the protection circuit 1 and other electronic components or circuits 1000 are provided in the core circuit 100 of the electronic device 13B. When a transient event occurs at the bonding pad 12 , the protection circuit 1 provides or triggers a discharge path between the bonding pad 12 and the ground terminal GND. A large amount of charge on the bonding pad 12 can be quickly conducted to the ground terminal GND through this discharge path, thereby protecting the electronic components in the core circuit 100 or the circuit 1000 from being damaged by large currents accompanying transient events.

Although the present invention has been disclosed above in terms of preferred embodiments, they are not intended to limit the present invention. Anyone skilled in the art can make modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention is The scope of protection shall be determined by the appended patent application scope.

1,1A,1B,1C,1D: Protection circuit

10: Trigger circuit

11: Discharge circuit

12:Joining pad

13A,13B: Electronic devices

20,21,23:NMOS transistor

22: Resistor

40:NPN type bipolar junction transistor (BJT)

60,61,63:NMOS transistor

62: Resistor

80:NPN type bipolar junction transistor (BJT)

100:Core circuit

200,210,230: drain (first electrode terminal)

201,211,231: Source (second electrode terminal)

202,212,232: Gate (control electrode terminal)

233:Base

1000: Electronic components or circuits

600,610,630: drain (first electrode terminal)

601,611,631: Source (second electrode terminal)

602,612,632: Gate (control electrode terminal)

633:Base

GND: ground terminal

N20, N21, N60: nodes

P30,P60: discharge path

R30, R31, R60, R61: internal conduction resistance

T60: power supply terminal

V30, V60: trigger voltage

VCC, VDD: supply voltage

Figure 1 shows a protection circuit according to an embodiment of the present invention. Figure 2 shows a protection circuit according to another embodiment of the present invention. Figures 3A and 3B show the operation diagram of the protection circuit of Figure 2. Figure 4 shows a protection circuit according to another embodiment of the present invention. Figure 5 shows a parasitic NPN bipolar junction transistor in the protection circuit of Figure 4. Figure 6 shows a protection circuit according to another embodiment of the present invention. Figures 7A and 7B illustrate the operation of the protection circuit of Figure 6. Figure 8 shows a protection circuit according to another embodiment of the present invention. Figure 9 shows a parasitic NPN bipolar junction transistor in the protection circuit of Figure 8. Figure 10A shows an electronic circuit according to an embodiment of the present invention, which has a protection circuit according to any embodiment of the present invention. Figure 10B shows an electronic circuit according to another embodiment of the present invention, which has a protection circuit according to any embodiment of the present invention.

1A: Protection circuit

10: Trigger circuit

11: Discharge circuit

12:Joining pad

20,21,23:NMOS transistor

22: Resistor

200,210,230: drain (first electrode terminal)

201,211,231: Source (second electrode terminal)

202,212,232: Gate (control electrode terminal)

GND: ground terminal

N20, N21: node

Claims (14)

A protection circuit coupled to a bonding pad includes: a trigger circuit including a first transistor and a second transistor that are coupled in series between the bonding pad and a ground terminal and have a first conductivity type, Wherein, the trigger circuit detects whether a transient event occurs on the bonding pad; and a discharge circuit is coupled between the bonding pad and the ground terminal and is controlled by the trigger circuit. The discharge circuit includes a A third transistor of the first conductivity type is between the bonding pad and the ground terminal; wherein the first transistor has a first electrode terminal coupled to the bonding pad and a first node coupled to a second electrode terminal, and the second transistor has a first electrode terminal coupled to the first node and a second electrode terminal coupled to the ground terminal; and wherein, when the transient event occurs on the bonding pad At this time, the trigger circuit generates a trigger voltage at the first node to turn on the third transistor, thereby providing a discharge path between the bonding pad and the ground terminal. The protection circuit of claim 1, wherein when the transient event occurs on the bonding pad, both the first transistor and the second transistor are turned on. The protection circuit of claim 1, wherein the first conductivity type is N type. The protection circuit of claim 1, wherein: the trigger circuit further includes a resistor; the first transistor further has a control electrode terminal coupled to a second node; the second transistor further has a control electrode terminal coupled to the second node. a control electrode terminal of the node; the third transistor has a first electrode terminal coupled to the bonding pad, coupled to the ground terminal a second electrode terminal and a control electrode terminal coupled to the first node, and the trigger voltage is generated at the first node; and the resistor is coupled between the second node and the ground terminal. The protection circuit of claim 4, wherein the third transistor further has a base, and the base of the third transistor is coupled to the second node. The protection circuit of claim 4 or 5, wherein when receiving a supply voltage on the bonding pad, the first transistor, the second transistor, and the third transistor are all turned off. The protection circuit of claim 1, wherein: the trigger circuit further includes a resistor; the first transistor further has a control electrode terminal; the second transistor further has a control electrode terminal coupled to a power terminal; The three-transistor has a first electrode terminal coupled to the bonding pad, a second electrode terminal coupled to the ground terminal, and a control electrode terminal coupled to the first node, and the trigger voltage is generated at the first node ; And the resistor is coupled between the control electrode terminal of the first transistor and the first node. The protection circuit of claim 7, wherein the third transistor further has a base, and the base of the third transistor is coupled to the first node. The protection circuit of claim 7 or 8, wherein when a first supply voltage is received on the bonding pad and a second supply voltage is received at the power terminal, the first transistor and the third transistor are turned off, and The second transistor is turned on. The protection circuit of claim 9, wherein the first supply voltage is greater than at the second supply voltage. The protection circuit of claim 1, wherein when the transient event occurs on the bonding pad, the first transistor, the second transistor, and the third transistor are all turned on. The protection circuit of claim 1, wherein the voltage withstand level of the third transistor is higher than the voltage withstand levels of the first transistor and the second transistor. The protection circuit of claim 1, wherein the voltage resistance of the first transistor is higher than the voltage resistance of the second transistor and the second transistor. The protection circuit of claim 1, wherein the protection circuit is a transient voltage suppressor (Transient Voltage Suppressor, TVS).

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