TWI587593B - Integrated circuits and electrostatic discharge protection circuits - Google Patents

Description

Integrated circuit and electrostatic discharge protection circuit

The present invention relates to an integrated circuit, and more particularly to an integrated circuit having an electrostatic discharge protection circuit.

As the semiconductor circuit develops, the component size has been reduced to the sub-micron stage to improve the performance and speed of the integrated circuit. However, the size reduction of the component has some reliability problems, especially the integrated circuit. It has the greatest impact on the protection of Electrostatic Discharge (ESD). When the component size is reduced due to advanced process technology, the electrostatic discharge protection capability is also reduced, resulting in a significant reduction in ESD tolerance of the component. Therefore, an electrostatic discharge protection circuit is required to provide a discharge path for electrostatic charge discharge. Among them, how to provide an ESD protection circuit can quickly provide the most important issue of the discharge circuit.

Accordingly, the present invention provides an electrostatic discharge protection circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between the power terminal and the ground terminal, and has a control electrode terminal coupled to the first node to receive the first signal. The second MOS transistor has a control electrode end coupled to the first node and a first electrode end, and a second electrode end having a base end coupled to the first MOS transistor. Third gold oxide semi-electric crystal The body has a control electrode end coupled to the second node to receive the second signal, a first electrode end coupled to the first node, and a second electrode end coupled to the base end of the first MOS transistor. The first signal and the second signal are inverted from each other.

The present invention provides an integrated circuit including a core circuit and an electrostatic discharge protection circuit. The core circuit is coupled between the first bonding pad and the second bonding pad. The ESD protection circuit is coupled to the first bonding pad. When an electrostatic discharge event occurs on the first bond pad, the electrostatic discharge protection circuit provides a discharge path between the first bond pad and the second bond pad to protect the core circuit. The electrostatic discharge protection circuit includes a first MOS transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between the first bond pad and the second bond pad, and has a control electrode end coupled to the first node to receive the first signal. The second MOS transistor has a control electrode end coupled to the first node and a first electrode end, and a second electrode end having a base end coupled to the first MOS transistor. The third MOS transistor has a control electrode end coupled to the second node to receive the second signal, a first electrode end coupled to the first node, and a second electrode coupled to the base end of the first MOS transistor extreme. The first signal and the second signal are inverted from each other.

1‧‧‧ integrated circuit

10‧‧‧ core circuit

11‧‧‧Electrostatic discharge protection circuit

20, 40, 60, 80‧‧‧ Electrostatic Discharge Detection Circuit

21, 41, 61, 81‧‧ ‧ inverter

C20, C40, C60, C80‧‧‧ capacitors

GND‧‧‧ Grounding

N20...N23, N30, N40...N43, N50, N60, N80‧‧‧ NMOS transistors

ND20, ND40, ND60, ND80‧‧‧ common nodes

ND21, ND41, ND61, ND81‧‧‧ nodes

P20, P40, P60...P63, P70, P80...P83, P90‧‧‧ PMOS transistor

PAD10, PAD11‧‧‧ joint pad

R20, R40, R60, R80‧‧‧ resistors

S20, S21, S40, S41, S60, S61, S80, S81‧‧‧ signals

T20, T40, T60, T80‧‧‧ power terminal

T21, T41, T61, T81‧‧‧ grounding end

VDD‧‧‧ operating voltage

Fig. 1 shows an integrated circuit according to an embodiment of the present invention.

Fig. 2 is a view showing an electrostatic discharge protection circuit for realizing an electrostatic discharge path by an N-type transistor according to an embodiment of the present invention.

Fig. 3 is a view showing an electrostatic discharge protection circuit for realizing an electrostatic discharge path with an N-type transistor according to another embodiment of the present invention.

Fig. 4 is a view showing an electrostatic discharge protection circuit for realizing an electrostatic discharge path by an N-type transistor according to still another embodiment of the present invention.

Fig. 5 is a view showing an electrostatic discharge protection circuit for realizing an electrostatic discharge path by an N-type transistor according to still another embodiment of the present invention.

Fig. 6 is a view showing an electrostatic discharge protection circuit for realizing an electrostatic discharge path with a P-type transistor according to an embodiment of the present invention.

Fig. 7 is a view showing an electrostatic discharge protection circuit for realizing an electrostatic discharge path with a P-type transistor according to another embodiment of the present invention.

Figure 8 is a diagram showing an electrostatic discharge protection circuit for realizing an electrostatic discharge path with a P-type transistor in accordance with still another embodiment of the present invention.

Figure 9 is a diagram showing an electrostatic discharge protection circuit for realizing an electrostatic discharge path with a P-type transistor according to still another embodiment of the present invention.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

Fig. 1 is a view showing an integrated circuit according to an embodiment of the present invention. Referring to FIG. 1, the integrated circuit 1 includes a core circuit 10 and an electrostatic discharge protection circuit 11. The core circuit 10 is coupled to the pads PAD10 and PAD11. The bonding pad PAD11 is coupled to the ground GND. When the core circuit 10 is in a normal operation mode, an operating voltage VDD is supplied to the bonding pad PAD10; and when the core circuit 10 is not in a normal operation mode, the bonding pad PAD10 does not receive the operating voltage VDD. The ESD protection circuit 11 is coupled between the bonding pads PAD10 and PAD11. During the non-normal operation mode of the core circuit 10, an electrostatic discharge event occurs on the bonding pad PAD10. The ESD protection circuit 11 provides a discharge path between the bonding pads PAD10 and PAD11 to allow electrostatic charges (electrostatic discharge current) on the bonding pad PAD10 to be conducted to the bonding point PAD11 through the discharging path, thereby protecting the core. The components within circuit 10 are not subject to electrostatic charge. Various embodiments of the electrostatic discharge circuit 11 will be described in detail below.

Figure 2 is a diagram showing an electrostatic discharge protection circuit in accordance with an embodiment of the present invention. In order to clearly show the circuit configuration of the electrostatic discharge protection circuit 11, FIG. 2 shows only the electrostatic discharge protection circuit 11 and the bonding pads PAD10 and PAD11. Referring to FIG. 2, the ESD protection circuit 11 includes an ESD detection circuit 20, an inverter 21, an N-type Metal-Oxide-Semiconductor (NMOS) transistor N20 to N22, and a power supply terminal T20. And the ground terminal T21. The power terminal T20 is coupled to the bonding pad PAD10, and the ground terminal T21 is coupled to the bonding pad PAD11. The electrostatic discharge detecting circuit 20 includes a resistor R20 and a capacitor C20 connected in series. The resistor R20 is coupled between the power terminal T20 and the common node ND20. The capacitor C20 is coupled between the common node ND20 and the ground terminal T21. There is a signal S20 on the common node ND20. The inverter 21 is coupled to the common node ND20 to receive the signal S20, and inverts the signal S20 to generate the signal S21 on the node ND21. The inverter 21 includes a P-type Metal-Oxide-Semiconductor (PMOS) transistor P20 and an NMOS transistor N23. The gate (control electrode end) of the PMOS transistor P20 is coupled to the common node ND20, the source (electrode end) is coupled to the power terminal T20, and the drain (electrode end) is coupled to the node ND21. The base and the source of the PMOS transistor P20 are coupled to each other. The gate of the NMOS transistor N23 is coupled to the common node ND20, the drain is coupled to the node ND21, and the source thereof is coupled to the ground terminal T21. The base and the source of the NMOS transistor N23 are coupled to each other. The gate of the NMOS transistor N20 is coupled to the node ND21 to receive the signal S21, which The drain is coupled to the power terminal T20, and the source thereof is coupled to the ground terminal T21. The gate and the drain of the NMOS transistor N21 are coupled to the node ND21, and the source thereof is coupled to the base of the NMOS transistor N20. The base of the NMOS transistor N21 is coupled to the ground terminal T21. The gate of the NMOS transistor N22 is coupled to the node ND20 to receive the signal S20, the drain is coupled to the node ND21 to receive the signal S21, and the source thereof is coupled to the base of the NMOS transistor N20. The base of the NMOS transistor N22 is coupled to the ground terminal T21.

When the core circuit 10 is in the normal operating mode, an operating voltage VDD is provided to the bond pad PAD10, and the bond pad PAD11 is coupled to ground (eg, 0 volts (V)). At this time, the signal S20 on the node ND20 has a high voltage level, that is, the node ND20 has a high voltage. The inverter 21 inverts the high voltage level signal S20 to generate a low voltage level signal S21 at the node ND21. In detail, the high voltage on the node ND20 turns off the PMOS transistor P20 and turns on the NMOS transistor N23. Therefore, the signal S21 on the node ND21 has a low voltage level, that is, the node ND21 has a low voltage (0 V) to turn off the NMOS transistors N20 and N21. Further, the high voltage on the node ND20 turns on the NMOS transistor N22. The substrate of the NMOS transistor N20 is pulled to 0 V through the turned-on NMOS transistor N22. As a result, the gate of the NMOS transistor N20 and the substrate are both at 0V. Therefore, during normal operation of the core circuit 10, the NMOS transistor N20 can be stably in an off state, which does not have any discharge path between the bonding pads PAD10 and PAD11 in the electrostatic discharge protection circuit 11, avoiding affecting the core circuit. 10 operations.

When the core circuit 10 is not in the normal operation mode, the operating voltage VDD is not supplied to the bonding pad PAD10. When a positive electrostatic discharge event occurs on the bonding pad PAD10, the voltage on the power supply terminal T20 instantaneously increases. At this time, based on the element characteristics of the capacitor C20, the signal S20 on the node ND20 has a low voltage level, that is, the node ND20 has a low voltage to turn off the NMOS transistor N22. The inverter 21 inverts the low voltage level signal S20 to generate a high voltage level signal S21 at the node ND21. In detail, the low voltage on the node ND20 turns off the NMOS transistor N23 and turns on the PMOS transistor P20. Therefore, the signal S21 on the node ND21 has a high voltage level, that is, the node ND21 has a high voltage to turn on the NMOS transistors N20 and N21. Due to the conduction of the NMOS transistor N21, there is a voltage difference between the gate and the source of the NMOS transistor N21 (that is, V _TH , that is, the threshold voltage of the NMOS transistor N21). According to the above, the gates of the NMOS transistors N20 and N21 are connected to each other through the node ND21, and the source of the NMOS transistor N21 is coupled to the base of the NMOS transistor N20. In other words, the NMOS transistor N20 has an NMOS transistor N21 between the gate of the NMOS transistor N20 and the substrate. Therefore, there is a voltage difference between the gate of the NMOS transistor N20 and the substrate, that is, the voltage (gate-base voltage, V _GB ) is not equal to zero. In this way, it is ensured that the NMOS transistor N20 can be turned on. Due to the conduction of the NMOS transistor N20, a discharge path is formed between the power supply terminal T20 and the ground terminal T21 (ie, between the bonding pads PAD10 and PAD11) to allow the electrostatic charge on the bonding pad PAD10 to conduct through the discharge path. To the junction PAD11, thereby protecting the components within the core circuit 10 from electrostatic charges.

In one embodiment, the gate-to-matrix voltage of the NMOS transistor N20 can be increased to accelerate conduction. Therefore, the electrostatic discharge circuit 11 further includes one or more NMOS transistors connected in series with the NMOS transistor N21. Referring to FIG. 3, the electrostatic discharge circuit 11 further includes an NMOS transistor N30. The gate and the drain of the NMOS transistor N30 are both coupled to the source of the NMOS transistor N21, and the source thereof is coupled to the base of the NMOS transistor N20. The base of the NMOS transistor N30 is coupled to the ground terminal T21. In the architecture of FIG. 3, the source of the NMOS transistor N21 is coupled to the base of the NMOS transistor N20 through the NMOS transistor N30. In the second and third figures, elements having the same reference numerals have the same operations, and the description thereof will be omitted. In this embodiment, when the core circuit 10 is not in the normal operation mode and an electrostatic discharge event occurs on the bonding pad PAD10, the NMOS transistors N21 and N30 are both turned on. At this time, the voltage difference between the gate of the NMOS transistor N21 and the source of the NMOS transistor N30 is twice _VTH . According to the above, the gates of the NMOS transistors N20 and N21 are connected to each other through the node ND21, and the source of the NMOS transistor N30 is coupled to the base of the NMOS transistor N20. In other words, there are two NMOS transistors N21 and N30 between the gate of the NMOS transistor N20 and the substrate. Therefore, the gate-substrate voltage V _GB (equal to twice V _TH ) of the NMOS transistor N20 in FIG. 3 is larger than the gate-matrix voltage V _GB of the NMOS transistor N20 in FIG. 2 (equal to V _TH ). In comparison with the embodiment of Fig. 2, when an electrostatic discharge event occurs on the bonding pad PAD10, the NMOS transistor N20 of Fig. 3 can be turned on more quickly, i.e., the discharge path can be provided in a short time.

In the embodiment of Fig. 3, an NMOS transistor connected in series with the NMOS transistor N21 is taken as an example. In other embodiments, the number of NMOS transistors connected in series with the NMOS transistor N21 may depend on system requirements. When the number of NMOS transistors connected in series with the NMOS transistor N21 is larger, the gate-base voltage V _{GB of} the NMOS transistor N20 is larger, so that an electrostatic discharge event occurs on the bonding pad PAD10, and the NMOS transistor N20 is more Can be turned on faster.

Figure 4 is a diagram showing an electrostatic discharge protection circuit in accordance with another embodiment of the present invention. In order to clearly show the circuit structure of the electrostatic discharge protection circuit 11, FIG. 4 shows only the electrostatic discharge protection circuit 11 and the bonding pads PAD10 and PAD11. Referring to FIG. 4, the electrostatic discharge protection circuit 11 includes an electrostatic discharge detection circuit. The circuit 40, the inverter 41, the NMOS transistors N40 to N42, the power supply terminal T40, and the ground terminal T41. The power terminal T40 is coupled to the bonding pad PAD10, and the ground terminal T41 is coupled to the bonding pad PAD11. The electrostatic discharge detecting circuit 40 includes a resistor R40 and a capacitor C40 connected in series. The capacitor C40 is coupled between the power terminal T40 and the common node ND40. The resistor R40 is coupled between the common node ND40 and the ground terminal T41. There is a signal S40 on the common node ND40. The inverter 41 is coupled to the common node ND40 to receive the signal S40, and inverts the signal S40 to generate the signal S41 on the node ND41. The inverter 41 includes a PMOS transistor P40 and an NMOS transistor N43. The gate (control electrode end) of the PMOS transistor P40 is coupled to the common node ND40, the source (electrode end) is coupled to the power terminal T40, and the drain (electrode end) is coupled to the node ND41. The base and the source of the PMOS transistor P40 are coupled to each other. The gate of the NMOS transistor N43 is coupled to the common node ND40, the drain is coupled to the node ND41, and the source thereof is coupled to the ground terminal T41. The base and the source of the NMOS transistor N43 are coupled to each other. The gate of the NMOS transistor N40 is coupled to the common node ND40 to receive the signal S40, the drain is coupled to the power terminal T40, and the source thereof is coupled to the ground terminal T41. The gate and the drain of the NMOS transistor N41 are coupled to the common node ND40, and the source thereof is coupled to the base of the NMOS transistor N40. The base of the NMOS transistor N41 is coupled to the ground terminal T41. The gate of the NMOS transistor N42 is coupled to the node ND41 to receive the signal S41, the drain is coupled to the node ND40 to receive the signal S40, and the source thereof is coupled to the base of the NMOS transistor N40. The base of the NMOS transistor N42 is coupled to the ground terminal T41.

When the core circuit 10 is in the normal operating mode, an operating voltage VDD is provided to the bond pad PAD 10, and the bond pad PAD11 is coupled to ground (eg, 0 volts (V)). At this time, the signal S40 on the node ND40 has a low voltage level, that is, the node ND40 has a low voltage to turn off the NMOS transistors N40 and N41. Inverter 41 The low voltage level signal S40 is inverted to generate a high voltage level signal S41 on the node ND41. In detail, the low voltage on the node ND40 turns off the NMOS transistor N43 and turns on the PMOS transistor P40. Therefore, the signal S41 on the node ND41 has a high voltage level, that is, the node ND41 has a high voltage to turn on the NMOS transistor N42. The substrate of the NMOS transistor N40 is pulled to the low voltage of the node ND40 through the turned-on NMOS transistor N42. As a result, the gate of the NMOS transistor N40 and the substrate are both at the same low voltage. Therefore, during normal operation of the core circuit 10, the NMOS transistor N40 can be stably turned off, which does not have any discharge path between the bonding pads PAD10 and PAD11 in the electrostatic discharge protection circuit 11, avoiding affecting the core circuit. 10 operations.

When the core circuit 10 is not in the normal operation mode, the operating voltage VDD is not supplied to the bonding pad PAD10. When an electrostatic discharge event occurs on the bonding pad PAD10, the voltage on the power supply terminal T40 instantaneously increases. At this time, based on the element characteristics of the capacitor C40, the signal S40 on the node ND40 has a high voltage level, that is, the node ND40 has a high voltage to turn on the NMOS transistors N40 and N41. The inverter 41 inverts the high voltage level signal S40 to generate a low voltage level signal S41 on the node ND41. In detail, the high voltage on the node ND40 turns off the PMOS transistor P40 and turns on the NMOS transistor N43. Therefore, the signal S21 on the node ND41 has a low voltage level, that is, the node ND41 has a low voltage to turn off the NMOS transistor N42. Due to the conduction of the NMOS transistor N41, there is a voltage difference between the gate and the source of the NMOS transistor N41 (that is, V _TH , that is, the threshold voltage of the NMOS transistor N41). According to the above, the gates of the NMOS transistors N40 and N41 are connected to each other through the node ND40, and the source of the NMOS transistor N41 is coupled to the base of the NMOS transistor N40. In other words, the NMOS transistor N40 has an NMOS transistor N41 between the gate of the NMOS transistor N40 and the substrate. Therefore, there is a voltage difference between the gate of the NMOS transistor N40 and the substrate, that is, the voltage (gate-base voltage, V _GB ) is not equal to zero. In this way, it is ensured that the NMOS transistor N40 can be turned on. Due to the conduction of the NMOS transistor N40, a discharge path is formed between the power supply terminal T40 and the ground terminal T41 (ie, between the bonding pads PAD10 and PAD11) to allow electrostatic charges on the bonding pad PAD10 to conduct through the discharge path. To the junction PAD11, thereby protecting the components within the core circuit 10 from electrostatic charges.

In one embodiment, the gate-matrix voltage of NMOS transistor N40 can be increased to accelerate its conduction. Therefore, the electrostatic discharge circuit 11 may further include one or more NMOS transistors serially connected to the NMOS transistor N41. Referring to FIG. 5, the electrostatic discharge circuit 11 further includes an NMOS transistor N50. The gate and the drain of the NMOS transistor N50 are both coupled to the source of the NMOS transistor N41, and the source thereof is coupled to the base of the NMOS transistor N40. The base of the NMOS transistor N50 is coupled to the ground terminal T41. In the architecture of FIG. 5, the source of the NMOS transistor N41 is coupled to the base of the NMOS transistor N40 through the NMOS transistor N50. In the fourth and fifth figures, elements having the same reference numerals have the same operations, and the description thereof will be omitted. In this embodiment, when the core circuit 10 is not in the normal operation mode and an electrostatic discharge event occurs on the bond pad PAD10, the NMOS transistors N41 and N50 are both turned on. At this time, the gate-substrate voltage V _GB of the NMOS transistor N40 in FIG. 5 is equal to twice the V _TH which is larger than the gate-base voltage V _GB of the NMOS transistor N40 in FIG. 4 (equal to V _TH ). Compared with the embodiment of Fig. 4, when an electrostatic discharge event occurs on the bonding pad PAD10, the NMOS transistor N40 of Fig. 5 can be turned on more quickly, i.e., the discharge path can be provided in a short time.

In the embodiment of Fig. 5, an NMOS transistor connected in series with the NMOS transistor N41 is taken as an example. In other embodiments, the number of NMOS transistors connected in series with the NMOS transistor N41 may depend on system requirements. When the number of NMOS transistors connected in series with the NMOS transistor N41 is larger, the gate-substrate voltage V _{GB of} the NMOS transistor N40 is larger, so that an electrostatic discharge event occurs on the bonding pad PAD10, and the NMOS transistor N40 is more Can be turned on faster.

In the above embodiment, the transistor used to form the electrostatic discharge path is exemplified by an NMOS transistor. In other embodiments, the electrostatic discharge path can be formed through the PMOS. Referring to Figure 6, there is shown an electrostatic discharge protection circuit in accordance with yet another embodiment of the present invention. Referring to FIG. 6, the ESD protection circuit 11 includes an ESD detection circuit 60, an inverter 61, a P-type Metal-Oxide-Semiconductor (PMOS) transistor P60-P62, and a power supply terminal T60. And the ground terminal T61. The power terminal T60 is coupled to the bonding pad PAD10, and the ground terminal T61 is coupled to the bonding pad PAD11. The electrostatic discharge detecting circuit 60 includes a resistor R60 and a capacitor C60 connected in series. The capacitor C60 is coupled between the power terminal T60 and the common node ND60. The resistor R60 is coupled between the common node ND60 and the ground terminal T61. There is a signal S60 on the common node ND60. The inverter 61 is coupled to the common node ND60 to receive the signal S60, and inverts the signal S60 to generate the signal S61 on the node ND61. The inverter 61 includes a PMOS transistor P63 and an NMOS transistor N60. The gate (control electrode end) of the PMOS transistor P63 is coupled to the common node ND60, the source (electrode end) is coupled to the power terminal T60, and the drain (electrode end) is coupled to the node ND61. The base and the source of the PMOS transistor P63 are coupled to each other. The gate of the NMOS transistor N60 is coupled to the common node ND60, the drain is coupled to the node ND61, and the source thereof is coupled to the ground terminal T61. The base and the source of the NMOS transistor N60 are coupled to each other. The gate of the PMOS transistor P60 is coupled to the node ND61 to receive the signal S61, which The source is coupled to the power terminal T60, and the drain is coupled to the ground terminal T61. The gate and the source of the PMOS transistor P61 are coupled to the node ND61, and the drain of the PMOS transistor P61 is coupled to the base of the PMOS transistor P60. The base of the PMOS transistor P61 is coupled to the power terminal T60. The gate of the PMOS transistor P62 is coupled to the node ND60 to receive the signal S60, the source thereof is coupled to the node ND61 to receive the signal S61, and the drain thereof is coupled to the base of the PMOS transistor P60. The base of the PMOS transistor P62 is coupled to the power terminal T60.

When the core circuit 10 is in the normal operating mode, an operating voltage VDD is provided to the bond pad PAD10, and the bond pad PAD11 is coupled to ground (eg, 0 volts (V)). At this time, the signal S60 on the node ND60 has a low voltage level, that is, the node ND60 has a low voltage. The inverter 61 inverts the low voltage level signal S60 to generate a high voltage level signal S61 on the node ND61. In detail, the low voltage on the node ND60 turns off the NMOS transistor N60 and turns on the PMOS transistor P63. Therefore, the signal S61 on the node ND61 has a high voltage level, that is, the node ND61 has a high voltage (equal to the operating voltage) to turn off the PMOS transistors P60 and P61. In addition, the low voltage on node ND60 turns on PMOS transistor P62. The substrate of the PMOS transistor P60 is pulled to the high voltage of the node ND61 through the turned-on PMOS transistor P62. As a result, the gate of the PMOS transistor P60 and the substrate are at the same high level. Therefore, during normal operation of the core circuit 10, the PMOS transistor P60 can be stably turned off, which does not have any discharge path between the bonding pads PAD10 and PAD11 in the electrostatic discharge protection circuit 11, avoiding affecting the core circuit. 10 operations.

When the core circuit 10 is not in the normal operation mode, the operating voltage VDD is not supplied to the bonding pad PAD10. When an electrostatic discharge event occurs on the bonding pad PAD10, the voltage on the power supply terminal T6O instantaneously increases. At this time, based on the element characteristics of the capacitor C60, the signal S60 on the node ND60 has a high voltage level, that is, the node ND60 has a high voltage to turn off the PMOS transistor P62. The inverter 61 inverts the high voltage level signal S60 to generate a low voltage level signal S61 on the node ND61. In detail, the high voltage on the node ND60 turns off the PMOS transistor P63 and turns on the NMOS transistor N60. Therefore, the signal S61 on the node ND61 has a low voltage level, that is, the node ND61 has a low voltage (equal to 0 V) to turn on the PMOS transistors P60 and P61. Due to the conduction of the PMOS transistor P61, there is a voltage difference between the gate and the drain of the PMOS transistor P61 (that is, V _TH , that is, the threshold voltage of the PMOS transistor P61). According to the above, the gates of the PMOS transistors P60 and P61 are connected to each other through the node ND61, and the drain of the PMOS transistor P61 is coupled to the base of the PMOS transistor P60. In other words, the PMOS transistor P60 has a PMOS transistor P61 between the gate and the substrate. Therefore, there is a voltage difference between the gate of the PMOS transistor P60 and the substrate, that is, the voltage (gate-base voltage, V _GB ) is not equal to zero. In this way, it is ensured that the PMOS transistor P60 can be turned on. Due to the conduction of the PMOS transistor P60, a discharge path is formed between the power supply terminal T60 and the ground terminal T61 (ie, between the bonding pads PAD10 and PAD11) to allow the electrostatic charge on the bonding pad PAD10 to conduct through the discharge path. To the junction PAD11, thereby protecting the components within the core circuit 10 from electrostatic charges.

In an embodiment, the gate-matrix voltage of the PMOS transistor P60 can be increased to accelerate conduction. Therefore, the electrostatic discharge circuit 11 further includes one or more PMOS transistors serially connected to the PMOS transistor P61. Referring to FIG. 7, the electrostatic discharge circuit 11 further includes a PMOS transistor P70. The gate and the source of the PMOS transistor P70 are both coupled to the drain of the PMOS transistor P61, and the drain of the PMOS transistor P70 is coupled to the base of the PMOS transistor P60. The base of the PMOS transistor P70 is coupled to the power terminal T60. In the architecture of FIG. 7, the drain of the PMOS transistor P61 is coupled to the base of the PMOS transistor P60 through the PMOS transistor P70. In the sixth and seventh figures, elements having the same reference numerals have the same operations, and the description thereof will be omitted. In this embodiment, when the core circuit 10 is not in the normal operation mode and an electrostatic discharge event occurs on the bond pad PAD10, the PMOS transistors P61 and P70 are both turned on. At this time, the voltage difference between the gate of the PMOS transistor P61 and the drain of the PMOS transistor P70 is twice _VTH . According to the above, the gates of the PMOS transistors P60 and P61 are connected to each other through the node ND61, and the drain of the PMOS transistor P70 is coupled to the base of the PMOS transistor P60. In other words, there are two PMOS transistors P61 and P70 between the gate of the PMOS transistor P60 and the substrate. Therefore, the gate-substrate voltage V _GB (equal to twice V _TH ) of the PMOS transistor P60 in FIG. 7 is larger than the gate-base voltage V _GB of the PMOS transistor P60 in FIG. 6 (equal to V _TH ). In comparison with the embodiment of Fig. 6, when an electrostatic discharge event occurs on the bonding pad PAD10, the PMOS transistor P60 of Fig. 7 can be turned on more quickly, i.e., the discharge path can be provided in a short time.

In the embodiment of Fig. 7, a PMOS transistor connected in series with the PMOS transistor P61 is taken as an example. In other embodiments, the number of PMOS transistors connected in series with the PMOS transistor P61 may depend on system requirements. When the number of PMOS transistors connected in series with the PMOS transistor P61 is larger, the gate-substrate voltage V _{GB of} the PMOS transistor P60 is larger, so that the electrostatic discharge event occurs on the bonding pad PAD10, the more the PMOS transistor P60 is. Can be turned on faster.

Figure 8 is a diagram showing an electrostatic discharge protection circuit in accordance with another embodiment of the present invention. In order to clearly show the circuit structure of the electrostatic discharge protection circuit 11, FIG. 8 only shows the electrostatic discharge protection circuit 11 and the bonding pad PAD10 and PAD11. Referring to FIG. 8, the ESD protection circuit 11 includes an ESD detection circuit 80, an inverter 81, PMOS transistors P80 to P82, a power supply terminal T80, and a ground terminal T81. The power terminal T80 is coupled to the bonding pad PAD10, and the ground terminal T81 is coupled to the bonding pad PAD11. The electrostatic discharge detecting circuit 80 includes a resistor R80 and a capacitor C80 connected in series. The resistor R80 is coupled to the power terminal T80 and the common node ND80. The capacitor C80 is coupled between the common node ND80 and the ground terminal T81. There is a signal S80 on the common node ND80. The inverter 81 is coupled to the common node ND80 to receive the signal S80, and inverts the signal S80 to generate the signal S81 on the node ND81. The inverter 81 includes a PMOS transistor P83 and an NMOS transistor N80. The gate (control electrode end) of the PMOS transistor P83 is coupled to the common node ND80, the source (electrode end) is coupled to the power terminal T80, and the drain (electrode end) is coupled to the node ND81. The base and the source of the PMOS transistor P83 are coupled to each other. The gate of the NMOS transistor N80 is coupled to the common node ND80, the drain is coupled to the node ND81, and the source thereof is coupled to the ground terminal T81. The base and the source of the NMOS transistor N80 are coupled to each other. The gate of the PMOS transistor P80 is coupled to the common node ND80 to receive the signal S80, the drain is coupled to the power terminal T80, and the source thereof is coupled to the ground terminal T81. The gate and the source of the PMOS transistor P81 are coupled to the common node ND80, and the drain of the PMOS transistor P81 is coupled to the base of the PMOS transistor P80. The base of the PMOS transistor P81 is coupled to the power terminal T80. The gate of the PMOS transistor P82 is coupled to the node ND81 to receive the signal S81, the source thereof is coupled to the node ND80 to receive the signal S80, and the drain thereof is coupled to the base of the PMOS transistor P80. The base of the PMOS transistor P82 is coupled to the power terminal T80.

When the core circuit 10 is in the normal operating mode, an operating voltage VDD is provided to the bond pad PAD10, and the bond pad PAD11 is coupled to ground (eg, 0 volts (V)). At this time, the signal S80 on the node ND80 has a high voltage level, that is, a section. Point ND80 has a high voltage to turn off PMOS transistors P80 and P81. The inverter 81 inverts the high voltage level signal S80 to generate a low voltage level signal S81 at the node ND81. In detail, the high voltage on the node ND80 turns off the PMOS transistor P83 and turns on the NMOS transistor N80. Therefore, the signal S81 on the node ND81 has a low voltage level, that is, the node ND81 has a low voltage to turn on the PMOS transistor P82. The substrate of the PMOS transistor P80 is pulled to the high voltage of the node ND80 through the turned-on PMOS transistor P82. As a result, the gate of the PMOS transistor P80 and the substrate are both at the same high voltage. Therefore, during normal operation of the core circuit 10, the PMOS transistor P80 can be stably turned off, which does not have any discharge path between the bonding pads PAD10 and PAD11 in the electrostatic discharge protection circuit 11, avoiding affecting the core circuit. 10 operations.

When the core circuit 10 is not in the normal operation mode, the operating voltage VDD is not supplied to the bonding pad PAD10. When an electrostatic discharge event occurs on the bonding pad PAD10, the voltage on the power supply terminal T80 instantaneously increases. At this time, based on the element characteristics of the capacitor C80, the signal S80 on the node ND80 has a low voltage level, that is, the node ND80 has a low voltage to turn on the PMOS transistors P80 and P81. The inverter 81 inverts the low voltage level signal S80 to generate a high voltage level signal S81 at the node ND81. In detail, the low voltage on the node ND80 turns off the NMOS transistor N80 and turns on the PMOS transistor P83. Therefore, the signal S81 on the node ND81 has a high voltage level, that is, the node ND81 has a high voltage to turn off the PMOS transistor P82. Due to the conduction of the PMOS transistor P81, there is a voltage difference between the gate and the drain of the PMOS transistor P81 (that is, V _TH , that is, the threshold voltage of the PMOS transistor P81). According to the above, the gates of the PMOS transistors P80 and P81 are connected to each other through the node ND80, and the drain of the PMOS transistor P81 is coupled to the base of the PMOS transistor P80. In other words, the PMOS transistor P80 has a PMOS transistor P81 between the gate and the substrate. Therefore, there is a voltage difference between the gate of the PMOS transistor P80 and the substrate, that is, the voltage (gate-base voltage, V _GB ) is not equal to zero. In this way, it is ensured that the PMOS transistor P80 can be turned on. Due to the conduction of the PMOS transistor P80, a discharge path is formed between the power supply terminal T80 and the ground terminal T81 (ie, between the bonding pads PAD10 and PAD11) to allow the electrostatic charge on the bonding pad PAD10 to conduct through the discharge path. To the junction PAD11, thereby protecting the components within the core circuit 10 from electrostatic charges.

In an embodiment, the gate-matrix voltage of the PMOS transistor P80 can be increased to accelerate its conduction. Therefore, the electrostatic discharge circuit 11 may further include one or more PMOS transistors serially connected to the PMOS transistor P90. Referring to FIG. 9, the electrostatic discharge circuit 11 further includes a PMOS transistor P90. The gate and the source of the PMOS transistor P90 are both coupled to the drain of the PMOS transistor P81, and the drain of the PMOS transistor P90 is coupled to the base of the PMOS transistor P80. The base of the PMOS transistor P90 is coupled to the power terminal T80. In the architecture of FIG. 9, the drain of the PMOS transistor P81 is coupled to the base of the PMOS transistor P80 through the PMOS transistor P90. In the eighth and ninth drawings, elements having the same reference numerals have the same operations, and the description thereof will be omitted. In this embodiment, when the core circuit 10 is not in the normal operation mode and an electrostatic discharge event occurs on the bond pad PAD10, the PMOS transistors P81 and P90 are both turned on. At this time, the gate-substrate voltage V _GB of the PMOS transistor P80 in FIG. 9 is equal to twice the V _TH which is larger than the gate-base voltage V _GB of the PMOS transistor P80 in FIG. 8 (equal to V _TH ). In comparison with the embodiment of Fig. 8, when an electrostatic discharge event occurs on the bonding pad PAD10, the PMOS transistor P80 of Fig. 9 can be turned on more quickly, i.e., the discharge path can be provided in a short time.

In the embodiment of Fig. 9, a PMOS transistor connected in series with the PMOS transistor P81 is taken as an example. In other embodiments, the number of PMOS transistors connected in series with the PMOS transistor P81 may depend on system requirements. When the number of PMOS transistors connected in series with the PMOS transistor P81 is larger, the gate-substrate voltage V _{GB of} the PMOS transistor P80 is larger, so that the electrostatic discharge event occurs on the bonding pad PAD10, the more the PMOS transistor P80 is. Can be turned on faster.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

11‧‧‧Electrostatic discharge protection circuit

20‧‧‧Electrostatic Discharge Detection Circuit

21‧‧‧Inverter

C20‧‧‧ capacitor

GND‧‧‧ Grounding

N20...N23‧‧‧NMOS transistor

ND20‧‧‧Common node

ND21‧‧‧ node

P20‧‧‧ PMOS transistor

PAD10, PAD11‧‧‧ joint pad

R20‧‧‧Resistors

S20, S21‧‧ signals

T20‧‧‧ power terminal

T21‧‧‧ grounding terminal

VDD‧‧‧ operating voltage

Claims (20)

An ESD protection circuit includes: a first MOS transistor coupled between a power terminal and a ground, and having a control electrode end coupled to a first node to receive a first signal; a second MOS transistor having a control electrode end coupled to the first node and a first electrode end, and a second electrode end having a base end coupled to the first MOS transistor; and a third gold An oxygen semi-transistor having a control electrode end coupled to a second node for receiving a second signal, a first electrode end coupled to the first node, and a base coupled to the base end of the first MOS transistor a second electrode end, wherein the first signal and the second signal are opposite to each other. The electrostatic discharge protection circuit of claim 1, further comprising: a fourth gold oxide semi-transistor coupled to the second electrode end of the second metal oxide semiconductor and the first gold oxide half Between the base ends of the crystal and having a control electrode end coupled to the second electrode end of the second MOS transistor. The electrostatic discharge protection circuit of claim 1, further comprising: a resistor and a capacitor connected in series between the power terminal and the ground, wherein the second node is interposed between the resistor and the resistor Between the capacitors, the second signal is generated at the second node; and an inverter receives the second signal and inverts the second signal to generate the first signal. The electrostatic discharge protection circuit of claim 3, wherein the first, second, and third MOS transistors are N-type MOS transistors: The resistor is coupled between the power terminal and the second node, and the capacitor is coupled between the second node and the ground. The electrostatic discharge protection circuit of claim 3, wherein the first, second, and third MOS transistors are P-type MOS transistors: and the capacitor is coupled to the power terminal And the second node, and the resistor is coupled between the second node and the ground. The electrostatic discharge protection circuit of claim 3, further comprising: a fourth gold-oxygen semi-transistor coupled to the second electrode end of the second gold-oxygen semiconductor and the first gold-oxygen semi-electric Between the base ends of the crystal and having a control electrode end coupled to the second electrode end of the second MOS transistor. The electrostatic discharge protection circuit of claim 1, further comprising: a resistor and a capacitor connected in series between the power terminal and the ground, wherein the first node is between the resistor and Between the capacitors, the first signal is generated at the first node; and an inverter receives the first signal and inverts the first signal to generate the second signal. The electrostatic discharge protection circuit of claim 7, wherein the first, second, and third MOS transistors are N-type MOS transistors: and the capacitor is coupled to the power terminal And the first node, and the resistor is coupled between the first node and the ground. The electrostatic discharge protection circuit of claim 7, wherein the first, second, and third MOS transistors are P-type MOS transistors: And the resistor is coupled between the power terminal and the first node, and the capacitor is coupled between the first node and the ground. The electrostatic discharge protection circuit of claim 7, further comprising: a fourth gold oxide semi-transistor coupled to the second electrode end of the second gold-oxygen semiconductor and the first gold-oxygen semi-electric Between the base ends of the crystal and having a control electrode end coupled to the second electrode end of the second MOS transistor. An integrated circuit includes: a core circuit coupled between a first bonding pad and a second bonding pad; and an electrostatic discharge protection circuit coupled to the first bonding pad, wherein when the first bonding The electrostatic discharge protection circuit provides a discharge path between the first bonding pad and a second bonding pad to protect the core circuit when an electrostatic discharge event occurs on the pad; wherein the electrostatic discharge protection circuit includes: a MOS transistor coupled between the first bonding pad and the second bonding pad, and having a control electrode end coupled to a first node to receive a first signal; a second MOS half-electric a crystal having a control electrode end coupled to the first node and a first electrode end, and a second electrode end having a base end coupled to the first MOS transistor; and a third MOS semi-transistor having a control electrode end coupled to a second node to receive a second signal, a first electrode end coupled to the first node, and And a second electrode end coupled to the base end of the first MOS transistor, wherein the first signal and the second signal are opposite to each other. The integrated circuit of claim 11, further comprising: a fourth MOS transistor, coupled to the second electrode end of the second MOS transistor and the first MOS transistor Between the base ends and a control electrode end coupled to the second electrode end of the second MOS transistor. The integrated circuit of claim 11, further comprising: a resistor and a capacitor connected in series between the first bonding pad and the second bonding pad, wherein the second node contacts the resistor Between the capacitor and the capacitor, the second signal is generated at the second node; and an inverter receives the second signal and inverts the second signal to generate the first signal. The integrated circuit of claim 13, wherein the first, second, and third MOS transistors are N-type MOS transistors: and the resistor is coupled to the first Between the bonding pad and the second node, and the capacitor is coupled between the second node and the second bonding pad. The integrated circuit of claim 13, wherein the first, second, and third MOS transistors are P-type MOS transistors: and the capacitor is coupled to the first bond Between the pad and the second node, and the resistor is coupled between the second node and the second bonding pad. The integrated circuit of claim 13, further comprising: a fourth oxy-halide transistor coupled to the second electrode end of the second MOS transistor and the first MOS transistor Between the base ends and a control electrode end coupled to the second electrode end of the second MOS transistor. The integrated circuit of claim 11, further comprising: a resistor and a capacitor connected in series between the first bonding pad and the second bonding pad, wherein the first node is between Between the resistor and the capacitor, the first signal is generated at the first node; and an inverter receives the first signal and inverts the first signal to generate the second detection. The integrated circuit of claim 17, wherein the first, second, and third MOS transistors are N-type MOS transistors: and the capacitor is coupled to the first bond The pad is coupled to the first point, and the resistor is coupled between the common first point and the second bonding pad. The integrated circuit of claim 17, wherein the first, second, and third MOS transistors are P-type MOS transistors: and the resistor is coupled to the first bond The pad is coupled to the first node, and the capacitor is coupled between the common first point and the second bonding pad. The integrated circuit of claim 17, further comprising: a fourth oxy-halide transistor coupled to the second electrode end of the second MOS transistor and the first MOS transistor Between the base ends and a control electrode end coupled to the second electrode end of the second MOS transistor.