CN116845842A - Protection circuit - Google Patents

Abstract

A protection circuit. The protection circuit is coupled to a bonding pad and comprises a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor and a second transistor coupled in series between the pad and a ground terminal and having a first conductivity type. The trigger circuit detects whether a transient event occurs on the bond pad. The discharging circuit is coupled between the welding pad and the grounding end and is controlled by the trigger circuit. When a transient event occurs on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the bonding pad and the ground terminal.

Description

Protection circuit

Technical Field

The present application relates to a protection circuit, and more particularly, to a protection circuit with high voltage tolerance and capable of providing a discharge path rapidly.

Background

With the development of semiconductor processes for integrated circuits, the semiconductor device size has been reduced to sub-micron level to improve the performance and operation speed of the integrated circuits. However, the reduction in device size results in semiconductor devices that are susceptible to large current damage caused by voltage spikes. Therefore, when a large current/large voltage occurs on a pad (pad) for input/output to which an integrated circuit is coupled in an extremely short time, a protection circuit capable of stably providing a discharge path in response to the large current/large voltage is required. For example, electrostatic discharge (Electrostatic Discharge, ESD) protection circuits, transient voltage suppressors (Transient Voltage Suppressor, TVS) or other protection devices or circuits may provide a discharge path to protect semiconductor devices from high currents. Therefore, the discharge performance (i.e., protection capability) of such a protection device or circuit is important.

Disclosure of Invention

In view of this, the present application proposes a protection circuit. The protection circuit is coupled to a pad (pad) and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor and a second transistor coupled in series between the pad and a ground terminal and having a first conductivity type. The trigger circuit detects whether a transient event occurs on the bond pad. The discharging circuit is coupled between the welding pad and the grounding end and is controlled by the trigger circuit. When a transient event occurs on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the bonding pad and the ground terminal.

Drawings

Fig. 1 shows a protection circuit according to an embodiment of the application.

Fig. 2 shows a protection circuit according to another embodiment of the application.

Fig. 3A and 3B are schematic diagrams illustrating the operation of the protection circuit of fig. 2.

Fig. 4 shows a protection circuit according to another embodiment of the application.

Fig. 5 shows a parasitic NPN bipolar junction transistor in the protection circuit of fig. 4.

Fig. 6 shows a protection circuit according to another embodiment of the application.

Fig. 7A and 7B are schematic diagrams illustrating the operation of the protection circuit of fig. 6.

Fig. 8 shows a protection circuit according to another embodiment of the application.

Fig. 9 shows a parasitic NPN bipolar junction transistor in the protection circuit of fig. 8.

Fig. 10A shows an electronic circuit according to an embodiment of the application with a protection circuit according to any of the embodiments of the application.

Fig. 10B shows an electronic circuit according to another embodiment of the application with a protection circuit according to any of the embodiments of the application.

Reference numerals:

1,1A,1B,1C,1D protection circuit

10 trigger circuit

11 discharge circuit

12 welding pad (pad)

13A,13B electronic device

20,21,23: NMOS transistors

22 resistor

40 NPN Bipolar Junction Transistor (BJT)

60,61,63: NMOS transistors

62 resistor

80 NPN Bipolar Junction Transistor (BJT)

100 core circuit

1000 electronic component or circuit

600,610,630 drain (first electrode terminal)

601,611,631 Source (second electrode terminal)

602,612,632 grid electrode (control electrode terminal)

633 base electrode

GND ground terminal

N20, N21, N60: nodes

P30 discharge path

R30, R31, R60, R61, internal resistance of conduction

V30, V60 trigger voltage

VCC, VDD supply voltage

Detailed Description

In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Fig. 1 shows a protection circuit according to an embodiment of the application. Referring to fig. 1, fig. 1 shows a pad (pad) 12 in addition to a protection circuit 1 for the sake of detailed description. As shown in fig. 1, the protection circuit 1 is coupled to the bonding pad 12 and includes a trigger circuit 10 and a discharge circuit 11. The trigger circuit 10 and the discharge circuit 11 are coupled between the pad 12 and the ground GND.

When the protection circuit 1 operates in a normal operation mode, a supply voltage is supplied to the pads 12. At this time, the trigger circuit 10 controls the discharge circuit 11 not to provide any discharge path between the pad 12 and the ground GND. When the protection circuit 1 is not operated in the normal operation mode, the pad 12 does not receive any supply voltage. At this time, the trigger circuit 10 detects whether a transient event occurs on the pad 12. When detecting whether a transient event occurs on the pad 12, the trigger circuit 10 generates a signal or voltage to control or trigger the discharge circuit 11 to provide a discharge path between the pad 12 and the ground GND.

In this embodiment, the transient event may be an event involving a large voltage or a large current. For example, the transient event may be an electrostatic discharge (Electrostatic Discharge, ESD) event or a surge (charge) event. In an embodiment, the protection circuit 1 may be an electrostatic discharge (Electrostatic Discharge, ESD) protection circuit, a transient voltage suppressor (Transient Voltage Suppressor, TVS).

Fig. 2 shows a protection circuit according to another embodiment of the application. The protection circuit 1 of fig. 1 may be implemented as the protection circuit 1A of fig. 2. Referring to fig. 2, the trigger circuit 10 of the protection circuit 1A may include transistors 20 and 21 and a resistor 22. Transistors 20 and 21 have the same conductivity type and each has three electrode terminals, a first electrode terminal, a second electrode terminal, and a control electrode terminal, respectively. In this embodiment, the transistors 20 and 21 are implemented as N-type Metal-Oxide-Semiconductor (NMOS) transistors, i.e., the conductivity types of the transistors 20 and 21 are N-type. The first electrode terminal, the second electrode terminal, and the control electrode terminal of each of the transistors 20 and 21 are the drain, the source, and the gate of the NMOS transistor, respectively. As shown in fig. 2. The drain (first electrode terminal) 200 of the NMOS transistor 20 is coupled to the pad 12, the source (second electrode terminal) 201 is coupled to the node N20, and the gate (control electrode terminal) 202 is coupled to the node N21. The drain 210 of the NMOS transistor 21 is coupled to the node N20, the source 211 is grounded GND, and the gate 212 is coupled to the node N21. According to the above connection structure, the NMOS transistors 20 and 21 are serially coupled between the pad 12 and the ground GND. The resistor 22 is coupled between the node N21 and the ground GND.

As shown in fig. 2, the discharge circuit 11 includes a transistor 23. The transistor 23 has three electrode terminals, a first electrode terminal, a second electrode terminal, and a control electrode terminal, respectively. In this embodiment, the transistor 23 is also implemented as an NMOS transistor. The first electrode terminal, the second electrode terminal, and the control electrode terminal of the transistor 23 are the drain, the source, and the gate of the NMOS transistor 23, respectively. The drain 230 of the NMOS transistor 23 is coupled to the pad 12, the source 231 thereof is grounded GND, and the gate 232 thereof is coupled to the node N20. According to the above connection structure, the NMOS transistor 23 is also coupled between the pad 12 and the ground GND.

In the embodiment of the present application, the withstand voltage of the NMOS transistor 23 is higher than those of the NMOS transistors 20 and 21. In one example, the NMOS transistors 20 and 23 are high voltage tolerant transistors, and the NMOS transistor 23 has a higher voltage withstand than the NMOS transistor 20. For example, the NMOS transistor 20 is a transistor with a voltage withstand of 20V (volts), the NMOS transistor 21 is a transistor with a voltage withstand of 5V, and the NMOS transistor 23 is a transistor with a voltage withstand of 24V, but the application is not limited thereto.

In one embodiment, NMOS transistors 20 and 23 may be implemented as high voltage tolerant transistors by increasing the size (e.g., thickness, lateral diffusion distance) of the doped region of their drains.

In one embodiment, the channel width of NMOS transistors 20 and 21 is approximately several hundred micrometers (um), while the channel width of NMOS transistor 23 is approximately 100-150 kilomicrometers (kum). Resistor 22 has a resistance value in the range of about 1 to 10 kiloohms (kohm).

The detailed operation of the protection circuit 1A will be described below.

Referring to fig. 3A, when the protection circuit 1A operates in a normal operation mode, a supply voltage VDD is supplied to the pad 12. In this embodiment, the supply voltage VDD is, for example, a voltage of 24V. At this time, since the resistor 22 is coupled between the node N21 and the ground GND, the voltage at the node N21 is at a low level with respect to the supply voltage VDD, i.e. the voltages at the gates 202 and 212 of the NMOS transistors 20 and 21 are both at a low level. Based on the low level voltages on gates 202 and 212, NMOS transistors 20 and 21 are both turned off. In fig. 3A and subsequent figures, the turned-OFF transistor will be indicated by "(OFF)". Since both NMOS transistors 20 and 21 are turned OFF, the voltage on node N20 is at a low level with respect to the supply voltage VDD, i.e., the voltage on gate 232 of NMOS transistor 23 is at a low level, which turns NMOS transistor 23 OFF (OFF).

As can be seen from the above, in the normal operation mode, all NMOS transistors coupled between the pad 12 and the ground GND in the protection circuit 1A are turned off. In other words, the protection circuit 1A intercepts any discharge path between the pad 12 and the ground GND. Therefore, in the normal operation mode, the protection circuit 1A does not cause unnecessary leakage current, and the arrangement of the protection circuit 1A is prevented from causing unnecessary power consumption.

Referring to fig. 3B, in the case where the protection circuit 1A is not in the normal operation mode, the supply voltage VDD is not supplied to the pad 12, i.e., the pad 12 is in the floating state, or the voltage of the pad 12 is equal to 0V. When a transient event (e.g., an ESD event or a surge event) occurs on the bond pad 12, the voltage of the bond pad 12 increases instantaneously. The drain 200 and gate 202 of transistor 20 have parasitic capacitance therebetween, which forms an RC circuit with resistor 22. The voltage on node N21 increases instantaneously with the voltage of pad 12 through the coupling effect of parasitic capacitance between drain 200 and gate 202. At this time, in response to the momentary increase of the voltage on the node N21, the NMOS transistors 20 and 21 are turned on momentarily. In fig. 3B and subsequent figures, the turned-ON transistor will be indicated by "(ON)".

Due to the conduction of the NMOS transistors 20 and 21, the NMOS transistors 20 and 21 each have the conduction internal resistances R30 and R31. The conductive internal resistances R30 and R31 form a voltage divider. The voltage divider divides the voltage difference between the pad 12 and the ground GND to generate the trigger voltage V30 at the node N20. The trigger voltage V30 generated by the voltage dividing operation has a high level voltage to turn ON (ON) the NMOS transistor 23. Therefore, a discharging path P30 is formed between the pad 12 and the ground GND, so that the charge of the large current accompanied by the transient event on the pad 12 is conducted to the ground GND through the discharging path P30.

According to the above, when a transient event occurs on the pad 12, the trigger circuit 10 can rapidly generate the high-level trigger voltage V30 through the operation of the NMOS transistors 20 and 21 and the resistor 22 to trigger the discharge circuit 11 to provide the discharge path P30, so that a large amount of charges on the pad 12 can rapidly be conducted to the ground GND through the discharge path P30, thereby protecting the devices in other circuits coupled to the pad 12 from being damaged by large currents.

In the embodiment of fig. 2, although not shown in fig. 2, the base (bulk) of NMOS transistor 23 may be connected to its source 231.

Fig. 4 shows a protection circuit according to another embodiment of the application. The protection circuit 1 of fig. 1 may be implemented as the protection circuit 1B of fig. 4. The circuit architecture of the protection circuit 1B of fig. 4 is substantially the same as that of the protection circuit 1A of fig. 2. Referring to fig. 4, the difference between the protection circuits 1B and 1A is the base (bulk) 233 of the NMOS transistor 23. Base 233 of NMOS transistor 23 is coupled to node N21, i.e., base 233 is coupled to gates 202 and 212 of NMOS transistors 20 and 21.

Since the circuit architecture of the protection circuit 1B of fig. 4 and 5 is substantially the same as that of the protection circuit 1A of fig. 2, the operation of the protection circuit 1B is also substantially the same as that of the protection circuit 1A, and the above description about fig. 3A and 3B can be referred to. Hereinafter, the same operations will be omitted, and only the operation of the NMOS transistor 23 will be specifically described.

Referring to fig. 4, the drain 230, the source 231, and the base 233 of the nmos transistor 23 form a parasitic NPN bipolar junction transistor (bipolar junction transistor, BJT) 40.NMOS transistor 23The drain 230, the source 231, and the base 233 serve as the collector (C), the emitter (E), and the base (B) of the NPN BJT 40, respectively. When the protection circuit 1B operates in a normal operation mode, the voltage on the node N21 is at a low level with respect to the supply voltage VDD. Based on the low voltage on node N21 and the source 231 coupled to ground GND, NPN BJT 40 turns off. In the case where the protection circuit 1B is not in the normal operation mode and a transient event occurs on the pad 12, since the voltage on the node N21 has a high level, the base-emitter voltage (V _BE ) Greater than 0.7V, which renders NPN BJT 40 conductive. At this time, the charge of the large current associated with the transient event on the pad 12 is also conducted to the ground GND through the turned-on NPN BJT 40.

According to the above, in the protection circuit 1B of fig. 4, the base 233 of the NMOS transistor 23 is coupled to the node N21. Therefore, when a transient event occurs on the pad 12, the parasitic NPN BJT 40 is turned on rapidly in response to the high level voltage of the node N21, thereby improving the overall discharging capability of the NMOS transistor 23.

Fig. 6 shows a protection circuit according to another embodiment of the application. The protection circuit 1 of fig. 1 may be implemented as the protection circuit 1C of fig. 6. Referring to fig. 6, the trigger circuit 10 of the protection circuit 1C may include transistors 60 and 61 and a resistor 62. The transistors 60 and 61 have the same conductivity type, and each has three electrode terminals, a first electrode terminal, a second electrode terminal, and a control electrode terminal, respectively. In this embodiment, the transistors 60 and 61 are both implemented as NMOS transistors, i.e., the conductivity types of the transistors 60 and 61 are N-type. The first electrode terminal, the second electrode terminal, and the control electrode terminal of each of the transistors 60 and 61 are the drain, the source, and the gate of the NMOS transistor, respectively. As shown in fig. 6. The drain 600 of the NMOS transistor 60 is coupled to the pad 12, and the source 601 is coupled to the node N60. The drain 610 of the NMOS transistor 61 is coupled to the node N60, the source 611 is grounded GND, and the gate 612 is coupled to the power terminal T60. According to the above connection structure, the NMOS transistors 60 and 61 are serially coupled between the pad 12 and the ground GND. Resistor 62 is coupled between gate 602 of NMOS transistor 60 and node N60.

As shown in fig. 6, the discharge circuit 11 includes a transistor 63. The transistor 63 has three electrode terminals, a first electrode terminal, a second electrode terminal, and a control electrode terminal, respectively. In this embodiment, the transistor 63 is also implemented as an NMOS transistor. The first electrode terminal, the second electrode terminal, and the control electrode terminal of the transistor 63 are the drain, the source, and the gate of the NMOS transistor 63, respectively. The drain 630 of the NMOS transistor 63 is coupled to the pad 12, the source 631 is grounded GND, and the gate 632 is coupled to the node N60. According to the above connection structure, the NMOS transistor 63 is also coupled between the pad 12 and the ground GND.

In the embodiment of the present application, the withstand voltage of the NMOS transistor 63 is higher than those of the NMOS transistors 60 and 61. In one example, the NMOS transistors 60 and 63 are high voltage tolerant transistors, and the NMOS transistor 63 has a higher voltage withstand than the NMOS transistor 60. For example, the NMOS transistor 60 is a transistor having a withstand voltage of 20V (volts), the NMOS transistor 61 is a transistor having a withstand voltage of 5V, and the NMOS transistor 63 is a transistor having a withstand voltage of 24V.

In one embodiment, the NMOS transistors 60 and 63 may be implemented as high voltage tolerant transistors by increasing the size of the doped region of their drains (e.g., the vertical doping depth or the lateral diffusion distance), but the application is not limited thereto.

In one embodiment, the channel width of NMOS transistors 60 and 61 is approximately several hundred micrometers (um), while the channel width of NMOS transistor 63 is approximately 100-150 kilomicrometers (kum). Resistor 62 has a resistance value in the range of about 1 to 10 kiloohms (kohm).

The detailed operation of the protection circuit 1C will be described below.

Referring to fig. 7A, when the protection circuit 1C is operated in a normal operation mode, one supply voltage VDD is provided to the pad 12 and the other supply voltage VCC is provided to the power terminal T60. In this embodiment, the supply voltage VDD is, for example, 24V, and the supply voltage VCC is, for example, 5V. At this time, since the supply voltage VCC of 5V is supplied to the gate 612 of the NMOS transistor 61 through the power supply terminal T60, the NMOS transistor 61 is always in the ON state (ON). The voltage on node N60 is at a low level with respect to the supply voltage VDD by the turned-on NMOS transistor 61, i.e., the voltage on the gate 632 of the NMOS transistor 63 is at a low level. Based on the low level voltage on the gate 632, the NMOS transistor 63 turns OFF (OFF). In addition, the voltage of the gate 602 is at a low level with respect to the supply voltage VDD by the resistor 62 coupled between the gate 602 of the NMOS transistor 60 and the node N60. Based on the low level voltage of the gate 602, the NMOS transistor 60 is turned OFF (OFF).

As can be seen from the above, in the normal operation mode, the NMOS transistors 60 and 63 coupled between the pad 12 and the ground GND in the protection circuit 1C are turned off. In other words, the protection circuit 1C intercepts any discharge path between the pad 12 and the ground GND. Therefore, in the normal operation mode, the protection circuit 1C does not cause unnecessary leakage current, and the arrangement of the protection circuit 1C is prevented from causing unnecessary power consumption.

Referring to fig. 7B, in the case that the protection circuit 1C is not in the normal operation mode, the supply voltage VDD is not supplied to the bonding pad 12, and the supply voltage VCC is not supplied to the power terminal T60, i.e. the bonding pad 12 and/or the power terminal T60 are in the floating state, or the voltage of the bonding pad 12 and/or the power terminal T60 is equal to 0V. When a transient event (e.g., an ESD event or a surge event) occurs on the bond pad 12, the voltage of the bond pad 12 increases instantaneously. The drain 600 and gate 602 of transistor 60 have parasitic capacitance therebetween, which forms an RC circuit with resistor 62. The voltage at the gate 602 of the NMOS transistor 60 increases instantaneously with the voltage at the pad 12 by the coupling effect of the parasitic capacitance between the drain 600 and the gate 602. At this time, the NMOS transistor 60 is turned ON (ON) in response to the momentary increase in the voltage of the gate 602. Further, since the power supply terminal T60 is in a floating state or the voltage of the power supply terminal T60 is equal to 0v, the nmos transistor 61 is in a fully-ON state or a weakly-ON state (ON).

Due to the conduction of the NMOS transistors 60 and 61, the NMOS transistors 60 and 61 each have the conduction internal resistances R60 and R61. The conductive internal resistances R60 and R61 form a voltage divider. The voltage divider divides the voltage difference between the pad 12 and the ground GND to generate the trigger voltage V60 at the node N60. The trigger voltage V60 generated by the voltage dividing operation has a high level voltage to turn on the NMOS transistor 63. Therefore, a discharging path P60 is formed between the pad 12 and the ground GND, so that the charge of the large current associated with the transient event on the pad 12 is conducted to the ground GND through the discharging path P60.

According to the above, when a transient event occurs on the pad 12, the trigger circuit 10 can rapidly generate the high-level trigger voltage V60 through the operation of the NMOS transistors 60 and 61 and the resistor 62 to trigger the discharge circuit 11 to provide the discharge path P60, so that a large amount of charges on the pad 12 can rapidly be conducted to the ground GND through the discharge path P60, thereby protecting the devices in other circuits coupled to the pad 12 from being damaged by large currents.

In the embodiment of fig. 6, although not shown in fig. 6, the base of NMOS transistor 63 may be connected to its source 631.

Fig. 8 shows a protection circuit according to another embodiment of the application. The protection circuit 1 of fig. 1 may be implemented as the protection circuit 1D of fig. 8. The circuit architecture of the protection circuit 1D of fig. 8 is substantially the same as that of the protection circuit 1C of fig. 6. Referring to fig. 8, the difference between the protection circuits 1D and 1C is the base (bulk) 633 of the NMOS transistor 63. The base 633 of the NMOS transistor 63 is coupled to the node N60, i.e., the base 633 is coupled to the gate 632 of the NMOS transistor 63.

Since the circuit architecture of the protection circuit 1D of fig. 8 is substantially the same as that of the protection circuit 1C of fig. 6, the operation of the protection circuit 1D is also substantially the same as that of the protection circuit 1C, and the above description about fig. 7A and 7B can be referred to. Hereinafter, the same operations will be omitted, and only the operation of the NMOS transistor 63 will be specifically described.

Referring to fig. 8 and 9, the drain 630, source 631, and base 633 of the nmos transistor 63 form a parasitic NPN Bipolar Junction Transistor (BJT) 80. The drain 630, source 631, and base 633 of the NMOS transistor 63 serve as the collector (C), emitter (E), and base (B) of the NPN BJT 80, respectively. When the protection circuit 1D operates in a normal operation mode, the voltage on the node N60 is at a low level with respect to the supply voltage VDD. NPN BJT based on the low voltage on the node N60 and the source 631 coupled to the ground GND80 is turned off. In the case where the protection circuit 1D is not in the normal operation mode and a transient event occurs on the pad 12, since the trigger voltage V60 on the node N60 has a high level, the base-emitter voltage (V _BE ) Greater than 0.7V, which turns on NPN BJT 80. At this time, the charge of the large current associated with the transient event on the pad 12 is also conducted to the ground GND through the turned-on NPN BJT 80.

According to the above, in the protection circuit 1D of fig. 8, the base 633 of the NMOS transistor 63 is coupled to the node N60. Therefore, when a transient event occurs on the pad 12, the parasitic NPN BJT 80 can be turned on rapidly in response to the high level voltage of the node N60, thereby improving the overall discharging capability of the NMOS transistor 63.

Fig. 10A shows an electronic circuit according to an embodiment of the application. Referring to fig. 10A, the electronic device 13A includes a core circuit 100, a pad 12, and the protection circuit 1 shown in fig. 1. The protection circuit 1 may be implemented by any of the protection circuits 1A to 1D shown in fig. 2, 4, 6, and 8. In the embodiment of fig. 10A, the protection circuit 1 is arranged outside the core circuit 100. When an transient event occurs in the pad 12, the protection circuit 1 provides or triggers a discharge path between the pad 12 and the ground GND. The large amount of charge on the pad 12 can quickly be conducted to ground GND through the discharge path, thereby protecting the components or circuits within the core circuit 100 from the large currents associated with transient events.

In other embodiments, the protection circuit 1 may be provided inside the core circuit 100. As shown in fig. 10B, the protection circuit 1 and other electronic components or circuits 1000 are provided in the core circuit 100 of the electronic device 13B. When an transient event occurs in the pad 12, the protection circuit 1 provides or triggers a discharge path between the pad 12 and the ground GND. The large amount of charge on the pad 12 can quickly be conducted to the ground GND through the discharge path, thereby protecting the electronic components or circuits 1000 within the core circuit 100 from the large currents associated with transient events.

Although the application has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this application.

Claims (15)

1. A protection circuit, coupled to a pad, comprising:

a trigger circuit including a first transistor and a second transistor coupled in series between the pad and a ground terminal and having a first conductivity type, wherein the trigger circuit detects whether a transient event occurs on the pad; and

the discharging circuit is coupled between the welding pad and the grounding end and is controlled by the trigger circuit;

when the transient event occurs on the welding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the welding pad and the grounding terminal.

2. The protection circuit of claim 1, wherein the first transistor and the second transistor are both turned on when the transient event occurs on the pad.

3. The protection circuit of claim 1, wherein the discharge circuit comprises a third transistor of the first conductivity type coupled between the pad and the ground.

4. A protection circuit according to claim 3, wherein the first conductivity type is N-type.

5. A protection circuit according to claim 3, characterized in that:

the trigger circuit further comprises a resistor;

the first transistor is provided with a first electrode terminal coupled with the welding pad, a second electrode terminal coupled with a first node and a control electrode terminal coupled with a second node;

the second transistor is provided with a first electrode terminal coupled with the first node, a second electrode terminal coupled with the grounding terminal and a control electrode terminal coupled with the second node;

the third transistor is provided with a first electrode terminal coupled with the welding pad, a second electrode terminal coupled with the grounding terminal and a control electrode terminal coupled with the first node, and the trigger voltage is generated at the first node; and

the resistor is coupled between the second node and the ground.

6. The protection circuit of claim 5, wherein the third transistor further has a base, and wherein the base of the third transistor is coupled to the second node.

7. The protection circuit of claim 5 or 6, wherein the first transistor, the second transistor, and the third transistor are turned off when a supply voltage is received on the pad.

8. A protection circuit according to claim 3, characterized in that:

the trigger circuit further comprises a resistor;

the first transistor is provided with a first electrode terminal coupled with the welding pad, a second electrode terminal coupled with a first node and a control electrode terminal;

the second transistor is provided with a first electrode terminal coupled with the first node, a second electrode terminal coupled with the grounding terminal and a control electrode terminal coupled with a power supply terminal;

the third transistor is provided with a first electrode terminal coupled with the welding pad, a second electrode terminal coupled with the grounding terminal and a control electrode terminal coupled with the first node, and the trigger voltage is generated at the first node; and

the resistor is coupled between the control electrode terminal of the first transistor and the first node.

9. The protection circuit of claim 8, wherein the third transistor further has a base, and wherein the base of the third transistor is coupled to the first node.

10. The protection circuit of claim 8 or 9, wherein the first transistor and the third transistor are turned off and the second transistor is turned on when a first supply voltage is received on the pad and a second supply voltage is received at the power supply terminal.

11. The protection circuit of claim 10, wherein the first supply voltage is greater than the second supply voltage.

12. The protection circuit of claim 3, wherein the first transistor, the second transistor, and the third transistor are all turned on when the transient event occurs on the pad.

13. A protection circuit according to claim 3, wherein the third transistor has a higher withstand voltage than the first transistor and the second transistor.

14. The protection circuit according to claim 1, wherein a withstand voltage level of the first transistor is higher than a withstand voltage level of the second transistor and the second transistor.

15. The protection circuit of claim 1, wherein the protection circuit is a transient voltage suppressor.