TWI817701B - Semiconductor structure and the method for forming the same - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate including a trench between active regions, a tunneling dielectric layer disposed on the substrate, a floating gate disposed on the tunneling dielectric layer, an isolation feature, which has a first opening and a second opening below the first opening, disposed in the trench and on the substrate, mask disposed on the sidewall of the first opening, and a dielectric stack layer disposed directly above the mask and the second opening.

Description

Semiconductor structures and methods of forming them

The present disclosure relates to a semiconductor structure, and in particular to a flash memory.

As the size of semiconductor components continues to shrink, many challenges arise. For example, in flash memory, control of device dents is important for device reliability. For example, when forming openings between floating gates, due to process shrinkage, the depth of the openings formed by the etching process becomes difficult to control, which will result in subsequent formation positions of the control gates being different, and the etching process may cause floating gates to form. The loss of the gate electrode will lead to a decrease in reliability and yield. Therefore, the industry still needs to improve the structure and formation method of flash memory to overcome the problems caused by shrinking device size.

Embodiments of the present invention provide a semiconductor structure, including a substrate including trenches between a plurality of active regions; a tunnel dielectric layer disposed on the substrate; and a floating gate layer disposed on the tunnel dielectric layer. ;Isolation components arranged in the trench and on the substrate, The isolation component has a first opening and a second opening located below the first opening; a mask disposed on the side wall of the first opening; and a dielectric stack layer disposed directly above the mask and directly above the second opening. .

Embodiments of the present invention provide a method for forming a semiconductor structure, which includes sequentially forming a tunnel dielectric layer, a floating gate layer, an oxide layer, and a capping layer on a substrate; forming a trench on the substrate, the tunnel dielectric layer, and the floating gate layer. in the gate layer, oxide layer and cap layer; forming an isolation component in the trench; using the cap layer as an etching mask to etch the isolation component to form the first opening; forming a plurality of masks on the side walls of the first opening and the first opening. on a portion of the bottom of an opening; using a plurality of masks as etching masks to etch the isolation component to form a second opening; and forming a dielectric stack layer directly above the plurality of masks and directly above the second opening.

100:Substrate

110: Tunnel dielectric layer

200: Floating gate layer

210:Oxide layer

300: cover

400:Isolation components

400T:Trench

500: Mask layer

500’:mask

600:Sacrificial layer

600’:Sacrificial piece

700: Dielectric stack layer

800: Control gate layer

1000: Etching process

1100:Deposition process

1200: Etching process

1300: Etching process

1400: Etching process

AA: active area

T500, T600: Width

O1: Open your mouth

O2:Open your mouth

W1: Width

W2: Width

1-8 are schematic cross-sectional views illustrating different stages of forming a semiconductor structure according to some embodiments of the present invention.

9-10 are schematic cross-sectional views showing different stages of forming a semiconductor structure according to other embodiments of the present invention.

1-8 are schematic cross-sectional views illustrating different stages of forming a semiconductor structure according to some embodiments of the present invention.

Referring to Figure 1, a substrate 100 is provided. The substrate 100 may be an element semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a carbonized substrate. Silicon substrate, gallium arsenide substrate, gallium phosphide substrate, indium phosphide substrate, indium arsenide substrate and/or indium antimonide substrate; or alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and /or a combination of the above. In some embodiments, the semiconductor substrate 100 may be a semiconductor-on-insulator substrate.

Continuing to refer to FIG. 1 , a tunnel dielectric layer 110 , a floating gate layer 200 , an oxide layer 210 and a capping layer 300 are formed on the substrate 100 .

The tunnel dielectric layer 110 may include oxide, nitride, oxynitride, or a combination of the foregoing. In one embodiment, the tunnel dielectric layer 110 may be silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination of the foregoing. High dielectric constant materials can be metal oxides, metal nitrides, metal silicides, transition metal oxides, transition metal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, zirconosilicates, Zircoaluminate. In one embodiment, the tunnel dielectric layer 110 may be formed by a deposition process or a thermal oxidation process. The aforementioned deposition process may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other suitable processes.

The floating gate layer 200 may include conductive materials, such as doped or undoped polycrystalline silicon, amorphous silicon, metal, metal nitride, conductive metal oxide, or combinations thereof, and its formation method may include, for example, CVD, PVD , ALD, sputtering, resistance heating evaporation, electron beam evaporation or other suitable processes.

The oxide layer 210 may include, for example, tetraethoxysilane (TEOS), and its formation method may include, for example, CVD, PVD, ALD, or other suitable processes. capping layer 300 may include nitride, such as silicon nitride, and its formation method may include, for example, CVD, PVD, ALD, or other suitable processes. The oxide layer 210 and the capping layer 300 can serve as protective layers to protect the floating gate layer 200 from loss during the subsequent etching process.

Continuing to refer to FIG. 1 , isolation components 400 are formed between the active areas AA of the substrate 100 . Specifically, a trench 400T is formed in the substrate 100, the tunnel dielectric layer 110, the floating gate layer 200, the oxide layer 210 and the capping layer 300, and the isolation component 400 is formed in the trench 400T. In one embodiment, the active area AA can be defined by the isolation component 400 . The isolation component 400 may include a dielectric material, which may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, fluorosilicate glass, undoped silicon glass, organic Silicate glass, SiO _x C _y , spin-on glass, tetraethoxysilane, low-k dielectric materials, or combinations thereof.

In one embodiment, the trench 400T can be formed by first etching the capping layer 300, the floating gate layer 200, the tunneling dielectric layer 110, and the substrate 100 through an anisotropic dry etching process, and then through a process similar to The above-mentioned deposition process deposits the isolation component material, and then removes excess isolation component material through a planarization process or an etching process to form the isolation component 400 . In one embodiment, the capping layer 300 and the isolation component 400 may include nitride (such as silicon nitride) and oxide (such as spin-on glass), respectively. In one embodiment, the top surface of the isolation component 400 is flush with the top surface of the cover layer 300 . The aforementioned etching process may include, for example, a dry or wet etching process. The aforementioned planarization process may include chemical mechanical polishing.

Referring to FIG. 2 , the upper part of the isolation component 400 is etched through the etching process 1000 to form the opening O1 . In one embodiment, the bottom surface of the opening O1 is formed higher than the top surface of the tunnel dielectric layer 110 . In one embodiment, the opening O1 has Width W1. In one embodiment, the etching process 1000 includes an anisotropic dry etching process.

Next, referring to Figure 3-5, a mask 500' is formed on the side wall of the opening O1 and a part of the bottom of the opening O1.

Specifically, as shown in FIG. 3 , the mask layer 500 and the sacrificial layer 600 are compliantly formed through a deposition process 1100 . That is, the mask layer 500 and the sacrificial layer 600 are sequentially formed along the top surface of the cover layer 300, the bottom surface and side walls of the opening O1. Mask layer 500 may include nitride, such as silicon nitride. Sacrificial layer 600 may include an oxide, such as a high temperature oxide or silicon oxide. In one embodiment, the mask layer 500 and the sacrificial layer 600 can be formed through CVD, PVD, ALD, or other suitable processes. In a specific embodiment, compared to forming the sacrificial layer 600 through a CVD process, which results in excessive thickness at the corners, forming the sacrificial layer 600 through an ALD process can form a more uniform thickness profile at the corners.

As shown in Figure 3, the mask layer 500 has a width T500, and the sacrificial layer 600 has a width T600. In one embodiment, the width T600 can be used to control the width of the subsequently formed second opening (Fig. 6), and further control whether to set an air gap between adjacent active areas (refer to Figs. 8 and 10).

Next, as shown in FIG. 4 , the lateral portion of the sacrificial layer 600 is removed through the etching process 1200 to form a plurality of sacrificial members 600' on the sidewalls of the opening O1. In detail, the sacrificial layer 600 on the top surface of the cover layer 300 and the top surface of the isolation component 400 is removed to leave a plurality of sacrificial pieces 600' on the side walls of the opening O1. In one embodiment, the etching process 1200 includes an anisotropic dry etching process with etch selectivity.

Next, as shown in FIG. 5, the lateral portion of the mask layer 500 is removed through the etching process 1300 to form a plurality of masks 500' on the side walls of the opening O1. In detail, the mask layer 500 that is not covered by the sacrificial layer 600' (ie, the mask layer 500 on the cover layer 300 and the mask layer 500 on the isolation component 400 and between the sacrificial component 600') is removed, so as to A plurality of masks 500' are left on the side walls of the opening O1. In one embodiment, the capping layer 300 and the oxide layer 210 are further removed through the etching process 1300 . In one embodiment, the top surface of the mask 500' is no higher than the top surface of the floating gate layer 200 to ensure that the mask layer 500 between the sacrificial members 600' can be cut off to expose the underlying isolation components. 400. In one embodiment, the mask 500' is L-shaped, which not only serves as an etching mask for subsequent formation of openings, but also protects the sidewalls of the floating gate layer 200 from being lost in the subsequent etching process.

In one embodiment, the etching process 1300 includes an isotropic wet etching process with etch selectivity, which etch the mask layer 500 , the capping layer 300 and the oxide layer without substantially etching the floating gate layer 200 210. In another embodiment, the etching process 1300 includes an anisotropic dry etching process and an isotropic wet etching process with etching selectivity. Specifically, the mask layer 500 between the sacrificial members 600' can be cut off first by dry etching, and the mask layer 500 on the floating gate layer 200 can be removed, and then the capping layer can be removed by dry etching or wet etching. 300, and then remove the oxide layer 210 through a dry etching process. This prevents lateral etching. It should be noted that due to the effects of wet etching, the top surface of the mask 500 may be slightly lower than the top surface of the floating gate layer 200 . The wet etching process may include a phosphoric acid (H ₃ PO ₄ ) solution and the dry etching process may include a halogenated hydrocarbon etchant (eg, CF ₄ , CHF ₃ , CH ₂ F ₂ , etc.).

Next, as shown in FIG. 6 , using the mask 500 as an etching mask, the isolation component 400 is etched through the etching process 1400 to form the opening O2 . Furthermore, in one embodiment, the sacrificial member 600' may be removed during the etching of the isolation component 400, or may be removed before or after the isolation component 400 is etched. In some embodiments, the bottom surface of the opening O2 is lower than the bottom surface of the tunnel dielectric layer 110 . In other words, as shown in FIG. 6 , the bottom of the opening O2 extends downward to between two adjacent active areas AA. In one embodiment, the width W2 of the opening O2 is smaller than the width W1 of the first opening (W2<W1).

In one embodiment, the etching process 1400 includes an isotropic wet etching process with etching selectivity, such as buffered hydrofluoric acid, dilute hydrofluoric acid solution, etc. Compared with using a dry etching process, using a wet etching process can prevent plasma from attacking the floating gate layer 200 .

In one embodiment, since the sacrificial member 600' and the isolation member 400 both include oxide, and the mask 500' includes nitride, the etching process 1400 can simultaneously remove the sacrificial member without substantially removing the mask 500'. 600' and part of the isolation component 400, thereby reducing process complexity. In one embodiment, since the opening O1 is formed by a dry etching process and the opening O2 is formed by a wet etching process, the width W1 of the opening O1 does not substantially change toward the substrate 100 in the normal direction of the substrate 100 , and the width of the opening O2 decreases toward the substrate 100 . Furthermore, in one embodiment, the opening O1 is square (with corners), and the opening O2 is arc-shaped (or bowl-shaped).

Next, referring to FIG. 7 , a dielectric stack layer 700 is compliantly formed on the substrate 100 . In detail, the dielectric stack layer 700 covers the floating gate 200, shields Cover 500', and isolation member 400 exposed in opening O2. The dielectric stack 700 may include a single-layer structure or a multi-layer structure, for example, may be only silicon nitride or silicon oxide, or may also be an oxide-nitride-oxide structure or an oxide-nitride-oxide- Nitride structure. In one embodiment, a method of forming the dielectric stack layer 700 may include, for example, CVD, PVD, ALD, or other suitable processes.

Next, referring to FIG. 8 , the control gate layer 800 is comprehensively formed on the dielectric stack layer 700 . The control gate layer 800 may include a conductive material similar to that described above, such as polysilicon, and its formation method may include, for example, CVD, PVD, ALD, or other suitable processes.

9-10 are schematic cross-sectional views showing different stages of forming a semiconductor structure according to other embodiments of the present invention.

Continuing from FIG. 6 , the structure of FIG. 9 is generally similar to that of FIG. 7 , except that the dielectric stack layer 700 is suspended above the opening O2 . That is, the dielectric stack layer 700 covers the floating gate 200 and the mask 500', but does not cover the isolation component 400 exposed in the opening O2. Therefore, an air gap G is provided in the opening O2, and the air gap G is between the dielectric stack layer 700 and the isolation component 400. In one embodiment, by setting an air gap G in the isolation component 400 between two adjacent active areas AA, the interference between adjacent active areas can be further reduced. In one embodiment, due to stress effects, the dielectric stack layer 700 between the two masks 500' is dish-shaped, that is, the two sides are higher than the middle.

Next, similar to the embodiment of FIG. 8 , a control gate layer 800 is formed on the dielectric stack layer 700 to obtain the semiconductor structure as shown in FIG. 10 .

In summary, compared with the previous single opening formed only by a dry etching process or only a wet etching process, according to embodiments of the present invention, by forming an oxide on the top of the floating gate layer , cover layer, and form a mask on the side wall of the floating gate layer, and form two openings in segments, which can reduce the loss of the floating gate layer during the etching process, and can better control the overall opening ( The outline of the two openings) and the uniformity of all openings ensure the subsequent control of the position of the gate layer formation and improve the reliability of the structure. Furthermore, according to embodiments of the present invention, by forming openings extending to adjacent active areas, the dielectric stack layer can be further extended to adjacent active areas, thereby reducing operational interference between adjacent active areas. In addition, an embodiment of the present invention can further reduce the operational interference of adjacent active areas and improve the reliability of the structure by setting an air gap at the opening.

100:Substrate

110: Tunnel dielectric layer

200: Floating gate layer

400:Isolation parts

500’:mask

700: Dielectric stack layer

O1: Open your mouth

O2:Open your mouth

Claims (13)

A semiconductor structure includes: a substrate including a trench between a plurality of active regions; a tunneling dielectric layer disposed on the substrate; and a floating gate layer disposed on the tunneling dielectric on the layer; an isolation component disposed in the trench and on the substrate, wherein the isolation component has a first opening and a second opening located below the first opening; a mask disposed on the first opening The side walls and bottom of the shield are L-shaped; and a dielectric stack layer is disposed directly above the shield and directly above the second opening. The semiconductor structure of claim 1, wherein a bottom surface of the second opening is lower than a bottom surface of the tunnel dielectric layer. The semiconductor structure of claim 1, wherein in the normal direction of the substrate, the width of the first opening does not substantially change toward the substrate, and the width of the second opening decreases toward the substrate. The semiconductor structure of claim 1, wherein an air gap is provided in the second opening, wherein the air gap is between the isolation component and the dielectric stack layer. The semiconductor structure of claim 1, wherein the dielectric stack layer is suspended above the second opening. The semiconductor structure of claim 1, wherein the dielectric stack layer is disposed on the side surface and the bottom surface of the first opening and the side surface and the bottom surface of the second opening. A method for forming a semiconductor structure, including: sequentially forming a tunnel dielectric layer, a floating gate layer, an oxide layer and a capping layer on a substrate; forming a trench on the substrate, the tunnel dielectric forming an isolation component in the trench in the electrical layer, the floating gate layer, the oxide layer, and the cap layer; etching the isolation component using the cap layer as an etching mask to form a first opening; Forming a plurality of masks on the sidewalls of the first opening and a portion of the bottom of the first opening; etching the isolation component using the masks as etching masks to form a second opening; and forming a dielectric The layers are stacked directly above the masks and directly above the second opening. The method of forming a semiconductor structure as claimed in claim 7, wherein the step of forming the first opening includes using a dry etching process, and wherein the step of forming the second opening includes using a wet etching process. As in the method of forming a semiconductor structure according to claim 7, the steps of forming the masks include: sequentially forming a mask layer and a sacrificial layer along the sidewall and bottom surface of the first opening; and sequentially removing the sacrificial layer. The transverse portion and the transverse portion of the mask layer are used to form a plurality of sacrificial members and a plurality of masks on the side walls of the first opening respectively; and the sacrificial members are removed. The method of forming a semiconductor structure according to claim 9, wherein the step of removing the lateral portion of the sacrificial layer includes etching the sacrificial layer through an anisotropic dry etching process. The method of forming a semiconductor structure as claimed in claim 9, wherein the step of removing the lateral portion of the mask layer includes etching the mask layer not covered by the sacrificial members through a wet etching process. The method of forming a semiconductor structure as claimed in claim 7, wherein the step of forming the first opening includes exposing sidewalls of the floating gate layer but not exposing sidewalls of the tunnel dielectric layer. The method of forming a semiconductor structure as claimed in claim 7, wherein before forming the second opening, the method further includes: removing the capping layer and the oxide layer.

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