TWI817588B - A pixel circuit with a biological identification function - Google Patents

Abstract

Disclosed is a pixel circuit with a biological identification function that is arranged on an array substrate. The array substrate has a pixel array composed of a plurality of rows of pixels and a plurality of rows of pixels. The pixel circuit with a biological identification function is characterized in that: every two adjacent row pixels share one scan line; every two adjacent row pixels share one storage capacitor; and every two adjacent row pixels share one reset line.

Description

Pixel circuit with biometric identification function

The present invention relates to a pixel circuit, and in particular, to a pixel circuit with a biometric recognition function.

In the prior art, the pixel array and pixel circuit of the fingerprint recognition device have different designs according to different functions. FIG. 1 is a schematic diagram of a pixel circuit with a fingerprint recognition function in the prior art. FIG. 2 is a schematic diagram of a pixel circuit with a fingerprint recognition function in the prior art. FIG. 3 is a schematic diagram of a pixel array with fingerprint recognition function in the prior art. FIG. 4 is a schematic diagram of a pixel with a fingerprint recognition function in the prior art. Usually, each column of pixels or row of pixels has its own electronic components or wiring. For example, in the pixel circuit 100 shown in FIG. 1 , column pixel N has a scanning line S_N, a reset line RST_N, and a storage capacitor. C1_N, storage capacitor C2_N, transistor T1_N, transistor T2_N, transistor T3_N, transistor T4_N, ground VP, sampling switch, diode D_N, piezoelectric material 10, communication output TRX_N and readout line; column pixel N +1 There are scan line S_N+1, reset line RST_N+1, storage capacitor C1_N+1, storage capacitor C2_N+1, transistor T1_N+1, transistor T2_N+1, transistor T3_N+1, transistor T4_N+ 1. Ground VP, sampling switch, diode D_N+1, piezoelectric material 10, communication output TRX_N+1 and readout lines. In addition, as shown in FIG. 2 , the pixel circuit 200 includes a scanning line S_N, a scanning line S_N+1, a storage capacitor C, a transistor DT, a piezoelectric material 20, a transistor M1, a transistor T4_N, a ground VP, Diode D1, communication output TRX_N and readout line.

In addition, Figure 3 corresponds to Figure 1, taking a 2*2 pixel array 100' as an example. Column pixel N and column pixel N+1 each have two pixels, and each pixel has a sensing area 103a, 103b, 103c, and 103d respectively correspond to the components and wiring in Figure 1. In addition, Figure 4 corresponds to Figure 2, taking a 1*1 pixel array 200' as an example. The pixel array 200' has a sensing area 230, a scanning line S_N, a scanning line S_N+1, a via hole Via_1, and a via hole Via_2. I won’t go into details here.

However, as application functions increase and circuits become increasingly complex, the required circuits increase, resulting in a larger unlocking area and improved unlocking accuracy. This requires more pixel circuits to be designed as shared circuits.

To sum up, how to provide a fingerprint identification device that can meet the above requirements is a problem that the industry needs to solve.

In view of the above, one aspect of the present disclosure provides a pixel circuit 1000 with a biometric recognition function, which is configured on an array substrate. The array substrate has a pixel array composed of a plurality of columns of pixels and a plurality of rows of pixels. The pixel circuit with biometric identification function is characterized by: every two adjacent columns of pixels share a scan line; every two adjacent columns of pixels share a storage capacitor; and every two adjacent columns of pixels share a Reset line.

According to one or more embodiments of the present disclosure, a first communication output and a second communication output of the two adjacent columns retrieve data from the common scan line through the shared storage capacitor, and the shared reuse Setting the line resets the storage capacitor.

According to one or more embodiments of the present disclosure, a first communication output and a second communication output of the two adjacent columns store a sampling potential through the shared storage capacitor at different times, and the shared scanning potential is line to retrieve data, and the shared reset line resets the storage capacitor.

According to one or more embodiments of the present disclosure, a first sampling switch and a second sampling switch of the two adjacent columns perform fingerprint recognition driving of the two adjacent columns.

According to one or more embodiments of the present disclosure, a first sampling switch and a second sampling switch in two adjacent columns have a switching on function in a wiring area outside a sensing area.

According to one or more embodiments of the present disclosure, the two adjacent columns further include: two diodes, each having a first terminal and a second terminal; two first transistors, each having a control terminal. , a first terminal and a second terminal, wherein each control terminal of the first transistors is electrically coupled to the common reset line, and each first terminal of the first transistors is electrically connected respectively. is coupled to a D-Bias and each first terminal of each diode, and each second terminal of the first transistors is electrically coupled to each second terminal of each diode; a second transistor having a control terminal, a first terminal and a second terminal, wherein the first terminal of the second transistor is grounded; a third transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is electrically coupled to the scan line and a first terminal of the shared storage capacitor, and the first terminal of the third transistor is electrically coupled to the The second terminal of the second transistor, and the second terminal of the third transistor are electrically coupled to a voltage readout line; a first storage capacitor having a first terminal and a second terminal; a first Two storage capacitors have a first terminal and a second terminal; two fourth transistors respectively have a control terminal, a first terminal and a second terminal, wherein the respective control terminals are electrically coupled to different Sampling switch; the first terminal of the fourth transistor is electrically coupled to the control terminal of the second transistor, and the second terminal of the fourth transistor is electrically coupled to the first storage capacitor. The first terminal, the second terminal of the first transistor and the second terminal of the diode; the first terminal of the other fourth transistor is electrically coupled to the common storage a second terminal of the capacitor, and The second terminal of the fourth transistor is electrically coupled to the first terminal of the second storage capacitor, the second terminal of the other first transistor, and the second terminal of the other diode; A fifth piezoelectric material has a first end and a second end, wherein the first end of the fifth piezoelectric material is electrically coupled to the second end of the first storage capacitor, and the fifth piezoelectric material The second end of the electrical material is electrically coupled to a first communication output; and a sixth piezoelectric material has a first end and a second end, wherein the first end of the sixth piezoelectric material is electrically coupled The second end of the second storage capacitor is connected to the second end of the fifth piezoelectric material, and the second end of the fifth piezoelectric material is electrically coupled to a second communication output.

According to one or more embodiments of the present disclosure, the shared scan line and the shared reset line of the shared storage capacitor are located in one of the two adjacent columns of pixels.

According to one or more embodiments of the present disclosure, the light-transmitting area of the corresponding pixel in another column of pixels has a larger light-transmitting area than that of one of the column of pixels.

According to one or more embodiments of the present disclosure, the common reset line is located between the two adjacent columns of pixels.

According to one or more embodiments of the present disclosure, the common reset line is located outside the sensing areas of the two adjacent columns of pixels.

100: Pixel circuit

N: column of pixels

S_N: scan line

RST_N: reset line

C1_N: storage capacitor

C2_N: storage capacitor

T1_N: Transistor

T2_N: Transistor

T3_N: Transistor

T4_N: transistor

VP: ground

D_N: diode

10: Piezoelectric materials

TRX_N: Communication output

N+1: column of pixels

S_N+1: scan line

RST_N+1: reset line

C1_N+1: storage capacitor

C2_N+1: storage capacitor

T1_N+1: transistor

T2_N+1: transistor

T3_N+1: transistor

T4_N+1: transistor

D_N+1: Diode

TRX_N+1: Communication output

200:Pixel circuit

S_N+1: scan line

C: storage capacitor

DT: Transistor

20: Piezoelectric materials

M1: transistor

T4_N: Transistor

D1: Diode

TRX_N: Communication output

100’: pixel array

103a, 103b, 103c, 103d: sensing area

200’: Pixel array

230: Sensing area

Via_1, Via_2: via holes

1000: Pixel circuit

1000’: pixel array

S22:Scan line

RST22: reset line

C22: storage capacitor

T22: transistor

T33: transistor

I, II, III, IV: Area

D: Diode

T1: the first transistor

T2: Second transistor

T3: The third transistor

Vout(Rx): voltage readout line

C1_N: first storage capacitor

C1_N+1: second storage capacitor

T4A, T4B: the fourth transistor

A, B: Sampling switch

1010: The fifth piezoelectric material

TRX_N: first communication output

1010: The sixth piezoelectric material

TRX_N+1: Second communication output

In order to make the above and other objects, features, advantages and embodiments of the present invention easier to understand, the accompanying drawings are described as follows:

FIG. 1 is a schematic diagram of a pixel circuit with a fingerprint recognition function in the prior art.

FIG. 2 is a schematic diagram of a pixel circuit with a fingerprint recognition function in the prior art.

FIG. 3 is a schematic diagram of a pixel array with fingerprint recognition function in the prior art.

FIG. 4 is a schematic diagram of a pixel with a fingerprint recognition function in the prior art.

FIG. 5 is a schematic diagram of a pixel array with biometric recognition function according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a pixel circuit with biometric recognition function according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a pixel array with biometric recognition function according to an embodiment of the present invention.

FIG. 8 is a schematic diagram illustrating the configuration of a sampling switch according to an embodiment of the present invention.

In accordance with common practice, the various features and components in the figures are not drawn to actual scale, but are drawn in a manner intended to best present the specific features and components relevant to the present invention. In addition, the same or similar element symbols are used to refer to similar elements and components between different drawings.

In order to facilitate the review committee to have a further understanding of the purpose, shape, structural device characteristics and functions of the present invention, the detailed description is as follows with reference to the embodiments and drawings.

The following disclosure provides different embodiments or examples to achieve different features of the provided subject matter. The specific examples of components and arrangements described below are for simplifying the present disclosure and are not intended to be limiting; the size and shape of the components are not limited by the disclosed range or numerical value, but may depend on the process conditions of the components or the required requirements. characteristic. For example, cross-sectional views are used to describe the technical features of the present invention, and these cross-sectional views are schematic diagrams of idealized embodiments. Therefore, variations in the shapes shown in the illustrations due to manufacturing processes and/or tolerances are to be expected and should not be limited thereby.

Furthermore, spatially relative terms such as "below", "below", "below", "above" and "above" are used to easily describe what is in the diagram. between depicted elements or features In addition, spatially relative terms include the different orientations of components in use or operation in addition to the directions depicted in the illustrations.

First, please refer to FIGS. 5 to 6 . FIG. 5 is a schematic diagram of a pixel array with biometric recognition function according to an embodiment of the present invention. FIG. 6 is a schematic diagram of a pixel circuit with biometric recognition function according to an embodiment of the present invention. FIG. 7 is a schematic diagram of a pixel array with biometric recognition function according to an embodiment of the present invention.

As shown in Figure 5, in one embodiment of the present invention, a pixel circuit 1000 with a biometric recognition function is configured on an array substrate (not shown). The array substrate is composed of a plurality of columns of pixels and a plurality of rows of pixels. A pixel array. In FIGS. 5 and 6 , only column N (or N-th column) and column N+1 (or N+1-th column) are used to illustrate the pixel circuit 1000 and pixels with biometric recognition function in the present invention. The array 1000' is not used to limit the present invention. The value of N is a natural number and can be determined according to design requirements.

It should be noted here that, compared with the prior art of FIGS. 1 and 3 , the pixel circuit with biometric recognition function disclosed in the embodiment of the present invention has two adjacent columns of pixels in each group. Because of a scan line, a storage capacitor and a reset line, the sensing area of one column of pixels in each group of two adjacent columns of pixels that was originally supposed to be configured with the scan line, storage capacitor and reset line becomes transparent. The light area, that is, increases the light-transmitting area of the light-transmitting area in the column of pixels. Next, the detailed description is as follows using Figure 5, Figure 6 and Figure 7:

As shown in FIG. 6 , the pixel circuit 1000 with biometric recognition function in an embodiment of the present invention is characterized in that: every two adjacent columns of pixels N and N+1 share a scanning line S22; every two adjacent columns The pixels share a storage capacitor C22; and every two adjacent columns of pixels share a reset line RST22. This point can be clearly seen in the corresponding pixel array 1000' shown in Figure 5. If you refer to Figure 1 and Figure 3 at the same time, you can know that the scan line S_N+1, the reset line RST_N+1, the storage capacitor C2_N+1, and even the transistor T2_N+1 and the transistor originally configured for the pixel N+1 T3_N+1, in the present invention of Figures 5 to 7 They are omitted in the embodiment, and the scanning line S22, the reset line RST22, the storage capacitor C22, the transistor T22 and the transistor T33 are shared with the adjacent column of pixels N. If we further compare FIG. 3 with FIG. 7 , also looking at the pixel column N+1, the pixel array 1000' according to the embodiment of the present invention is significantly improved because the regions III and IV of the pixel column N+1 become light-transmitting regions. Increase the light transmission area of the light transmission area. As shown in Figures 5 and 7, the scan line S_N+1, the reset line RST_N+1, the storage capacitor C2_N+1, and even the transistor T2_N+1 and the transistor T3_N+1 that should have been configured in areas III and IV, All are replaced by the scan line S22, the reset line RST22, the storage capacitor C22, the transistor T22 and the transistor T33 corresponding to area I and area II in the pixel N+1, that is, the adjacent pixels N and pixels in the column N+1. N+1 shares the scan line S22, the reset line RST22, the storage capacitor C22, the transistor T22 and the transistor T33. For example, in the embodiment of the present invention, when N is 1, each pixel in the adjacent column 1 and 2 will share a set of scan lines S22, reset lines RST22, and storage capacitors C22. , transistor T22 and transistor T33; each pixel of adjacent column pixel 3 and column 4 will share a set of scan line S22, reset line RST22, storage capacitor C22, transistor T22 and transistor T33; And so on.

Next, please refer to Figure 5 and Figure 6 again. The two adjacent columns N and N+1 further include: two diodes D having a first end and a second end respectively; two first transistors T1 , respectively having a control terminal, a first terminal and a second terminal, wherein each control terminal of the first transistors T1 is electrically coupled to the common reset line RST22, and the first transistors T1 Each first terminal of T1 is electrically coupled to a D-Bias and each first terminal of each diode D, and each second terminal of the first transistors T1 is electrically coupled to each Each second terminal of the diode D.

As shown in FIG. 5 and FIG. 6 , the two adjacent columns N and N+1 further include: a second transistor T2 having a control terminal, a first terminal and a second terminal, wherein the second transistor T2 The first terminal of the third transistor T3 is grounded; a third transistor T3 has a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor T3 is electrically coupled to the scan line S22 and the a first terminal of shared storage capacitor C22, and the The first terminal of the third transistor T3 is electrically coupled to the second terminal of the second transistor T2, and the second terminal of the third transistor T3 is electrically coupled to a voltage readout line Vout(Rx ).

As shown in Figure 5 and Figure 6, the two adjacent columns N and N+1 further include: a first storage capacitor C1_N having a first terminal and a second terminal; a second storage capacitor C1_N+1 having A first terminal and a second terminal; two fourth transistors T4A and T4B respectively have a control terminal, a first terminal and a second terminal, wherein the respective control terminals are electrically coupled to different sampling switches. A, B; the first terminal of the fourth transistor T4A is electrically coupled to the control terminal of the second transistor T2, and the second terminal of the fourth transistor T4A is electrically coupled to the control terminal of the second transistor T2. The first terminal of a storage capacitor C1_N, the second terminal of the first transistor T1 and the second terminal of the diode D; the first terminal of the other fourth transistor T4B is electrically coupled to a second terminal of the common storage capacitor C22, and the second terminal of the fourth transistor T4B is electrically coupled to the first terminal of the second storage capacitor C1_N+1 and the other third terminal. The second terminal of a transistor T1 and the second terminal of the other diode D.

As shown in FIG. 5 and FIG. 6 , the two adjacent columns N and N+1 further include: a fifth piezoelectric material 1010 having a first end and a second end, wherein the fifth piezoelectric material 1010 has a first end and a second end. The first terminal is electrically coupled to the second terminal of the first storage capacitor C1_N, and the second terminal of the fifth piezoelectric material 1010 is electrically coupled to a first communication output TRX_N; and a sixth piezoelectric The material 1010 has a first end and a second end, wherein the first end of the sixth piezoelectric material 1010 is electrically coupled to the second end of the second storage capacitor C1_N+1, and the fifth piezoelectric material 1010 has a first end and a second end. The second end of the electrical material 1010 is electrically coupled to a second communication output TRX_N+1.

In one embodiment of the present invention, the common scan line S22 and the common reset line RST22 of the common storage capacitor C22 are located in one of the two adjacent columns of pixels N and N+1.

In one embodiment of the present invention, compared with one of the rows of pixels N, the light-transmitting area of the corresponding pixel in the other row of pixels N+1 has a larger light-transmitting area.

In an embodiment of the present invention, the common reset line RST22 is located between the two adjacent columns of pixels N and N+1.

In one embodiment of the present invention, the common reset line RST22 is located outside the sensing areas of the two adjacent columns of pixels N and N+1.

In one embodiment of the present invention, the first communication output TRX and the second communication output TRX of the two adjacent columns retrieve data from the common scan line S22 through the shared storage capacitor C22, and the shared re-circulation Setting RST22 resets the storage capacitor.

In one embodiment of the present invention, the first communication output TRX and the second communication output TRX of the two adjacent columns store a sampling potential through the shared storage capacitor C22 at different times, and the shared scanning line S22 retrieves data, and the shared reset line RST22 resets the storage capacitor.

In one embodiment of the present invention, the sampling switch A and the sampling switch B of the two adjacent columns are driven for fingerprint recognition of the two adjacent columns.

In addition, as shown in FIG. 8 , in one embodiment of the present invention, the sampling switch A and the sampling switch B in the two adjacent columns have the function of switching on in a wiring area outside a sensing area.

The above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced. without departing from the spirit and scope of the technical solution of the present invention.

1000: Pixel circuit

S22:Scan line

RST22: reset line

C22: storage capacitor

T22: transistor

T33: transistor

D: Diode

T1: the first transistor

Vout(Rx): voltage readout line

C1_N: first storage capacitor

C1_N+1: second storage capacitor

T4A, T4B: the fourth transistor

A, B: Sampling switch

1010: The fifth piezoelectric material

TRX_N: first communication output

TRX_N+1: Second communication output

1010: The fifth piezoelectric material

Claims (9)

A pixel circuit with a biometric recognition function is configured on an array substrate. The array substrate has a pixel array composed of a plurality of columns of pixels and a plurality of rows of pixels. The pixel circuit with a biometric recognition function is characterized by: Every two adjacent columns of pixels share a scan line; every two adjacent columns of pixels share a storage capacitor; and every two adjacent columns of pixels share a reset line; the two adjacent columns further include: Two diodes respectively have a first terminal and a second terminal; two first transistors respectively have a control terminal, a first terminal and a second terminal, wherein each of the first transistors The control terminals are electrically coupled to the common reset line, and each first terminal of the first transistors is electrically coupled to a D-Bias and each first terminal of each diode, And each second terminal of the first transistors is electrically coupled to each second terminal of each diode; a second transistor has a control terminal, a first terminal and a second terminal. , wherein the first terminal of the second transistor is grounded; a third transistor has a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is electrically coupled to the A scan line and a first terminal of the shared storage capacitor, and the first terminal of the third transistor is electrically coupled to the second terminal of the second transistor, and the second terminal of the third transistor The terminal is electrically coupled to a voltage readout line; a first storage capacitor has a first terminal and a second terminal; A second storage capacitor has a first terminal and a second terminal; two fourth transistors have a control terminal, a first terminal and a second terminal respectively, wherein the respective control terminals are electrically coupled to Different sampling switches; the first terminal of the fourth transistor is electrically coupled to the control terminal of the second transistor, and the second terminal of the fourth transistor is electrically coupled to the first storage The first end of the capacitor, the second end of the first transistor and the second end of the diode; the first end of the other fourth transistor is electrically coupled to the common a second terminal of the storage capacitor, and the second terminal of the fourth transistor is electrically coupled to the first terminal of the second storage capacitor, the second terminal of the other first transistor and the other the second end of the diode; a fifth piezoelectric material having a first end and a second end, wherein the first end of the fifth piezoelectric material is electrically coupled to the first storage capacitor the second end, and the second end of the fifth piezoelectric material is electrically coupled to a first communication output; and a sixth piezoelectric material has a first end and a second end, wherein the sixth piezoelectric material The first terminal of the piezoelectric material is electrically coupled to the second terminal of the second storage capacitor, and the second terminal of the fifth piezoelectric material is electrically coupled to a second communication output. The pixel circuit with biometric recognition function as described in claim 1, wherein a first communication output and a second communication output of the two adjacent columns retrieve data from the shared scan line through the shared storage capacitor, The shared reset line resets the storage capacitor. The pixel circuit with biometric recognition function as described in claim 1, wherein a first communication output and a second communication output of the two adjacent columns store a sampling potential through the shared storage capacitor at different times, Data is retrieved from the shared scan line, and the shared reset line resets the storage capacitor. The pixel circuit with biometric identification function as described in claim 1, wherein a first sampling switch and a second sampling switch of the two adjacent columns drive fingerprint identification of the two adjacent columns. The pixel circuit with biometric recognition function as described in claim 1, wherein a first sampling switch and a second sampling switch in the two adjacent columns have a switching on function in a wiring area outside a sensing area. The pixel circuit with biometric recognition function as described in claim 1, wherein the shared scan line and the shared reset line of the shared storage capacitor are located in one of the two adjacent columns of pixels. The pixel circuit with biometric recognition function as described in claim 6, wherein compared with one of the pixels in the column, the light-transmitting area of the corresponding pixel in the other column of pixels has a larger light transmission area. The pixel circuit with biometric recognition function as described in claim 1, wherein the shared reset line is located between the two adjacent columns of pixels. The pixel circuit with biometric recognition function as described in claim 1, wherein the shared reset line is located outside the sensing areas of the two adjacent rows of pixels.

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