TWI817491B - Boost converter with high efficiency - Google Patents

Abstract

A boost converter includes a bridge rectifier, a boost inductor, a supply circuit, a power switch element, a PWM (Pulse Width Modulation) IC (Integrated Circuit), an output stage circuit, a voltage divider circuit, a logic circuit, and an active rectifying circuit. The bridge rectifier generates a rectified voltage according to a first input voltage and a second input voltage. The supply circuit generates a supply voltage according to the rectified voltage. The PWM IC is supplied by the supply voltage, and generates a start-up voltage. The output stage circuit generates an output voltage. The voltage divider circuit generates a divided voltage according to the output voltage. The logic circuit generates a logic voltage according to the start-up voltage and the divided voltage. The active rectifying circuit selectively controls the rectified voltage according to the logic voltage.

Description

High efficiency boost converter

The present invention relates to a boost converter, and in particular to a boost converter with high efficiency.

In traditional boost converters, the bridge rectifier usually has large power losses. However, if the bridge rectifier is replaced by an active circuit component, there is often a risk that the active circuit component will be burned out by the initial excessive surge current. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by previous technologies.

In a preferred embodiment, the present invention proposes a boost converter, including: a bridge rectifier that generates a rectified potential based on a first input potential and a second input potential; a boost inductor that receives the rectified potential ; A power supply circuit that generates a supply potential based on the rectified potential; a power switch that modulates the potential based on a pulse width to selectively couple the boost inductor to a ground potential; a pulse width A modulation integrated circuit is powered by the supply potential and generates the pulse width modulation potential and a starting potential; an output stage circuit is coupled to the boost inductor and generates an output potential; A voltage dividing circuit generates a divided voltage potential based on the output potential; a logic circuit generates a logic potential based on the starting potential and the divided voltage potential; and an active rectification circuit receives the first input potential and The second input potential, wherein the active rectification circuit selectively controls the rectification potential according to the logic potential.

In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are listed below and described in detail with reference to the accompanying drawings.

Certain words are used in the specification and patent claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and the patent application do not use differences in names as a way to distinguish components, but differences in functions of components as a criterion for distinction. The words "include" and "include" mentioned throughout the specification and the scope of the patent application are open-ended terms, and therefore should be interpreted as "include but not limited to." The term "approximately" means that within an acceptable error range, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain error range. In addition, the word "coupling" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connections. Two devices.

FIG. 1 is a schematic diagram of a boost converter 100 according to an embodiment of the present invention. For example, the boost converter 100 can be applied to desktop computers, notebook computers, or all-in-one computers. As shown in Figure 1, the boost converter 100 includes: a bridge rectifier 110, a boost inductor LU, a power supply circuit 120, a power switch 130, and a pulse width modulation integrated circuit (Pulse Width Modulation IC). Integrated Circuit (PWM IC) 140, an output stage circuit 150, a voltage dividing circuit 160, a logic circuit 170, and an active rectifier circuit 180. It should be noted that, although not shown in FIG. 1 , the boost converter 100 may further include other components, such as a voltage regulator or/and a negative feedback circuit.

The bridge rectifier 110 can generate a rectified potential VR according to a first input potential VIN1 and a second input potential VIN2, wherein one of the first input potential VIN1 and the second input potential VIN2 can have any frequency and any amplitude. AC voltage. For example, the frequency of the AC voltage can be about 50Hz or 60Hz, and the root mean square value of the AC voltage can be about 90V to 264V, but it is not limited thereto. The boost inductor LU receives the rectified potential VR. The power supply circuit 120 can generate a supply potential VCC according to the rectified potential VR. The power switch 130 can selectively couple the boost inductor LU to a ground potential VSS (eg, 0V) according to a pulse width modulation potential VM. For example, if the pulse width modulation potential VM is a high logic level (ie, logic “1”), the power switch 130 may couple the boost inductor LU to the ground potential VSS (ie, the power The switch 130 can be approximated as a short-circuit path); conversely, if the pulse width modulation potential VM is a low logic level (ie, logic "0"), the power switch 130 will not convert the boost inductor LU is coupled to ground potential VSS (ie, power switch 130 may approximate an open path). The pulse width modulation integrated circuit 140 can be powered by the supply potential VCC, and can generate a pulse width modulation potential VM and a starting potential VE. In some embodiments, if the supply potential VCC is a high logic level, the pulse width modulation integrated circuit 140 will generate a start-up potential VE with a high logic level; conversely, if the supply potential VCC is a low logic level, Then the pulse width modulation integrated circuit 140 will generate the activation potential VE with a low logic level. The output stage circuit 150 is coupled to the boost inductor LU and can generate an output potential VOUT. For example, the output potential VOUT can be a DC potential, and its potential level can be about 400V, but it is not limited thereto. The voltage dividing circuit 160 can generate a divided voltage potential VD according to the output potential VOUT. For example, the divided voltage potential VD may be a specific ratio of the output potential VOUT. The logic circuit 170 can generate a logic potential VG according to the starting potential VE and the divided voltage potential VD. The active rectification circuit 180 may receive the first input potential VIN1 and the second input potential VIN2, wherein the active rectification circuit 180 may selectively control the rectification potential VR according to the logic potential VG. In some embodiments, if the logic potential VG is a high logic level, the active rectification circuit 180 will be enabled; conversely, if the logic potential VG is a low logic level, the active rectification circuit 180 will be disabled. Under this design, both the active rectifier circuit 180 and the bridge rectifier 110 can provide rectification functions. Since the non-ideal losses of the active rectifier circuit 180 are relatively low, it can further improve the overall conversion efficiency when the boost converter 100 operates in a steady state.

The following embodiments will introduce the detailed structure and operation of the boost converter 100 . It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the invention.

Figure 2 is a circuit diagram of a boost converter 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the boost converter 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a boost inductor LU, a A power supply circuit 220, a power switch 230, a pulse width modulation integrated circuit 240, an output stage circuit 250, a voltage dividing circuit 260, a logic circuit 270, and an active rectifier circuit 280. The first input node NIN1 and the second input node NIN2 of the boost converter 200 can be used to receive a first input potential VIN1 and a second input potential VIN2. The output node NOUT of the boost converter 200 can be used to output an output potential VOUT.

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and a first positive temperature coefficient (Positive Temperature Coefficient, PTC) resistor RP1, and a second positive temperature coefficient resistor RP2. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to the first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 . The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to the second input node NIN2, and the cathode of the second diode D2 is coupled to a second node N2 To output the rectified potential VR. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a third node N3, and the cathode of the third diode D3 is coupled to the first input node NIN1 . The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to a ground potential VSS (for example: 0V), and the cathode of the fourth diode D4 is coupled to the ground potential VSS (for example: 0V). Two input nodes NIN2. The first positive temperature coefficient resistor RP1 has a first terminal and a second terminal, wherein the first terminal of the first positive temperature coefficient resistor RP1 is coupled to the first node N1, and the first positive temperature coefficient resistor RP1 The second terminal is coupled to the second node N2. The second positive temperature coefficient resistor RP2 has a first terminal and a second terminal, wherein the first terminal of the second positive temperature coefficient resistor RP2 is coupled to the third node N3, and the second positive temperature coefficient resistor RP2 The second terminal is coupled to the ground potential VSS.

The boost inductor LU has a first terminal and a second terminal, wherein the first terminal of the boost inductor LU is coupled to the second node N2 to receive the rectified potential VR, and the second terminal of the boost inductor LU is coupled to a fourth node N4.

The power supply circuit 220 can generate a supply potential VCC according to the rectified potential VR. For example, after the boost converter 200 has received the first input potential VIN1 and the second input potential VIN2, the power supply circuit 220 will generate the supply potential VCC with a high logic level according to the rectification potential VR; otherwise, the supply potential VCC will remain at a low logic level.

The power switch 230 includes a switching transistor MS. For example, the switching transistor MS can be an N-type metal oxide semiconductor field effect transistor. The switching transistor MS has a control end, a first end, and a second end. The control end of the switching transistor MS is used to receive a pulse width modulation potential VM. The first end of the switching transistor MS is coupled to the ground potential VSS, and the second terminal of the switching transistor MS is coupled to the fourth node N4.

The pulse width modulation integrated circuit 240 can be powered by the supply potential VCC, and can be used to generate the pulse width modulation potential VM and a starting potential VE. For example, if the supply potential VCC is a high logic level, the pulse width modulation integrated circuit 240 will generate a start-up potential VE with a high logic level; conversely, if the supply potential VCC is a low logic level, the pulse width modulation integrated circuit 240 will generate a start-up potential VE with a high logic level. The width modulation integrated circuit 240 will generate the activation potential VE with a low logic level. In addition, the pulse width modulation potential VM can be maintained at a fixed potential when the boost converter 200 is first initialized, and can provide a periodic clock waveform after the boost converter 200 enters the normal use stage.

The output stage circuit 250 includes a fifth diode D5 and an output capacitor CO. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to the fourth node N4, and the cathode of the fifth diode D5 is coupled to the output node NOUT. The output capacitor CO has a first terminal and a second terminal, wherein the first terminal of the output capacitor CO is coupled to the output node NOUT, and the second terminal of the output capacitor CO is coupled to the ground potential VSS.

The voltage dividing circuit 260 includes a first resistor R1 and a second resistor R2. The first resistor R1 has a first terminal and a second terminal, wherein the first terminal of the first resistor R1 is coupled to the output node NOUT to receive the output potential VOUT, and the second terminal of the first resistor R1 is Coupled to a fifth node N5 to output a divided voltage potential VD. The second resistor R2 has a first terminal and a second terminal, wherein the first terminal of the second resistor R2 is coupled to the fifth node N5, and the second terminal of the second resistor R2 is coupled to the ground. Potential VSS.

The logic circuit 270 includes an AND Gate 275 . In detail, the AND gate 275 has a first input end, a second input end, and an output end, wherein the first input end of the AND gate 275 is used to receive the starting potential VE, and the second input end of the AND gate 275 It is used to receive the divided voltage potential VD, and the output end of the AND gate 275 is used to output a logic potential VG. That is, only when the startup potential VE and the voltage dividing potential VD are both high logic levels, the logic circuit 270 will generate a logic potential VG with a high logic level; otherwise, the logic circuit 270 will generate a logic potential VG with a low logic level. Logic potential VG.

The active rectification circuit 280 includes a controller 285, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The controller 285 can selectively generate a first control potential VC1, a second control potential VC2, a third control potential VC3, and a fourth control potential VC4 according to the logic potential VG. In some embodiments, if the logic potential VG is a high logic level, the controller 285 will be enabled to generate the aforementioned first control potential VC1, second control potential VC2, third control potential VC3, and fourth Control potential VC4; on the contrary, if the logic potential VG is a low logic level, the controller 285 will be disabled and will not generate any control potential.

For example, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may each be an N-type MOSFET. The first transistor M1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first transistor M1 is used to receive the first control potential VC1. The first terminal of the first transistor M1 is is coupled to the second node N2, and the second terminal of the first transistor M1 is coupled to the first input node NIN1 to receive the first input potential VIN1. The second transistor M2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second transistor M2 is used to receive the second control potential VC2. The first terminal of the second transistor M2 is is coupled to the second node N2, and the second terminal of the second transistor M2 is coupled to the second input node NIN2 to receive the second input potential VIN2. The third transistor M3 has a control terminal, a first terminal, and a second terminal. The control terminal of the third transistor M3 is used to receive the third control potential VC3. The first terminal of the third transistor M3 is is coupled to the first input node NIN1, and the second terminal of the third transistor M3 is coupled to the ground potential VSS. The fourth transistor M4 has a control terminal, a first terminal, and a second terminal. The control terminal of the fourth transistor M4 is used to receive the fourth control potential VC4. The first terminal of the fourth transistor M4 is is coupled to the second input node NIN2, and the second terminal of the fourth transistor M4 is coupled to the ground potential VSS.

In some embodiments, the operating principle of the boost converter 200 may be as follows. Initially, the boost converter 200 begins to receive the first input potential VIN1 and the second input potential VIN2. Then, after the pulse width modulation integrated circuit 240 receives the supply potential VCC with a high logic level, it will generate a start-up potential VE with a high logic level. In addition, after the output stage circuit 250 has established the normal output potential VOUT, it can also raise the divided voltage potential VD to a high logic level. At this time, the logic circuit 270 will generate a logic potential VG with a high logic level to enable the active rectification circuit 280, so that the bridge rectifier 210 and the active rectification circuit 280 jointly generate and control the rectification potential VR.

After a period of time, the boost converter 200 will operate in a stable state (also known as a thermal engine state). Since the temperature of the boost converter 200 gradually increases, the resistance values of both the first positive temperature coefficient resistor RP1 and the second positive temperature coefficient resistor RP2 become very large. In other words, the overall impedance value of the bridge rectifier 210 will be much larger than the overall impedance value of the active rectification circuit 280 , so the input current IIN of the boost converter 200 will mainly flow to the active rectification circuit 280 . At this time, the aforementioned rectification potential VR will be mainly generated and controlled by the active rectification circuit 280 (instead of the bridge rectifier 210 at the beginning), so that the overall conversion efficiency of the boost converter 200 can be greatly improved.

Figure 3 shows the waveform of the input current IIN of a conventional boost converter, in which the horizontal axis represents time ( μ s) and the vertical axis represents the current value (mA) of the input current IIN. As shown in Figure 3, the traditional boost converter starts to connect an input power supply at an initial time point TN, which will cause the input current IIN to suddenly increase, commonly known as "inrush current". However, excessive inrush current may burn out the active components in conventional boost converters.

Figure 4 shows a waveform diagram of the input current IIN of the boost converter 200 according to an embodiment of the present invention. The horizontal axis represents time (μs), and the vertical axis represents the current value (mA) of the input current IIN. It must be noted that the active rectification circuit 280 is enabled after the output stage circuit 250 has established a normal output potential VOUT. According to the measurement results in Figure 4, since the active rectifier circuit 280 will not withstand the initial The inrush current is large, so the design of the present invention can greatly reduce the probability of the active rectifier circuit 280 being accidentally burned.

The present invention proposes a novel boost converter, which can include a bridge rectifier and an active rectification circuit at the same time. According to actual measurement results, using the boost converter designed as mentioned above can effectively improve the overall conversion efficiency and reduce the risk of damage to its active components, so it is very suitable for use in various devices.

It is worth noting that the above-mentioned potential, current, resistance value, inductance value, capacitance value, and other component parameters are not limiting conditions of the present invention. Designers can adjust these settings according to different needs. The boost converter of the present invention is not limited to the state shown in Figures 1-4. The present invention may only include any one or multiple features of any one or multiple embodiments of Figures 1-4. In other words, not all features shown in the figures need to be implemented in the boost converter of the present invention at the same time. Although the embodiment of the present invention uses a metal oxide semi-field effect transistor as an example, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field effect transistors or fins. type field effect transistor, etc., without affecting the effect of the present invention.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other. They are only used to distinguish two items with the same Different components with names.

Although the present invention is disclosed above in terms of preferred embodiments, they are not intended to limit the scope of the present invention. Anyone skilled in the art can make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100,200:Boost converter

110,210: Bridge rectifier

120,220: Power supply circuit

130,230:Power switcher

140,240: Pulse width modulation integrated circuit

150,250: Output stage circuit

160,260: voltage divider circuit

170,270:Logic circuit

180,280: Active rectification circuit

275:And gate

285:Controller

CO: output capacitor

D1: first diode

D2: Second diode

D3: The third diode

D4: The fourth diode

D5: The fifth diode

IIN: input current

LU: Boost inductor

M1: the first transistor

M2: Second transistor

M3: The third transistor

M4: The fourth transistor

MS: switching transistor

N1: first node

N2: second node

N3: The third node

N4: fourth node

N5: fifth node

NIN1: first input node

NIN2: second input node

NOUT: output node

R1: first resistor

R2: second resistor

RP1: The first positive temperature coefficient resistor

RP2: Second positive temperature coefficient resistor

TN: initial time point

VC1: first control potential

VC2: second control potential

VC3: The third control potential

VC4: The fourth control potential

VCC: supply potential

VD: voltage dividing potential

VE: starting potential

VG: logic potential

VIN1: first input potential

VIN2: second input potential

VM: pulse width modulation potential

VOUT: output potential

VR: rectifier potential

VSS: ground potential

Figure 1 is a schematic diagram of a boost converter according to an embodiment of the present invention. Figure 2 is a circuit diagram showing a boost converter according to an embodiment of the present invention. Figure 3 is a waveform diagram showing the input current of a conventional boost converter. FIG. 4 is a waveform diagram showing the input current of the boost converter according to an embodiment of the present invention.

100:Boost converter

110: Bridge rectifier

120:Power supply circuit

130:Power switcher

140: Pulse width modulation integrated circuit

150: Output stage circuit

160: Voltage dividing circuit

170:Logic circuit

180: Active rectification circuit

LU: Boost inductor

VCC: supply potential

VD: voltage dividing potential

VE: starting potential

VG: logic potential

VIN1: first input potential

VIN2: second input potential

VM: pulse width modulation potential

VOUT: output potential

VR: rectifier potential

VSS: ground potential

Claims (10)

A boost converter including: A bridge rectifier generates a rectified potential based on a first input potential and a second input potential; A boost inductor receives the rectified potential; a power supply circuit that generates a supply potential based on the rectified potential; a power switch that selectively couples the boost inductor to a ground potential based on a pulse width modulated potential; A pulse width modulation integrated circuit is powered by the supply potential and generates the pulse width modulation potential and a starting potential; An output stage circuit is coupled to the boost inductor and generates an output potential; A voltage dividing circuit generates a divided voltage potential based on the output potential; A logic circuit that generates a logic potential based on the starting potential and the divided voltage potential; and An active rectification circuit receives the first input potential and the second input potential, wherein the active rectification circuit selectively controls the rectification potential according to the logic potential. The boost converter of claim 1, wherein the bridge rectifier includes: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the first diode The cathode is coupled to a first node; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the The cathode is coupled to a second node to output the rectified potential; a third diode has an anode and a cathode, wherein the anode of the third diode is coupled to a third node, and the The cathode of a third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to the ground potential. , and the cathode of the fourth diode is coupled to the second input node. The boost converter of claim 2, wherein the bridge rectifier further includes: a first positive temperature coefficient resistor having a first terminal and a second terminal, wherein the first positive temperature coefficient resistor has a first terminal and a second terminal. One end is coupled to the first node, and the second end of the first positive temperature coefficient resistor is coupled to the second node; and a second positive temperature coefficient resistor has a first end and a second terminal, wherein the first terminal of the second positive temperature coefficient resistor is coupled to the third node, and the second terminal of the second positive temperature coefficient resistor is coupled to the ground potential. The boost converter of claim 2, wherein the boost inductor has a first terminal and a second terminal, and the first terminal of the boost inductor is coupled to the second node to receive the rectified potential, The second terminal of the boost inductor is coupled to a fourth node. The boost converter of claim 4, wherein the power switcher includes: A switching transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the switching transistor is used to receive the pulse width modulation potential, and the third terminal of the switching transistor One terminal is coupled to the ground potential, and the second terminal of the switching transistor is coupled to the fourth node. The boost converter of claim 4, wherein the output stage circuit includes: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the fourth node, and the cathode of the fifth diode is coupled to an output node to output the output potential; and An output capacitor has a first terminal and a second terminal, wherein the first terminal of the output capacitor is coupled to the output node, and the second terminal of the output capacitor is coupled to the ground potential. The boost converter of claim 6, wherein the voltage dividing circuit includes: a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the output node to receive the output potential, and the first terminal of the first resistor The two terminals are coupled to a fifth node to output the divided voltage potential; and a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the fifth node, and the second terminal of the second resistor is coupled to connected to this ground potential. The boost converter of claim 2, wherein the logic circuit includes: An AND gate has a first input end, a second input end, and an output end, wherein the first input end of the AND gate is used to receive the starting potential, and the second input end of the AND gate is is used to receive the divided voltage potential, and the output end of the AND gate is used to output the logic potential. The boost converter of claim 8, wherein the active rectification circuit includes: A controller selectively generates a first control potential, a second control potential, a third control potential, and a fourth control potential according to the logic potential. For example, the boost converter of claim 9, wherein the active rectification circuit further includes: A first transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the first control potential, and the third terminal of the first transistor One terminal is coupled to the second node, and the second terminal of the first transistor is coupled to the first input node to receive the first input potential; A second transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used to receive the second control potential, and the third terminal of the second transistor One terminal is coupled to the second node, and the second terminal of the second transistor is coupled to the second input node to receive the second input potential; A third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the third control potential, and the third terminal of the third transistor One terminal is coupled to the first input node, and the second terminal of the third transistor is coupled to the ground potential; and A fourth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is used to receive the fourth control potential, and the third terminal of the fourth transistor One terminal is coupled to the second input node, and the second terminal of the fourth transistor is coupled to the ground potential.

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