TWI817385B - Dual-sided conductive stacked structure and fabrication method thereof - Google Patents

Dual-sided conductive stacked structure and fabrication method thereof Download PDF

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TWI817385B
TWI817385B TW111108958A TW111108958A TWI817385B TW I817385 B TWI817385 B TW I817385B TW 111108958 A TW111108958 A TW 111108958A TW 111108958 A TW111108958 A TW 111108958A TW I817385 B TWI817385 B TW I817385B
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conductive layer
double
laminated structure
substrate
sided
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TW111108958A
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Chinese (zh)
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TW202337277A (en
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陳筱茜
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大陸商業成科技(成都)有限公司
大陸商業成光電(深圳)有限公司
大陸商業成光電(無錫)有限公司
英特盛科技股份有限公司
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections

Abstract

A dual-sided conductive stacked structure and fabrication method thereof are provided. The structure includes a substrate, a first conductive layer and a second conductive layer. The substrate has an upper surface and a lower surface opposite to the upper surface. At least one via hole is formed between the upper and the lower surface. The first conductive layer covers the upper, lower surfaces and sidewalls of the via hole. The second conductive layer covers the first conductive layer which is configured on the upper surface of the substrate as well as the first conductive layer which is configured on the lower surface of the substrate, such that the upper and lower surfaces of the substrate are electrically conductive. The present invention achieves to reduce the conventional process flow and cost. In addition, superior cleanliness in a drill process is maintained. Variability in a conventional chemical plating process is avoided as well.

Description

雙面導電的層疊結構及其製造方法Double-sided conductive laminated structure and manufacturing method thereof

本發明係有關於一種透明顯示裝置之導電結構,特別是一種其中具有雙面導電層,並可省卻現有製程步驟及製程成本的一種雙面導電的層疊結構及其製造方法。The present invention relates to a conductive structure of a transparent display device, in particular, a double-sided conductive laminated structure and a manufacturing method thereof that have a double-sided conductive layer and can save existing process steps and costs.

按,電路板自其起源到目前之高密度設計,通常都與絲網印刷(silk screen printing)或網版印刷有直接且密切的關係,故稱之為印刷電路板。目前除了最大量的應用在電路板之外,其他電子工業上有厚膜(thick film)的混成電路(Hybrid circuit)、晶片電阻(Chip resist)、以及表面黏裝(Surface mounting)之錫膏印刷等也都有其應用之處。一般來說,印刷電路板(printed circuit board,PCB)的功能為提供完成第一層級構裝的元件與其他必須的電子電路零件接合的基地,以組成一個具有特定功能的模組或成品。因此,PCB板在整個電子產品中,扮演了整合連結總其成所有功能的重要角色;舉例來說,目前透明顯示裝置中都會使用到PCB板,並將其與厚銅基材製程作一結合,以從而形成一種雙面的導電層結構,如圖示第1A圖至第1F圖所示。From its origin to the current high-density design, circuit boards are usually directly and closely related to silk screen printing or screen printing, so they are called printed circuit boards. In addition to the largest number of applications in circuit boards, other electronic industries include thick film hybrid circuits, chip resistors, and surface mounting solder paste printing. etc. also have their applications. Generally speaking, the function of a printed circuit board (PCB) is to provide a base for the first-level assembly of components to be joined with other necessary electronic circuit parts to form a module or finished product with specific functions. Therefore, PCB boards play an important role in integrating and connecting all functions of the entire electronic product; for example, PCB boards are currently used in transparent display devices and are combined with thick copper substrate manufacturing processes , thereby forming a double-sided conductive layer structure, as shown in Figures 1A to 1F.

請參照第1A圖至第1F圖,首先,基板10係經過適當的清洗(CLN)製程,之後,如第1B圖所示,利用濺鍍(sputter)製程在基板10之表面製作厚度約為0.1微米的導電層11,之後,如第1C圖所示,再通過電鍍(electroplating)製程增厚平面,該電鍍之增厚厚度約為8至16微米的金屬銅層12,以藉此厚銅降低金屬阻抗。隨後,再如第1D圖所示,對該結構進行鑽孔(drill)製程,以在其中形成複數個貫通孔13,之後,在第1E圖中進行化鍍(electroless)製程,或又稱「化學敷鍍處理」、或「無電鍍處理」,以在該些貫通孔13的表面形成化鍍金屬層20,並且,如第1F圖所示,藉由該化鍍金屬層20連接貫通孔13,使基板10的正、反金屬層形成導通。完成之後,再於第1F圖中進行第二次電鍍製程,使金屬銅層12增厚厚度至約為8微米。完成上述該等製程之後,再接續進行後續之微影、蝕刻、印刷等製程步驟。Please refer to Figures 1A to 1F. First, the substrate 10 undergoes an appropriate cleaning (CLN) process. Then, as shown in Figure 1B, a sputtering process is used to create a thickness of approximately 0.1 on the surface of the substrate 10. Micron conductive layer 11, and then, as shown in Figure 1C, the plane is thickened through an electroplating process. The electroplating thickens the metal copper layer 12 with a thickness of about 8 to 16 microns, so that the thick copper reduces the Metal resistance. Subsequently, as shown in Figure 1D, a drilling process is performed on the structure to form a plurality of through holes 13 therein, and then an electroless plating process, also known as "electroless plating" is performed as shown in Figure 1E. "Electroless plating treatment" or "electroless plating treatment" to form an electroless metal plating layer 20 on the surface of the through holes 13, and, as shown in Figure 1F, the through holes 13 are connected through the electroless metal plating layer 20 , causing the front and reverse metal layers of the substrate 10 to become conductive. After completion, a second electroplating process is performed in Figure 1F to thicken the metal copper layer 12 to about 8 microns. After completing the above-mentioned processes, subsequent process steps such as lithography, etching, and printing are continued.

值得注意的是,在現有的製程步驟中,由於在進行濺鍍製程之前,為了俾利後續金屬導電層的附著,一般會在基板10之表面先濺鍍有一層介質層。請參照第2圖所示,其顯示先前技術之厚銅基材中具有一介質層之結構示意圖,該介質層22之材質例如可選為:鎳(Ni)或者鉻(Cr),從而使貫通孔13的孔壁呈現三層的疊層結構(包含:基板10/介質層22/金屬銅層12)。不過,這樣的三層疊層結構通常在後續的化鍍製程中會引發不少問題,舉例來說,常會產生其導體層與非導體化鍍鍍層之間不夠均勻的問題,更甚者,請參見第3圖所示,會使所形成的化鍍金屬層20有嚴重選擇性(selectivity)差異的缺失。It is worth noting that in the existing process steps, before performing the sputtering process, in order to facilitate the adhesion of the subsequent metal conductive layer, a dielectric layer is generally sputtered on the surface of the substrate 10 . Please refer to Figure 2, which shows a schematic structural diagram of a dielectric layer in a thick copper substrate in the prior art. The material of the dielectric layer 22 can be, for example, nickel (Ni) or chromium (Cr), so that through The hole wall of the hole 13 presents a three-layer stacked structure (including: substrate 10/dielectric layer 22/metal copper layer 12). However, such a three-layer stacked structure usually causes many problems in the subsequent electroless plating process. For example, the problem of insufficient uniformity between the conductive layer and the non-conductive plating layer is often caused. Worse, please refer to As shown in FIG. 3 , the formed electroless metal layer 20 will have a serious lack of selectivity difference.

除此之外,這樣的三層疊層結構(包含:基板/介質層/金屬銅層),在之後進行鑽孔製程時,也會因其多層結構的特性,而在鑽孔時產生並形成較多的膠渣、以及鑽污,進一步地影響後續化鍍製程之變異。是以,有鑒於此等缺失,本發明人係有感於上述缺失之可改善,且依據多年來從事此方面之相關經驗,悉心觀察且研究之,並配合學理之運用,而提出一種設計新穎且極具創新之本發明,其係揭露一種改良後之雙面導電的層疊結構及其製造方法,通過採用此種改良後之雙面導電的層疊結構及其製造方法,不僅可較佳地改進現有技術所存在已久的缺失,且能有效地省卻並節省現有製程所必須進行的步驟及相關的製程成本。以下,本申請人係針對關於此發明具體之架構及實施方式,提供詳述於下。In addition, such a three-layer stacked structure (including: substrate/dielectric layer/metal copper layer) will also produce and form relatively large holes during the drilling process due to the characteristics of the multi-layer structure. Excessive slag and drill dirt will further affect the variation of the subsequent electroless plating process. Therefore, in view of these deficiencies, the inventor feels that the above deficiencies can be improved, and based on his years of relevant experience in this area, careful observation and research, and the application of academic theories, he proposes a novel design. The extremely innovative invention discloses an improved double-sided conductive laminated structure and a manufacturing method thereof. By using this improved double-sided conductive laminated structure and its manufacturing method, not only can the It solves the long-standing shortcomings of the existing technology, and can effectively eliminate and save the necessary steps and related process costs of the existing manufacturing process. Below, the applicant provides a detailed description of the specific structure and implementation of the invention.

為解決習知技術存在的問題,本發明之一目的係在於提供一種創新的雙面導電的層疊結構,其係針對現行的厚銅基材結構作一改良,相較於現有技術,本發明係通過採用化鍍製程完成基材上、下表面及通孔的導電層,從而可省卻習知濺鍍層及第二次電鍍層的兩道製程步驟,有效降低製程之複雜度及其製程成本。In order to solve the problems existing in the prior art, one purpose of the present invention is to provide an innovative double-sided conductive laminated structure, which is an improvement on the current thick copper substrate structure. Compared with the existing technology, the present invention By using the chemical plating process to complete the conductive layers on the upper and lower surfaces of the substrate and the through holes, the conventional two process steps of sputtering layer and second electroplating layer can be omitted, effectively reducing the complexity of the process and its process cost.

再者,本發明之又一目的亦在於藉由此種雙面導電的層疊結構,其中在進行鑽孔製程前,僅含有單一材質的基材,因此當在進行後續的化鍍製程時,由於化鍍製程係直接化鍍於單一材質的基材上,因此便無先前技術中所述導體或層別結構之差異,自然可由此解決先前技術中所述製程不均或有化鍍厚度選擇性之問題。Furthermore, another object of the present invention is to use this double-sided conductive laminated structure, which only contains a single material substrate before the drilling process. Therefore, when the subsequent chemical plating process is performed, due to The electroless plating process is directly electroless plating on a single material substrate, so there is no difference in conductor or layer structure as described in the prior art. This can naturally solve the uneven process or electroless plating thickness selectivity described in the prior art. problem.

更甚者,本發明之再一目的係在於提供一種雙面導電的層疊結構及其製造方法,相較於現有技藝採用的多層結構(其中具有異材質的介質層),利用本發明所揭露之技術方案,基於僅使用單一材質的基材,可以在後續進行鑽孔製程時減少膠渣以及鑽污的產生,使其維持良好的潔淨度、製程可控、且單純度高。What's more, another object of the present invention is to provide a double-sided conductive laminated structure and a manufacturing method thereof. Compared with the multi-layer structure (which has dielectric layers of different materials) used in the prior art, the method disclosed in the present invention is used. The technical solution is based on using only a single base material, which can reduce the generation of slag and drilling dirt during the subsequent drilling process, maintaining good cleanliness, controllable process, and high simplicity.

除此之外,本發明所揭露之雙面導電的層疊結構及其製造方法亦可與透明顯示裝置之製程作一結合,以更進一步地廣泛應用於顯示器產品及其領域,藉此確信可增進本發明之產業效益與產業應用性。In addition, the double-sided conductive laminated structure and its manufacturing method disclosed in the present invention can also be combined with the manufacturing process of transparent display devices, so as to be further widely used in display products and their fields, thereby ensuring that it can enhance Industrial benefits and industrial applicability of the present invention.

鑒於以上,本發明主要係揭露一種使用單一材質的基材,其為一種雙面導電的層疊結構,其中包括有:一基材、一第一導電層、以及一第二導電層。基材具有一上表面與相對於該上表面之一下表面,並且,基材之該上表面與下表面之間係形成有至少一通孔。第一導電層係覆蓋於該基材之上表面、下表面、以及該至少一通孔之孔壁。所述的第二導電層係覆蓋位於該基材之上表面的第一導電層,同時,所述的第二導電層亦覆蓋位於該基材之下表面的第一導電層,從而使該基材之上表面與下表面提供電性導通。In view of the above, the present invention mainly discloses a substrate using a single material, which is a double-sided conductive laminated structure, which includes: a substrate, a first conductive layer, and a second conductive layer. The base material has an upper surface and a lower surface opposite to the upper surface, and at least one through hole is formed between the upper surface and the lower surface of the base material. The first conductive layer covers the upper surface, the lower surface of the substrate, and the hole wall of the at least one through hole. The second conductive layer covers the first conductive layer located on the upper surface of the base material. At the same time, the second conductive layer also covers the first conductive layer located on the lower surface of the base material, so that the base material The upper surface and lower surface of the material provide electrical conduction.

根據本發明之實施例,該基材之材質為透明或半透明材料。基材之厚度係大於25微米。並且,基材之穿透率(transmittance)係大於80%。According to an embodiment of the present invention, the substrate is made of a transparent or translucent material. The thickness of the substrate is greater than 25 microns. Moreover, the transmittance of the base material is greater than 80%.

根據本發明之實施例,所述的第一導電層係通過一化鍍製程而形成。According to an embodiment of the present invention, the first conductive layer is formed through an electroless plating process.

根據本發明之實施例,所述的第二導電層係通過一電鍍製程而形成。在一實施例中,第二導電層之材質為銅。According to an embodiment of the present invention, the second conductive layer is formed through an electroplating process. In one embodiment, the second conductive layer is made of copper.

根據本發明之實施例,第一導電層之材質為金屬或其合金。在一實施例中,該第一導電層之材質為銅。第一導電層之厚度例如可介於0.3至3.0微米之間。並且,第一導電層之均勻性(uniformity)係小於20%。According to an embodiment of the present invention, the material of the first conductive layer is metal or an alloy thereof. In one embodiment, the first conductive layer is made of copper. The thickness of the first conductive layer may range from 0.3 to 3.0 microns, for example. Moreover, the uniformity of the first conductive layer is less than 20%.

除此之外,依據本發明之諸多實施態樣,所述通孔亦不以其孔徑形狀為限,舉例而言,通孔的實施態樣包括可為:圓形孔、方形孔、菱形孔、倒梯形孔、梯形孔、或是具有不規則孔壁等結構的通孔形狀。在本發明之均等且不脫離本發明之發明精神下,本領域具通常知識者係可依其實際製程及需求調整應用,仍應隸屬於本發明之發明範疇。In addition, according to many embodiments of the present invention, the through hole is not limited to its aperture shape. For example, the embodiments of the through hole include: circular holes, square holes, and rhombus holes. , inverted trapezoidal hole, trapezoidal hole, or through hole shape with irregular hole wall and other structures. As long as the present invention is equal and does not deviate from the inventive spirit of the present invention, those with ordinary knowledge in the art can adjust the application according to the actual process and needs, and it should still fall within the scope of the present invention.

根據本發明之一實施例,為了增加第一導電層覆蓋時的附著力,可進一步在第一導電層覆蓋該基材之上表面、下表面、以及該至少一通孔之孔壁的接觸面上形成有至少一微結構,以通過該至少一微結構增加第一導電層接著時的附著力。According to an embodiment of the present invention, in order to increase the adhesion when covering the first conductive layer, the first conductive layer can further cover the upper surface, the lower surface of the substrate, and the contact surface of the hole wall of the at least one through hole. At least one microstructure is formed to increase the adhesion of the first conductive layer during adhesion through the at least one microstructure.

在一實施例中,所述的至少一微結構例如可呈鋸齒狀。In one embodiment, the at least one microstructure may be in a zigzag shape, for example.

在一實施例中,所述的至少一微結構係可具有凹凸之高度差。In one embodiment, the at least one microstructure may have a height difference between concave and convex.

本發明不以此等微結構的分佈密度或是分佈態樣為限制。大抵而言,本技術領域具通常知識之人士當可在本發明所教示之技術思想下自行修飾其變化例;惟在本發明之均等且不脫離本發明之發明精神下,仍應隸屬於本發明之發明範疇。The present invention is not limited by the distribution density or distribution pattern of these microstructures. Generally speaking, those with ordinary knowledge in the technical field can modify the modifications themselves based on the technical ideas taught by the present invention; however, as long as the present invention is equal and does not deviate from the spirit of the invention, it should still be subject to the present invention. Invention scope of invention.

另一方面而言,本發明係同時提供一種雙面導電的層疊結構的製造方法,包括以下步驟:首先提供一基材,該基材具有一上表面與相對於該上表面之一下表面。之後,在該基材之上表面與下表面之間係形成有至少一通孔。之後,通過一化鍍製程形成一第一導電層,所述的第一導電層係覆蓋該基材之上表面、下表面、以及該至少一通孔之孔壁。再通過一電鍍製程形成一第二導電層,其係覆蓋位於該基材之上表面的該第一導電層,所述的第二導電層亦覆蓋位於該基材之下表面的該第一導電層,從而使該基材之上表面與下表面提供電性導通。On the other hand, the present invention also provides a method for manufacturing a double-sided conductive laminated structure, which includes the following steps: firstly providing a substrate having an upper surface and a lower surface opposite to the upper surface. Afterwards, at least one through hole is formed between the upper surface and the lower surface of the base material. After that, a first conductive layer is formed through an electroless plating process, and the first conductive layer covers the upper surface, the lower surface of the substrate, and the hole wall of the at least one through hole. A second conductive layer is then formed through an electroplating process, which covers the first conductive layer located on the upper surface of the base material. The second conductive layer also covers the first conductive layer located on the lower surface of the base material. layer, thereby providing electrical conduction between the upper surface and the lower surface of the substrate.

緣此,根據本發明上列所揭露之種種多樣化的實施方式及其實施態樣,可以顯見,本發明主要係藉由所揭露的雙面導電的層疊結構,藉此改良現有的基材結構,從而使得化鍍製程能夠直接化鍍於單一材質的基材上,因此便可避免掉先前技術中所述導體或層別結構之差異,由此解決先前技術中所述製程不均或有化鍍厚度選擇性之問題,確實地改善並解決了先前技術中所揭之種種缺失。Therefore, based on the various diversified embodiments and implementation aspects disclosed above, it can be seen that the present invention mainly improves the existing substrate structure through the disclosed double-sided conductive laminated structure. , so that the electroless plating process can be directly electroplated on a substrate of a single material, thereby avoiding the differences in conductors or layer structures described in the prior art, thus solving the uneven or chemical process problems described in the prior art. The problem of plating thickness selectivity has indeed improved and solved various deficiencies exposed in the previous technology.

在底下的實施方式內容中,本申請人係進一步地藉由具體實施例配合所附的圖式詳加說明,當可使本領域之技術人士更加容易地瞭解本發明之目的、技術內容、特點及其所達成之功效。In the following implementation details, the applicant further explains in detail through specific embodiments in conjunction with the attached drawings, which will make it easier for those skilled in the art to understand the purpose, technical content, and characteristics of the present invention. and the results achieved.

以上有關於本發明的內容說明,與以下的實施方式係用以示範與解釋本發明的精神與原理,並且提供本發明的專利申請範圍更進一步的解釋。有關本發明的特徵、實作與功效,茲配合圖式作較佳實施例詳細說明如下。The above description of the present invention and the following embodiments are used to demonstrate and explain the spirit and principles of the present invention, and to provide further explanation of the patent application scope of the present invention. Regarding the characteristics, implementation and effects of the present invention, the preferred embodiments are described in detail below with reference to the drawings.

承以前列先前技術所舉,由於現有技藝所採用的多層結構在進行鑽孔製程時會伴隨產生有較嚴重的膠渣、以及鑽污等問題,同時,也會在化鍍製程中產生均勻度不佳與選擇性差異等缺失。因此,基於改良此等缺失,本發明遂針對這些種種問題提出一種較佳的改良設計,其為一種創新的雙面導電的層疊結構及其製造方法,其中僅使用單一材質的基材,並且,以化鍍製程同時完成基材之上、下表面及通孔的導電層覆蓋,相較於現有技術中具有介質層的疊層結構,本發明可控單純度高,亦無製程選擇性或不均等缺失。Following the previous technology, the multi-layer structure used in the existing technology will be accompanied by serious problems such as slag and drilling dirt during the drilling process. At the same time, it will also cause uniformity during the electroless plating process. Poor and selective differences and other missing. Therefore, based on improving these deficiencies, the present invention proposes a better improved design to address these various problems, which is an innovative double-sided conductive laminated structure and its manufacturing method, in which only a single material substrate is used, and, The electroless plating process is used to simultaneously complete the conductive layer coverage on the upper and lower surfaces of the substrate and the through holes. Compared with the stacked structure with a dielectric layer in the prior art, the present invention has high controllability and simplicity, and has no process selectivity or no process. Equality is missing.

請參照第11圖所示,其係為根據本發明實施例雙面導電的層疊結構的製造方法之步驟流程圖,該製造方法主要包含步驟S111、步驟S113、步驟S115、以及步驟S117。為了能更詳盡理解本發明所公開之技術方案,請同時配合參閱第4A圖至第4D圖所示之結構,其為根據本發明實施例之各製程對應之結構示意圖。如第4A圖及第11圖之步驟S111所示,首先提供一基材40,並且對基材40進行適當的清洗(CLN)製程。該基材40具有一上表面411與相對於該上表面411之一下表面412。根據本發明之實施例,基材40之材質可以是但不限於透明或半透明的材料,如:聚酯(PET)、透明聚醯亞胺(Colorless Polyimide,CPI)、聚醯亞胺(Polyimide,PI)、聚偏二氟乙烯(Polyvinylidene fluoride,PVDF)等等。Please refer to FIG. 11 , which is a step flow chart of a manufacturing method of a double-sided conductive laminated structure according to an embodiment of the present invention. The manufacturing method mainly includes step S111, step S113, step S115, and step S117. In order to understand the technical solutions disclosed in the present invention in more detail, please also refer to the structures shown in Figures 4A to 4D, which are schematic structural diagrams corresponding to various processes according to embodiments of the present invention. As shown in step S111 of FIG. 4A and FIG. 11 , a substrate 40 is first provided, and an appropriate cleaning (CLN) process is performed on the substrate 40 . The base material 40 has an upper surface 411 and a lower surface 412 opposite to the upper surface 411 . According to embodiments of the present invention, the material of the base material 40 may be, but is not limited to, transparent or translucent materials, such as: polyester (PET), transparent polyimide (CPI), polyimide (Polyimide) , PI), polyvinylidene fluoride (PVDF), etc.

根據本發明之一實施例,所述之基材40的厚度係大於25微米,基材之穿透率(transmittance)係大於80%。According to an embodiment of the present invention, the thickness of the base material 40 is greater than 25 microns, and the transmittance of the base material is greater than 80%.

之後,如本發明第4B圖及第11圖之步驟S113所示,對該基材40進行一鑽孔製程,以在所述的基材40之上表面411與下表面412之間形成至少一個通孔42,通孔42形成於所述基材40之該上表面411與該下表面412之間。After that, as shown in step S113 in Figure 4B and Figure 11 of the present invention, a drilling process is performed on the base material 40 to form at least one hole between the upper surface 411 and the lower surface 412 of the base material 40. The through hole 42 is formed between the upper surface 411 and the lower surface 412 of the base material 40 .

之後,如本發明第4C圖及第11圖之步驟S115所示,對該基材40進行化鍍製程,以形成一第一導電層50。第一導電層50同時覆蓋於基材40之上表面411、下表面412、以及通孔42之孔壁。根據本發明之實施例,第一導電層50是通過所述的化鍍製程而形成。第一導電層50之材質為金屬或其合金,舉例來說,第一導電層50之材質為銅。第一導電層50之厚度係介於0.3至3.0微米之間, 並且,第一導電層之均勻性(uniformity)係小於20%。Thereafter, as shown in step S115 of FIG. 4C and FIG. 11 of the present invention, an electroless plating process is performed on the base material 40 to form a first conductive layer 50 . The first conductive layer 50 simultaneously covers the upper surface 411 and the lower surface 412 of the substrate 40 and the hole wall of the through hole 42 . According to an embodiment of the present invention, the first conductive layer 50 is formed through the electroless plating process. The material of the first conductive layer 50 is metal or its alloy. For example, the material of the first conductive layer 50 is copper. The thickness of the first conductive layer 50 is between 0.3 and 3.0 microns, and the uniformity of the first conductive layer is less than 20%.

之後,如本發明第4D圖及第11圖之步驟S117所示,於所述的第一導電層50上進行電鍍製程,以形成一第二導電層60。根據本發明之實施例,所形成的第二導電層60覆蓋位於基材40之上表面411的第一導電層50,該第二導電層60亦覆蓋位於40基材之下表面412的第一導電層50,從而使該基材40之上表面411與下表面412形成電性導通。由此,獲得了本發明所公開之雙面導電的層疊結構100。在本發明之實施例中,所述的第二導電層60係通過一電鍍製程而形成,第二導電層60之材質為銅。Thereafter, as shown in step S117 of FIG. 4D and FIG. 11 of the present invention, an electroplating process is performed on the first conductive layer 50 to form a second conductive layer 60 . According to an embodiment of the present invention, the second conductive layer 60 formed covers the first conductive layer 50 located on the upper surface 411 of the substrate 40 , and the second conductive layer 60 also covers the first conductive layer 50 located on the lower surface 412 of the substrate 40 . The conductive layer 50 forms an electrical connection between the upper surface 411 and the lower surface 412 of the base material 40 . Thus, the double-sided conductive laminated structure 100 disclosed in the present invention is obtained. In the embodiment of the present invention, the second conductive layer 60 is formed through an electroplating process, and the material of the second conductive layer 60 is copper.

在完成本發明所公開之雙面導電的層疊結構100之後,接續進行微影、蝕刻、印刷等製程。大抵來說,在本發明所屬技術領域中具備通常知識之人士當可在本發明所教示之技術思想下自行修飾其變化例;惟在本發明之均等且不脫離本發明之發明精神下,仍應隸屬於本發明之發明範疇。After completing the double-sided conductive laminated structure 100 disclosed in the present invention, processes such as photolithography, etching, and printing are continued. Generally speaking, those with ordinary knowledge in the technical field to which the present invention belongs can modify the modifications on their own under the technical ideas taught by the present invention; however, as long as the present invention is equal and does not deviate from the inventive spirit of the present invention, it is still possible to It should fall within the scope of the present invention.

緣此,根據本發明所揭露的技術方案,可以明顯看出,在進行鑽孔製程時,本發明僅使用單一材質的基材40,而無先前技術所採用的介質層,因此可控單純度高,同時,在進行鑽孔時,也較無膠渣及髒污的產生。另一方面來說,本發明係以化鍍製程同時完成基材40之上表面411、下表面412及其通孔42的導電層覆蓋,相較於現有技術中具有介質層的疊層結構,本發明可控單純度高,亦可避免習知製程具有選擇性不佳或不均等之缺失。Therefore, according to the technical solution disclosed in the present invention, it can be clearly seen that when performing the drilling process, the present invention only uses a single material substrate 40 without the dielectric layer used in the previous technology, so the simplicity can be controlled. At the same time, there is less slag and dirt generated when drilling. On the other hand, the present invention uses an electroless plating process to simultaneously complete the conductive layer covering of the upper surface 411, the lower surface 412 and the through holes 42 of the substrate 40. Compared with the stacked structure with a dielectric layer in the prior art, The present invention has high controllability and simplicity, and can also avoid the shortcomings of poor selectivity or unevenness in conventional manufacturing processes.

請參閱第5圖,其為根據本發明實施例雙面導電的層疊結構在基材表面形成有微結構之示意圖。其中,本發明係亦可進而在第一導電層50覆蓋基材40之上表面411、下表面412、以及通孔42之孔壁的接觸面上形成有至少一微結構511,以通過該至少一微結構511增加第一導電層50覆蓋時的附著力。換言之,在本發明第11圖之步驟S115通過化鍍製程形成第一導電層50的步驟中,更可包括:在第一導電層50覆蓋基材40之上表面411、下表面412、以及通孔42之孔壁的接觸面上形成所述的微結構511,以通過該微結構511增加第一導電層50覆蓋時的附著力。詳細而言,請參見第6圖與第7圖,第6圖公開先前技術未在基板10之表面進行破壞以形成微結構之示意圖,第7圖為根據本發明一實施例,於基材40之表面進行破壞以形成有微結構之示意圖。由第6圖與第7圖可以明顯見得,根據本發明之實施例,所述的微結構511例如可呈鋸齒狀,抑或是,所述的微結構511可設計具有凹凸之高度差,藉此便可些微地破壞原有基材40之表面,使微結構511與所化鍍的第一導電層50之間形成非平滑接著,從而可以增加金屬化鍍時的表面附著力。Please refer to Figure 5, which is a schematic diagram of a double-sided conductive laminated structure with microstructures formed on the surface of a substrate according to an embodiment of the present invention. Among them, the present invention can also further form at least one microstructure 511 on the contact surface of the first conductive layer 50 covering the upper surface 411, the lower surface 412 of the substrate 40 and the hole wall of the through hole 42, so as to pass through the at least one microstructure 511. A microstructure 511 increases the adhesion when covered by the first conductive layer 50 . In other words, in step S115 of Figure 11 of the present invention, the step of forming the first conductive layer 50 through the electroless plating process may further include: covering the upper surface 411, the lower surface 412, and the through layer of the first conductive layer 50 of the base material 40. The microstructure 511 is formed on the contact surface of the hole wall of the hole 42 so as to increase the adhesion when covered by the first conductive layer 50 through the microstructure 511 . For details, please refer to Figures 6 and 7. Figure 6 discloses a schematic diagram of the prior art without damaging the surface of the substrate 10 to form a microstructure. Figure 7 shows a method of forming a microstructure on the substrate 40 according to an embodiment of the present invention. A schematic diagram of destroying the surface to form a microstructure. It can be clearly seen from Figures 6 and 7 that according to the embodiment of the present invention, the microstructure 511 can be in a zigzag shape, for example, or the microstructure 511 can be designed to have a concave and convex height difference. This can slightly damage the surface of the original substrate 40 and form a non-smooth connection between the microstructure 511 and the plated first conductive layer 50, thereby increasing the surface adhesion during metallization plating.

因此,鑒於上述種種本發明所列舉之諸多實施態樣,本發明之重要核心概念乃在於可針對現行的厚銅基材結構作一改良,相較於現有技術,本發明在進行鑽孔製程前,僅含有單一材質的基材,因此當在進行後續的化鍍製程時,由於化鍍製程係直接化鍍於單一材質的基材上,因此便無先前技術中所述導體或層別結構之差異,自然可由此解決先前技術中所述製程不均或產生有化鍍厚度選擇性之問題。Therefore, in view of the various embodiments of the present invention listed above, the important core concept of the present invention is to make an improvement on the current thick copper substrate structure. Compared with the prior art, the present invention can , only contains a single material base material, so when the subsequent electroless plating process is performed, since the electroless plating process is directly electroless plating on the single material base material, there is no conductor or layered structure as described in the prior art. The difference can naturally solve the problem of uneven process or selective electroless plating thickness in the prior art.

更進一步而言,請參閱第8、9、10圖所示,其係為根據本發明所公開之通孔的其他實施態樣,如該等圖式所示,本發明並不以通孔的形成形狀,或其孔徑形狀為限,前述第4B~4D圖以及第5圖所繪製之通孔僅是為了解釋本發明技術方案的其中一種示性例,在本發明之其他實施例中,通孔的實施態樣亦包括可為:圓形孔、方形孔、菱形孔、倒梯形孔、梯形孔、或是具有不規則孔壁等結構的通孔形狀。舉例來說,可以如第8圖所示為梯形孔42A,可以如第9圖所示為倒梯形孔42B,亦可以如第10圖所示為不規則形孔42C。大抵而言,本領域具通常知識者係可依其實際製程及需求調整其通孔的形狀,惟在本發明之均等且不脫離本發明之發明精神下,仍應隸屬於本發明之發明範疇。Furthermore, please refer to Figures 8, 9, and 10, which are other embodiments of through holes disclosed according to the present invention. As shown in these figures, the present invention does not use through holes. The formation shape, or the shape of the aperture is limited to the above. The through holes drawn in Figures 4B to 4D and Figure 5 are only for explaining one of the exemplary examples of the technical solution of the present invention. In other embodiments of the present invention, through holes The holes may also be implemented in a circular hole, a square hole, a diamond hole, an inverted trapezoidal hole, a trapezoidal hole, or a through hole shape with an irregular hole wall structure. For example, it can be a trapezoidal hole 42A as shown in Figure 8, an inverted trapezoidal hole 42B as shown in Figure 9, or an irregular hole 42C as shown in Figure 10. Generally speaking, those with ordinary knowledge in the art can adjust the shape of the through holes according to the actual manufacturing process and needs. However, as long as the invention is equal and does not deviate from the spirit of the invention, it should still fall within the scope of the invention. .

由此觀之,足以可見本發明主要係通過採用化鍍製程同時完成基材之上、下表面及通孔的導電層,從而可省卻習知濺鍍層及第二次電鍍層的兩道製程步驟,有效改良現有製程之複雜度及其製程成本。From this point of view, it can be seen that the present invention mainly uses an electroless plating process to simultaneously complete the conductive layers on the upper and lower surfaces of the substrate and the through holes, thereby eliminating the conventional two process steps of sputtering layer and second electroplating layer. , effectively improving the complexity of the existing process and its process cost.

又一方面而言,利用本發明所揭露之技術方案,基於僅使用單一材質的基材,可以在後續進行鑽孔製程時減少膠渣以及鑽污的產生,使其維持良好的潔淨度、製程可控、且單純度高。On the other hand, by using the technical solution disclosed in the present invention and using only a single material as a base material, the generation of slag and drilling dirt can be reduced during the subsequent drilling process, thereby maintaining good cleanliness and process quality. Controllable and simple.

除此之外,可以確立的是,通過本發明所公開之技術特徵及其技術手段,應用本發明所揭露之雙面導電的層疊結構,可進一步地廣泛應用於透明顯示裝置,進而有效提升本發明之應用性與符合市場需求。In addition, it can be established that through the technical features and technical means disclosed in the present invention, the double-sided conductive laminated structure disclosed in the present invention can be further widely used in transparent display devices, thereby effectively improving the present invention. The applicability of the invention and its compliance with market demand.

是以,鑒於以上所述,可明顯觀之,相較於習知技術,本發明係成功地解決先前技術中尚存的問題,經證實可實現顯著且更有效益的發明功效。故根據本發明所揭露之技術方案,確實具有極佳之產業利用性及競爭力。顯見本發明所揭露之技術特徵、方法手段與達成之功效係顯著地不同於現行方案,實非為熟悉該項技術者能輕易完成者,故應具備有專利要件。Therefore, in view of the above, it is obvious that compared with the conventional technology, the present invention successfully solves the existing problems in the prior art, and is proven to achieve significant and more effective inventive effects. Therefore, the technical solution disclosed in the present invention indeed has excellent industrial applicability and competitiveness. It is obvious that the technical features, methods and effects disclosed in the present invention are significantly different from existing solutions and cannot be easily accomplished by those familiar with the technology. Therefore, patent requirements should be met.

值得提醒的是,根據本發明所教示之技術方案,本領域具通常知識者當可在其實際實施層面上自行變化其設計,而皆屬於本發明之發明範圍。本發明在前述段落中所列舉出之數個示性例,其目的是為了善加解釋本發明主要之技術特徵,而使本領域人員可理解並據以實施之,惟本發明當不以該些示性例為限。It is worth reminding that based on the technical solutions taught in the present invention, those with ordinary knowledge in the art can change the design on their own at the actual implementation level, which all fall within the scope of the present invention. The purpose of the several illustrative examples listed in the preceding paragraphs of the present invention is to better explain the main technical features of the present invention, so that those in the art can understand and implement them accordingly. However, the present invention should not be based on these examples. Limited to some illustrative examples.

10…基板 11…導電層 12…金屬銅層 13…貫通孔 20…化鍍金屬層 22…介質層 40…基材 411…上表面 412…下表面 42…通孔 42A…梯形孔 42B…倒梯形孔 42C…不規則形孔 50…第一導電層 60…第二導電層 100…雙面導電的層疊結構 511…微結構 S111、S113、S115、S117…步驟 10…Substrate 11…conductive layer 12…metallic copper layer 13…through hole 20…Electroless metal plating layer 22…medium layer 40…Substrate 411…upper surface 412…lower surface 42…through hole 42A…trapezoidal hole 42B…inverted trapezoidal hole 42C…Irregular shaped hole 50…first conductive layer 60…Second conductive layer 100...Double-sided conductive laminated structure 511…Microstructure S111, S113, S115, S117… steps

第1A至第1F圖為先前技術採用厚銅基材製程之各步驟對應的結構示意圖。 第2圖為先前技術之厚銅基材中具有介質層之結構示意圖。 第3圖為依據第2圖結構形成化鍍金屬層時具有選擇性問題之結構示意圖。 第4A至4D圖為根據本發明實施例形成雙面導電的層疊結構之各製程步驟所對應之結構示意圖。 第5圖為根據本發明實施例雙面導電的層疊結構在基材表面形成有微結構之示意圖。 第6圖為先前技術未在基板之表面進行破壞以形成微結構之示意圖。 第7圖為根據本發明之一實施例在基材之表面進行破壞以形成微結構之示意圖。 第8圖係為根據本發明一實施例所公開具有梯形孔之示意圖。 第9圖係為根據本發明另一實施例所公開具有倒梯形孔之示意圖。 第10圖係為根據本發明再一實施例所公開具有不規則形孔之示意圖。 第11圖係為根據本發明實施例雙面導電的層疊結構的製造方法之步驟流程圖。 Figures 1A to 1F are schematic structural diagrams corresponding to each step of the prior art process using thick copper substrates. Figure 2 is a schematic diagram of the structure of a thick copper substrate with a dielectric layer in the prior art. Figure 3 is a schematic structural diagram of the selectivity problem when forming an electroless metal layer based on the structure of Figure 2. 4A to 4D are structural schematic diagrams corresponding to each process step of forming a double-sided conductive laminated structure according to embodiments of the present invention. Figure 5 is a schematic diagram of a double-sided conductive laminated structure with microstructures formed on the surface of a substrate according to an embodiment of the present invention. Figure 6 is a schematic diagram of the prior art without damaging the surface of the substrate to form microstructures. Figure 7 is a schematic diagram of destroying the surface of a substrate to form microstructures according to an embodiment of the present invention. Figure 8 is a schematic diagram of a trapezoidal hole according to an embodiment of the present invention. Figure 9 is a schematic diagram of an inverted trapezoidal hole according to another embodiment of the present invention. Figure 10 is a schematic diagram of an irregular-shaped hole according to yet another embodiment of the present invention. FIG. 11 is a flow chart of a method for manufacturing a double-sided conductive laminated structure according to an embodiment of the present invention.

40…基材 411…上表面 412…下表面 50…第一導電層 60…第二導電層 100…雙面導電的層疊結構 40…Substrate 411…upper surface 412…lower surface 50…first conductive layer 60…Second conductive layer 100...Double-sided conductive laminated structure

Claims (23)

一種雙面導電的層疊結構,包括:一基材,具有一上表面與相對於該上表面之一下表面,該基材之該上表面與該下表面之間係形成有至少一通孔;一第一導電層,其係覆蓋於該基材之該上表面、該下表面、以及該至少一通孔之孔壁;以及一第二導電層,其係覆蓋位於該基材之該上表面的該第一導電層,該第二導電層亦覆蓋位於該基材之該下表面的該第一導電層,從而使該基材之該上表面與該下表面提供電性導通;其中,在該第一導電層覆蓋該基材之該上表面、該下表面、以及該至少一通孔之孔壁的接觸面上係形成有至少一微結構,以通過該至少一微結構增加該第一導電層覆蓋時的附著力。 A double-sided conductive laminated structure includes: a base material having an upper surface and a lower surface relative to the upper surface; at least one through hole is formed between the upper surface and the lower surface of the base material; a first A conductive layer covering the upper surface, the lower surface, and the hole wall of at least one through hole of the base material; and a second conductive layer covering the third conductive layer located on the upper surface of the base material. A conductive layer, the second conductive layer also covers the first conductive layer located on the lower surface of the base material, thereby providing electrical conduction between the upper surface and the lower surface of the base material; wherein, in the first At least one microstructure is formed on the contact surface of the upper surface, the lower surface, and the hole wall of the at least one through hole covered by the conductive layer to increase the coverage of the first conductive layer through the at least one microstructure. of adhesion. 如請求項1所述之雙面導電的層疊結構,其中,該第一導電層係通過一化鍍製程而形成。 The double-sided conductive laminated structure as claimed in claim 1, wherein the first conductive layer is formed through an electroless plating process. 如請求項1所述之雙面導電的層疊結構,其中,該第二導電層係通過一電鍍製程而形成。 The double-sided conductive laminated structure as claimed in claim 1, wherein the second conductive layer is formed through an electroplating process. 如請求項1所述之雙面導電的層疊結構,其中,該第一導電層之材質為金屬或其合金。 The double-sided conductive laminated structure as claimed in claim 1, wherein the first conductive layer is made of metal or an alloy thereof. 如請求項4所述之雙面導電的層疊結構,其中,該第一導電層之材質為銅。 The double-sided conductive laminated structure as claimed in claim 4, wherein the first conductive layer is made of copper. 如請求項1所述之雙面導電的層疊結構,其中,該至少一微結構係呈鋸齒狀。 The double-sided conductive laminated structure as claimed in claim 1, wherein the at least one microstructure is in a zigzag shape. 如請求項1所述之雙面導電的層疊結構,其中,該至少一微結構係具有凹凸之高度差。 The double-sided conductive laminated structure as claimed in claim 1, wherein the at least one microstructure has a height difference between concave and convex. 如請求項1所述之雙面導電的層疊結構,其中,該第一導電層之厚度係介於0.3至3.0微米之間。 The double-sided conductive laminated structure as claimed in claim 1, wherein the thickness of the first conductive layer is between 0.3 and 3.0 microns. 如請求項1所述之雙面導電的層疊結構,其中,該第一導電層之均勻性係小於20%。 The double-sided conductive laminated structure as claimed in claim 1, wherein the uniformity of the first conductive layer is less than 20%. 如請求項1所述之雙面導電的層疊結構,其中,該基材之材質為透明或半透明材料。 The double-sided conductive laminated structure as claimed in claim 1, wherein the substrate is made of a transparent or translucent material. 如請求項1所述之雙面導電的層疊結構,其中,該基材之厚度係大於25微米。 The double-sided conductive laminated structure as claimed in claim 1, wherein the thickness of the substrate is greater than 25 microns. 如請求項1所述之雙面導電的層疊結構,其中,該基材之穿透率係大於80%。 The double-sided conductive laminated structure as claimed in claim 1, wherein the transmittance of the substrate is greater than 80%. 一種雙面導電的層疊結構的製造方法,包括以下步驟:提供一基材,該基材具有一上表面與相對於該上表面之一下表面;在該基材之該上表面與該下表面之間係形成有至少一通孔;通過一化鍍製程形成一第一導電層,該第一導電層係覆蓋該基材之該上表面、該下表面、以及該至少一通孔之孔壁;以及通過一電鍍製程形成一第二導電層,其係覆蓋位於該基材之該上表面的該第一導電層,該第二導電層亦覆蓋位於該基材之該下表面的該第一導電層,從而使該基材之該上表面與該下表面提供電性導通。 A method for manufacturing a double-sided conductive laminated structure, including the following steps: providing a base material having an upper surface and a lower surface relative to the upper surface; between the upper surface and the lower surface of the base material At least one through hole is formed between them; a first conductive layer is formed through a chemical plating process, and the first conductive layer covers the upper surface, the lower surface of the substrate, and the hole wall of the at least one through hole; and through An electroplating process forms a second conductive layer that covers the first conductive layer located on the upper surface of the substrate, and the second conductive layer also covers the first conductive layer located on the lower surface of the substrate, Thereby, the upper surface and the lower surface of the base material are electrically connected. 如請求項13所述之雙面導電的層疊結構的製造方法,其中,該第一導電層之材質為金屬或其合金。 The manufacturing method of a double-sided conductive laminated structure as claimed in claim 13, wherein the material of the first conductive layer is metal or an alloy thereof. 如請求項14所述之雙面導電的層疊結構的製造方法,其中,該第一導電層之材質為銅。 The manufacturing method of a double-sided conductive laminated structure as claimed in claim 14, wherein the first conductive layer is made of copper. 如請求項13所述之雙面導電的層疊結構的製造方法,其中,在通過該化鍍製程形成該第一導電層的步驟中,更包括:在該第一導電層覆蓋 該基材之該上表面、該下表面、以及該至少一通孔之孔壁的接觸面上形成至少一微結構,以通過該至少一微結構增加該第一導電層覆蓋時的附著力。 The manufacturing method of a double-sided conductive laminated structure as claimed in claim 13, wherein the step of forming the first conductive layer through the electroless plating process further includes: covering the first conductive layer At least one microstructure is formed on the contact surface of the upper surface, the lower surface, and the hole wall of the at least one through hole of the substrate, so as to increase the adhesion when covering the first conductive layer through the at least one microstructure. 如請求項16所述之雙面導電的層疊結構的製造方法,其中,該至少一微結構係呈鋸齒狀。 The manufacturing method of a double-sided conductive laminated structure as claimed in claim 16, wherein the at least one microstructure is in a zigzag shape. 如請求項16所述之雙面導電的層疊結構的製造方法,其中,該至少一微結構係具有凹凸之高度差。 The manufacturing method of a double-sided conductive laminated structure as claimed in claim 16, wherein the at least one microstructure has a height difference between concave and convex. 如請求項13所述之雙面導電的層疊結構的製造方法,其中,該第一導電層之厚度係介於0.3至3.0微米之間。 The manufacturing method of a double-sided conductive laminated structure as claimed in claim 13, wherein the thickness of the first conductive layer is between 0.3 and 3.0 microns. 如請求項13所述之雙面導電的層疊結構的製造方法,其中,該第一導電層之均勻性係小於20%。 The manufacturing method of a double-sided conductive laminated structure as claimed in claim 13, wherein the uniformity of the first conductive layer is less than 20%. 如請求項13所述之雙面導電的層疊結構的製造方法,其中,該基材之材質為透明或半透明材料。 The manufacturing method of a double-sided conductive laminated structure as claimed in claim 13, wherein the base material is made of a transparent or translucent material. 如請求項13所述之雙面導電的層疊結構的製造方法,其中,該基材之厚度係大於25微米。 The method for manufacturing a double-sided conductive laminated structure as claimed in claim 13, wherein the thickness of the substrate is greater than 25 microns. 如請求項13所述之雙面導電的層疊結構的製造方法,其中,該基材之穿透率係大於80%。The manufacturing method of a double-sided conductive laminated structure as claimed in claim 13, wherein the transmittance of the substrate is greater than 80%.
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