TWI817049B - 用於積體電路之背面整合式電壓調節器 - Google Patents

用於積體電路之背面整合式電壓調節器 Download PDF

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TWI817049B
TWI817049B TW109135652A TW109135652A TWI817049B TW I817049 B TWI817049 B TW I817049B TW 109135652 A TW109135652 A TW 109135652A TW 109135652 A TW109135652 A TW 109135652A TW I817049 B TWI817049 B TW I817049B
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package
die
voltage regulator
integrated voltage
asic
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TW202131420A (zh
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楠勳 金
權雲星
甘後樂
沈柔政
米卡伊爾 波波維奇
澤圭 姜
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美商谷歌有限責任公司
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Abstract

本技術係關於一種積體電路(IC)封裝。該IC封裝可包括一封裝基板、一IC晶粒及一整合式電壓調節器晶粒。該IC晶粒可包括一金屬層及一矽層。該金屬層可連接至該封裝基板。該整合式電壓調節器晶粒可鄰近於該矽層定位，並經由一或多個穿模通孔或穿介電質通孔連接至該封裝基板。該IC晶粒可為一特殊應用積體電路(ASIC)晶粒。

Description

用於積體電路之背面整合式電壓調節器
包括一或多個特殊應用積體電路(ASIC)晶粒之ASIC封裝正在變得愈來愈有能力進行高速處理。隨著ASIC晶粒之處理速度繼續增加，由ASIC晶粒消耗之電力亦可能增加。ASIC晶粒之電力消耗之增加可能導致ASIC封裝內之熱增加，此可能導致ASIC封裝中之組件發生故障或降低ASIC封裝之效能。
本發明之一個態樣提供一種積體電路(IC)封裝。該IC封裝可包括一封裝基板、一IC晶粒及一整合式電壓調節器晶粒。該IC晶粒可包括一金屬層及一矽層。該金屬層可連接至該封裝基板。該整合式電壓調節器晶粒可鄰近於該矽層定位，並經由一或多個穿模通孔(TMV)或穿介電質通孔(TDV)連接至該封裝基板。
在一些情況下，該整合式電壓調節器晶粒被一配電網路(PDN)連接至該矽層。在一些實例中，該PDN包括在該矽層內之一或多個穿矽通孔(TSV)。在一些實例中，該PDN進一步包括一重佈層，該重佈層經組態以自該整合式電壓調節器晶粒提供電力給該等TSV。在一些實例 中，該等TSV及該重佈層形成一電感器。
在一些情況下，該一或多個TMV中之每一TMV在一第一端上被一覆晶凸塊連接至該封裝基板並在一第二相對端處連接至該整合式電壓調節器晶粒。
在一些情況下，該矽層經由一或多個覆晶凸塊連接至該封裝基板。
在一些情況下，該封裝基板經組態以連接至一平台柵格陣列(LGA)插座或球狀柵格陣列(BGA)插座。在一些實例中，電力經由該LGA插座或該BGA插座輸送至該整合式電壓調節器晶粒。在一些實例中，該封裝基板包括一重佈層，該重佈層經組態以將該電力自該LGA插座或該BGA插座路由至該一或多個TMV。
本技術之另一態樣係關於一種積體電路(IC)封裝，該積體電路(IC)封裝包括一封裝基板、一特殊應用積體電路(ASIC)晶粒及一整合式電壓調節器晶粒。該ASIC晶粒可包括一金屬層及一矽層，該金屬層連接至該封裝基板。該整合式電壓調節器晶粒可鄰近於該矽層定位，並經由一或多個穿模通孔(TMV)或穿介電質通孔(TDV)連接至該封裝基板，該整合式電壓調節器晶粒經組態以提供電力給該ASIC晶粒。
在一些情況下，該整合式電壓調節器晶粒被一配電網路(PDN)連接至該矽層。在一些實例中，該PDN包括在該矽層內之一或多個穿矽通孔(TSV)，且該整合式電壓調節器晶粒經組態以經由該等TSV提供電力給該ASIC晶粒。在一些實例中，該PDN進一步包括一重佈層，該重佈層經組態以自該整合式電壓調節器晶粒提供電力給該等TSV。在一些實例中，該等TSV及該重佈層形成一電感器。
在一些情況下，該一或多個TMV中之每一TMV在一第一端上被一覆晶凸塊連接至該封裝基板並在一第二相對端處連接至該整合式電壓調節器晶粒。
在一些情況下，該矽層經由一或多個覆晶凸塊連接至該封裝基板。
在一些情況下，該封裝基板經組態以連接至一平台柵格陣列(LGA)插座或球狀柵格陣列(BGA)插座。在一些實例中，電力經由該LGA插座或該BGA插座輸送至該整合式電壓調節器晶粒。在一些實例中，該封裝基板包括一重佈層，該重佈層經組態以將該電力自該LGA插座或該BGA插座路由至該一或多個TMV。
在一些情況下，該IC封裝進一步包括深渠溝電容器，該等深渠溝電容器嵌入至該矽層中或堆疊在該矽層上以供該整合式電壓調節器晶粒使用。
101:ASIC封裝
103:ASIC晶粒
105:整合式電壓調節器晶粒/ASIC晶粒
107:背面配電網路PDN
109:封裝基板
119:頂側
129:底側
131:矽基板
133:金屬層
140:外殼
171:穿矽通孔(TSV)
173:重佈層
191:連接器/連接器襯墊
192:連接器/連接器襯墊
193:連接器/連接器襯墊
197:連接器
198:連接器
199:連接器
301:部分
305:TMV
315:第一端
325:相對端
396:覆晶凸塊
397:連接器襯墊
398:經焊接覆晶凸塊
399:連接器襯墊
405:TMV
409:PCB
470:TSV
480:箭頭/電力
490:箭頭/電力
492:連接器
494:連接器襯墊
509:封裝基板
519:頂側
590:連接器外部集合/外部
595:連接器內部集合/內部
601:ASIC封裝
605:整合式電壓調節器晶粒/ASIC晶粒
607:ASIC晶粒
609:封裝基板
615:TMV
695:連接器內部集合
696:箭頭
圖1係根據本發明之態樣的具有整合式電壓調節器晶粒之ASIC封裝的側剖視圖。
圖2A係根據本發明之態樣之封裝基板的俯視圖。
圖2B係根據本發明之態樣之封裝基板之底部的視圖。
圖3A係根據本發明之態樣的具有整合式電壓調節器晶粒之ASIC封裝的側剖視圖。
圖3B係根據本發明之態樣之ASIC封裝之一部分的分解側剖視圖。
圖4A係根據本發明之態樣之ASIC封裝的側剖視圖，其展 示向整合式電壓調節器晶粒之電力輸送。
圖4B係根據本發明之態樣之ASIC封裝的側剖視圖，其展示自整合式電壓調節器晶粒向ASIC晶粒之電力輸送。
圖5係根據本發明之態樣的具有內部連接器及外部連接器之封裝基板的俯視圖。
圖6係根據本發明之態樣之ASIC封裝的側剖視圖，其展示資料通信。
本技術大體上係關於將電壓調節器晶粒整合至特殊應用積體電路(ASIC)封裝之背面上。例如，且如圖1中所展示，ASIC封裝101包括ASIC晶粒103，ASIC晶粒103包括矽基板131(其亦可稱為矽層131)及一或多個金屬層133。ASIC晶粒103可被定位成使得金屬層鄰近於封裝基板109。整合式電壓調節器晶粒105可鄰近於矽基板131安裝至ASIC晶粒103之背面。電力可由整合式電壓調節器晶粒105使用背面配電網路PDN 107輸送至ASIC晶粒103，背面配電網路PDN 107包括穿矽通孔(TSV)171及重佈層173。ASIC封裝101可包括外殼，諸如外殼140，ASIC封裝101之組件中之至少一些組件可位於該外殼中。
如先前所描述，ASIC晶粒之處理速度之增加可增加操作ASIC晶粒所需之電力量。歸因於由通過典型ASIC封裝載送電力之導線及/或其他此類連接產生之銅損耗，在ASIC封裝內由ASIC晶粒汲取之電力之增加可能導致ASIC封裝內之熱增加。銅損耗，亦被稱為「I2R損耗」，係在電流通過佈線時耗散之熱量，其中「I」係流過銅佈線之電流且「R」係佈線之電阻。由ASIC晶粒增加之電力汲取所產生的溫度之升高可能導致 焊接點之焊料電遷移及潛在故障。溫度之升高亦可能影響ASIC封裝內之ASIC晶粒及其他組件之熱效能，從而可能導致ASIC晶粒之故障、ASIC封裝之其他組件之故障或降低之處理效能。
為了減少或補救由導線、諸如銅平面之平面、重佈層及/或通過ASIC封裝將電力載送至ASIC晶粒之其他此類連接所產生之銅損耗量，可將電壓調節器整合至ASIC封裝中。
封裝基板109可經組態以將ASIC封裝101連接至電路板或其他此類晶片載體。就此而言，分別如圖2A及圖2B中所展示，封裝基板109可在其頂側及底側上具有連接器陣列。在一些情況下，連接器可包括在封裝基板109之側上。參考圖1，儘管封裝基板109被展示為在外殼140外部，但封裝基板109可完全或部分地定位在外殼140內。
參考圖2A，封裝基板109之頂側119展示複數個連接器，包括連接器191至193。為了清楚起見，僅標記了封裝基板109之頂側119上之連接器之一部分。如本文中所描述，包括連接器191至193之連接器可為連接器襯墊，ASIC封裝101之其他組件可連接至該等連接器襯墊上。連接器襯墊可為金、鎳、錫、銅、焊料或其他此類導電材料。
封裝基板109之頂側119可包括以任何佈局配置之任何數目個連接器襯墊。就此而言，圖2A中所展示之包括連接器襯墊191至193之連接器之配置及數目僅僅用於繪示。例如，封裝基板之頂側上之連接器襯墊之數目及配置可基於ASIC封裝101內之ASIC晶粒103、整合式電壓調節器晶粒105及/或其他組件之設計及配置，以允許將ASIC封裝附接至封裝基板119之頂側。
圖2B展示封裝基板之底側129，底側129包括複數個連接 器，包括連接器197至199。為了清楚起見，僅標記了底側129上之連接器之一部分。包括連接器197至199之連接器可經組態以將ASIC封裝101連接至或以其他方式安裝至印刷電路板(PCB)、插座或其他此類晶片載體。連接器可為焊球、接腳、插座等等。連接器197至199可為金、鎳、錫、銅、焊料或其他此類導電材料。
封裝基板之底側129可包括任何配置之任何數目個連接器。就此而言，圖2B中所展示之包括連接器197至199之連接器之配置及數目僅僅用於繪示。例如，封裝基板之底側129上之連接器可為配置為球狀柵格陣列(BGA)之焊球。其他此類配置及連接器可包括以平台柵格陣列(LGA)配置之觸點、以接腳柵格陣列(PGA)配置之連接器接腳等等。
整合式電壓調節器晶粒105可連接至封裝基板109之頂側119上之一或多個連接器襯墊。例如，如圖3A中所展示，電壓調節器晶粒105與封裝基板109之間的連接可經由一或多個穿模通孔(TMV)來進行，諸如TMV 305。為了清楚起見，僅標記了圖3A中所展示之TMV之一部分。
每一TMV可經由連接器襯墊或其他此類連接器將整合式電壓調節器晶粒105連接至封裝基板109。例如，TMV 305之第一端315可附接至連接器襯墊399，且TMV 305之相對端325可附接至整合式電壓調節器晶粒105。
TMV與連接器襯墊之間的連接可經由經焊接覆晶凸塊來進行。例如，圖3B展示ASIC封裝101之部分301的分解側視圖，部分301包括TMV 305與連接器襯墊399之間的連接。TMV 305之第一端315經由經焊接覆晶凸塊398在封裝基板109之頂側119上連接至連接器襯墊399。儘 管在圖3B中將TMV展示為經由經焊接覆晶凸塊連接，但可使用其他連接器及連接。
ASIC晶粒103之金屬層133亦可連接至封裝基板109。金屬層133至封裝基板109之連接可經由覆晶凸塊及連接器襯墊或其他此類連接器來進行。例如，且如圖3B中進一步所展示，覆晶凸塊396在封裝基板之頂側119上將金屬層133連接至連接器襯墊397。儘管在圖3B中將覆晶凸塊展示為焊接至連接器襯墊上，諸如將覆晶凸塊396焊接至連接器襯墊397上，但可使用其他連接。
可由外部電源將電力供應至ASIC封裝101。就此而言，外部電源可通過晶片載體提供電力給ASIC封裝101，ASIC封裝101安裝至該晶片載體。例如，且如圖4A中所繪示，被展示為箭頭490之電力可自外部電源(未展示)供應至PCB 409。PCB 409可將電力供應至封裝基板上之連接器。
封裝基板可包括重佈層，該重佈層被蝕刻至該封裝基板上或以其他方式嵌入在該封裝基板內，該重佈層將電力在該封裝基板之底側129上之連接器與封裝基板109之頂側上之連接器襯墊119之間進行路由。例如，在封裝基板109之底側129上之連接器492處由PCB或其他此類晶片安裝件輸送之電力490可由重佈層路由至封裝基板之頂側119上之連接器襯墊494。儘管圖4A繪示電力490供應至連接器492並路由至連接器襯墊494，但電力可供應至封裝基板109之底側上之連接器中之任一連接器，且在一些情況下供應至多於一個連接器。電力可由重佈層自一或多個連接器路由至連接器襯墊中之一或多個連接器襯墊。例如，電力可自封裝基板109之底側129上之連接器中之一或多個連接器路由至封裝基板109之頂側 119上之一個、兩個、三個或更多個連接器襯墊。
電力可由一或多個TMV自封裝基板109載送至整合式電壓調節器晶粒105。例如，圖4A展示電力490被TMV 405自連接器襯墊494路由至整合式電壓調節器晶粒105。為了清楚起見，電力被展示為僅通過TMV 405路由。在一些情況下，電力可由多於一個TMV路由至整合式電壓調節器晶粒105。
由整合式電壓調節器晶粒接收之電力可被視為輸入電力供應。該輸入電力供應相比於直接輸送至ASIC晶粒之輸入電力供應可以較高電壓位準及較低電流位準輸送至整合式電壓調節器晶粒105。整合式電壓調節器晶粒105可以不同供應電壓位準提供電力給ASIC晶粒103。例如，整合式電壓調節器晶粒105可作為開關電壓調節器操作，並基於ASIC封裝101內之ASIC晶粒或其他組件之需要來調節供應至ASIC晶粒之電壓量。
整合式電壓調節器晶粒105可經由背面TSV將電力輸送至ASIC晶粒103。例如，且如圖4B中所展示，由箭頭480繪示之電力可自整合式電壓調節器晶粒105提供至重佈層173。重佈層173可將電力引導至嵌入在ASIC晶粒103之矽層131內之一或多個TSV 470，包括TSV 171。儘管圖4B繪示電力輸送至所有TSV 470，但電力可輸送至任何數目個TSV。
參考圖4B，重佈層173可被蝕刻至矽層131中及/或定位在矽層131上方。重佈層173與TSV一起可用於產生供整合式電壓調節器晶粒105使用之電感器。深渠溝電容器(DTC)亦可嵌入至ASIC晶粒103之矽層131中以供整合式電壓調節器晶粒105使用。就此而言，開關電壓調節器通常需要很多電感器及電容器來操作。在整合式電壓調節器晶粒105係 開關電壓調節器的情況下，重佈層173、TSV 470以及DTC之嵌入式矽(未展示)可提供電感器及電容器之至少一些功能性。在一些情況下，電感器及DTC可堆疊至ASIC晶粒上。
如本文中所論述，增加ASIC晶粒之處理速度可增加操作ASIC晶粒所需之電力量。歸因於由通過ASIC封裝載送電力之導線及/或其他此類連接所產生之銅損耗，不具有整合式電壓調節器晶粒之ASIC封裝內之ASIC晶粒汲取之電力之增加可能會導致ASIC封裝內之熱增加。藉由在ASIC封裝中整合整合式電壓調節器晶粒，諸如在ASIC封裝101中整合整合式電壓調節器晶粒105，可限制、控制或以其他方式調節ASIC封裝自外部電源汲取之電力。例如，整合式電壓調節器晶粒105可對ASIC封裝101內之組件(諸如ASIC晶粒103)汲取之電力量加上限(cap)。在一些實例中，整合式電壓調節器晶粒105可包括閉合迴路回饋系統以提供穩定電壓輸出。
在另一實例中，諸如當ASIC晶粒103之溫度高於特定值或ASIC晶粒103不需要全電力進行操作時，整合式電壓調節器晶粒105可節流所汲取之電力量。整合式電壓調節器晶粒105亦可接受較高輸入電壓，藉此減少由外部電力供應器(external power supply)供應至ASIC封裝101之電流。因此，可減少由ASIC封裝上或ASIC封裝內之導線、跡線及/或其他此類連接所載送之電流量，從而減少銅損耗量，並最小化ASIC封裝中之電遷移故障風險。此外，整合式電壓調節器晶粒105可減少總電力消耗並提高ASIC封裝101之電力效率。
電壓調節器可維持來自外部電源之一致電力汲取，藉此防止或減少由ASIC封裝101上或ASIC封裝101內之導線、跡線及/或其他此 類連接所載送之電力增加之次數。在一些情況下，整合式電壓調節器晶粒105可包括閉合迴路回饋系統以最小化輸出之電壓波動。就此而言，回饋感測線可監測由整合式電壓調節器晶粒105輸出之電壓，並將所監測之電壓位準回饋至整合式電壓調節器晶粒105。回饋感測線可具有高頻寬，因此整合式電壓調節器晶粒105可能夠快速地補償電壓波動。藉此，可減少由電壓波動引起之感應雜訊。
典型的ASIC晶粒將自封裝基板上較靠近ASIC晶粒之連接器接收電力，以減少由電力輸送所產生之熱量。因此，可能需要使資料信號穿越自ASIC晶粒至位於封裝基板之外部上之連接器的較長路徑，藉此減慢了ASIC封裝之處理速度。圖5繪示分別在封裝基板509之頂側519上之連接器內部集合595及外部集合590。在典型的ASIC封裝中，電力可由封裝基板509之內部集合595內之連接器輸送，且資料可由封裝基板509之外部集合590內之連接輸送。
參考圖6，藉由在ASIC晶粒607上方定位整合式電壓調節器晶粒605，並經由位於ASIC晶粒607之外部周圍之TMV 615將整合式電壓調節器晶粒505連接至封裝基板，ASIC晶粒607與封裝基板609之間的資料連接可移動至連接器內部集合695。因此，可減少資料自ASIC晶粒607行進至封裝基板609所需要之距離資料，如由箭頭696所繪示，從而提高了通信速度並減少了信號損失。資料連接可由封裝基板中之重佈層路由，且可包括SERDES連接、並列連接、串列連接等等。
儘管分別參考單一ASIC晶粒103、607描述了本文中所描述之實例ASIC封裝101及601，但每一ASIC封裝可包括任何數目個ASIC晶粒。此外，每一ASIC封裝可包括任何數目個電壓調節器或其他組件。 另外，儘管本文中所描述之封裝被描述為具有ASIC晶粒之ASIC封裝，但可使用任何類型之晶粒，諸如記憶體晶粒或積體電路晶粒。
本文中所描述之特徵允許將整合式電壓調節器晶粒整合至ASIC封裝中。藉此，可減少由將電力通過ASIC封裝載送至ASIC晶粒之導線、跡線及/或其他此類連接所產生之銅損耗。此外，藉由在ASIC晶粒上方定位整合式電壓調節器晶粒，可減少ASIC晶粒與PCB之間的距離資料通信行進。
儘管已參考特定實施例描述了本文中之技術，但應理解，此等實施例僅僅說明本技術之原理及應用。因此，應理解，在不脫離如由所附申請專利範圍所界定的本技術之精神及範疇的情況下，可對說明性實施例作出多種修改，且可設計出其他配置。
101:ASIC封裝
103:ASIC晶粒
105:整合式電壓調節器晶粒/ASIC晶粒
107:背面配電網路PDN
109:封裝基板
131:矽基板
133:金屬層
140:外殼
171:穿矽通孔(TSV)
173:重佈層

Claims (20)

  1. 一種積體電路(IC)封裝，其包含：一封裝基板；一IC晶粒，該積體電路晶粒包括一金屬層及一矽層，該金屬層連接至該封裝基板；及一整合式電壓調節器晶粒，其經組態以提供電力至該IC晶粒，該整合式電壓調節器晶粒鄰近於該矽層定位，並經由一或多個穿模通孔(TMV)或一或多個穿介電質通孔(TDV)連接至該封裝基板，其中該整合式電壓調節器晶粒經組態以經由該一或多個TMV或該一或多個TDV接收電力。
  2. 如請求項1之IC封裝，其中該整合式電壓調節器晶粒被一配電網路(PDN)連接至該矽層。
  3. 如請求項2之IC封裝，其中該PDN包括在該矽層內之一或多個穿矽通孔(TSV)。
  4. 如請求項3之IC封裝，其中該PDN進一步包括一重佈層，該重佈層經組態以自該整合式電壓調節器晶粒提供電力給該一或多個TSV。
  5. 如請求項4之IC封裝，其中該一或多個TSV及該重佈層形成一電感器。
  6. 如請求項1之IC封裝，其中該一或多個TMV或TDV中之每一者在一第一端上被一覆晶凸塊連接至該封裝基板並在一第二相對端處連接至該整合式電壓調節器晶粒。
  7. 如請求項1之IC封裝，其中該矽層經由一或多個覆晶凸塊連接至該封裝基板。
  8. 如請求項1之IC封裝，其中該封裝基板經組態以連接至一平台柵格陣列(LGA)插座或球狀柵格陣列(BGA)插座。
  9. 如請求項8之IC封裝，其中電力經由該LGA插座或該BGA插座輸送至該整合式電壓調節器晶粒。
  10. 如請求項9之IC封裝，其中該封裝基板包括一重佈層，該重佈層經組態以將該電力自該LGA插座或該BGA插座路由至該一或多個TMV。
  11. 一種積體電路(IC)封裝，其包含：一封裝基板；一特殊應用積體電路(ASIC)晶粒，該ASIC晶粒包括一金屬層及一矽層，該金屬層連接至該封裝基板；及一整合式電壓調節器晶粒，該整合式電壓調節器晶粒鄰近於該矽層定位，並經由一或多個穿模通孔(TMV)或一或多個穿介電質通孔(TDV)連接至該封裝基板，該整合式電壓調節器晶粒經組態以提供電力給該ASIC 晶粒，其中該整合式電壓調節器晶粒經組態以經由該一或多個TMV或該一或多個TDV接收電力。
  12. 如請求項11之IC封裝，其中該整合式電壓調節器晶粒被一配電網路(PDN)連接至該矽層。
  13. 如請求項12之IC封裝，其中該PDN包括在該矽層內之一或多個穿矽通孔(TSV)，且該整合式電壓調節器晶粒經組態以經由該一或多個TSV提供電力給該ASIC晶粒。
  14. 如請求項13之IC封裝，其中該PDN進一步包括一重佈層，該重佈層經組態以自該整合式電壓調節器晶粒提供電力給該一或多個TSV。
  15. 如請求項14之IC封裝，其中該一或多個TSV及該重佈層形成一電感器以供該整合式電壓調節器晶粒使用。
  16. 如請求項11之IC封裝，其中該一或多個TMV或TDV中之每一者在一第一端上被一覆晶凸塊連接至該封裝基板並在一第二相對端處連接至該整合式電壓調節器晶粒。
  17. 如請求項11之IC封裝，其中該矽層經由一或多個覆晶凸塊連接至該封裝基板。
  18. 如請求項11之IC封裝，其中該封裝基板經組態以連接至一平台柵格陣列(LGA)插座或球狀柵格陣列(BGA)插座。
  19. 如請求項18之IC封裝，其中電力經由該LGA插座或該BGA插座輸送至該整合式電壓調節器晶粒，且該封裝基板包括一重佈層，該重佈層經組態以將該電力自該LGA插座或該BGA插座路由至該一或多個TMV或TDV。
  20. 如請求項15之IC封裝，其進一步包含深渠溝電容器，該等深渠溝電容器嵌入至該矽層中或堆疊在該矽層上以供該整合式電壓調節器晶粒使用。
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