TWI813455B - Address conversion system and address conversion method - Google Patents

Abstract

An address translation conversion includes a storage device, a memory bus and a processor. The processor is configured for executing the following steps according to a plurality of commands of the storage device: creating a real buffer on the storage device; generating a fake buffer in the fake capacity of the storage device by creating a fake buffer algorithm; establishing a coupling relationship between a real buffer and a fake buffer through a coupling algorithm of the memory bus; receiving a compressed data from a first device by the real buffer; when the second device wants to read the fake buffer, a coupler of the memory bus guides the second device to the real buffer through the coupling relationship for reading; transmitting the compressed data of the real buffer to the coupler by the memory bus; decompressing the compressed data into a decompressed data by the coupler.

Description

Address translation system and address translation method

This case relates to a conversion system and a conversion method, and in particular to an address conversion system and an address conversion method.

Currently, data transmission between hardware (or components) on a System on a Chip (SOC) requires a buffer (Buffer) set in the memory to play the role of intermediate data transmission, and is assisted by other devices. Compress and decompress data so that two components with different addresses can transmit data smoothly. However, two different components usually require two buffers, but the two buffers will consume resources in the memory, causing a waste of resources. It also leads to the situation that only transmitting data consumes resources in the memory.

This summary is intended to provide a simplified summary of the disclosure to provide the reader with a basic understanding of the disclosure. This summary is not an extensive overview of the disclosure, and it is not intended to identify key/critical elements of the embodiments or to delineate the scope of the disclosure.

One of the technical aspects of this case relates to an address translation system. The address translation system includes storage devices, memory buses, and processors. A memory bus is used to couple a first device to a second device. The processor is used to perform the following steps according to a plurality of instructions of the storage device: generate a physical buffer in the storage device; generate a virtual buffer in the virtual capacity of the storage device through a virtual buffer algorithm; use a coupler of the memory bus Establish a coupling relationship between the physical buffer and the virtual buffer through a coupling algorithm; use the physical buffer to receive compressed data from the first device; when the second device wants to read the virtual buffer, use the coupler to guide through the coupling relationship The second device reads the physical buffer; transmits the compressed data of the physical buffer to the coupler through the memory bus; decompresses the compressed data into decompressed data through the coupler; and uses the memory bus Transfer the decompressed data to the second device.

Another technical aspect of this case relates to an address translation method. The address translation method includes: generating a physical buffer in the storage device; generating a virtual buffer in the virtual capacity of the storage device through a virtual buffer algorithm; using the memory bus to create a physical buffer and a virtual buffer through a coupling algorithm The coupling relationship; receiving compressed data from the first device through the physical buffer; when the second device wants to read the virtual buffer, the coupler guides the second device to the physical buffer for reading through the coupling relationship; borrow The compressed data in the physical buffer is transmitted to the coupler through the memory bus; the compressed data is decompressed into decompressed data through the coupler; and the decompressed data is transmitted to the second device through the memory bus.

Therefore, according to the technical content of this case, the address translation system and address translation method shown in the embodiment of this case can reduce the consumption of resources in the memory, so as to achieve the effect of transferring data between two hardwares with different addresses.

After referring to the following embodiments, those with ordinary knowledge in the technical field to which this case belongs can easily understand the basic spirit and other purposes of the invention, as well as the technical means and implementation styles adopted in this case.

In order to make the description of this disclosure more detailed and complete, the following provides an illustrative description of the implementation aspects and specific embodiments of this case; but this is not the only form of implementing or using the specific embodiments of this case. The embodiments cover features of multiple specific embodiments as well as method steps and their sequences for constructing and operating these specific embodiments. However, other specific embodiments may also be used to achieve the same or equivalent functions and step sequences.

Unless otherwise defined in this specification, the scientific and technical terms used herein have the same meanings as commonly understood and customary by a person with ordinary knowledge in the technical field to which the subject matter belongs. In addition, unless there is conflict with the context, the singular noun used in this specification covers the plural form of the noun; and the plural noun used also covers the singular form of the noun.

In addition, as used herein, "coupling" or "connection" may refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other, or it may also refer to two or more components that are in direct physical or electrical contact with each other. components interact or act with each other.

Certain words are used in the specification and patent claims to refer to specific components. However, those with ordinary skill in the art will understand that the same components may be referred to by different names. The specification and the patent application do not use the difference in name as a way to distinguish components, but the difference in function of the components as the basis for differentiation. The "include" mentioned in the specification and the scope of the patent application is an open-ended term, so it should be interpreted as "include but not limited to".

Figure 1 is a schematic block diagram of an address translation system according to an embodiment of the present invention. As shown in the figure, the address translation system 100 includes a storage device 110, a memory bus 120 and a processor 130. In connection relationship, the storage device 110 is coupled to the memory bus 120 , and the memory bus 120 is coupled to the processor 130 .

In order to reduce the consumption of memory resources and achieve the effect of transferring data between two hardwares with different addresses, this project provides an address conversion system 100 as shown in Figure 1, and its related operations are described in detail below.

In one embodiment, the coupler 121 of the memory bus 120 is used to couple the first device 900 to the second device 910 . In one embodiment, the processor 130 is used to perform the following steps according to a plurality of instructions of the storage device 110: generate a physical buffer 111 in the storage device 110; generate a virtual buffer 111 in the virtual capacity of the storage device 110 through a virtual buffer algorithm. Buffer 113; establish a coupling relationship between the physical buffer 111 and the virtual buffer 113 through the coupling algorithm through the coupler 121 of the memory bus 120; receive compressed data from the first device 900 through the physical buffer 111; when the When the two devices 910 want to read the virtual buffer 113, the coupler 121 guides the second device 910 to the physical buffer 111 for reading through the coupling relationship; the memory bus 120 compresses the compressed data of the physical buffer 111. transmitted to the coupler 121; decompressing the compressed data into decompressed data through the coupler 121; and transmitting the decompressed data to the second device 910 through the memory bus 120.

In order to make the above operations of the address translation system 100 easy to understand, please also refer to Figure 2 . Figure 2 is a block diagram of a processor of an address translation system according to an embodiment of the present invention.

Please also refer to FIG. 1 . In operation, in one embodiment, the coupler 121 of the memory bus 120 is used to couple the first device 900 to the second device 910 . For example, the coupler 121 of the memory bus 120 may be used to map, bind, or couple the first device 900 to the second device 910 . In some embodiments, the first device 900 may contain one address, the second device 910 may contain another address, and the coupler 121 of the memory bus 120 may be used to map and combine the addresses of the first device 900 Or coupled to another address of the second device 910, but this case is not limited to this.

In addition, in some embodiments, the first device 900 may be an in-house IP, that is, a component produced by the own company. In addition, the first device 900 may also be a video decoder. The second device 910 can be an outsourced product (Vendor IP), that is, a component produced by an outsourced company. In addition, the second device 910 can also be a graphics processor (Graphics Processing Unit, GPU), but this case does not apply. limit. In some embodiments, the first device 900 and the second device 910 may be located on a system on a chip (SOC), but the present case is not limited to this. In some embodiments, the first device 900 can also be a graphics processing unit (GPU), and the second device 910 can also be a video decoder. In this case, the memory bus 120 can have a decompression function. The design (Design) or function (Function) of the data in the graphics processor, but this case is not limited to this.

In some embodiments, the processor 130 is configured to perform the following steps according to a plurality of instructions from the storage device 110: generating the physical buffer 111 in the storage device 110. For example, the storage device 110 can be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM, hereinafter referred to as DDR) with a capacity of 4GB, and the physical buffer 111 can be located in the storage device. Among the 0~4GB of 110, in other words, the resources that can be used by the physical buffer 111 are 0~4GB, but this case is not limited to this.

Please refer to Figure 2. In one embodiment, the processor 130 may include a memory allocator and be used to generate the physical buffer 111 and the virtual buffer 113 for the storage device 110, but this case is not limited to this. . In some embodiments, the memory allocator 130 may be a third algorithm 135A (for example: a semiconductor memory management (RXX dvrMemory Manager) algorithm, as shown in Figure 2 ), and the third algorithm Method 135A (for example: Semiconductor A's memory management (RXX dvrMemory Manager) algorithm) 135A can be a software module developed by Semiconductor A (RXX) Company based on the Linux operating system, but this case is not limited to this.

Then, the processor 130 generates a virtual buffer 113 in the virtual capacity of the storage device 110 through a virtual buffer algorithm. For example, the virtual buffer algorithm can be the first algorithm 131A (for example: the Linux kernel algorithm, as shown in Figure 2), and the virtual capacity can be the virtual address space (fake address space), The virtual buffer 113 may be a sparse memory (Sparse Memory) block 113. In other words, the processor 130 may register the sparse memory (Sparse Memory) in the first algorithm 131A (for example, the Linux kernel algorithm). Memory) block 113, but this case is not limited to this.

In some embodiments, the total capacity of the storage device 110 may be 4GB, the physical buffer 111 may be the first buffer (Buffer 1), the virtual buffer 113 may be the second buffer (Buffer 2), and the second buffer (Buffer 2) can be a sparse memory (Sparse Memory) block 113. The processor 130 can generate a virtual address space (fake address space) in the storage device 110 through a virtual buffer algorithm. The first buffer (Buffer 1) can The 0~4GB area of the storage device 110 is used, while the sparse memory block 113 uses the 4~5GB area in the virtual address space (fake address space) (which does not actually exist for the storage device 110) , however, the sparse memory (Sparse Memory) block 113 has kernel pages structure characteristics, so for the second device 910, the sparse memory (Sparse Memory) block 113 can be regarded as an actual existing memory. physical memory, but this case is not limited to this. Therefore, the address translation system 100 does not need to add hardware (eg, additional memory capacity) or resources to couple the first device 900 to the second device 910 .

In some embodiments, the physical buffer 111 may be the first buffer (Buffer 1), the virtual buffer 113 may be the second buffer (Buffer 2), and the first buffer (Buffer 1) and the second buffer The total number of (Buffer 2) can be 12 blocks. Of course, the total number of the first buffer (Buffer 1) and the second buffer (Buffer 2) can be more or less, but this case is not limited to this.

Next, the coupling relationship between the physical buffer 111 and the virtual buffer 113 is established through the coupling algorithm through the coupler 121 of the memory bus 120 . For example, the memory bus 120 may include a bus detection switch (MonitorWrapper) 121, and the bus detection switch (MonitorWrapper) 121 may couple the first address of the buffer 111 to the virtual buffer through a coupling algorithm. The second address of District 113, but this case is not limited to this.

Then, compressed data is received from the first device 900 through the physical buffer 111 . For example, the first device 900 can be a home-made product (In-house IP) 900, which can output compressed data, and the compressed data can be written into the physical buffer 111, but this case is not limited to this.

Next, when the second device 910 wants to read the virtual buffer 113, the coupler 121 guides the second device 910 to the physical buffer 111 for reading through the coupling relationship. For example, the second device 910 can be an outsourced product (Vendor IP) 910, and the memory bus 120 can include a bus detection converter (MonitorWrapper) 121. When the outsourced product (Vendor IP) 910 wants to read the virtual When buffer 113 is reached, the monitoring converter (MonitorWrapper) 121 can be used to guide the outsourced product (Vendor IP) 910 to the physical buffer 111 for reading through the coupling relationship, but this case is not limited to this.

Subsequently, the compressed data in the physical buffer 111 is transmitted to the coupler 121 through the memory bus 120 . Then, the compressed data is decompressed into decompressed data through the memory bus 120 . Next, the decompressed data is sent to the second device 910 through the memory bus 120 . For example, the buffer 111 can transmit compressed data to the coupler 121. After the coupler 121 can receive the compressed data, the coupler 121 decompresses the compressed data into decompressed data, and then stores the compressed data. The device bus 120 transmits the decompressed data to the second device 910, but this case is not limited to this.

In some embodiments, the processor 130 is further configured to perform the following steps according to the plurality of instructions from the storage device 110: transmit a generate buffer instruction through the first device 900; and use a buffer algorithm to store the buffer according to the generate buffer instruction. Device 110 generates physical buffer 111. For example, the physical buffer 111 can be the first buffer (Buffer 1), and the buffer generation instruction can be a buffer output request (request output Buffer) instruction, but this case is not limited to this.

In some embodiments, the processor 130 is further configured to perform the following steps according to the plurality of instructions of the storage device 110: transmitting a return buffer instruction to the first device 900; and transmitting a generate virtual buffer instruction through the second device 910. For example, the return buffer instruction can be a return buffer 1 instruction, and the virtual buffer generation instruction can be a buffer input request (request input Buffer) instruction, but this case is not limited to this.

In some embodiments, the processor 130 is further configured to perform the following steps according to the plurality of instructions of the storage device 110: according to the generate virtual buffer instruction, generate the virtual buffer 113 in the virtual capacity of the storage device 110 through the virtual buffer algorithm. . For example, the processor 130 may use a virtual buffer algorithm (eg, a Linux kernel algorithm) in the storage device according to a virtual buffer instruction (eg, a request input buffer instruction). A virtual buffer 113 (for example: second buffer (Buffer 2)) is generated in the virtual capacity of 110 (for example, fake address space), but this case is not limited to this.

In some embodiments, the processor 130 is further configured to perform the following steps according to the plurality of instructions of the storage device 110: outputting the coupling instruction to the coupler 121 of the memory bus 120; and using the coupler 121 to couple according to the coupling instruction. The algorithm couples the first address of the physical buffer 111 to the second address of the virtual buffer 113 . For example, the coupling instruction may be an allocate fake Buffer 2 instruction. The coupling instruction is written to the coupler 121 (for example, the bus detection converter (MonitorWrapper) 121) of the memory bus 120 to Mapping, binding or coupling the second address of the virtual buffer 113 (for example: the second buffer (Buffer 2)) to the physical buffer 111 (for example: the first buffer (Buffer 2)) 1)), but this case is not limited to this.

In some embodiments, the coupling algorithm can be used by the sink detection switch (MonitorWrapper) 121 to monitor the address (eg, read address) of the second device 910 in real-time. When the start address (read address) falls between the second address of the virtual buffer 113 (for example: the start address (start address) and the end address (end address) of the second buffer (Buffer 2) ), the read address (read address) is subjected to a first conversion (for example: Level-0 address translator) to convert the read address (read address) into a first buffer (Buffer 1) The corresponding address (for example: the first buffer read address (Buffer 1_read_address)).

Then, perform a second conversion (for example: first-level conversion (Level-1 translator)) on the first buffer read address (Buffer 1_read_address) to obtain the corresponding data offset of the first buffer (Buffer 1) ( For example: the first buffer offset address (Buffer 1_offset_address)) and the first cache (for example: header cache). In addition, a first cache (eg, header cache) can generate a second cache (eg, decompressor/data cache).

Next, after the interface of the storage device 110 (for example, the memory interface (DDR interface)) receives the first buffer offset address (Buffer 1_offset_address) and the decompressed data cache (Decompressor/data cache), the memory interface ( DDR interface) drives the monitoring converter (MonitorWrapper) 121 to decompress the compressed data of the first device 900 (for example: home-made product (In-house IP)) according to the decompressed data cache (Decompressor/data cache). Decompress data. Then, the monitoring converter (MonitorWrapper) 121 transmits the decompressed data to the second device 910 (for example, an outsourced product (Vendor IP)), but this case is not limited to this.

In some embodiments, the processor 130 is further configured to perform the following steps according to the plurality of instructions of the storage device 110: transmitting a return virtual buffer instruction to the second device 910. For example, the instruction to return the virtual buffer can be an instruction to return the second buffer (return Buffer 2), but this case is not limited to this.

In some embodiments, the processor 130 is further configured to perform the following steps according to the plurality of instructions of the storage device 110: the first device 900 transmits the compressed data to the physical buffer 111 according to the return buffer instruction. For example, the first device 900 can transmit the compressed data to the first buffer (Buffer 1) according to the return Buffer 1 instruction, but the present case is not limited to this.

In some embodiments, the processor 130 is further configured to perform the following steps according to the plurality of instructions from the storage device 110: sending a read data instruction to the memory bus 120 through the second device 910 according to the return virtual buffer instruction; and Whether the virtual read data command is received from the second device 910 is confirmed through the coupler 121 . For example, the read data command may be a read data from Buffer 2 command, and the virtual read data command may be a fake read trigger command. The second device 910 A read data from Buffer 2 command can be sent to the memory bus 120 according to a return Buffer 2 command, and the coupler 121 can further identify the data from the second device 910 Whether the output read data from Buffer 2 command is a fake read trigger command, but this case is not limited to this.

In some embodiments, the processor 130 is further configured to perform the following steps according to the plurality of instructions of the storage device 110: confirming that a virtual read data instruction is received from the second device 910 through the coupler 121 to send a read buffer instruction to the physical buffer 111; and transmit the compressed data to the coupler 121 through the physical buffer 111 according to the read buffer instruction. For example, the read buffer instruction may be a request read from Buffer 1 instruction, and the coupler 121 may recognize the second buffer read data output from the second device 910 (read The data from Buffer 2) instruction is a faked read trigger instruction, and the coupler 121 can then transmit a read request from the first buffer (request read from Buffer 1) instruction to the physical buffer 111, and the physical buffer The zone 111 transmits the compressed data to the coupler 121 according to the request read from Buffer 1 instruction. Coupler 121 may then decompress the compressed data into decompressed data. Next, the memory bus 120 can transmit the decompressed data to the second device 910, but this case is not limited to this.

In some embodiments, the virtual buffer algorithm includes a Linux algorithm and coupler 121 includes a decompressor. For example, the virtual buffer algorithm may be an algorithm technology related to the first algorithm 131A (for example: Linux kernel, as shown in Figure 2), and the decompressor may be any generic entity or As a software decompressor, the coupler 121 may include a monitoring converter (MonitorWrapper) and a decompressor (Decompressor), but this case is not limited to this.

Referring to Figure 2, in some embodiments, the processor 130 includes a plurality of algorithms. For example, the processor 130 may include a first algorithm 131A, a second algorithm 133A, and a third algorithm 135A. The first algorithm 131A may be a Linux kernel pages algorithm, and the second algorithm 131A may be a Linux kernel pages algorithm. 133A may be a sparse memory (Sparse Memory) algorithm, the third algorithm 135A may be a semiconductor memory management (RXX dvrMemory Manager) algorithm, and a semiconductor memory management (RXX dvrMemory Manager) algorithm may be based on Linux On the operating system, a software module developed by A Semiconductor Semiconductor (RXX), in other words, A Semiconductor's memory management (RXX dvrMemory Manager) algorithm can provide the underlying Sparse memory (Sparse) using the Linux system core (Linux kernel). Memory) technology and the memory management model developed by RXX Semiconductor Company, but this case is not limited to this.

In some embodiments, the storage device 110 may include a first algorithm 131A, a second algorithm 133A, and a third algorithm 135A (not shown in the figure). For example, the first algorithm 131A can be a Linux kernel pages algorithm, the second algorithm 133A can be a sparse memory algorithm, and the third algorithm 135A can be a semiconductor memory algorithm. Memory management (RXX dvrMemory Manager) algorithm, but this case is not limited to this.

In some embodiments, this solution achieves the effect of reducing the size of the physical buffer 111 by using the virtual buffer 113 . For example, the size of the virtual buffer 113 (for example: the second buffer (Buffer 2)) can be , and the size (size) of the physical buffer 111 (for example: the first buffer (Buffer 1)) of the storage device 110 can be , the reduction ratio can be 50%, and the reduction ratio can be related to the compression rate (compression rate) of the first device 900 (for example, the home-made product (In-house IP) 900), but this case is not limited to this.

In some embodiments, the buffer of the traditional memory has a first volume, and the physical buffer 111 (for example, the first buffer (Buffer 1)) of the storage device 110 in this case has a second volume, and the second volume is less than First volume. For example, through the virtual buffer creation technology of this case, the buffer size can be effectively reduced. In some embodiments, the second device 910 (for example: outsourcing product (Vendor IP) 910) reads (read/write) instructions through the virtual buffer 113 (for example: the second buffer (Buffer 2)), and The second device 910 (for example: outsourcing product (Vendor IP) 910) can think that it is reading the complete buffer size (buffer size) instead of the physical buffer 111 (for example: the first buffer (Buffer 1)) There is a compressed size (size) in , but this case is not limited to this.

In some embodiments, the MonitorWrapper 121 may have the function of level 1 address translation without processing the virtual buffer 113 (for example, the second buffer (Buffer 2) ) mechanism. Furthermore, the buffer size (buffer size) and buffer size read by the first device 900 (for example: self-made product (In-house IP) 900) and the second device 910 (for example: outsourced product (Vendor IP) 910) The buffer address can be the same. That is, for the first device 900 (for example: self-made product (In-house IP) 900) and the second device 910 (for example: outsourced product (Vendor IP) 910), the physical buffer 111 of the storage device 110 ( For example: the memory size occupied by the first buffer (Buffer 1) is equivalent to the size of the original virtual buffer 113 (for example: the second buffer (Buffer 2)) and cannot be made smaller. But this case is not limited to this.

Figure 3 is a flow chart illustrating an address translation method according to an embodiment of the present invention. To make the address translation method 300 in Figure 3 easy to understand, please refer to Figure 1 and Figure 3 together. The address translation method 300 in Figure 3 includes the following steps:

Step 301: Generate the physical buffer 111 in the storage device 110;

Step 302: Generate the virtual buffer 113 in the virtual capacity of the storage device 110 through the virtual buffer algorithm;

Step 303: Establish the coupling relationship between the physical buffer 111 and the virtual buffer 113 through the coupling algorithm through the coupler 121 of the memory bus 120;

Step 304: Receive compressed data from the first device 900 through the physical buffer 111;

Step 305: When the second device 910 wants to read the virtual buffer 113, the coupler 121 guides the second device 910 to the physical buffer 111 through the coupling relationship to read;

Step 306: Transmit the compressed data of the physical buffer 111 to the coupler 121 through the memory bus 120;

Step 307: Decompress the compressed data into decompressed data through the coupler 121;

Step 308: Send the decompressed data to the second device via the memory bus 120.

In one embodiment, please refer to 301 , the processor 130 generates the physical buffer 111 in the storage device 110 . For example, the storage device 110 can be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM, hereinafter referred to as DDR) with a capacity of 4GB, and the physical buffer 111 can be a storage device. Among the 0~4GB of the device 110, in other words, the resources that can be used by the physical buffer 111 are 0~4GB, but this case is not limited to this.

Please refer to Figure 2. In one embodiment, the processor 130 may include a memory allocator and be used to generate the physical buffer 111 and the virtual buffer 113 for the storage device 110, but this case is not limited to this. . In some embodiments, the memory allocator 130 may be a third algorithm 135A (for example: a semiconductor memory management (RXX dvrMemory Manager) algorithm, as shown in Figure 2 ), and the third algorithm Method 135A (for example: Semiconductor A's memory management (RXX dvrMemory Manager) algorithm) can be a software module developed by Semiconductor Company A based on the Linux operating system, but this case is not limited to this.

In one embodiment, referring to step 302, the processor 130 generates the virtual buffer 113 in the virtual capacity of the storage device 110 through a virtual buffer algorithm. For example, the virtual buffer algorithm can be the first algorithm 131A (for example: the Linux kernel algorithm, as shown in Figure 2), and the virtual capacity can be the virtual address space (fake address space), The virtual buffer 113 may be a sparse memory (Sparse Memory) block 113. In other words, the processor 130 may register the sparse memory (Sparse Memory) in the first algorithm 131A (for example, the Linux kernel algorithm). Memory) block 113, but this case is not limited to this.

In some embodiments, the total capacity of the storage device 110 may be 4GB, the physical buffer 111 may be the first buffer (Buffer 1), the virtual buffer 113 may be the second buffer (Buffer 2), and the second buffer (Buffer 2) can be a sparse memory (Sparse Memory) block 113. The processor 130 can generate a virtual address space (fake address space) in the storage device 110 through a virtual buffer algorithm. The first buffer (Buffer 1) can The 0~4GB area of the storage device 110 is used, while the sparse memory block 113 uses the 4~5GB area in the virtual address space (fake address space) (which does not actually exist for the storage device 110) , however, the sparse memory (Sparse Memory) block 113 has kernel pages structure characteristics, so for the second device 910, the sparse memory (Sparse Memory) block 113 can be regarded as an actual existing memory. physical memory, but this case is not limited to this. Therefore, the address translation system 100 does not need to add hardware (eg, additional memory capacity) or resources to couple the first device 900 to the second device 910 .

In some embodiments, the physical buffer 111 may be the first buffer (Buffer 1), the virtual buffer 113 may be the second buffer (Buffer 2), and the first buffer (Buffer 1) and the second buffer The total number of (Buffer 2) can be 12 blocks. Of course, the total number of the first buffer (Buffer 1) and the second buffer (Buffer 2) can be more or less, but this case is not limited to this.

In one embodiment, refer to step 303, the coupler 121 of the memory bus 120 establishes a coupling relationship between the physical buffer 111 and the virtual buffer 113 through a coupling algorithm. For example, the memory bus 120 may include a bus detection switch (MonitorWrapper) 121, and the bus detection switch (MonitorWrapper) 121 may couple the first address of the buffer 111 to the virtual buffer through a coupling algorithm. The second address of District 113, but this case is not limited to this.

In one embodiment, please refer to step 304 to receive compressed data from the first device 900 through the physical buffer 111 . For example, the first device 900 can be a home-made product (In-house IP) 900, which can output compressed data, and the compressed data can be written into the buffer 111, but this case is not limited to this.

In one embodiment, please refer to step 305. When the second device 910 wants to read the virtual buffer 113, the coupler 121 guides the second device 910 to the physical buffer 111 for reading through the coupling relationship. For example, the second device 910 can be an outsourced product (Vendor IP) 910, and the memory bus 120 can include a bus detection converter (MonitorWrapper) 121. When the outsourced product (Vendor IP) 910 wants to read the virtual When buffer 113 is reached, the confluence detection converter (MonitorWrapper) 121 can be used to guide the outsourced product (Vendor IP) 910 to the physical buffer 111 for reading through the coupling relationship, but this case is not limited to this.

In one embodiment, referring to step 306 , the physical buffer 111 transmits the compressed data to the coupler 121 via the memory bus 120 . In one embodiment, please refer to step 307 to decompress the compressed data into decompressed data through the coupler 121 . In one embodiment, please refer to step 308 to transmit the decompressed data to the second device 910 via the memory bus 120 . For example, the physical buffer 111 can transmit compressed data to the coupler 121. After the coupler 121 can receive the compressed data, the coupler 121 decompresses the compressed data into decompressed data, and then, The memory bus 120 transmits the decompressed data to the second device 910, but this case is not limited to this.

Figures 4 to 6 are flow charts illustrating another address translation method according to an embodiment of the present invention. In order to make the address translation method 400 of Figures 4 to 6 easy to understand, please refer to Figures 1, 2, and 4 to 6 together. The address translation method 400 in Figures 4 to 6 includes the following steps:

Step 401: Send a buffer creation command through the first device 900;

Step 402: Generate the physical buffer 111 in the storage device 110 through the buffer algorithm according to the generate buffer instruction;

Step 403: Send the return buffer command to the first device 900;

Step 404: Send a virtual buffer generation instruction through the second device 910;

Step 405: Generate the virtual buffer 113 in the virtual capacity of the storage device 110 through the virtual buffer algorithm according to the generate virtual buffer instruction;

Step 406: Output the coupling command to the coupler 121 of the memory bus 120;

Step 407: The coupler 121 couples the first address of the physical buffer 111 to the second address of the virtual buffer 113 through a coupling algorithm according to the coupling instruction;

Step 408: Send the return virtual buffer instruction to the second device 910;

Step 409: Use the first device 900 to transmit the compressed data to the physical buffer 111 according to the return buffer command;

Step 410: Send the read data command to the memory bus 120 through the second device 910 according to the return virtual buffer command;

Step 411: Confirm whether a virtual read data command is received from the second device 910 through the coupler 121;

Step 412: Confirm that the virtual read data command is received from the second device 910 through the coupler 121 to send the read buffer command to the physical buffer 111;

Step 413: Transmit the compressed data to the coupler 121 through the physical buffer 111 according to the read buffer command;

Step 414: Decompress the compressed data into decompressed data through the coupler 121;

Step 415: Send the decompressed data to the second device 910 via the memory bus 120.

In one embodiment, please refer to step 301, step 401 and step 402. The step of the processor 130 generating the buffer 111 in the storage device 110 includes: sending a generate buffer instruction through the first device 900; and the processor 130 generates a buffer according to The buffer command generates a physical buffer 111 in the storage device 110 through a buffer algorithm. For example, the physical buffer 111 can be the first buffer (Buffer 1), and the buffer generation instruction can be a buffer output request (request output Buffer) instruction, but this case is not limited to this.

In one embodiment, please refer to step 301, step 403 and step 404. The step of the processor 130 generating the physical buffer 111 in the storage device 110 further includes: the processor 130 sends a return buffer instruction to the first device 900; and The second device 910 transmits a generate virtual buffer instruction. For example, the return buffer instruction can be a return buffer 1 instruction, and the virtual buffer generation instruction can be a buffer input request (request input Buffer) instruction, but this case is not limited to this.

In one embodiment, please refer to step 302 and step 405. The step of the processor 130 generating the virtual buffer 113 in the virtual capacity of the storage device 110 through the virtual buffer algorithm includes: the processor 130 generates a virtual buffer instruction according to The virtual buffer 113 is generated in the virtual capacity of the storage device 110 through a virtual buffer algorithm. For example, the processor 130 may create a virtual buffer algorithm (eg, a Linux kernel algorithm) in the storage according to a virtual buffer instruction (eg, a request input buffer instruction). The virtual buffer 113 (for example, the second buffer (Buffer 2)) is generated in the virtual capacity (for example, fake address space) of the device 110, but this case is not limited to this.

In one embodiment, please refer to step 303, step 406 and step 407. The step of establishing the coupling relationship between the physical buffer 111 and the virtual buffer 113 through the coupling algorithm through the memory bus 120 includes: the processor 130 outputs the coupling instructions to the coupler 121 of the memory bus 120; and the coupler 121 couples the first address of the physical buffer 111 to the second address of the virtual buffer through a coupling algorithm according to the coupling instruction. For example, the coupling instruction may be an allocate fake Buffer 2 instruction. The coupling instruction is written to the coupler 121 (for example, the bus detection converter (MonitorWrapper) 121) of the memory bus 120 to Mapping, binding or coupling the second address of the virtual buffer 113 (for example: the second buffer (Buffer 2)) to the buffer 111 (for example: the first buffer (Buffer 1) )), but this case is not limited to this.

In some embodiments, the coupling algorithm can be used by the sink detection switch (MonitorWrapper) 121 to monitor the address (eg, read address) of the second device 910 in real-time. When the read position (read address) falls within the second address of the virtual buffer 113 (for example: between the start address (start address) and the end address (end address) of the second buffer (Buffer 2)) , then the read address (read address) is subjected to the first conversion (for example: Level-0 address translator) to convert the read address (read address) into the first buffer (Buffer 1 ) corresponding address (for example: the first buffer read address (Buffer 1_read_address)).

Then, perform a second conversion (for example: first-level conversion (Level-1 translator)) on the first buffer read address (Buffer 1_read_address) to obtain the corresponding data offset of the first buffer (Buffer 1) ( For example: the first buffer offset address (Buffer 1_offset_address)) and the first cache (for example: header cache). In addition, a first cache (eg, header cache) can generate a second cache (eg, decompressor/data cache).

Next, after the interface of the storage device 110 (for example, the memory interface (DDR interface)) receives the first buffer offset address (Buffer 1_offset_address) and the decompressed data cache (Decompressor/data cache), the memory interface ( DDR interface) drives the monitoring converter (MonitorWrapper) 121 according to the decompressed data cache (Decompressor/data cache) to decompress the compressed data of the first device 900 (for example: home-made product (In-house IP)) into decompressed data. Decompress data. Then, the monitoring converter (MonitorWrapper) 121 transmits the decompressed data to the second device 910 (for example, an outsourced product (Vendor IP)), but this case is not limited to this.

In one embodiment, please refer to step 303 and step 408. The step of establishing the coupling relationship between the physical buffer 111 and the virtual buffer 113 through the coupling algorithm through the memory bus 120 further includes: the processor 130 returns the virtual buffer. area command to the second device 910. For example, the instruction to return the virtual buffer can be an instruction to return the second buffer (return Buffer 2), but this case is not limited to this.

In one embodiment, please refer to step 304 and step 409. The step of receiving compressed data from the first device 900 through the physical buffer 111 includes: transmitting the compressed data to the entity according to the return buffer command by the first device 900. Buffer 111. For example, the first device 900 can transmit the compressed data to the first buffer (Buffer 1) according to the return Buffer 1 instruction, but the present case is not limited to this.

In one embodiment, please refer to step 305, step 410 and step 411. When the second device 910 wants to read the virtual buffer 113, the memory bus 120 guides the second device 910 to the physical buffer through the coupling relationship. The step of reading in the area 111 includes: sending a read data command to the memory bus 120 by the second device 910 according to the return virtual buffer command; and confirming whether a virtual read is received from the second device 910 by the coupler 121 Get data command.

For example, the read data instruction may be a read data from Buffer 2 instruction, and the virtual read data instruction may be a fake read trigger instruction. The second device 910 A read data from Buffer 2 command can be sent to the memory bus 120 according to a return Buffer 2 command, and the coupler 121 can further confirm (or identify) the data from the second buffer (return Buffer 2). Whether the second buffer read data (read data from Buffer 2) command output by the second device 910 is a fake read trigger command, but this case is not limited to this.

In one embodiment, please refer to step 306, step 412 and step 413. The step of transmitting the compressed data to the memory bus 120 through the physical buffer 111 includes: confirming the reception from the second device 910 through the coupler 121. The virtual read data command is used to send the read buffer command to the physical buffer 111; and the physical buffer 111 sends the compressed data to the coupler 121 according to the read buffer command.

For example, the read buffer instruction may be a request read from Buffer 1 instruction, and the coupler 121 may confirm (or identify) the second buffer read output from the second device 910 The data (read data from Buffer 2) command is a faked read trigger command, and the coupler 121 can then transmit a read request (request read from Buffer 1) command to the physical buffer 111 , the physical buffer 111 transmits the compressed data to the coupler 121 according to the request read from Buffer 1 instruction, but this case is not limited to this.

In one embodiment, please refer to step 307 and step 414 to decompress the compressed data into decompressed data through the coupler 121 . In one embodiment, please refer to steps 307 and 415 to transmit the decompressed data to the second device 910 through the memory bus 120 . For example, after the coupler 121 can receive compressed data, the coupler 121 decompresses the compressed data into decompressed data, and then the memory bus 120 transmits the decompressed data to the second device 910. However, in this case Not limited to this.

In some embodiments, the virtual buffer algorithm includes a Linux algorithm and coupler 121 includes a decompressor. For example, the virtual buffer algorithm may be an algorithm technology related to the first algorithm 131A (for example: Linux kernel, as shown in Figure 2), and the decompressor may be any generic entity or As a software decompressor, the memory bus 120 may include a bus detection converter (MonitorWrapper) and a decompressor (Decompressor), but this case is not limited to this.

It can be seen from the above embodiments that the application of this case has the following advantages. The address translation system and address translation method shown in the embodiment of this case can reduce the consumption of memory resources and achieve the effect of transferring data between two hardwares with different addresses.

Although the above implementation mode discloses specific examples of the present case, it is not intended to limit the present case. Persons with ordinary knowledge in the technical field to which the present case belongs can, without departing from the principles and spirit of the present case, proceed with it. Various changes and modifications, therefore the scope of protection in this case shall be subject to the scope of the accompanying patent application.

100: Address translation system 110:Storage device 111:Buffer 113:Virtual buffer 120:Memory bus 121: Coupler (convergence detection converter) 130, 130A: Processor 900: First device (homemade product) 910: Second device (outsourced product) 131A: First algorithm (algorithm) 133A: Second algorithm (algorithm) 135A: The third algorithm (algorithm) 300, 400: Address conversion method 301~307: Steps 401~414: Steps

In order to make the above and other purposes, features, advantages and embodiments of this case more obvious and understandable, the attached drawings are described as follows: Figure 1 is a schematic block diagram of an address translation system according to an embodiment of the present invention. Figure 2 is a schematic block diagram of a processor of an address translation system according to an embodiment of the present invention. Figure 3 is a flow chart illustrating an address translation method according to an embodiment of the present invention. Figures 4 to 6 are flow charts illustrating another address translation method according to an embodiment of the present invention. In accordance with common practice, the various features and components in the drawings are not drawn to scale, but are drawn in such a way as to best present the specific features and components relevant to this case. In addition, the same or similar reference symbols are used to refer to similar elements/components in different drawings.

Domestic storage information (please note in order of storage institution, date, and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100: Address translation system

110:Storage device

111:Entity buffer

113:Virtual buffer

120:Memory bus

121:Coupler

130: Processor

900:First device

910:Second device

Claims (10)

An address translation system, including: a storage device; a memory bus, including: a coupler, used to couple a first device to a second device; and a processor, used according to the storage device A plurality of instructions to perform the following steps: create a physical buffer in the storage device; create a virtual buffer in a virtual capacity of the storage device through a virtual buffer algorithm; through the coupling of the memory bus The device establishes a coupling relationship between the physical buffer and the virtual buffer through a coupling algorithm; receives compressed data from the first device through the physical buffer; when the second device wants to read the virtual buffer , the coupler guides the second device to the physical buffer for reading through the coupling relationship; transmits a compressed data of the physical buffer to the coupler through the memory bus; through the memory bus The coupler decompresses the compressed data into decompressed data; and transmits the decompressed data to the second device through the memory bus. The address translation system as described in claim 1, wherein The processor is further configured to perform the following steps according to the instructions of the storage device: transmit a generate buffer instruction through the first device; and generate a buffer in the storage device through a buffer algorithm according to the generate buffer instruction. The entity buffer. The address translation system of claim 2, wherein the processor is further configured to perform the following steps according to the instructions of the storage device: sending a return buffer instruction to the first device; and through the second device Send a generate virtual buffer command. The address translation system as described in claim 3, wherein the processor is further configured to perform the following steps according to the instructions of the storage device: according to the generate virtual buffer instruction to use the virtual buffer algorithm to generate data in the storage device. The virtual buffer is generated in the virtual capacity of the device. The address translation system of claim 4, wherein the processor is further configured to perform the following steps according to the instructions of the storage device: outputting a coupling instruction to the coupler of the memory bus; and by The coupler couples a first address of the physical buffer to a second address of the virtual buffer through the coupling algorithm according to the coupling instruction. The address translation system of claim 5, wherein the processor is further configured to perform the following steps according to the instructions of the storage device: Send a return virtual buffer command to the second device. The address translation system of claim 6, wherein the processor is further configured to perform the following steps according to the instructions of the storage device: transmit the compressed data through the first device according to the return buffer instruction. to the entity buffer. The address translation system of claim 7, wherein the processor is further configured to perform the following steps according to the instructions of the storage device: transmit a read by the second device according to the return virtual buffer instruction. data commands to the memory bus; and confirming whether a virtual read data command is received from the second device through the coupler. The address translation system of claim 8, wherein the processor is further configured to perform the following steps according to the instructions of the storage device: confirm receipt of the virtual read data from the second device through the coupler The instruction is to send a read buffer command to the physical buffer; and the compressed data is sent to the coupler through the physical buffer according to the read buffer command. An address translation method, including: generating a physical buffer in a storage device; using a virtual buffer algorithm in a virtual capacity of the storage device Generate a virtual buffer; use a coupler of a memory bus to establish a coupling relationship between the physical buffer and the virtual buffer through a coupling algorithm; use the coupler to use the coupling algorithm to combine the physical buffer and the virtual buffer. A first address of the physical buffer is coupled to a second address of the virtual buffer; compressed data is received from a first device through the physical buffer; when a second device wants to read the virtual buffer At this time, the coupler guides the second device to the physical buffer for reading through the coupling relationship; transmits a compressed data of the physical buffer to the coupler through the memory bus; The coupler decompresses the compressed data into decompressed data and transmits the decompressed data to the second device through the memory bus.

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