TWI813455B - Address conversion system and address conversion method - Google Patents
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Abstract
Description
本案係有關於一種轉換系統及轉換方法,且特別是關於一種位址轉換系統及位址轉換方法。This case relates to a conversion system and a conversion method, and in particular to an address conversion system and an address conversion method.
目前,位於系統單晶片(System on a Chip, SOC)上硬體(或元件)間的資料傳送,需要透過在記憶體內設置的緩衝區(Buffer)做中間傳送資料的角色,並透過其他器件協助將資料壓縮及解壓縮,讓兩個不同位址的元件可以傳送資料順利。然而,兩個不同的元件通常需要搭配兩個緩衝區,但兩個緩衝區會消耗記憶體內的資源,造成資源上的浪費,也導致僅僅傳送資料卻造成消耗記憶體內資源的情況。Currently, data transmission between hardware (or components) on a System on a Chip (SOC) requires a buffer (Buffer) set in the memory to play the role of intermediate data transmission, and is assisted by other devices. Compress and decompress data so that two components with different addresses can transmit data smoothly. However, two different components usually require two buffers, but the two buffers will consume resources in the memory, causing a waste of resources. It also leads to the situation that only transmitting data consumes resources in the memory.
發明內容旨在提供本揭示內容的簡化摘要,以使閱讀者對本揭示內容具備基本的理解。此發明內容並非本揭示內容的完整概述,且其用意並非在指出本案實施例的重要/關鍵元件或界定本案的範圍。This summary is intended to provide a simplified summary of the disclosure to provide the reader with a basic understanding of the disclosure. This summary is not an extensive overview of the disclosure, and it is not intended to identify key/critical elements of the embodiments or to delineate the scope of the disclosure.
本案內容之一技術態樣係關於一種位址轉換系統。位址轉換系統包含儲存裝置、記憶器匯流排及處理器。記憶器匯流排用以將第一裝置耦合至第二裝置。處理器用以根據儲存裝置的複數個指令以執行以下步驟:於儲存裝置產生實體緩衝區;透過虛擬緩衝區演算法於儲存裝置的虛擬容量中產生虛擬緩衝區;藉由記憶器匯流排的耦合器透過耦合演算法建立實體緩衝區與虛擬緩衝區的耦合關係;藉由實體緩衝區從第一裝置接受壓縮資料;當第二裝置欲讀取虛擬緩衝區時,藉由耦合器透過耦合關係導引第二裝置至實體緩衝區進行讀取;藉由記憶器匯流排將實體緩衝區的壓縮資料傳送至耦合器;藉由耦合器將壓縮資料解壓縮為解壓縮資料;以及藉由記憶器匯流排將解壓縮資料傳送至第二裝置。One of the technical aspects of this case relates to an address translation system. The address translation system includes storage devices, memory buses, and processors. A memory bus is used to couple a first device to a second device. The processor is used to perform the following steps according to a plurality of instructions of the storage device: generate a physical buffer in the storage device; generate a virtual buffer in the virtual capacity of the storage device through a virtual buffer algorithm; use a coupler of the memory bus Establish a coupling relationship between the physical buffer and the virtual buffer through a coupling algorithm; use the physical buffer to receive compressed data from the first device; when the second device wants to read the virtual buffer, use the coupler to guide through the coupling relationship The second device reads the physical buffer; transmits the compressed data of the physical buffer to the coupler through the memory bus; decompresses the compressed data into decompressed data through the coupler; and uses the memory bus Transfer the decompressed data to the second device.
本案內容之另一技術態樣係關於一種位址轉換方法。位址轉換方法包含:於儲存裝置產生實體緩衝區;透過虛擬緩衝區演算法於儲存裝置的虛擬容量中產生虛擬緩衝區;藉由記憶器匯流排透過耦合演算法建立實體緩衝區與虛擬緩衝區的耦合關係;藉由實體緩衝區從第一裝置接受壓縮資料;當第二裝置欲讀取虛擬緩衝區時,藉由耦合器透過耦合關係導引第二裝置至實體緩衝區進行讀取;藉由記憶器匯流排將實體緩衝區的壓縮資料傳送至耦合器;藉由耦合器將壓縮資料解壓縮為解壓縮資料;以及藉由記憶器匯流排將解壓縮資料傳送至第二裝置。Another technical aspect of this case relates to an address translation method. The address translation method includes: generating a physical buffer in the storage device; generating a virtual buffer in the virtual capacity of the storage device through a virtual buffer algorithm; using the memory bus to create a physical buffer and a virtual buffer through a coupling algorithm The coupling relationship; receiving compressed data from the first device through the physical buffer; when the second device wants to read the virtual buffer, the coupler guides the second device to the physical buffer for reading through the coupling relationship; borrow The compressed data in the physical buffer is transmitted to the coupler through the memory bus; the compressed data is decompressed into decompressed data through the coupler; and the decompressed data is transmitted to the second device through the memory bus.
因此,根據本案之技術內容,本案實施例所示之位址轉換系統及位址轉換方法得以降低記憶體內資源之消耗,以達到兩個不同位址的硬體傳遞資料的效果。Therefore, according to the technical content of this case, the address translation system and address translation method shown in the embodiment of this case can reduce the consumption of resources in the memory, so as to achieve the effect of transferring data between two hardwares with different addresses.
在參閱下文實施方式後,本案所屬技術領域中具有通常知識者當可輕易瞭解本案之基本精神及其他發明目的,以及本案所採用之技術手段與實施態樣。After referring to the following embodiments, those with ordinary knowledge in the technical field to which this case belongs can easily understand the basic spirit and other purposes of the invention, as well as the technical means and implementation styles adopted in this case.
為了使本揭示內容的敘述更加詳盡與完備,下文針對了本案的實施態樣與具體實施例提出了說明性的描述;但這並非實施或運用本案具體實施例的唯一形式。實施方式中涵蓋了多個具體實施例的特徵以及用以建構與操作這些具體實施例的方法步驟與其順序。然而,亦可利用其他具體實施例來達成相同或均等的功能與步驟順序。In order to make the description of this disclosure more detailed and complete, the following provides an illustrative description of the implementation aspects and specific embodiments of this case; but this is not the only form of implementing or using the specific embodiments of this case. The embodiments cover features of multiple specific embodiments as well as method steps and their sequences for constructing and operating these specific embodiments. However, other specific embodiments may also be used to achieve the same or equivalent functions and step sequences.
除非本說明書另有定義,此處所用的科學與技術詞彙之含義與本案所屬技術領域中具有通常知識者所理解與慣用的意義相同。此外,在不和上下文衝突的情形下,本說明書所用的單數名詞涵蓋該名詞的複數型;而所用的複數名詞時亦涵蓋該名詞的單數型。Unless otherwise defined in this specification, the scientific and technical terms used herein have the same meanings as commonly understood and customary by a person with ordinary knowledge in the technical field to which the subject matter belongs. In addition, unless there is conflict with the context, the singular noun used in this specification covers the plural form of the noun; and the plural noun used also covers the singular form of the noun.
另外,關於本文中所使用之「耦接」或「連接」,可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,亦可指二或多個元件相互操作或動作。In addition, as used herein, "coupling" or "connection" may refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other, or it may also refer to two or more components that are in direct physical or electrical contact with each other. components interact or act with each other.
在說明書及申請專利範圍中使用了某些詞彙來指稱特定的元件。然而,所屬技術領域中具有通常知識者應可理解,同樣的元件可能會用不同的名詞來稱呼。說明書及申請專利範圍並不以名稱的差異做為區分元件的方式,而是以元件在功能上的差異來做為區分的基準。在說明書及申請專利範圍所提及的「包含」為開放式的用語,故應解釋成「包含但不限定於」。Certain words are used in the specification and patent claims to refer to specific components. However, those with ordinary skill in the art will understand that the same components may be referred to by different names. The specification and the patent application do not use the difference in name as a way to distinguish components, but the difference in function of the components as the basis for differentiation. The "include" mentioned in the specification and the scope of the patent application is an open-ended term, so it should be interpreted as "include but not limited to".
第1圖係依照本案一實施例繪示一種位址轉換系統的方塊示意圖。如圖所示,位址轉換系統100包含儲存裝置110、記憶器匯流排120及處理器130。於連接關係,儲存裝置110耦接於記憶器匯流排120,記憶器匯流排120耦接於處理器130。Figure 1 is a schematic block diagram of an address translation system according to an embodiment of the present invention. As shown in the figure, the
為降低消耗記憶體內資源之消耗,以達到兩個不同位址的硬體傳遞資料的效果,本案提供如第1圖所示之位址轉換系統100,其相關操作詳細說明如後。In order to reduce the consumption of memory resources and achieve the effect of transferring data between two hardwares with different addresses, this project provides an
在一實施例中,記憶器匯流排120的耦合器121用以將第一裝置900耦合至第二裝置910。在一實施例中,處理器130用以根據儲存裝置110的複數個指令以執行以下步驟:於儲存裝置110產生實體緩衝區111;透過虛擬緩衝區演算法於儲存裝置110的虛擬容量中產生虛擬緩衝區113;藉由記憶器匯流排120的耦合器121透過耦合演算法建立實體緩衝區111與虛擬緩衝區113的耦合關係;藉由實體緩衝區111從第一裝置900接受壓縮資料;當第二裝置910欲讀取虛擬緩衝區113時,藉由耦合器121透過耦合關係導引第二裝置910至實體緩衝區111進行讀取;藉由記憶器匯流排120將實體緩衝區111的壓縮資料傳送至耦合器121;藉由耦合器121將壓縮資料解壓縮為解壓縮資料;以及藉由記憶器匯流排120將解壓縮資料傳送至第二裝置910。In one embodiment, the
為使位址轉換系統100之上述操作易於理解,請一併參閱第2圖,第2圖係依照本案一實施例繪示一種位址轉換系統之處理器的方塊示意圖。In order to make the above operations of the
請一併參閱第1圖,於操作上,在一實施例中,記憶器匯流排120的耦合器121用以將第一裝置900耦合至第二裝置910。舉例而言,記憶器匯流排120的耦合器121可以用以將第一裝置900映射(mapping)、結合(bind)或耦合(coupling)至第二裝置910。在一些實施例中,第一裝置900可以包含一位址,第二裝置910可以包含另一位址,記憶器匯流排120的耦合器121可以用以將第一裝置900的位址映射、結合或耦合至第二裝置910的另一位址,但本案不以此為限。Please also refer to FIG. 1 . In operation, in one embodiment, the
此外,在一些實施例中,第一裝置900可以為自製產品(In-house IP),即為自家公司生產的元件,此外,第一裝置900也可以為影像解碼器(video decoder)。第二裝置910可以為外購產品(Vendor IP),即為外購其他公司生產的元件,此外,第二裝置910也可以為圖形處理器(Graphics Processing Unit, GPU),但本案不以此為限。在一些實施例中,第一裝置900及第二裝置910可以位於系統單晶片(System on a Chip, SOC)上,但本案不以此為限。在一些實施例中,第一裝置900也可以為圖形處理器(Graphics Processing Unit, GPU),第二裝置910也可以為影像解碼器(video decoder),此時記憶器匯流排120可以具有解壓縮圖形處理器中資料的設計(Design)或功能(Function),但本案不以此為限。In addition, in some embodiments, the
在一些實施例中,處理器130用以根據儲存裝置110的複數個指令以執行以下步驟:於儲存裝置110產生實體緩衝區111。舉例而言,儲存裝置110可以為容量4GB的雙倍資料率同步動態隨機存取記憶體(Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM,以下簡稱為DDR),實體緩衝區111可以位於儲存裝置110 的0~4GB中,換句話說,實體緩衝區111可以使用的資源為0~4GB,但本案不以此為限。In some embodiments, the
請參閱第2圖,在一實施例中,處理器130可以包含記憶體分配器(memory allocator),並用以於儲存裝置110產生實體緩衝區111及虛擬緩衝區113,但本案不以此為限。在一些實施例中,記憶體分配器( memory allocator)130可以為第三演算法135A(例如:甲半導體記憶體管理(RXX dvrMemory Manager)演算法,如第2圖所示),且第三演算法135A(例如:甲半導體記憶體管理(RXX dvrMemory Manager)演算法)135A可以為基於Linux作業系統上,甲半導體(RXX)公司所開發的軟體模組,但本案不以此為限。Please refer to Figure 2. In one embodiment, the
然後,處理器130透過虛擬緩衝區演算法於儲存裝置110的虛擬容量中產生虛擬緩衝區113。舉例而言,虛擬緩衝區演算法可以為第一演算法131A(例如:Linux系統核心(Linux kernel)演算法,如第2圖所示),虛擬容量可以為虛擬地址空間(fake address space),虛擬緩衝區113可以為稀疏記憶體(Sparse Memory)區塊113,換句話說,處理器130可以於第一演算法131A(例如:Linux系統核心(Linux kernel)演算法)註冊稀疏記憶體(Sparse Memory)區塊113,但本案不以此為限。Then, the
在一些實施例中,儲存裝置110的總容量可以為4GB,實體緩衝區111可以為第一緩衝器(Buffer 1),虛擬緩衝區113可以為第二緩衝器(Buffer 2),第二緩衝器(Buffer 2)可以為稀疏記憶體(Sparse Memory)區塊113,處理器130可以透過虛擬緩衝區演算法於儲存裝置110產生虛擬地址空間(fake address space),第一緩衝器(Buffer 1)可以使用儲存裝置110 的0~4GB區域,而稀疏記憶體(Sparse Memory)區塊113則使用虛擬地址空間(fake address space)中的4~5GB區域(對於儲存裝置110而言,實際上不存在),然而,稀疏記憶體(Sparse Memory)區塊113具有核心分頁結構(kernel pages structure)特性,故對第二裝置910而言,稀疏記憶體(Sparse Memory)區塊113可以視為實際存在的記憶體(physical memory),但本案不以此為限。故位址轉換系統100不須為將第一裝置900耦接於第二裝置910而增加硬體(例如:額外的記憶體容量)或資源。In some embodiments, the total capacity of the
在一些實施例中,實體緩衝區111可以為第一緩衝器(Buffer 1),虛擬緩衝區113可以為第二緩衝器(Buffer 2),而第一緩衝器(Buffer 1)及第二緩衝器(Buffer 2)的總數量可以為12塊,當然第一緩衝器(Buffer 1)及第二緩衝器(Buffer 2)的總數量可以更多或更少,但本案不以此為限。In some embodiments, the
再來,藉由記憶器匯流排120的耦合器121透過耦合演算法建立實體緩衝區111與虛擬緩衝區113的耦合關係。舉例而言,記憶器匯流排120可以包含匯流偵測轉換器(MonitorWrapper)121,且匯流偵測轉換器(MonitorWrapper)121可以透過耦合演算法以將緩衝區111的第一位址耦合於虛擬緩衝區113的第二位址,但本案不以此為限。Next, the coupling relationship between the
然後,藉由實體緩衝區111從第一裝置900接受壓縮資料。舉例而言,第一裝置900可為自製產品(In-house IP)900,其可以輸出壓縮資料(compressed data),壓縮資料可以寫入實體緩衝區111,但本案不以此為限。Then, compressed data is received from the
再來,當第二裝置910欲讀取虛擬緩衝區113時,藉由耦合器121透過耦合關係導引第二裝置910至實體緩衝區111進行讀取。舉例而言,第二裝置910可為外購產品(Vendor IP )910,且記憶器匯流排120可以包含匯流偵測轉換器(MonitorWrapper)121,當外購產品(Vendor IP)910欲讀取虛擬緩衝區113時,可以藉由匯流偵測轉換器(MonitorWrapper)121透過耦合關係導引外購產品(Vendor IP) 910至實體緩衝區111進行讀取,但本案不以此為限。Next, when the
隨後,藉由記憶器匯流排120將實體緩衝區111的壓縮資料傳送至耦合器121。然後,藉由記憶器匯流排120將壓縮資料解壓縮為解壓縮資料。再來,藉由記憶器匯流排120將解壓縮資料傳送至第二裝置910。舉例而言,緩衝區111可以將壓縮資料(compressed data)傳送至耦合器121,耦合器121可以接受壓縮資料後,耦合器121將壓縮資料解壓縮為解壓縮資料(decompressed data),然後,記憶器匯流排120將解壓縮資料傳送至第二裝置910,但本案不以此為限。Subsequently, the compressed data in the
在一些實施例中,處理器130更用以根據儲存裝置110的複數指令以執行以下步驟:藉由第一裝置900傳送生成緩衝區指令;以及根據生成緩衝區指令以透過緩衝區演算法於儲存裝置110產生實體緩衝區111。舉例而言,實體緩衝區111可以為第一緩衝器(Buffer 1),生成緩衝區指令可以為緩衝器輸出請求(request output Buffer)指令,但本案不以此為限。In some embodiments, the
在一些實施例中,處理器130更用以根據儲存裝置110的複數指令以執行以下步驟:傳送返回緩衝區指令至第一裝置900;以及藉由第二裝置910傳送生成虛擬緩衝區指令。舉例而言,返回緩衝區指令可以為返回第一緩衝器(return Buffer 1)指令,生成虛擬緩衝區指令可以為緩衝器輸入請求(request input Buffer)指令,但本案不以此為限。In some embodiments, the
在一些實施例中,處理器130更用以根據儲存裝置110的複數指令以執行以下步驟:根據生成虛擬緩衝區指令以透過虛擬緩衝區演算法於儲存裝置110的虛擬容量中產生虛擬緩衝區113。舉例而言,處理器130可以根據虛擬緩衝區指令(例如:緩衝器輸入請求(request input Buffer)指令)以透過虛擬緩衝區演算法(例如:Linux系統核心(Linux kernel)演算法) 於儲存裝置110的虛擬容量(例如fake address space)中產生虛擬緩衝區113(例如:第二緩衝器(Buffer 2)),但本案不以此為限。In some embodiments, the
在一些實施例中,處理器130更用以根據儲存裝置110的複數指令以執行以下步驟:輸出耦合指令至記憶器匯流排120的耦合器121;以及藉由耦合器121根據耦合指令以透過耦合演算法將實體緩衝區111的第一位址耦合於虛擬緩衝區113的第二位址。舉例而言,耦合指令可以為分配虛擬第二緩衝器(allocate fake Buffer 2)指令,耦合指令寫入記憶器匯流排120的耦合器121(例如:匯流偵測轉換器(MonitorWrapper)121)用以將虛擬緩衝區113(例如:第二緩衝器(Buffer 2))的第二位址映射(mapping)、結合(bind)或耦合(coupling)至實體緩衝區111(例如:第一緩衝器(Buffer 1))的第一位址,但本案不以此為限。In some embodiments, the
在一些實施例中,耦合演算法可以為匯流偵測轉換器(MonitorWrapper)121用以即時(real-time)的監督第二裝置910的位址(例如:讀取位置(read address))。當起始位址(read address)落在虛擬緩衝區113的第二位址(例如:第二緩衝器(Buffer 2)的起始位址(start address)、結束位址(end address)之間),則將讀取位址(read address)進行第一轉換(例如:零階位址轉換(Level-0 address translator))以將讀取位址(read address)轉換為第一緩衝器(Buffer 1)相對應的位址(例如:第一緩衝器讀取位址(Buffer 1_read_address))。In some embodiments, the coupling algorithm can be used by the sink detection switch (MonitorWrapper) 121 to monitor the address (eg, read address) of the
然後,將第一緩衝器讀取位址(Buffer 1_read_address)進行第二轉換(例如:第一階轉換(Level-1 translator))以取得第一緩衝器(Buffer 1)相對應的資料偏移(例如:第一緩衝器偏移位址(Buffer 1_offset_address))及第一快取(例如:首標快取(header cache))。此外,第一快取(例如:首標快取(header cache))可以生成第二快取(例如:解壓縮資料快取(Decompressor/data cache))。Then, perform a second conversion (for example: first-level conversion (Level-1 translator)) on the first buffer read address (Buffer 1_read_address) to obtain the corresponding data offset of the first buffer (Buffer 1) ( For example: the first buffer offset address (Buffer 1_offset_address)) and the first cache (for example: header cache). In addition, a first cache (eg, header cache) can generate a second cache (eg, decompressor/data cache).
再來,儲存裝置110的介面(例如:記憶體界面(DDR interface))接收第一緩衝器偏移位址(Buffer 1_offset_address)及解壓縮資料快取(Decompressor/data cache)後,記憶體界面(DDR interface)根據解壓縮資料快取(Decompressor/data cache)以驅動匯流偵測轉換器(MonitorWrapper)121將第一裝置900(例如:自製產品(In-house IP))的壓縮資料解壓縮為解壓縮資料(decompress data)。然後,匯流偵測轉換器(MonitorWrapper)121將解壓縮資料傳送至第二裝置910(例如:外購產品(Vendor IP)),但本案不以此為限。Next, after the interface of the storage device 110 (for example, the memory interface (DDR interface)) receives the first buffer offset address (Buffer 1_offset_address) and the decompressed data cache (Decompressor/data cache), the memory interface ( DDR interface) drives the monitoring converter (MonitorWrapper) 121 to decompress the compressed data of the first device 900 (for example: home-made product (In-house IP)) according to the decompressed data cache (Decompressor/data cache). Decompress data. Then, the monitoring converter (MonitorWrapper) 121 transmits the decompressed data to the second device 910 (for example, an outsourced product (Vendor IP)), but this case is not limited to this.
在一些實施例中,處理器130更用以根據儲存裝置110的複數指令以執行以下步驟:傳送返回虛擬緩衝區指令至第二裝置910。舉例而言,返回虛擬緩衝區指令可以為返回第二緩衝器(return Buffer 2)指令,但本案不以此為限。In some embodiments, the
在一些實施例中,處理器130更用以根據儲存裝置110的複數指令以執行以下步驟:第一裝置900根據返回緩衝區指令以將壓縮資料傳送至實體緩衝區111。舉例而言,第一裝置900可以根據返回第一緩衝器(return Buffer 1)指令以將壓縮資料傳送至第一緩衝器(Buffer 1),但本案不以此為限。In some embodiments, the
在一些實施例中,處理器130更用以根據儲存裝置110的複數指令以執行以下步驟:藉由第二裝置910根據返回虛擬緩衝區指令以傳送讀取資料指令至記憶器匯流排120;以及藉由耦合器121確認是否從第二裝置910接收虛擬讀取資料指令。舉例而言,讀取資料指令可以為從第二緩衝器讀取資料(read data from Buffer 2)指令,虛擬讀取資料指令可以為虛擬讀取資料器(faked read trigger )指令,第二裝置910可以根據返回第二緩衝器(return Buffer 2)指令以傳送從第二緩衝器讀取資料(read data from Buffer 2)指令至記憶器匯流排120,且耦合器121可以進一步辨識從第二裝置910輸出的第二緩衝器讀取資料(read data from Buffer 2)指令是否為虛擬讀取觸發器(faked read trigger) 指令,但本案不以此為限。In some embodiments, the
在一些實施例中,處理器130更用以根據儲存裝置110的複數指令以執行以下步驟:藉由耦合器121確認有從第二裝置910接收虛擬讀取資料指令以傳送讀取緩衝區指令至實體緩衝區111;以及藉由實體緩衝區111根據讀取緩衝區指令以將壓縮資料傳送至耦合器121。舉例而言,讀取緩衝區指令可以為從第一緩衝器讀取請求(request read from Buffer 1)指令,耦合器121可以或辨識從第二裝置910輸出的第二緩衝器讀取資料(read data from Buffer 2)指令為虛擬讀取觸發器(faked read trigger) 指令,且耦合器121可以接著傳送從第一緩衝器讀取請求(request read from Buffer 1)指令至實體緩衝區111,實體緩衝區111根據從第一緩衝器讀取請求(request read from Buffer 1)指令以將壓縮資料傳送至耦合器121。然後,耦合器121可以將壓縮資料解壓縮為解壓縮資料。再來,記憶器匯流排120可以將解壓縮資料傳送至第二裝置910,但本案不以此為限。In some embodiments, the
在一些實施例中,虛擬緩衝區演算法包含Linux演算法,且耦合器121包含解壓縮器。舉例而言,虛擬緩衝區演算法可以與第一演算法131A(例如:Linux系統核心(Linux kernel),如第2圖所示)相關的演算法技術,解壓縮器可以為任何泛指實體或軟體上的解壓縮器(Decompressor),耦合器121可以包含匯流偵測轉換器(MonitorWrapper)及解壓縮器(Decompressor),但本案不以此為限。In some embodiments, the virtual buffer algorithm includes a Linux algorithm and
請參閱第2圖,在一些實施例中,處理器130包含複數個演算法。舉例而言,處理器130可以包含第一演算法131A、第二演算法133A及第三演算法135A,第一演算法131A可以為Linux系統核心頁面(Linux kernel pages)演算法,第二演算法133A可以為稀疏記憶體(Sparse Memory)演算法,第三演算法135A可以為甲半導體記憶體管理(RXX dvrMemory Manager)演算法,且甲半導體記憶體管理(RXX dvrMemory Manager)演算法可以為基於Linux作業系統上,甲半導體半導體(RXX)公司開發的軟體模組,換句話說,甲半導體記憶體管理(RXX dvrMemory Manager)演算法可以為底層使用Linux系統核心(Linux kernel)的稀疏記憶體(Sparse Memory)技術與甲半導體半導體(RXX)公司開發的記憶體管理模式,但本案不以此為限。Referring to Figure 2, in some embodiments, the
在一些實施例中,儲存裝置110可以包含第一演算法131A、第二演算法133A及第三演算法135A(圖中未示)。舉例而言,第一演算法131A可以為Linux系統核心頁面(Linux kernel pages)演算法,第二演算法133A可以為稀疏記憶體(Sparse Memory)演算法,第三演算法135A可以為甲半導體記憶體管理(RXX dvrMemory Manager)演算法,但本案不以此為限。In some embodiments, the
在一些實施例中,本案透過使用虛擬緩衝區113,以達到縮減實體緩衝區111之尺寸(size)的效果。舉例而言,虛擬緩衝區113(例如:第二緩衝器(Buffer 2))的尺寸(size)可以為
,而儲存裝置110的實體緩衝區111(例如:第一緩衝器(Buffer 1))的尺寸(size)可以為
,縮減比例可以為50%,而縮減比例可以與第一裝置900(例如:自製產品(In-house IP) 900)的壓縮速率(compress rate)相關,但本案不以此為限。
In some embodiments, this solution achieves the effect of reducing the size of the
在一些實施例中,傳統記憶體之緩衝器具有第一體積,而本案之儲存裝置110的實體緩衝區111(例如:第一緩衝器(Buffer 1))具有第二體積,且第二體積小於第一體積。舉例而言,透過本案的虛擬緩衝區建立技術,可以達到有效縮小緩衝器之體積(buffer size)的效果。在一些實施例中,第二裝置910(例如:外購產品(Vendor IP )910)透過虛擬緩衝區113(例如:第二緩衝器(Buffer 2))來讀取(read/write)指令,且第二裝置910(例如:外購產品(Vendor IP )910)可以認為自己讀的是完整的緩衝器尺寸(buffer size),而不是實體緩衝區111(例如:第一緩衝器(Buffer 1))中有被壓縮過的尺寸(size),但本案不以此為限。In some embodiments, the buffer of the traditional memory has a first volume, and the physical buffer 111 (for example, the first buffer (Buffer 1)) of the
在一些實施例中,匯流偵測轉換器(MonitorWrapper)121可以具有一階位址轉換(level 1 address translation)的功能,而不具有處理虛擬緩衝區113(例如:第二緩衝器(Buffer 2))的機制。進一步來說,第一裝置900(例如:自製產品(In-house IP) 900)與第二裝置910(例如:外購產品(Vendor IP )910)讀到的緩衝器尺寸(buffer size)跟緩衝器位址(buffer address)可以是同一個。意即,對於第一裝置900(例如:自製產品(In-house IP) 900)與第二裝置910(例如:外購產品(Vendor IP )910)而言,儲存裝置110的實體緩衝區111(例如:第一緩衝器(Buffer 1))所佔的記憶體尺寸(memory size)相當於原本虛擬緩衝區113(例如:第二緩衝器(Buffer 2))的尺寸(size),無法變小,但本案不以此為限。In some embodiments, the
第3圖係依照本案一實施例繪示一種位址轉換方法的流程圖。為使第3圖之位址轉換方法300易於理解,請一併參閱第1圖及第3圖。第3圖之位址轉換方法300包含以下步驟:Figure 3 is a flow chart illustrating an address translation method according to an embodiment of the present invention. To make the
步驟301:於儲存裝置110產生實體緩衝區111;Step 301: Generate the
步驟302:透過虛擬緩衝區演算法於儲存裝置110的虛擬容量中產生虛擬緩衝區113;Step 302: Generate the
步驟303:藉由記憶器匯流排120的耦合器121透過耦合演算法建立實體緩衝區111與虛擬緩衝區113的耦合關係;Step 303: Establish the coupling relationship between the
步驟304:藉由實體緩衝區111從第一裝置900接受壓縮資料;Step 304: Receive compressed data from the
步驟305:當第二裝置910欲讀取虛擬緩衝區113時,藉由耦合器121透過耦合關係導引第二裝置910至實體緩衝區111進行讀取;Step 305: When the
步驟306:藉由記憶器匯流排120將實體緩衝區111的壓縮資料傳送至耦合器121;Step 306: Transmit the compressed data of the
步驟307:藉由耦合器121將壓縮資料解壓縮為解壓縮資料;Step 307: Decompress the compressed data into decompressed data through the
步驟308:藉由記憶器匯流排120將解壓縮資料傳送至第二裝置。Step 308: Send the decompressed data to the second device via the
在一實施例中,請參閱301,處理器130於儲存裝置110產生實體緩衝區111。舉例而言,儲存裝置110可以為容量4GB的雙倍資料率同步動態隨機存取記憶體(Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM,以下簡稱為DDR),實體緩衝區111可以為於儲存裝置110 的0~4GB中,換句話說,實體緩衝區111可以使用的資源為0~4GB,但本案不以此為限。In one embodiment, please refer to 301 , the
請參閱第2圖,在一實施例中,處理器130可以包含記憶體分配器(memory allocator),並用以於儲存裝置110產生實體緩衝區111及虛擬緩衝區113,但本案不以此為限。在一些實施例中,記憶體分配器(memory allocator)130可以為第三演算法135A(例如:甲半導體記憶體管理(RXX dvrMemory Manager)演算法,如第2圖所示),且第三演算法135A(例如:甲半導體記憶體管理(RXX dvrMemory Manager)演算法)可以為基於Linux作業系統上,甲半導體公司開發的軟體模組,但本案不以此為限。Please refer to Figure 2. In one embodiment, the
在一實施例中,請參閱步驟302,處理器130透過虛擬緩衝區演算法於儲存裝置110的虛擬容量中產生虛擬緩衝區113。舉例而言,虛擬緩衝區演算法可以為第一演算法131A(例如:Linux系統核心(Linux kernel)演算法,如第2圖所示),虛擬容量可以為虛擬地址空間(fake address space),虛擬緩衝區113可以為稀疏記憶體(Sparse Memory)區塊113,換句話說,處理器130可以於第一演算法131A(例如:Linux系統核心(Linux kernel)演算法)註冊稀疏記憶體(Sparse Memory)區塊113,但本案不以此為限。In one embodiment, referring to step 302, the
在一些實施例中,儲存裝置110的總容量可以為4GB,實體緩衝區111可以為第一緩衝器(Buffer 1),虛擬緩衝區113可以為第二緩衝器(Buffer 2),第二緩衝器(Buffer 2)可以為稀疏記憶體(Sparse Memory)區塊113,處理器130可以透過虛擬緩衝區演算法於儲存裝置110產生虛擬地址空間(fake address space),第一緩衝器(Buffer 1)可以使用儲存裝置110 的0~4GB區域,而稀疏記憶體(Sparse Memory)區塊113則使用虛擬地址空間(fake address space)中的4~5GB區域(對於儲存裝置110而言,實際上不存在),然而,稀疏記憶體(Sparse Memory)區塊113具有核心分頁結構(kernel pages structure)特性,故對第二裝置910而言,稀疏記憶體(Sparse Memory)區塊113可以視為實際存在的記憶體(physical memory),但本案不以此為限。故位址轉換系統100不須為將第一裝置900耦接於第二裝置910而增加硬體(例如:額外的記憶體容量)或資源。In some embodiments, the total capacity of the
在一些實施例中,實體緩衝區111可以為第一緩衝器(Buffer 1),虛擬緩衝區113可以為第二緩衝器(Buffer 2),而第一緩衝器(Buffer 1)及第二緩衝器(Buffer 2)的總數量可以為12塊,當然第一緩衝器(Buffer 1)及第二緩衝器(Buffer 2)的總數量可以更多或更少,但本案不以此為限。In some embodiments, the
在一實施例中,請參閱步驟303,藉由記憶器匯流排120的耦合器121透過耦合演算法建立實體緩衝區111與虛擬緩衝區113的耦合關係。舉例而言,記憶器匯流排120可以包含匯流偵測轉換器(MonitorWrapper)121,且匯流偵測轉換器(MonitorWrapper)121可以透過耦合演算法以將緩衝區111的第一位址耦合於虛擬緩衝區113的第二位址,但本案不以此為限。In one embodiment, refer to step 303, the
在一實施例中,請參閱步驟304,藉由實體緩衝區111從第一裝置900接受壓縮資料。舉例而言,第一裝置900可為自製產品(In-house IP) 900,其可以輸出壓縮資料(compressed data),壓縮資料可以寫入緩衝區111,但本案不以此為限。In one embodiment, please refer to step 304 to receive compressed data from the
在一實施例中,請參閱步驟305,當第二裝置910欲讀取虛擬緩衝區113時,藉由耦合器121透過耦合關係導引第二裝置910至實體緩衝區111進行讀取。舉例而言,第二裝置910可為外購產品(Vendor IP) 910,且記憶器匯流排120可以包含匯流偵測轉換器(MonitorWrapper )121,當外購產品(Vendor IP) 910欲讀取虛擬緩衝區113時,可以藉由匯流偵測轉換器(MonitorWrapper )121透過耦合關係導引外購產品(Vendor IP) 910至實體緩衝區111進行讀取,但本案不以此為限。In one embodiment, please refer to step 305. When the
在一實施例中,請參閱步驟306,藉由記憶器匯流排120將實體緩衝區111將壓縮資料傳送至耦合器121。在一實施例中,請參閱步驟307,藉由耦合器121將壓縮資料解壓縮為解壓縮資料。在一實施例中,請參閱步驟308,藉由記憶器匯流排120將解壓縮資料傳送至第二裝置910。舉例而言,實體緩衝區111可以將壓縮資料(compressed data)傳送至耦合器121,耦合器121可以接受壓縮資料後,耦合器121將壓縮資料解壓縮為解壓縮資料(decompressed data),然後,記憶器匯流排120將解壓縮資料傳送至第二裝置910,但本案不以此為限。In one embodiment, referring to step 306 , the
第4圖至第6圖係依照本案一實施例繪示另一種位址轉換方法的流程圖。為使第4圖至第6圖之位址轉換方法400易於理解,請一併參閱第1圖、第2圖、第4圖至第6圖。第4圖至第6圖之位址轉換方法400包含以下步驟:Figures 4 to 6 are flow charts illustrating another address translation method according to an embodiment of the present invention. In order to make the
步驟401:藉由第一裝置900傳送生成緩衝區指令;Step 401: Send a buffer creation command through the
步驟402:根據生成緩衝區指令以透過緩衝區演算法於儲存裝置110產生實體緩衝區111;Step 402: Generate the
步驟403:傳送返回緩衝區指令至第一裝置900;Step 403: Send the return buffer command to the
步驟404:藉由第二裝置910傳送生成虛擬緩衝區指令;Step 404: Send a virtual buffer generation instruction through the
步驟405:根據生成虛擬緩衝區指令以透過虛擬緩衝區演算法於儲存裝置110的虛擬容量中產生虛擬緩衝區113;Step 405: Generate the
步驟406:輸出耦合指令至記憶器匯流排120的耦合器121;Step 406: Output the coupling command to the
步驟407:藉由耦合器121根據耦合指令以透過耦合演算法將實體緩衝區111的第一位址耦合於虛擬緩衝區113的第二位址;Step 407: The
步驟408:傳送返回虛擬緩衝區指令至第二裝置910;Step 408: Send the return virtual buffer instruction to the
步驟409:藉由第一裝置900根據返回緩衝區指令以將壓縮資料傳送至實體緩衝區111;Step 409: Use the
步驟410:藉由第二裝置910根據返回虛擬緩衝區指令以傳送讀取資料指令至記憶器匯流排120;Step 410: Send the read data command to the
步驟411:藉由耦合器121確認是否從第二裝置910接收虛擬讀取資料指令;Step 411: Confirm whether a virtual read data command is received from the
步驟412:藉由耦合器121確認有從第二裝置910接收虛擬讀取資料指令以傳送讀取緩衝區指令至實體緩衝區111;Step 412: Confirm that the virtual read data command is received from the
步驟413:藉由實體緩衝區111根據讀取緩衝區指令以將壓縮資料傳送至耦合器121;Step 413: Transmit the compressed data to the
步驟414:藉由耦合器121將壓縮資料解壓縮為解壓縮資料;Step 414: Decompress the compressed data into decompressed data through the
步驟415:藉由記憶器匯流排120將解壓縮資料傳送至第二裝置910。Step 415: Send the decompressed data to the
在一實施例中,請參閱步驟301、步驟401及步驟402,處理器130於儲存裝置110產生緩衝區111的步驟包含:藉由第一裝置900傳送生成緩衝區指令;以及處理器130根據生成緩衝區指令以透過緩衝區演算法於儲存裝置110產生實體緩衝區111。舉例而言,實體緩衝區111可以為第一緩衝器(Buffer 1),生成緩衝區指令可以為緩衝器輸出請求(request output Buffer )指令,但本案不以此為限。In one embodiment, please refer to step 301,
在一實施例中,請參閱步驟301、步驟403及步驟404,處理器130於儲存裝置110產生實體緩衝區111的步驟更包含:處理器130傳送返回緩衝區指令至第一裝置900;以及藉由第二裝置910傳送生成虛擬緩衝區指令。舉例而言,返回緩衝區指令可以為返回第一緩衝器(return Buffer 1)指令,生成虛擬緩衝區指令可以為緩衝器輸入請求(request input Buffer)指令,但本案不以此為限。In one embodiment, please refer to step 301,
在一實施例中,請參閱步驟302及步驟405,處理器130透過虛擬緩衝區演算法於儲存裝置110的虛擬容量中產生虛擬緩衝區113的步驟包含:處理器130根據生成虛擬緩衝區指令以透過虛擬緩衝區演算法於儲存裝置110的虛擬容量中產生虛擬緩衝區113。舉例而言,處理器130可以根據虛擬緩衝區指令(例如:緩衝器輸入請求(request input Buffer)指令)以透過建立虛擬緩衝區演算法(例如:Linux系統核心(Linux kernel)演算法) 於儲存裝置110的虛擬容量(例如fake address space)中產生虛擬緩衝區113(例如:第二緩衝器(Buffer 2)),但本案不以此為限。In one embodiment, please refer to step 302 and
在一實施例中,請參閱步驟303、步驟406及步驟407,藉由記憶器匯流排120透過耦合演算法建立實體緩衝區111與虛擬緩衝區113的耦合關係的步驟包含:處理器130輸出耦合指令至記憶器匯流排120的耦合器121;以及藉由耦合器121根據耦合指令以透過耦合演算法將實體緩衝區111的第一位址耦合於虛擬緩衝區的第二位址。舉例而言,耦合指令可以為分配虛擬第二緩衝器(allocate fake Buffer 2)指令,耦合指令寫入記憶器匯流排120的耦合器121(例如:匯流偵測轉換器(MonitorWrapper)121)用以將虛擬緩衝區113(例如:第二緩衝器(Buffer 2))的第二位址映射(mapping)、結合(bind)或耦合(coupling)至緩衝區111(例如:第一緩衝器(Buffer 1))的第一位址,但本案不以此為限。In one embodiment, please refer to step 303,
在一些實施例中,耦合演算法可以為匯流偵測轉換器(MonitorWrapper)121用以即時(real-time)的監督第二裝置910的位址(例如:讀取位置(read address))。當讀取位置(read address)落在虛擬緩衝區113的第二位址(例如:第二緩衝器(Buffer 2)的起始位址(start address)、結束位址(end address)之間),則將讀取位址(read address)進行第一轉換(例如:零階位址轉換(Level-0 address translator))以將讀取位址(read address)轉換為第一緩衝器(Buffer 1)相對應的位址(例如:第一緩衝器讀取位址(Buffer 1_read_address))。In some embodiments, the coupling algorithm can be used by the sink detection switch (MonitorWrapper) 121 to monitor the address (eg, read address) of the
然後,將第一緩衝器讀取位址(Buffer 1_read_address)進行第二轉換(例如:第一階轉換(Level-1 translator))以取得第一緩衝器(Buffer 1)相對應的資料偏移(例如:第一緩衝器偏移位址(Buffer 1_offset_address))及第一快取(例如:首標快取(header cache))。此外,第一快取(例如:首標快取(header cache))可以生成第二快取(例如:解壓縮資料快取(Decompressor/data cache))。Then, perform a second conversion (for example: first-level conversion (Level-1 translator)) on the first buffer read address (Buffer 1_read_address) to obtain the corresponding data offset of the first buffer (Buffer 1) ( For example: the first buffer offset address (Buffer 1_offset_address)) and the first cache (for example: header cache). In addition, a first cache (eg, header cache) can generate a second cache (eg, decompressor/data cache).
再來,儲存裝置110的介面(例如:記憶體界面(DDR interface))接收第一緩衝器偏移位址(Buffer 1_offset_address)及解壓縮資料快取(Decompressor/data cache)後,記憶體界面(DDR interface)根據解壓縮資料快取(Decompressor/data cache)以驅動匯流偵測轉換器(MonitorWrapper)121將第一裝置900(例如:自製產品(In-house IP) )的壓縮資料解壓縮為解壓縮資料(decompress data)。然後,匯流偵測轉換器(MonitorWrapper)121將解壓縮資料傳送至第二裝置910(例如:外購產品(Vendor IP)),但本案不以此為限。Next, after the interface of the storage device 110 (for example, the memory interface (DDR interface)) receives the first buffer offset address (Buffer 1_offset_address) and the decompressed data cache (Decompressor/data cache), the memory interface ( DDR interface) drives the monitoring converter (MonitorWrapper) 121 according to the decompressed data cache (Decompressor/data cache) to decompress the compressed data of the first device 900 (for example: home-made product (In-house IP)) into decompressed data. Decompress data. Then, the monitoring converter (MonitorWrapper) 121 transmits the decompressed data to the second device 910 (for example, an outsourced product (Vendor IP)), but this case is not limited to this.
在一實施例中,請參閱步驟303及步驟408,藉由記憶器匯流排120透過耦合演算法建立實體緩衝區111與虛擬緩衝區113的耦合關係的步驟更包含:處理器130傳送返回虛擬緩衝區指令至第二裝置910。舉例而言,返回虛擬緩衝區指令可以為返回第二緩衝器(return Buffer 2)指令,但本案不以此為限。In one embodiment, please refer to step 303 and
在一實施例中,請參閱步驟304及步驟409,藉由實體緩衝區111從第一裝置900接受壓縮資料的步驟包含:藉由第一裝置900根據返回緩衝區指令以將壓縮資料傳送至實體緩衝區111。舉例而言,第一裝置900可以根據返回第一緩衝器(return Buffer 1)指令以將壓縮資料傳送至第一緩衝器(Buffer 1),但本案不以此為限。In one embodiment, please refer to step 304 and
在一實施例中,請參閱步驟305、步驟410及步驟411,當第二裝置910欲讀取虛擬緩衝區113時,藉由記憶器匯流排120透過耦合關係導引第二裝置910至實體緩衝區111進行讀取的步驟包含:藉由第二裝置910根據返回虛擬緩衝區指令以傳送讀取資料指令至記憶器匯流排120;以及藉由耦合器121確認是否從第二裝置910接收虛擬讀取資料指令。In one embodiment, please refer to step 305,
舉例而言,讀取資料指令可以為從第二緩衝器讀取資料(read data from Buffer 2)指令,虛擬讀取資料指令可以為虛擬讀取觸發器(faked read trigger) 指令,第二裝置910可以根據返回第二緩衝器(return Buffer 2)指令以傳送從第二緩衝器讀取資料(read data from Buffer 2)指令至記憶器匯流排120,且耦合器121可以進一步確認(或辨識)從第二裝置910輸出的第二緩衝器讀取資料(read data from Buffer 2)指令是否為虛擬讀取觸發器(faked read trigger) 指令,但本案不以此為限。For example, the read data instruction may be a read data from Buffer 2 instruction, and the virtual read data instruction may be a fake read trigger instruction. The second device 910 A read data from Buffer 2 command can be sent to the
在一實施例中,請參閱步驟306、步驟412及步驟413,藉由實體緩衝區111將壓縮資料傳送至記憶器匯流排120的步驟包含:藉由耦合器121確認有從第二裝置910接收虛擬讀取資料指令以傳送讀取緩衝區指令至實體緩衝區111;以及藉由實體緩衝區111根據讀取緩衝區指令以將壓縮資料傳送至耦合器121。In one embodiment, please refer to step 306,
舉例而言,讀取緩衝區指令可以為從第一緩衝器讀取請求(request read from Buffer 1)指令,耦合器121可以確認(或辨識)從第二裝置910輸出的第二緩衝器讀取資料(read data from Buffer 2)指令為虛擬讀取觸發器(faked read trigger) 指令,且耦合器121可以接著傳送從第一緩衝器讀取請求(request read from Buffer 1)指令至實體緩衝區111,實體緩衝區111根據從第一緩衝器讀取請求(request read from Buffer 1)指令以將壓縮資料傳送至耦合器121,但本案不以此為限。For example, the read buffer instruction may be a request read from Buffer 1 instruction, and the
在一實施例中,請參閱步驟307及步驟414,藉由耦合器121將壓縮資料解壓縮為解壓縮資料。在一實施例中,請參閱步驟307及步驟415,藉由記憶器匯流排120將解壓縮資料傳送至第二裝置910。舉例而言,耦合器121可以接受壓縮資料後,耦合器121將壓縮資料解壓縮為解壓縮資料(decompressed data),然後,記憶器匯流排120將解壓縮資料傳送至第二裝置910,但本案不以此為限。In one embodiment, please refer to step 307 and step 414 to decompress the compressed data into decompressed data through the
在一些實施例中,虛擬緩衝區演算法包含Linux演算法,且耦合器121包含解壓縮器。舉例而言,虛擬緩衝區演算法可以與第一演算法131A(例如:Linux系統核心(Linux kernel),如第2圖所示)相關的演算法技術,解壓縮器可以為任何泛指實體或軟體上的解壓縮器(Decompressor),記憶器匯流排120可以包含匯流偵測轉換器(MonitorWrapper)及解壓縮器(Decompressor),但本案不以此為限。In some embodiments, the virtual buffer algorithm includes a Linux algorithm and
由上述本案實施方式可知,應用本案具有下列優點。本案實施例所示之位址轉換系統及位址轉換方法得以降低消耗記憶體內資源之消耗,以達到兩個不同位址的硬體傳遞資料的效果。It can be seen from the above embodiments that the application of this case has the following advantages. The address translation system and address translation method shown in the embodiment of this case can reduce the consumption of memory resources and achieve the effect of transferring data between two hardwares with different addresses.
雖然上文實施方式中揭露了本案的具體實施例,然其並非用以限定本案,本案所屬技術領域中具有通常知識者,在不悖離本案之原理與精神的情形下,當可對其進行各種更動與修飾,因此本案之保護範圍當以附隨申請專利範圍所界定者為準。Although the above implementation mode discloses specific examples of the present case, it is not intended to limit the present case. Persons with ordinary knowledge in the technical field to which the present case belongs can, without departing from the principles and spirit of the present case, proceed with it. Various changes and modifications, therefore the scope of protection in this case shall be subject to the scope of the accompanying patent application.
100:位址轉換系統
110:儲存裝置
111:緩衝區
113:虛擬緩衝區
120:記憶器匯流排
121:耦合器(匯流偵測轉換器)
130、130A:處理器
900:第一裝置(自製產品)
910:第二裝置(外購產品)
131A:第一演算法(演算法)
133A:第二演算法(演算法)
135A:第三演算法(演算法)
300、400:位址轉換方法
301~307:步驟
401~414:步驟
100: Address translation system
110:Storage device
111:Buffer
113:Virtual buffer
120:Memory bus
121: Coupler (convergence detection converter)
130, 130A: Processor
900: First device (homemade product)
910: Second device (outsourced product)
131A: First algorithm (algorithm)
133A: Second algorithm (algorithm)
135A: The third algorithm (algorithm)
300, 400:
為讓本案之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下: 第1圖係依照本案一實施例繪示一種位址轉換系統的方塊示意圖。 第2圖係依照本案一實施例繪示一種位址轉換系統之處理器的方塊示意圖。 第3圖係依照本案一實施例繪示一種位址轉換方法的流程圖。 第4圖至第6圖係依照本案一實施例繪示另一種位址轉換方法的流程圖。 根據慣常的作業方式,圖中各種特徵與元件並未依比例繪製,其繪製方式是為了以最佳的方式呈現與本案相關的具體特徵與元件。此外,在不同圖式間,以相同或相似的元件符號來指稱相似的元件/部件。 In order to make the above and other purposes, features, advantages and embodiments of this case more obvious and understandable, the attached drawings are described as follows: Figure 1 is a schematic block diagram of an address translation system according to an embodiment of the present invention. Figure 2 is a schematic block diagram of a processor of an address translation system according to an embodiment of the present invention. Figure 3 is a flow chart illustrating an address translation method according to an embodiment of the present invention. Figures 4 to 6 are flow charts illustrating another address translation method according to an embodiment of the present invention. In accordance with common practice, the various features and components in the drawings are not drawn to scale, but are drawn in such a way as to best present the specific features and components relevant to this case. In addition, the same or similar reference symbols are used to refer to similar elements/components in different drawings.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date, and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without
100:位址轉換系統 100: Address translation system
110:儲存裝置 110:Storage device
111:實體緩衝區 111:Entity buffer
113:虛擬緩衝區 113:Virtual buffer
120:記憶器匯流排 120:Memory bus
121:耦合器 121:Coupler
130:處理器 130: Processor
900:第一裝置 900:First device
910:第二裝置 910:Second device
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US18/320,185 US20240104032A1 (en) | 2022-09-28 | 2023-05-18 | Address conversion system and address conversion method |
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Citations (3)
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TW201435585A (en) * | 2013-03-05 | 2014-09-16 | Htc Corp | Electronic apparatus for data access and data access method therefor |
TW201918882A (en) * | 2017-11-13 | 2019-05-16 | 韓商愛思開海力士有限公司 | Memory system and operating method thereof |
TW202225983A (en) * | 2020-12-23 | 2022-07-01 | 美商英特爾公司 | Secure address translation services using bundle access control |
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- 2022-09-28 TW TW111136841A patent/TWI813455B/en active
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Patent Citations (4)
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---|---|---|---|---|
TW201435585A (en) * | 2013-03-05 | 2014-09-16 | Htc Corp | Electronic apparatus for data access and data access method therefor |
TW201918882A (en) * | 2017-11-13 | 2019-05-16 | 韓商愛思開海力士有限公司 | Memory system and operating method thereof |
CN109783397A (en) * | 2017-11-13 | 2019-05-21 | 爱思开海力士有限公司 | Storage system and its operating method |
TW202225983A (en) * | 2020-12-23 | 2022-07-01 | 美商英特爾公司 | Secure address translation services using bundle access control |
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