WO2016170673A1

WO2016170673A1 - Computer system and memory module

Info

Publication number: WO2016170673A1
Application number: PCT/JP2015/062491
Authority: WO
Inventors: 洋重田; 江口　賢哲
Original assignee: 株式会社日立製作所
Priority date: 2015-04-24
Filing date: 2015-04-24
Publication date: 2016-10-27

Abstract

Provided is computer system, comprising a storage device which stores compressed data, and a server computer which is connected to the storage device via a PCI-Express-compliant path. The server computer further comprises a processor module, a memory module, and an expansion unit which is capable of expanding the compressed data. The processor module and the memory module are connected via a first memory bus. The storage device receives a read request which is generated upon the execution of a program in the processor module, and DMA transfers compressed data, which is data which is to be accessed, via the PCI-Express-compliant path to a program-designated region. The expansion unit generates expanded data from the DMA-transferred compressed data, and stores the expanded data in the program-designated region.

Description

Computer system and memory module

The present invention relates generally to storage control, for example, to computer system and memory module technologies.

As the performance of the server computer and the storage device is improved and the bandwidth of the back end is increased by using the flash memory for the storage device, it is required to increase the bandwidth of the connection between the server computer and the storage computer. Japanese Patent Application Laid-Open No. 2004-228561 discloses a technology for broadening the SAN bandwidth in a computer system connected via a SAN (Storage Area Network) that connects such server computers and storage devices. More specifically, a cache control program executed by the server computer reads the compressed data stored in the storage device and writes it to the drive of the flash memory of the server computer. Then, the decompression program executed by the server computer reads the compressed data from the drive of the flash memory, decompresses it, and provides it to the database program or the like.

US2013 / 0332652

In Patent Document 1, it is possible to realize a wider connection band between the server computer and the storage computer, but it is impossible to realize a wider bandwidth of the internal bus in the server computer, particularly PCI-Express or SATA (Serial ATA). This problem is expected to become a problem especially when flash memory devices are connected by PCI-Express, or when the connection bandwidth between the server computer and the storage device is close to that of PCI-Express. The

Therefore, an object of the present invention is to provide a computer system and a memory module that efficiently use a connection bandwidth between a server computer and a storage device.

A computer system according to an embodiment includes a storage device that stores compressed data of access target data, and a server computer that is at least partially connected to the storage device via a path that conforms to PCI-Express.
The server computer includes a processor module capable of executing a program, a memory module capable of storing data, and a decompression unit capable of decompressing compressed data, and the processor module and the memory module are connected via a first memory bus. .
The storage apparatus receives a read request specifying access target data that is a request generated by execution of a program in the processor module, and sends compressed data of the access target data to a program through a PCI-Express compliant path. DMA transfer to the program designated area which is designated area.
The decompression unit generates decompressed data from the compressed data transferred by DMA, and stores the generated decompressed data in the program designated area.

According to the present invention, the connection bandwidth between the server computer and the storage device can be used efficiently.

It is a block diagram which shows the structural example of the computer system which concerns on 1st Embodiment. It is a schematic diagram explaining an example of the decompression process of the compressed data which concerns on 1st Embodiment. 4 is a flowchart illustrating an example of processing of the memory module according to the first embodiment. An example of the operation in the memory module when the external command and the compressed read command according to the first embodiment coexist is shown. An example of the operation in the memory module when the external command and the buffer write command according to the first embodiment coexist is shown. It is a block diagram which shows the structural example of the computer system which concerns on 2nd Embodiment. It is a schematic diagram which shows an example of the expansion | extension process of the compressed data which concerns on 2nd Embodiment. It is a flowchart which shows an example of a process of the memory module which concerns on 2nd Embodiment. It is a block diagram which shows the structural example of the computer system which concerns on 3rd Embodiment. An example of operation | movement of 3rd Embodiment is shown. It is a block diagram which shows the structural example of the computer system which concerns on 4th Embodiment.

Hereinafter, some embodiments will be described. In the following description, an ID is used as element identification information, but other types of identification information may be used instead of or in addition to the ID. In the following description, when a description is made without distinguishing the same type of element, a reference number or a common number in the reference number is used, and when a description is made by distinguishing the same type of element, the reference number of the element is used. Alternatively, an ID assigned to the element may be used instead of the reference code. For example, when the memory device 14 is described without being particularly distinguished, it is described as “memory device 14”, and when the individual memory device 14 is described with being distinguished, it is described as “memory device 14a”. There is. In the following description, the process may be described using “program” as a subject. However, the program is executed by a processor (for example, a CPU (Central Processing Unit)), so that a predetermined process is appropriately performed. Since the processing is performed using a memory device and / or an interface device (for example, a communication port), the subject of processing may be a processor. The process described with the program as the subject may be a process or system performed by a processor or an apparatus having the processor. The processor may include a hardware circuit that performs a part or all of the processing. The program may be installed in a computer-like device from a program source. The program source may be, for example, a storage medium that can be read by a program distribution server or a computer. In the following description, two or more programs may be realized as one program, or one program may be realized as two or more programs.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a computer system 1-1 according to the first embodiment.

The computer system 1-1 includes a server computer 2-1, a storage device 4, and a CPA 6. The CPA 6 has

EPs

51a and 51b serving as endpoints of PCIe (PCI-Express) devices, and may have a switch function for transmitting and receiving data between the PCIe devices connected to the

EPs

51a and 51b.

The server computer 2-1 is connected to the EP 51 a of the CPA 6 through the PCIe network 82. The storage device 4 is connected to the EP 51 b of the CPA 6 through the PCIe network 80. Therefore, the server computer 2-1 and the storage device 4 can bidirectionally transmit and receive data in accordance with the PCIe standard.

The storage device 4 performs data read processing / write processing and the like in response to a read / write request from the server computer 2-1. The storage device 4 includes one or more storage drives 42 that store data, and a storage controller 40 that controls the storage drives 42. The storage drive 42 may be, for example, an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof.

When the storage controller 40 receives a write request from the server computer 2-1, the storage controller 40 may compress the write data corresponding to the write request and write the compressed write data 110 to the storage drive 42. When the storage controller 40 receives a read request from the server computer 2-1, the storage controller 40 may read the compressed data 110 corresponding to the read request from the storage drive 42 and send the compressed data 110 to the server computer 2-1 as it is. .

The storage controller 40 and the storage drive 42 may be connected by a SAS 81. The storage controller 40 may perform RAID control of the plurality of storage drives 42 to form a RAID group.

The server computer 2-1 sends a read request to the storage device 4 to acquire read data, or sends a write request to the storage device 4 to write the write data. The server computer 2-1 includes a processor module 30 that executes a program and the like, and a memory module 10-1 that stores the program and data. The processor module 30 and the memory module 10-1 include a DDR (Double- It may be connected by IF (InterFace) based on the Data-Rate standard. An IF based on the DDR standard that connects the processor module 30 and the memory module 10 is referred to as a first DDR IF 91.

The processor module 30 includes a memory controller 34, an RC (Root Complex) 36 based on PCIe, and a CPU core 32, which may be connected by an internal bus 38 capable of bidirectional data transmission / reception.

The CPU core 32 may be a logic circuit that executes arithmetic processing based on a program or the like.

The memory controller 34 may be a logic circuit that transmits commands and data to the memory module 10 through the first DDR IF 91 and receives commands and data transmitted from the memory module 10 through the first DDR IF 91.

RC 36 is an IF for connecting a PCIe device compliant with the PCIe standard under the server computer 2.

The memory module 10-1 includes a control unit 12-1, an expansion unit 16, an expansion buffer unit 18, and one or more memory devices 14. The control unit 12-1 and the memory device 14 may be connected by a second DDR IF 92 that is an IF based on the DDR standard. The first DDR IF 91 may be connected to the control unit 12-1. The control unit 12-1, the expansion unit 16, and the expansion buffer unit 18 may be connected by an internal bus 94 capable of bidirectional data transmission / reception.

The decompression unit 16 is a logic circuit that decompresses the compressed data. The decompression unit 16 may be configured by an ASIC (Application Specific Integrated Circuit). Data decompressed by the decompression unit 16 may be referred to as decompressed data.

The decompression buffer unit 18 is a storage device that temporarily stores decompressed data.

The decompression completion flag 20 is a flag indicating whether or not decompression of compressed data in the memory module 10 and storage of the decompressed data in the memory device 14 are completed. The decompression completion flag 20 may be configured as a register controlled by the control unit 12-1.

The memory device 14 is a storage device that stores data. The memory device 14 is, for example, a DDR SDRAM that conforms to the DIMM (Dual Inline Memory Modules) standard.

In the first embodiment, the storage controller 40 maintains the compressed data 110 stored in the storage drive 42 in a compressed state (without expansion in the storage apparatus 4) through the

networks

80 and 82 and the CPA 6. DMA transfer to the server computer 2-1. Then, the RC 36 of the processor module 30 of the server computer 2-1 transfers the DMA-transferred compressed data 110 to the memory module 10-1. Then, the controller 12-1 of the memory module 10-1 stores the DMA-transferred compressed data 110 in the memory device 14. The decompressing unit 16 generates decompressed data 210 from the compressed data stored in the memory device 14 and stores the decompressed data 210 in the decompressing buffer unit 18. The control unit 12-1 stores the decompressed data 210 stored in the decompression buffer unit 18 in the memory device 14 at an appropriate timing. As a result, the compressed data 110 is transferred in the sections of the

networks

80 and 82, the CPA 6 and the first DDR IF 91. Therefore, compared with the case where the compressed data is decompressed and transferred by the storage apparatus 4, the data transfer amount ( Connection bandwidth) can be reduced. Details of this process will be described below.

FIG. 2 is a schematic diagram illustrating an example of compressed data decompression processing according to the first embodiment.

As shown in FIG. 2, the uncompressed data (decompressed data) 210 may be composed of a plurality of data blocks 211-214. Here, the size of one data block before compression is 8 KB. In this case, the size of the data 210 before compression is 32 KB. As shown in FIG. 2, the compressed data 210 may be composed of compressed blocks 111 to 114 compressed for each data block. Here, the size of the compressed block 111 of the data block 211 is 2 KB, the size of the compressed block 112 of the data block 212 is 4 KB, the size of the compressed block 113 of the data block 113 is 6 KB, and the size of the compressed block 114 of the data block 214 is 6 KB. And In this case, the size of the compressed data 110 (the total of the compressed blocks 111 to 114) is 18 KB.

Hereinafter, an example of processing until the compressed data 110 is stored in the memory device 14 of the server computer 2-1 in a compressed state will be described.
(S11) The read program of the processor module 30 transmits a read request for the compressed data 110 to the storage controller 40.
(S12) Upon receipt of the read request, the storage controller 40 transmits a DMA command including information on the compressed data 110 corresponding to the read request to the RC 36. Information related to the compressed data 110 includes the size of the data block before compression (8 KB), the number of data blocks constituting the compressed data (four), the size of the compressed data (18 KB), and the storage destination in the memory device 14. The first address (for example, address X) may be included. Receiving this notification, the RC 36 notifies the control unit 12-1 to prepare for reception related to the DMA transfer of the compressed data 110. Upon receiving this notification, the control unit 12-1 secures the storage area “address X to address X + 32 KB” in the memory device 14, for example.
(S13) The storage controller 40 transmits the compressed data 110 to the memory module 10-1 by DMA transfer. The compressed data 110 is transferred to the control unit 12-1 of the memory module 10-1 through the

networks

80 and 82, the CPA 6, and the RC 36.
(S14) The control unit 12-1 of the memory module 10-1 stores the received compressed data 110 in a storage area secured in the memory device 14 in a compressed state. At this time, the control unit 12 stores the compressed data 110 so that the end of the compressed data 110 is the end address “address X + 32 KB” of the storage area. For example, when the size of the compressed data is 18 KB, the control unit 12 stores the compressed data 110 from the position “address X + 14 KB” in the storage area.
(S15) The control unit 12 reads out one compressed block 111 (2 KB) constituting the compressed data 110 from the storage area through the second DDR IF 92, and passes it to the decompression unit 16. The decompression unit 16 generates the decompression block 211 (8 KB) from the compression block 111 (2 KB) and stores it in the decompression buffer unit 18.
(S16) The control unit 12 reads the decompression block 211 from the decompression buffer unit 18, transmits the decompression block 211 to the memory device 14 through the second DDR IF 92, and stores it from the head position “address X” of the storage area.
(S17) The control unit 12 reads the compressed block 112 (4 KB) from the storage area through the second DDR IF 92 and passes it to the decompression unit 16 as in S15. The decompression unit 16 generates a decompression block 212 (8 KB) from the compression block 112 (4 KB) and stores it in the decompression buffer unit 18.
(S18) As in S16, the control unit 12 reads the decompression block 212 from the decompression buffer unit 18, transmits the decompression block 212 to the memory device 14 through the second DDR IF 92, and is positioned next to the decompression block 211 in the storage area. Store from "address X + 8KB".
(S19) The compressed

blocks

113 and 114 are similarly expanded, and the expanded

blocks

213 and 214 are stored in the storage area.
(S20) After completing the decompression of all the compressed blocks 111 to 114, the control unit 12 changes the decompression completion flag 20 to “ON”.
(S21) The read program of the processor module 30 may check the decompression completion flag 20 in a predetermined cycle, and if the decompression completion flag 20 is “ON”, it may be determined that the read request processing has been completed. Instead of setting the decompression completion flag 20 to “ON”, the control unit 12 may notify the processor module 30 that the decompression has been completed.

According to the first embodiment, the capacity allocated to the decompression buffer unit 18 can be reduced to the size of the data block before compression (8 KB).

FIG. 3 is a flowchart showing an example of processing of the memory module 10-1 according to the first embodiment.

The control unit 12-1 of the memory module 10-1 receives a read / write command (including DMA transfer of compressed data from the storage controller 40) transmitted from the outside through the first DDR IF 91, and the internal of the memory module 10-1. It is necessary to process commands issued from the decompression unit 16 and the decompression buffer unit 18. When the processing of one decompression block is completed, the decompression unit 16 requests the next compressed block from the control unit 12-1. The decompression buffer unit 18 requests the control unit 12 to write the buffer data (that is, the decompressed block) to the memory device 14 when its buffer is full.

Therefore, the control unit 12-1 receives the read / write command (referred to as “external command”) received through the first DDR IF 91, the compressed block read command (referred to as “compressed read command”) received from the decompression unit 16, and the decompression buffer. The decompression block write command (referred to as “buffer write command”) received from the unit 18 needs to be processed. The compressed read command and buffer write command issued in the memory module 10-1 are sometimes collectively referred to as “internal commands”.

Here, for the external command received through the first DDR IF 91, the memory module 10-1 performs processing corresponding to the external command at the timing when the specified number of clocks has elapsed since the reception of the external command according to the DIMM standard. There is a need to. For example, when an external read command is received, the memory module 10-1 needs to return read data to the transmission source of the external read command at a timing 12 clocks after the external read command is received. For example, when an external write command is received, the memory module 10-1 receives write data transmitted from the transmission source of the external write command at a timing 11 clocks after the external write command is received. There is a need. Therefore, for example, the control unit 12-1 performs the following processing shown in FIG.

The control unit 12-1 confirms the command being received (S101).

When the command being received is only an external command or only an internal command (S101: only an external command or only an internal command), the control unit 12-1 performs the following processing. The control unit 12-1 secures a prescribed clock conforming to the DIMM standard for the address line and data line of the second DDR IF 92 (S110). Then, the control unit 12-1 returns to S101. The prescribed clock may be different for each command as follows, for example.

When only the external read command is being received, the control unit 12-1 sends the external read command to the memory device 14-1 after 6 clocks when the external read command is received for the address line of the second DDR IF92. To ensure. Then, the control unit 12-1 obtains, from the memory device 14 of the read data corresponding to the external read command, four clocks after 12 clocks at the time of receiving the external read command for the data line of the second DDR IF92. Secure.

When only the external write command is being received, the control unit 12-1 secures the address line of the second DDR IF 92 for sending the external write command to the memory device 14 after 6 clocks when the external write command is received. To do. Then, the control unit reserves four clocks for the data line of the second DDR IF 92 for 11 clocks after the reception of the external write command for sending the write data corresponding to the external write command to the memory device 14.

When only the compressed read command from the decompression unit 16 is being received, the control unit 12-1 uses the second DDR IF 92 address line for sending a compressed read command after at least 4 clocks have elapsed from the previously sent command. To ensure. When 4 clocks or more have elapsed from the previously sent command, the control unit 12-1 may reserve the latest clock for sending the compressed read command.

Next, processing of the control unit 12-1 when a plurality of commands (external commands and internal commands) are being received (S101: multiple commands) will be described.

In this case, the control unit 12-1 determines whether it is necessary to delay the internal command (S130). This is because, as described above, external commands need to be processed with a specified number of clocks according to the DIMM specification. However, if an internal command is processed first, external commands cannot be processed with a specified number of clocks. Because there is. In this case, the control unit 12-1 determines “YES” in S130, and delays the clock reserved for the internal command in the second DDR IF 92 (S120). That is, the control unit 12-1 reserves a clock later than the clock being secured for the internal command. As a result, the securing of the external command is prioritized in the second DDR IF 92, so that the external command can be processed with the specified number of clocks. Then, the control unit 12-1 returns to S101. When there is no need to delay the internal command (S130: NO), the control unit 12 may proceed to S110.

Through the above processing, the memory module 10-1 can achieve acquisition, decompression, and storage of the internal compressed block while satisfying the regulations regarding the number of clocks of the DIMM for the external command.

FIG. 4 shows an example of the operation in the memory module 10-1 when an external command and a compressed read command are mixed. Hereinafter, processing at several clocks will be described with reference to FIG.

<Clock “0”>
The control unit 12-1 receives the compression read command B1R from the decompression unit 16. Here, the control unit 12-1 determines that “only the compressed read command (internal command)” in S101 of FIG. 3, and sends the compressed read command B1R to the address line 92a of the second DDR IF. Then, the control unit 12-1 compresses the data corresponding to the compressed read command B1R for 4 clocks (clocks “6 to 9”) from the 6th clock after receiving the compressed read command B1R for the data line 92b of the second DDR IF. Secured for acquisition of lead block B1RD.

Also, the control unit 12-1 receives the external read command A1R through the address line 91a of the first DDR IF. Here, the control unit 12-1 determines that “only an external command” in S101 of FIG. 3, and after 6 clocks (clock “6”) at the time of receipt of the external read command A1R for the address line 92a of the second DDR IF. Reserved for sending the external read command A1R. Then, the control unit 12-1 sets the external read command A1R for 4 clocks (clocks “12 to 15”) after 12 clocks (K10) when the external read command A1R is received for the data line 92b of the second DDR IF. Secured for acquisition of corresponding external read data A1RD.

The control unit 12-1 sends the compressed read command B1R to the address line 92a of the second DDR IF, and for the data line 92b of the second DDR IF, four clocks (clocks “6-9” after 6 clocks from the sending). ") Is reserved for acquisition of the compressed read data B1RD. Then, the control unit 12-1 notifies the decompression unit 16 that the compressed read command B1R has been sent. Upon receiving this notification, the decompression unit 16 transmits the compressed read command B2R to the control unit 12-1 at the next clock.

<Clock “1”>
The control unit 12-1 receives the compression read command B2R from the decompression unit 16. Here, the control unit 12-1 determines to be “multiple commands” in S101 of FIG. 3 (because it has the external read command A1R and the compressed read command B2R), and needs to delay the compressed read command B2R (internal command). It is determined whether or not (S130). This determination is performed as follows, for example.

If the compressed read command B2R is sent to the address line 92a of the second DDR IF 4 clocks (clock "4") after the compressed read command B1R (clock "0"), the data line 92b of the second DDR IF Therefore, it is necessary to secure four clocks (clocks “10 to 13”), six clocks after sending the compressed read command B2R, for acquiring the compressed read data B2RD from the memory device. However, for the data line 92b of the second DDR IF, this clock “10 to 13” is partially overlapped with the clock “12 to 15” reserved for acquiring the external read data A1RD above. I can't. Therefore, the controller 12-1 determines in S130 that the compressed read command B2R needs to be delayed (S130: YES). In this case, the control unit 12-1 acquires the compressed read command B2R after completing the acquisition of the external read data A1RD (clock “15”) for the data line 92b of the second DDR IF (clock “16”). It is necessary to ensure. Therefore, the control unit 12-1 reserves the clock “10 (= 16-6)” for the second DDR IF command line 92a for acquisition of the compressed read command B2R, and the clock “16 to 16” for the second DDR IF data line 92b. 19 "is reserved for obtaining the compressed read data B2RD.

<Clock “6”>
The controller 12-1 sends the external read command A1R to the address line 92a of the second DDR IF. Further, the control unit 12-1 acquires the external read data B1RD through the data line 92b of the second DDR IF and passes it to the decompression unit 16 (clocks “6 to 9”).

<Clock “10”>
The control unit 12-1 sends the compressed read command B2R to the address line 92a of the second DDR IF, and for the data line 92b of the second DDR IF, four clocks (clocks “16 to 19”) 6 clocks after the sending. Is secured for obtaining the compressed read data B2RD. Then, the control unit 12-1 notifies the decompression unit 16 that the compressed read command B2R has been sent. Upon receiving this notification, the decompression unit 16 transmits a compressed read command B3R to the control unit 12-1 at the next clock. Also, the control unit 12-1 receives the external write command A2W through the address line 91a of the first DDR IF. Here, the control unit 12-1 determines that “external command only” in S101 of FIG. 3, and after 6 clocks (clock “16”) from the reception of the address line 92a of the second DDR IF, the control unit 12-1 receives the external write command A2W. For the data line 92b of the second DDR IF, 4 clocks (clocks “21 to 24”) 11 clocks after the reception are secured for sending the external write data A2WD.

<Clock “11”>
The control unit 12-1 receives the compression read command B3R from the decompression unit 16. Here, the control unit 12-1 determines “multiple commands” in S101 of FIG. 3 (because it has the external write command A2W and the compressed read command B3R), and determines whether or not it is necessary to delay the compressed read command B3R. Determine (S130). If the compressed read command B3R is sent to the address line 92a of the second DDR IF four clocks (clock "14") after the compressed read command B2R (clock "10"), the data line 92b of the second DDR IF is transmitted. Therefore, 4 clocks (clocks “20 to 23”) after 6 clocks when the compressed read command B3R is output must be secured for acquiring the compressed read data B3RD. However, for the data line 93b of the second DDR IF, this clock “20-23” cannot be secured because it partially overlaps with the clock “21-24” secured for sending the external write data A2WD. . Therefore, the control unit 12 determines that it is necessary to delay the compressed read command B3R in S130 (S130: YES). In this case, the control unit 12-1 reserves the second DDR IF address line 92a for sending the compressed read command B3R after 4 clocks (clock “20”) after sending the external write command A2W.

<Clock “12”>
The control unit 12-1 acquires the external read data A1RD through the data line 92b of the second DDR IF (clocks “12 to 15”). Then, the control unit 12-1 sends the external read data A1RD to the data line 91b of the first DDR IF.

<Clock “16”>
The controller 12-1 sends the external write command A2W to the address line 92a of the second DDR IF. Further, the control unit 12-1 acquires the compressed read data B2RD through the data line 92b of the second DDR IF and passes it to the decompression unit 16 (clocks “16 to 19”).

<Clock “20”>
The control unit 12-1 sends the compressed read command B3R to the address line 92a of the second DDR IF, and for the data line 92b of the second DDR IF, four clocks (clocks “26 to 29”) 6 clocks after the sending. Is secured for obtaining the compressed read data B2RD. Then, the control unit 12-1 notifies the decompression unit 16 that the compressed read command B3R has been sent. Upon receiving this notification, the decompression unit 16 transmits the compressed read command B4R to the control unit 12-1 at the next clock.

<Clock “21”>
The control unit 12-1 receives the compression read command B4R from the decompression unit 16. Here, the control unit 12-1 determines “compressed read command (internal command only)” in S101 in FIG. 3, and after sending the compressed read command B3R to the address line 92a of the second DDR IF, four clocks later ( Clock "24") is reserved for sending the compressed read command B4R. Further, the control unit 12-1 sends the external write data A2WD acquired through the data line 91b of the first DDR IF to the data line 92b of the second DDR IF (clocks “21 to 24”).

<Clock “26”>
The control unit 12-1 acquires the compressed read data B3RD through the data line 92b of the second DDR IF, and passes it to the decompression unit 16 (clocks “26 to 29”).

As described above, when the control unit 12-1 receives a compressed read command which is a kind of internal command while delaying the external command by 6 clocks, the control unit 12-1 supposes that the compressed read command is 4 from the transmission of the previous command. If the external read / write data corresponding to the external read / write command cannot be processed with the specified clock when it is sent to the address line 92a of the second DDR IF after the clock, the sending of the compressed read command is delayed. As a result, the memory module 10-1 can appropriately process the compressed read command while processing the external read / write command received through the first DDR IF 91 with the specified clock.

FIG. 5 shows an example of the operation in the memory module 10-1 when an external command and a buffer write command coexist. Hereinafter, processing at several clocks will be described with reference to FIG.

<Clock “0”>
The control unit 12-1 receives the buffer write command C1W from the buffer 18. Here, the control unit 12-1 determines that “only the buffer write command (internal command)” in S101 of FIG. 3, and sends the buffer write command C1W to the address line 92a of the second DDR IF. The control unit 12-1 then transfers the buffer corresponding to the buffer write command C1W for four clocks (clocks “5 to 8”) after five clocks at the time of transmission of the buffer write command C1W for the data line 92b of the second DDR IF. Secured for sending write data C1WD.

Also, the control unit 12-1 receives the external read command A1R through the address line 91a of the first DDR IF. Here, the control unit 12 determines that “external command only” in S101 of FIG. 3, and after 6 clocks (clock “6”) at the time of receiving the external read command A1R for the address line 92a of the second DDR IF, Reserved for sending the read command A1R. Then, the control unit 12-1 uses the data line 92b of the second DDR IF for four clocks (clocks “12 to 15”) after 12 clocks (K30) when the external read command A1R is received as the external read command A1R. Secured for acquisition of corresponding external read data A1RD.

The control unit 12-1 outputs the buffer write command C1W to the address line 92a of the second DDR IF, and for the data line 92b of the second DDR IF, four clocks (clocks “6-9” after 6 clocks from the transmission). ") Is reserved for acquisition of the compressed read data B1RD. Then, the control unit 12-1 notifies the decompression buffer unit 18 that the buffer write command C1W has been sent. Upon receiving this notification, the decompression buffer unit 18 sends a buffer write command C2W to the control unit 12-1 at the next clock.

<Clock “1”>
The control unit 12-1 receives the buffer write command C2W from the decompression buffer unit 18. Here, the control unit 12-1 determines “multiple commands” in S101 of FIG. 3 (because it has the external read command A1R and the buffer write command C2W), and determines whether or not the buffer write command C2W needs to be delayed. Determine (S130). This determination is performed as follows, for example.

If the buffer write command C2W is sent to the address line 92a of the second DDR IF 4 clocks after the buffer write command C1W (clock "4"), the buffer write command C2W is sent to the data line 92b of the second DDR IF. It is necessary to secure 4 clocks (clocks “9 to 12”) after 5 clocks for sending the buffer write block C2WD. However, for the data line 92b of the second DDR IF, this clock “9 to 12” is partially overlapped with the clock “12 to 15” reserved for acquiring the external read data A1R as described above. I can't. Therefore, the control unit 12-1 determines that it is necessary to delay the buffer write command (internal command) in S130 (S130: YES). In this case, the control unit 12-1 waits for one clock (clock “17”) after completing the acquisition of the external read data A1RD (clock “15”) for the second DDR IF data line 92 b, It is necessary to ensure transmission of the write block C2WD. Here, the reason is that one clock is left because the data line 92b of the second DDR IF needs to be switched from read to write. Therefore, the control unit 12-1 reserves the clock “12 (= 17-5)” for the second DDR IF command line 92a for sending the buffer write command C2W, and the clock “17 to 17” for the second DDR IF data line 92b. 20 "is reserved for sending buffer write data C2WD.

<Clock “5”>
The control unit 12-1 sends the buffer write data C1WD to the data line 92b of the second DDR IF (clocks “5 to 8”).

<Clock “6”>
The controller 12-1 sends the external read command A1R to the address line 92a of the second DDR IF.

<Clock “11”>
The control unit 12-1 receives the external write command A2W through the address line 91a of the first DDR IF. Here, the control unit 12-1 determines “multiple commands” in S101 of FIG. 3 (because it has the external write command A2W and the buffer write command C2W), and determines whether or not it is necessary to delay the buffer write command C2W. Determine (S130). This determination is performed as follows, for example.

Assuming that the external write command A2W is sent to the address line 92a of the second DDR IF 6 clocks after receiving the external write command A2W (clock “17”) as specified, the data line 92b of the second DDR IF It is necessary to secure 4 clocks (clocks “22 to 25”) 11 clocks after receiving the external write command A2W for sending the external write data A2WD. This does not overlap with the clocks “17 to 20” reserved for sending the buffer write data C2WD for the data line 92b of the second DDR IF. Therefore, the control unit 12-1 determines that it is not necessary to delay the buffer write command C2W (internal command) in S130 (S130: NO), and uses the buffer “12” for the clock “12” for the command line 92a of the second DDR IF. Keep reserved for C2W transmission.

<Clock “12”>
The control unit 12-1 sends the buffer write command C2W to the address line 92a of the second DDR IF. Then, the control unit 12-1 notifies the decompression buffer unit 18 that the buffer write command C2W has been sent. Upon receiving this notification, the decompression buffer unit 18 sends a buffer write command C3W to the control unit 12-1 at the next clock “13”. Further, the control unit 12-1 acquires the external read data A1RD through the data line 92b of the second DDR IF and sends it to the data line 91b of the first DDR IF (clocks “12 to 15”).

<Clock “13”>
The control unit 12-1 receives the buffer write command C3W from the decompression buffer unit 18. Here, the control unit 12-1 determines “multiple commands” in S101 of FIG. 3 (because it has the external write command A2W and the buffer write command C3W), and whether or not it is necessary to delay the buffer write command C3W. Is determined (S130). If the buffer write command C3W is transmitted 4 clocks after the buffer write command C2W (clock “16”), the data line 92b of the second DDR IF is 4 clocks (clock “5” after the transmission). 21 to 24 ") must be secured for sending the buffer write data C3WD corresponding to the buffer write command C3W. However, for the data line 92b of the second DDR IF, this clock “21 to 24” cannot be secured because it overlaps with the clock “22 to 25” secured for sending the external write data A2WD above. Therefore, the control unit 12-1 determines that it is necessary to delay the buffer write command C2W in S130 (S130: YES). In this case, the control unit 12-1 uses four clocks (clocks “26 to 29”) after transmission of the external write data A2WD is completed for transmission of the buffer write data C3WD to the data line 92b of the DDR IF. May be secured. Therefore, the control unit 12-1 reserves the clock “21 (= 26-5)” for the command line 92a of the second DDR IF for transmission of the buffer write command C3W, and the clock “26 to 26” for the data line 92b of the second DDR IF. 29 "is reserved for sending buffer write data C3WD.

<Clock “17”>
The controller 12-1 sends the external write command A2W to the address line 92a of the second DDR IF. Further, the control unit 12-1 sends the buffer write data C2WD to the data line 92b of the second DDR IF (clocks “17 to 20”).

<Clock “21”>
The control unit 12-1 sends the buffer write command C3W to the address line 92a of the second DDR IF. Then, the control unit 12-1 notifies the decompression buffer unit 18 that the buffer write command C3W has been sent. Receiving this notification, the decompression buffer unit 18 sends a buffer write command C4W to the control unit at the next clock “22”.

<Clock “22”>
The control unit 12-1 receives the buffer write command C4W from the decompression buffer unit 18. Here, the control unit 12-1 determines in S101 that “only a buffer write command (internal command)” and four clocks after sending the buffer write command C3W to the address line 92a of the second DDR IF (clock “25”). ") Is reserved for sending the received buffer write command C4W. Also, the control unit 12-1 sends the external write data A2WD acquired through the data line 91a of the first DDR IF to the data line 92b of the second DDR IF (clocks “22 to 25”).

<Clock “25”>
The control unit 12-1 sends the buffer write command C4W to the address line 92a of the second DDR IF. Then, the control unit 12-1 notifies the decompression buffer unit 18 that the buffer write command C2W has been sent.

<Clock “26”>
The control unit 12-1 sends the buffer write data C3WD to the data line 92b of the second DDR IF (clocks “26 to 29”).

As described above, when the control unit 12-1 receives a buffer write command which is a kind of internal command while delaying the external command by 6 clocks, the control unit 12-1 supposes that the buffer write command is 4 from the transmission of the previous command. If the external read / write data corresponding to the external read / write command cannot be processed with the specified clock when it is transmitted to the address line 92a of the second DDR IF after the clock, the transmission of the buffer write command is delayed. As a result, the memory module 10-1 can appropriately process the buffer write command while processing the external read / write command received through the first DDR IF 91 with the specified clock.

(Second Embodiment)
FIG. 6 is a block diagram illustrating a configuration example of the computer system 1-2 according to the second embodiment. FIG. 7 is a schematic diagram illustrating an example of compressed data decompression processing according to the second embodiment. In the description of the second embodiment, the same elements as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

The memory module 10-2 according to the second embodiment further includes a compression buffer unit 19 and a buffer free space register 22 indicating the free space of the compression buffer unit 19. Hereinafter, the capacity of the compression buffer unit 19 is set to 16 KB, the size of the data before compression (after decompression) is 64 KB, and the size of the compressed data is 32 KB, with reference to FIGS. 6 and 7, the server computer according to the second embodiment An operation example 2-2 will be described.

(S41) The read program of the processor module 30 transmits a read request for the compressed data 110 to the storage controller 40.
(S42) Upon receipt of the read request, the storage controller 40 transmits a DMA command including information on the compressed data 110 corresponding to the read request to the RC 36. The information regarding the compressed data 110 may include the size of data before compression (64 KB) and the start address (for example, address X) of the storage destination in the memory device 14. Receiving this notification, the RC 36 notifies the control unit 12-2 to prepare for reception of the compressed data 110 relating to DMA transfer. Upon receiving this notification, the control unit 12-2 secures the storage area “address X to address X + 64 KB” in the memory device 14, for example.
(S43) The storage controller 40 transmits the compressed data 110 to the memory module 10-2 by DMA transfer. The compressed data 110 is transferred to the control unit 12-2 of the memory module 10-2 through the

networks

80 and 82, the CPA 6, and the RC 36.
(S44) When the buffer free space register 22 is “16 KB”, the control unit 12-2 of the memory module 10-2 compresses the compressed data for 16KB indicated by the buffer free space 22 in the received compressed data 110. Store in the buffer unit 19. The decompression unit 16 extracts 12 KB of compressed data from the compression buffer unit 19 to generate decompressed data 221 and stores the decompressed data 221 in the storage area of the memory device 14. As a result, the buffer free capacity register 22 becomes “12 KB”.
(S45) Since the buffer free space register 22 is “12 KB”, the control unit 12-2 stores the compressed data for 12 KB indicated by the buffer free space register 22 in the compressed buffer unit 19 among the remaining compressed data 121. . The decompression unit 16 extracts 12 KB of compressed data from the compression buffer unit 19 to generate decompressed data 222 and stores the decompressed data 222 in the storage area of the memory device 14. By repeating S43 to S45, the decompressed data is stored in the storage area of the memory device 14.
(S46) After storing all the decompressed data in the storage area of the memory device 14, the control unit 12-2 sets the decompression completion flag 20 to “ON”.
(S47) The read program of the processor module 30 may check the decompression completion flag 20 at a predetermined cycle, and if the decompression completion flag 20 is “ON”, it may be determined that the read request processing has been completed.

According to the above processing, compared with the first embodiment, it is unnecessary to acquire compressed data from the memory device 14 through the second DDR IF 92 and pass it to the decompression unit 16 in the memory module 10-2. The data transfer amount in the second DDR IF 92 can be reduced.

FIG. 8 is a flowchart showing an example of processing of the memory module 10-2 according to the second embodiment. In the description of FIG. 8, the same processes as those in FIG.

The control unit 12-2 confirms the command being received (S201). When the command being received is a plurality of commands (S201: a plurality of commands), the control unit 12-2 performs the processing after S130 shown in FIG. When the command being received is only an internal command (S201: only the internal command), the control unit 12-2 performs the processing after S110 shown in FIG.

When the command being received is only an external command (S201: only external command), the control unit 12-2 performs the following processing. The control unit 12-2 uses a compressed data write command (referred to as “compressed write command”) transmitted from the storage controller 40 or a normal read / write command (“ It is determined whether it is a “normal command” (S204).

When the external command is a normal command (S204: normal command), the control unit 12-2 performs the processing after S110 shown in FIG.

If the external command is a compressed write command (S204: compressed write command), the control unit 12-2 receives the compressed data corresponding to the compressed write command and stores it in the compression buffer unit 19 (S206). Return to processing. The compressed data stored in the compression buffer unit 19 is expanded by the expansion unit 16 and written to the memory device 14 as described above.

(Third embodiment)
FIG. 9 is a block diagram illustrating a configuration example of a computer system 1-3 according to the third embodiment. FIG. 10 is a diagram for explaining an example of the operation of the third embodiment. Note that the CPA 6 and the storage device 4 in the third embodiment have the same configuration as in the first embodiment, and thus the description of the drawings is omitted.

The server computer 2-3 according to the third embodiment includes a plurality of memory modules 10-1a and 10-1b. The memory modules 10-1a and 10-1b according to the third embodiment may have the same configuration as the memory module 10-1 according to the first embodiment. Alternatively, the configuration may be the same as that of the memory module 10-2 according to the second embodiment.

The processor module 30 can transmit and receive data to and from the memory modules 10-1a and 10-1b through the first DDR IF 91. The control unit 12-1a of the memory module 10-1a can transmit and receive data to and from the memory device 14c through the second DDR IF 92c, and the control unit 12-1b of the memory module 10-1b can communicate with the memory device 14d through the second DDR IF 92d. Data can be sent and received. That is, the

second DDR IFs

92c and 92d are independent.

For example, the server computer 2-3 according to the present embodiment can operate as follows (see FIG. 10).
(S61) The RC 36 of the processor module 30 transfers the compressed data 400a transferred from the storage device 4 to the memory module 10-1a through the data line 91c of the first DDR IF 91. In the memory module 10-1a, the decompressed data 402a obtained by decompressing the compressed data 400a is stored in the storage area of the memory device 14c through the data line 92c of the second DDR IF.
(S62) After completing the transfer of the compressed data 400a, the RC 36 of the processor module 30 transfers the compressed data 400b transferred from the storage device 4 to the memory module 10-1b through the data line 91c of the first DDR IF 91. In the memory module 10-1b, the decompressed data 402b obtained by decompressing the compressed data 400b is stored in the storage area of the memory device 14d through the data line 92d of the second DDR IF.

For example, when the compression rates of the

compressed data

400a and 400b are 50%, when the compressed data 400b is transferred in S62, the memory module 10-1a completes the expansion of the previously transferred compressed data 400a. ing. Therefore, the processor module 30 can read the decompressed data 404a from the memory module 10-1a immediately after the completion of S62. Since the decompression of the compressed data 400b transferred to the memory module 10-1b is completed while the decompressed data 404a is being read, the processor module 30 immediately after reading the decompressed data 404a. The decompressed data 404b can be read from 1b.

In this way, by transferring the compressed data separately to the plurality of memory modules 10-1a, 10-1b, a predetermined amount of compressed data is expanded as compared with the case where the compressed data is transferred to one memory module 10. Thus, the time required for storing in the memory device 14 and the time required for the processor module 30 to acquire decompressed data from the memory module 10 can be reduced.

(Fourth embodiment)
FIG. 11 is a block diagram illustrating a configuration example of a computer system 1-4 according to the fourth embodiment. Note that the CPA 6 and the storage apparatus 4 in the fourth embodiment have the same configuration as that in the first embodiment, and thus the description of the drawings is omitted.

In the server computer 2-4 according to the fourth embodiment, the processor module 30-4 includes the decompression unit 16 included in the memory module 10 in the first to third embodiments. That is, the server computer 2-4 includes a processor module 30-4 and one or

more memory devices

14e and 14f. The processor module 30-4 includes the memory controller 34, the CPU core 32, the RC 36, and the decompression unit 16. And have. The processor module 30-4 may further include a cache unit 33. The processor module 30-4 can transmit / receive data to / from one or

more memory devices

14e and 14f through the second DDR IF 92.

The server computer 2-4 according to the present embodiment operates as follows, for example.
(S81) The RC 36 of the processor module 30-4 passes the compressed data DMA-transferred from the storage device 4 to the decompression unit 16.
(S82) The decompression unit 16 generates decompressed data 210 from the compressed data, and stores the decompressed data 210, for example, in the storage area of the memory device 14e through the second DDR IF 92. When the processor module 30-4 includes the cache unit 33, the decompressed data 210 may be once written in the cache unit 33 and then stored in the storage area of the memory device 14e.

In the case of the fourth embodiment, since the RC 36 buffers the received compressed data, it is not necessary to provide the compression buffer unit 19 in the memory module 10-2 as in the second embodiment.

Further, by decompressing the compressed data by the processor module 30-4, the decompressed data can be distributed and written to the plurality of

memory devices

14e and 14f by memory interleaving. That is, the I / O of decompressed data to the memory device 14 can be speeded up.

Although several embodiments have been described above, these are examples for explaining the present invention, and the scope of the present invention is not intended to be limited only to these embodiments. The present invention can be implemented in various other forms.

1: Computer system 2: Server computer 6: CPA 4: Storage device 10: Memory module 30: Processor module 40: Storage controller 42: Storage drive

Claims

A storage device that stores compressed data of access target data, and a server computer that is at least partially connected to the storage device via a path that conforms to PCI-Express,
The server computer includes a processor module capable of executing a program, a memory module capable of storing data, and a decompression unit capable of decompressing compressed data, and the processor module and the memory module are connected through a first memory bus. Has been
The storage device receives a read request specifying access target data that is a request generated by execution of a program in the processor module, and sends compressed data of the access target data to the PCI-Express compliant path Through the DMA (Direct Memory Access) to the program designated area that is designated by the program,
The decompression unit generates decompression data from the DMA-transferred compressed data, and stores the created decompression data in the program designated area.
2. The computer system according to claim 1, wherein when the compressed data is DMA-transferred, the storage apparatus notifies the memory module of information related to the compressed data before transferring the compressed data.
The program specified area is a specified area in the memory module,
The computer system according to claim 2, wherein the compressed data is transferred to the memory module through the first memory bus.
The decompression unit is included in the memory module,
The compressed data is stored in the program designated area in the memory module in a compressed state,
The computer system according to claim 3, wherein the decompressing unit generates decompressed data from the compressed data stored in the program designated area.
The computer system according to claim 4, wherein the compressed data is stored in the program designation area in the memory module in a trailing manner.
The memory module further includes a decompression buffer unit for temporarily storing decompressed data generated by the decompression unit,
The compressed data is compressed so that the decompressed data after decompression has a predetermined size or less,
The decompression unit generates decompressed data from the compressed data stored in the program designated area in the memory module, stores the generated decompressed data in the decompression buffer unit,
6. The computer system according to claim 5, wherein the decompressed data stored in the decompression buffer unit is stored in the program designation area in the memory module in a front-justified manner.
The computer system according to claim 6, wherein a program executed by the processor module monitors whether or not decompression processing of all compressed data transferred to the memory module is completed.
The decompression unit is included in the memory module,
The program designated area is a designated area in a memory device included in the memory module,
The memory module further includes a control unit that controls the decompression unit, the memory device, and an decompression buffer unit for temporarily storing decompressed data generated by the decompression unit,
The control unit and the memory device are connected through a second memory bus, the first memory bus and the second memory bus comply with DDR (Double-Data-Rate),
The controller is
If an external command received through the first memory bus is waiting to be sent to the second memory bus when an internal command is received from the decompression unit or the decompression buffer unit, the first command of the internal command is sent. 3. The computer system according to claim 2, wherein it is determined whether or not it is necessary to delay sending to the memory bus after sending the external command.
When the internal command is sent to the second memory bus, the control unit delays sending the internal command to the second memory device if the external command cannot realize processing conforming to DDR. The computer system according to claim 8, wherein it is determined that it is necessary to perform the operation.
The decompression unit is included in the processor module,
The server computer includes a plurality of memory devices,
The computer system according to claim 2, wherein the decompressed data generated by the decompressing unit from the compressed data is distributed and written to the plurality of memory devices by memory interleaving.
A decompression unit capable of decompressing the compressed data;
A memory device having a data storage area;
A control unit for controlling the decompression unit and the memory device,
The control unit is connected to a processor module capable of executing a program through a first memory bus, and connected to the memory device through a second memory bus,
The controller is
Based on the information about the compressed data notified before the compressed data is transferred, a storage area for storing the decompressed data obtained by decompressing the compressed data is secured in the memory device,
Causing the decompression unit to generate decompressed data from the compressed data DMA-transferred through the first memory bus;
A memory module for storing the decompressed data in a storage area secured in the memory device through the second memory bus.
The compressed data is compressed so that the decompressed data after decompression has a predetermined size or less,
The controller is
Storing the compressed data in a compressed state in a storage area secured in the memory device,
The compressed data stored in the storage area is acquired through the second memory bus, the decompression unit generates decompressed data,
The memory module according to claim 11, wherein the generated decompressed data is stored in the storage area secured in the memory device through the second memory bus in a right-justified manner.
The first memory bus and the second memory bus comply with DDR,
The controller is
When an internal command is received from the decompression unit, if an external command received through the first memory bus is waiting to be sent to the second memory bus, the internal command is sent to the second memory bus. The memory module according to claim 11, wherein it is determined whether or not it is necessary to delay after the external command is transmitted.