TWI813341B - Flip chip bonding method - Google Patents

Abstract

A flip-chip bonding method including the following steps is provided: providing a chip including a plurality of connection ends with a first distance therebetween at a first temperature; providing a substrate including a plurality of connection pads with a second distance therebetween at the first temperature; and heating the substrate to a second temperature, so that the plurality of connection ends of the chip being correspondingly connected to the plurality of connection pads of the substrate, wherein the second temperature is higher at the first temperature, and the first distance is greater than the second distance.

Description

Flip chip bonding method

The present invention relates to a wafer bonding method, and in particular to a flip-chip bonding method.

Flip chip bonding is a bonding technology in chip packaging. Different from traditional wire bonding, flip-chip bonding places the connection end of the chip facing the substrate and directly connects it to the connection pads on the substrate.

However, during flip-chip bonding, misbonding may occur due to the heating steps required in the process. Therefore, how to improve the bonding quality of flip-chip bonding has become an urgent issue to be solved.

The present invention provides a flip-chip bonding method, which can improve the bonding quality between a chip and a substrate.

The flip-chip bonding method of the present invention includes the following steps: providing at least one chip, wherein the chip includes a plurality of connection terminals, and there is a first distance between the plurality of connection terminals at a first temperature; providing at least one substrate, wherein the substrate includes a plurality of connection pads, and There is a second distance between the plurality of connection terminals at the first temperature; and the substrate is heated to a second temperature so that the plurality of connection terminals of the chip are correspondingly joined to the plurality of connection pads of the substrate, wherein the second temperature is higher than the first temperature. a temperature, and the first distance is greater than the second distance.

In one embodiment of the present invention, in the step of heating the substrate to the second temperature, the entire substrate is heated to the second temperature.

In an embodiment of the present invention, each connection end of the chip includes: a metal pillar and solder located on the metal pillar.

In an embodiment of the invention, the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the wafer.

In an embodiment of the present invention, the difference between the first distance and the second distance is between 10 microns and 20 microns.

In an embodiment of the present invention, the number of connection terminals of each chip is greater than two, and the first distance is the two connection terminals with the largest distance in each chip; and the number of connection pads of each substrate is greater than two, and The second distance is the two connection pads with the largest distance between each substrate.

In an embodiment of the present invention, the flip-chip bonding method further includes the following steps: providing a simulated substrate including a plurality of measurement points; measuring the distance between the plurality of measurement points at the first temperature and the second temperature. , to obtain the measurement results; and design the second distance based on the first distance and the measurement results.

In an embodiment of the present invention, in the step of providing at least one chip, a plurality of wafers are provided; in the step of providing at least one substrate, a plurality of wafers are provided; and in the step of providing a plurality of substrates, the plurality of substrates To be placed within the base frame.

In an embodiment of the present invention, the chip and the substrate are arranged in a one-to-one manner.

Based on the above, the flip-chip bonding method of the present invention can achieve better bonding quality between the chip and the substrate.

100:wafer

110:Metal pillar

120:Solder

130:Connection end

200:Substrate

210:Connection pad

220:Component

300:Substrate frame

400:Analog substrate

410:Measurement point

L1: first distance

L2: second distance

L3: The third distance

L4: distance

S11, S12, S21, S30, S40: steps

1A to 1D are schematic side views of a flip-chip bonding method according to an embodiment of the present invention.

FIG. 2 is a schematic top view of a flip-chip bonding method according to an embodiment of the present invention.

FIG. 3 is a partial flow diagram of a flip-chip bonding method according to an embodiment of the present invention.

FIG. 4 is a schematic side view of a flip-chip bonding method according to an embodiment of the present invention.

The present invention will be described more fully below with reference to the drawings of this embodiment. However, the present invention may also be embodied in various forms and should not be limited to the embodiments described herein. The dimensions of layers, regions or elements in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar components, and will not be repeated one by one in the following paragraphs. In addition, the directional terms mentioned in the embodiments, such as up or down, are only for reference to the directions in the attached drawings. Therefore, the directional term used is to use are used to illustrate but not to limit the invention.

Referring to FIG. 1A , a wafer 100 is provided. The chip 100 includes a plurality of connection terminals 130, and there is a first distance L1 between the plurality of connection terminals 130 at a first temperature.

In one embodiment, the number of connection terminals 130 can be adjusted according to design requirements. As shown in FIG. 1A , if the number of connection terminals 130 of a single wafer 100 is more than two, and the first distance L1 refers to the maximum spacing of the wafer 100 in the direction of its maximum size (such as the length direction), Two connecting terminals 130.

In one embodiment, the structure of the connection terminal 130 may include a metal pillar 110 and a solder 120 . Solder 120 is located on metal post 110 (lower in Figure 1A). The metal pillar 110 may provide better cushioning during thermal expansion and contraction.

In one embodiment, the melting point of the metal pillar 110 is greater than the melting point of the solder 120 . For example, the material of the metal pillar 110 is copper, and the material of the solder 120 is, for example, a tin alloy.

Referring to FIG. 1B , a substrate 200 is provided. The substrate 200 includes a plurality of connection pads 210, and there is a second distance L2 between the plurality of connection terminals 130 at the first temperature. The connection pad 210 is located on a surface of the substrate 200 .

In one embodiment, the number or arrangement of the connection pads 210 may be adjusted corresponding to the wafer 100 to which the connection pads 210 will be subsequently bonded. As shown in FIG. 1B , if the number of connection pads 210 of a single substrate 200 is more than two, and the second distance L2 refers to the maximum size direction of the corresponding wafer 100 (such as the length direction of the wafer 100 ), The two connection pads 210 have the largest spacing.

Please refer to FIG. 2 and FIG. 1B. In one embodiment, multiple substrates 200 can placed within the substrate frame 300. Moreover, in subsequent processes, each substrate 200 in the substrate frame 300 may be bonded to a corresponding wafer 100 .

In one embodiment, the substrate 200 may include a hard board (such as a glass board, a fiberglass board (such as an FR4 board); but not limited to). In one embodiment, the substrate 200 may be a rigid printed circuit board.

In one embodiment, the entire coefficient of thermal expansion (CTE) of the substrate 200 is greater than the entire coefficient of thermal expansion of the wafer 100 to be subsequently bonded thereon.

It is worth noting that, on a surface of the substrate 200, there may be other components 220 having the same or similar structure and/or material as the connection pad 210. However, the "connection pads 210" referred to herein are those to which the chip 100 is subsequently bonded. However, the present invention does not limit whether the aforementioned other components 220 can be combined with other components not shown. That is to say, although the aforementioned other components 220 are not bonded to the chip 100, they can still be combined with other components not shown. In addition, for clarity of illustration, not all connection pads 210 or other components 220 are labeled one by one in the drawings.

In this embodiment, the first distance L1 is greater than the second distance L2. In an embodiment, the second distance L2 may be designed in detail as described below.

Referring to FIG. 1B and FIG. 1C , the substrate 200 is heated to a second temperature, and there is a third distance L3 between the plurality of connection terminals 130 at the second temperature. The third distance L3 may be defined in the same or similar manner to the aforementioned second distance L2.

In this embodiment, due to thermal expansion, the third distance L3 is greater than the second distance L2. In one embodiment, the difference between the first distance L1 and the second distance L2 The value is greater than or equal to 10 micrometer (micrometer, μm), for example: between 10 micrometer (micrometer, μm) and 20 micrometer.

Please refer to FIG. 1A , FIG. 1C and FIG. 1D . After the substrate 200 is heated to the second temperature, the plurality of connection terminals 130 of the chip 100 are correspondingly connected to the plurality of connection pads 210 of the substrate 200 . In one embodiment, the connection end 130 of the chip 100 and the connection pad 210 of the substrate 200 may be connected in a one-to-one manner.

In one embodiment, in the step of heating the substrate 200 to the second temperature so that the connection end 130 of the chip 100 is correspondingly connected to the connection pad 210 of the substrate 200, the entire substrate 200 is heated to the second temperature.

In one embodiment, in order to reduce thermal damage to the chip 100, in the step of correspondingly bonding the connection end 130 of the chip 100 to the connection pad 210 of the substrate 200, the entire chip 100 is basically not heated to the second temperature.

In one embodiment, the solder 120 of the connection end 130 can be at least partially melted or softened in the second temperature environment; then, the molten or softened solder 120 is brought into contact with the corresponding connection pad 210; and then, by cooling Steps to solidify the solder 120 so that the chip 100 is fixed and bonded to the substrate 200 .

In one embodiment, in the direction defining the second distance L2 and/or the third distance L3, the size of the substrate 200 is greater than or equal to 10 millimeters (mm). Therefore, if the influence of thermal expansion is taken into consideration during the process of combining the chip 100 and the substrate 200, the bonding quality of the chip 100 and the substrate 200 can be improved.

In addition, in order to improve the bonding quality between the chip 100 and the substrate 200 through the aforementioned method, the second distance L2 of the substrate 200 can be designed as follows.

Referring to FIGS. 3 and 4 , an analog substrate 400 can be provided. The material of the simulation substrate 400 may be the same as or similar to the substrate 200 . A surface of the analog substrate 400 may include a plurality of measurement points 410 . The number and/or location of the measurement points 410 can be adjusted according to measurement requirements. For example, the corresponding measurement points 410 can be designed with reference to the number and/or location of the connection terminals 130 of the chip 100 .

The distance L4 between the two measurement points 410 is measured at the first temperature and the second temperature respectively to obtain corresponding measurement results. For example, since the material of the simulation substrate 400 can be the same or similar to the substrate 200 , the thermal expansion coefficient of the substrate 200 can be obtained by measuring changes in the distance between the points 410 at different temperatures. Furthermore, the design of the second distance L2 of the substrate 200 can be adjusted based on the aforementioned thermal expansion coefficient, so that the third distance L3 of the substrate 200 at the second temperature is the same as or similar to the first distance L1 of the wafer 100 . For example, the second distance L2 may be the expansion ratio of the first distance L1 divided by the distance L4 between the two measurement points 410 at the second temperature and the first temperature.

Based on the above, as shown in FIG. 3 , in one embodiment, the flip-chip bonding method may include the following steps.

Step S11: Provide a simulation substrate including a plurality of measurement points.

Step S12: Measure distances between multiple measurement points at the first temperature and the second temperature to obtain measurement results.

Step S21: Provide a chip including a plurality of connection terminals and a first distance between the plurality of connection terminals at a first temperature.

Step S30: Design the substrate based on the first distance and measurement results, where the substrate It includes a plurality of connection pads and has a second distance between the plurality of connection terminals at a first temperature, wherein the first distance is greater than the second distance.

Step S40: heating the substrate to a second temperature, so that the plurality of connection terminals of the wafer are correspondingly bonded to the plurality of connection pads of the substrate, wherein the second temperature is higher than the first temperature.

To sum up, the flip-chip bonding method of the present invention can achieve better bonding quality between the chip and the substrate.

S11, S12, S21, S30, S40: steps

Claims (6)

A flip-chip bonding method includes: providing a simulation substrate including a plurality of measurement points; measuring the distance between the plurality of measurement points at a first temperature and a second temperature to obtain a measurement result; providing At least two wafers, wherein each of the wafers includes a plurality of connection terminals, and the two connection terminals with the largest distance between each of the wafers at the first temperature are a first distance; providing at least two A substrate, wherein each of the substrates includes a plurality of connection pads, and a second distance is between the two connection pads with the largest distance in each of the substrates at the first temperature; The substrate is placed in a substrate frame; and after placing a plurality of the substrates in the substrate frame, heating the plurality of substrates to a second temperature so that the plurality of wafers in each of the plurality of wafers are Each of the connection terminals is bonded to a plurality of the connection pads of a corresponding one of the plurality of substrates, wherein: the second temperature is higher than the first temperature, and the first distance is greater than the first distance. Two distances, and the second distance is designed based on the first distance and the measurement result. The flip-chip bonding method according to claim 1, wherein in the step of heating the plurality of substrates to the second temperature, the entire plurality of substrates is heated to the second temperature. The flip-chip bonding method according to claim 1, wherein each of the connection ends of each of the wafers includes: a metal pillar and solder located on the metal pillar. The flip-chip bonding method according to claim 1, wherein the thermal expansion coefficient of each of the substrates is greater than the thermal expansion coefficient of each of the wafers. The flip-chip bonding method according to claim 1, wherein the difference between the first distance and the second distance is between 10 microns and 20 microns. The flip-chip bonding method according to claim 1, wherein the wafer and the substrate are arranged in a one-to-one manner.

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