TWI812576B - Flash memory apparatus, flash memory controller, and storage management method for flash memory - Google Patents

Abstract

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Description

Flash memory device, flash memory controller and flash memory storage management method

The present invention relates to a flash memory device, and more particularly to a flash memory device and a storage management method that perform error correction coding operations similar to a fault-tolerant disk array.

Generally speaking, for a flash memory controller to perform data writing to write a piece of data to a single-level unit data block or a multi-level unit data block, the traditional mechanism is adopted, for example, in a data block The last page of the word line is placed with the check codes corresponding to other data pages of the word line, so that the corresponding check codes can be used when writing fails, word lines are broken, or word lines are short-circuited. Error correction to a certain extent, however, such data storage rate is too low. For example, if a character line includes 8 data pages, only 7 data pages are used to store data, and another data page is used to store corrections. Verification code, in this case, 1/8 of a data block will be used to store verification codes instead of storing data, which is unacceptable from the user's point of view.

Therefore, one of the objects of the present invention is to provide a flash memory device and a corresponding flash memory storage management method, which uses an error correction coding operation similar to a fault-tolerant disk array to reduce the error incidence rate and reduce the cost of traditional mechanisms. The number of check codes that need to be used, and the required check codes are appropriately stored in the corresponding data page locations, so that the required check codes can still be used when writing fails, word lines are broken, and word lines are short-circuited. The code is used to perform error corrections to a certain extent and solve the above problems.

According to an embodiment of the present invention, a flash memory device is disclosed. The flash memory device includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of single-layer unit data blocks and at least one multi-layer unit data block. The flash memory The controller has a plurality of channels connected to the flash memory module respectively. The flash memory controller classifies a data to be written into multiple groups of data. The flash memory controller performs single-layer unit data writing respectively. Enter and perform an error correction coding operation similar to a fault-tolerant disk array to generate a corresponding check code, so as to write the data of the complex group and the corresponding check code to a plurality of single-layer unit data blocks; when the complex data block is completed When writing a single-layer unit data block, the flash memory module performs internal copying, and copies the plurality of groups of data and corresponding check codes stored in the plurality of single-layer unit data blocks according to the order of the data. Sequentially move and write to at least one multi-layer unit data block.

According to an embodiment of the present invention, a flash memory storage management method is also disclosed. The method includes: providing a flash memory module, the flash memory module including a plurality of single-layer unit data blocks and at least one multi-layer unit data block; classifying a piece of data to be written into a plurality of The data of the group; perform single-layer unit data writing and perform an error correction encoding operation similar to a fault-tolerant disk array to generate a corresponding check code, so as to write the data of the plurality of groups and the corresponding check code to the plurality of single-level unit data blocks; when the writing of the plurality of single-level unit data blocks is completed, an internal copy is performed to copy the data of the plurality of groups stored in the plurality of single-level unit data blocks and The corresponding check code is sequentially moved and written to the at least one multi-layer unit data block according to the order of data.

Please refer to FIG. 1 , which is a schematic diagram of a flash memory device 100 according to an embodiment of the present invention. The flash memory device 100 includes a flash memory module 105 and a flash memory controller 110. The flash memory module 105 is a flash memory module with a two-dimensional planar structure; however, this is not the case in this case. limit. The flash memory module 105 includes a plurality of flash memory chips (not shown in Figure 1). Each flash memory chip includes a plurality of single-level cell (SLC) data blocks. block) and multiple-level-cell data blocks (multiple-level-cell blocks). Each unit of a single-level cell data block can store 2 bits of data, and each unit of a multi-level cell data block can store 2 ^N Bit data, N is greater than or equal to 2 and is an integer. Multi-level cell data blocks, such as cells including MLC blocks (multi-level cell blocks), can store 2 ^2- bit data, TLC blocks (triple-level The unit of the QLC block (quad-level cell block) can store ²³ bits of data, the unit of the QLC block (quad-level cell block) can store ²⁴ bits of data, and so on.

The flash memory controller 110 can be connected to the flash memory module 105 through a plurality of channels, so that different channels can be used to write data to different flash memory chips at the same time, thereby increasing writing efficiency. The controller 110 includes an error correction code encoding circuit 1101 and a parity check code buffer 1102. The error correction code encoding circuit 1101 is used to encode data with an error correction code, such as in the embodiment of this case. Including encoding operations of Reed-Solomon codes and/or encoding operations of exclusive-OR (XOR) operations to generate corresponding check codes, and the check code buffer 1102 is used to The corresponding check code generated is temporarily stored, and the flash memory controller 110 uses a data management mechanism similar to a fault-tolerant disk array (Redundant Array of Independent Disks, RAID) to write a piece of data to different The flash memory chip reduces the error rate, and when writing data to the single-layer unit data block, it simultaneously considers the check codes of different encoding operations at the storage location of the single-layer unit data block and in the TLC data area. The storage location of the block allows correcting data errors when writing data to the single-layer unit data block and subsequent flash memory module 105 copying and moving data from the single-layer unit block to Data errors can also be corrected when TLC data blocks.

In practice, in order to improve the efficiency of data writing and reduce the error rate, the flash memory module 105 includes multiple channels (the embodiment of this case is 2 channels, but it is not limited). When one channel executes a certain data page When writing a page, another channel can be used to write another data page without waiting for the channel. Each channel has its own sequencer in the flash memory controller 110. ) and both include multiple flash memory chips (the embodiment of this case is two chips, but it is not limited), so that one channel can write different data pages to multiple flash memory chips at the same time without You need to wait for one of the chips. In addition, each flash memory chip can have a folded design with two different planes, so that one flash memory chip can use different planes at the same time when writing data. Two data blocks on two planes are used to write different data pages without waiting for one of the data blocks. Therefore, a super block of the flash memory module 105 is composed of multiple data pages of multiple flash memory chips in multiple channels. The above-mentioned flash memory controller 110 writes data in units of super data blocks. The data is first written into the single-layer unit data block in the flash memory module 105. The unit data blocks are buffered, and then the data is copied and moved from these single-layer unit data blocks to the TLC data blocks. In addition, it should be noted that in other embodiments, each flash memory chip may not have a folding design, that is, a flash memory chip uses a data block to execute a data page when writing data. Writing, writing of other data pages requires waiting time.

As for the data writing process, a piece of data will first be written by the flash memory controller 110 to a plurality of single-layer unit data blocks 1051A~1051C, and then moved from the single-layer unit data blocks 1051A~1051C. As for the multi-layer unit data block 1052, for example, in this embodiment, a multi-layer data block based on the TLC unit is used as an example. The TLC unit can store ²³ bits of information, that is, three single-layer unit data Data in blocks (hereinafter referred to as SLC data blocks) 1051A~1051C will be written to a TLC data block 1052. Accordingly, it is considered that the SLC data blocks 1051A~1051C need to be written together with the TLC data area. The writing of block 1052 is protected from error correction. The flash memory controller 110 classifies a piece of data into three groups of data. It should be noted that if it is a multi-layer data block based on an MLC unit, For example, since the MLC unit can store ²² bits of information, the flash memory controller 110 will classify the data into two groups of data. If the multi-layer data block is structured based on the QLC unit, For example, since the QLC unit can store ²⁴ bits of information, the flash memory controller 110 will classify the data into four groups of data; and so on. That is to say, when the unit of the above-mentioned multi-level unit data block 1052 can store information with 2 ^N bits, and N is greater than or equal to 2 and is an integer, the number of single-level unit data blocks will be designed as N SLC data blocks. The flash memory controller 110 classifies the data to be written into N groups of data, so as to write them into N SLC data blocks respectively.

In this embodiment, after the flash memory controller 110 classifies the data into three groups of data, it will then execute the first data writing (SLC program) to write the data of the first group into the above-mentioned data groups. The first SLC data block 1051A and the error correction code encoding circuit 1101 generate the corresponding check code and write it into the first SLC data block 1051A. In this way, the writing operation of the SLC data block is completed. The flash memory controller 110 then executes a second data writing (SLC program) to write the second group of data into the second SLC data block 1051B and uses the error correction code encoding circuit 1101 to generate a corresponding check The code is written into the second SLC data block 1051B, thereby completing the second SLC data block writing operation, and the flash memory controller 110 then performs the third data writing (SLC program) writes the data of the third group into the above-mentioned third SLC data block 1051C and uses the error correction code encoding circuit 1101 to generate the corresponding check code and writes it into the third SLC data block 1051C, thus completing The third write operation of the SLC data block.

When the flash memory controller 110 executes a certain data writing (SLC program) to write a certain group of data into a certain SLC data block, or after the data writing, the flash memory controller 110 will Detect whether there is an error. If there is an error in the data, for example, a program fail occurs when writing a certain SLC data block, a one word line open and/or a two word line short circuit occurs. line short), the flash memory controller 110 will use the corresponding check code generated by the error correction code encoding circuit 1101 during the data writing to correct the above error.

When the data of the above three groups are all written to the three SLC data blocks 1051A~1051C or when the data writing of a certain SLC data block is completed, the flash memory module 105 performs internal copying from the Copy and move the data of three groups or the data of a certain group in some SLC data blocks 1051A~1051C or a certain SLC data block and execute the data writing (TLC program) according to the data sequence of the three groups to a TLC data area. Block 1052 (also the aforementioned super data block), the TLC data block 1052 is composed of data pages of word lines of different flash memory chips of different channels, for example, one character of the TLC data block 1052 A data page of the line includes an upper data page (upper page), a middle data page (middle page) and a lower data page (lower page). The internal copying system of the flash memory module 105 is, for example, an SLC data area. Multiple data pages on the Nth word line of the block are written to multiple upper data pages on one of the word lines of the TLC data block 1052, and multiple data pages on the N+1th word line of the SLC data block are written to Write a data page to multiple intermediate data pages on the same word line of the TLC data block 1052, and write multiple data pages on the N+2th word line of the SLC data block to the TLC data area Block 1052 multiple lower data pages of the same character line. After the data of all three groups are written to the TLC data block 1052, the writing operation of the super data block is completed.

It should be noted that in order to make the internal copy easy to implement, comply with the randomizer seed rule requirements of TLC data block 1052, and at the same time consider the error correction coding capability to reduce the error rate, the internal copy operation is only based on the data. The data is moved to the upper, middle and lower data page positions of the plurality of word lines of the TLC data block 1052 in sequence, and the flash memory controller 110 writes the data of different groups and the corresponding generated checksums. When encoding to these SLC data blocks 1051A~1051C, at the same time according to the random seed number rule requirements of the TLC data block and considering the writing storage location of the check code of the error correction code, the error of the error correction code encoding circuit 1101 The correction coding capability can correct errors caused by a write failure of the SLC data block, a one-word line break, and/or a two-word line short circuit when executing a write operation of the SLC data block, and can correct the error caused by a write operation of the SLC data block. During the writing operation of the data block, errors caused by writing failure of the TLC data block 1052, open circuit of one word line and/or short circuit of two word lines are corrected.

In addition, if the flash memory module 105 performs memory garbage collection, the flash memory controller 110 reads data from the SLC data blocks 1051A~1051C through external reading and re-reads the data. Perform error correction encoding to perform data writing (SLC program), and/or read data from the TLC data block 1052 and re-encode error correction to perform data writing (SLC program). In addition, if data (SLC program) is written to an SLC data block and a sudden shutdown occurs, the flash memory controller 110 reads back the data from the SLC data block and re-encodes the error correction and writes the data. (SLC program) to another new SLC data block. In addition, if data (TLC program) is written to the TLC data block 1052 and a sudden shutdown occurs, the flash memory module 105 abandons the data currently stored in the TLC data block 1052 and retrieves the SLC data from the TLC data block 1052 . In blocks 1051A~1051C, the corresponding data is re-written (TLC program) to the TLC data block 1052 through internal copying.

Please refer to Figure 2. Figure 2 illustrates the first embodiment of the present invention. The flash memory controller 110 shown in Figure 1 executes SLC data writing (SLC program) to write data of a certain group into the flash memory. A schematic diagram of an SLC data block in the module 105 to perform an SLC data block write operation. The error correction code encoding circuit 1101 of the flash memory controller 110 performs a Reed Solomon (RS) encoding operation similar to a fault-tolerant disk array on the data to generate a corresponding check code. The check code buffer 1102 is used to temporarily store the generated corresponding check code.

The flash memory module 105 includes two channels and includes two flash memory chips and two sets of blocks of each chip with two different planes. In order to achieve writing efficiency, the flash memory controller 110 Data is written to two blocks of two flash memory chips in the flash memory module 105 through two channels. As shown in the embodiment of Figure 2, an SLC data block includes, for example, 128 word lines (represented by WL0 to WL127 respectively). The SLC data block may be composed of one SLC data block or a group of The composition of SLC sub-data blocks depends on the definition of the SLC data block. For convenience of description, in the embodiment, 128 character lines are regarded as the size of one SLC data block, in which each character line includes There are, for example, 8 data pages. Taking the first word line WL0 of the SLC data block as an example, the flash memory controller 110 writes data pages P1 and P2 to The flash memory chip CE0 then writes the data pages P3 and P4 to another flash memory chip CE1 through the same channel CH0 and the folding planes PLN0 and PLN1, and then writes the data pages P3 and P4 to the other flash memory chip CE1 through the other channel CH1 and the folding planes PLN0 and PLN1. Data pages P5 and P6 are written to the flash memory chip CE0, and then data pages P7 and P8 are written to the flash memory chip CE1 through the channel CH1 and the folding planes PLN0 and PLN1. Others follow suit.

The flash memory controller 110 sequentially sorts multiple word lines WL0 to WL127 of an SLC data block into a group of each M word lines, where M is a positive integer greater than or equal to 2, M such as is 3, for example, word lines WL0~WL2 are the first group, word lines WL3~WL5 are the second group, word lines WL6~WL8 are the third group, word lines WL9~WL11 are the fourth group..., word lines The element lines WL120~WL122 are the third to last group, the character lines WL123~WL125 are the second to last group, and the last group of character lines are WL126 and WL127, among which the first, third, fifth group...and so on The lines are odd-numbered groups of word lines, and the second, fourth, sixth, etc., group of word lines are even-numbered groups of word lines. The flash memory controller 110 writes data of one group of word lines at a time. (including the data of three character lines), the error correction code encoding circuit 1101 is used to perform error correction encoding on the data of the group of character lines, and the generated corresponding partial parity code (partial parity code) is output to Check code buffer 1102 to temporarily store part of the check code.

When temporarily storing part of the check code, the check code buffer 1102 stores the check code corresponding to the odd group of word line data in a first buffer 1102A, and stores the check code corresponding to the even group of word line data. Part of the check code is stored in a second buffer 1102B. For example, when writing the data pages P1 ~ P24 of the word lines WL0 ~ WL2, the error correction code encoding circuit 1101 executes an error for the data pages P1 ~ P24. Correct the code, and output the corresponding part of the generated check code to the check code buffer 1102, and temporarily store it in the first buffer area 1102A; then when writing the data pages P1~P24 of the word lines WL3~WL5, The error correction code encoding circuit 1101 performs error correction encoding on the data pages P1 to P24, and outputs the generated check code of the corresponding part to the check code buffer 1102, and temporarily stores it in the second buffer 1102B; then the error When data pages P25 ~ P48 of word lines WL6 ~ WL8 are written, the error correction code encoding circuit 1101 performs error correction coding on the data pages P25 ~ P48, and outputs the generated check code of the corresponding part to the check code The code buffer 1102 is temporarily stored in the first buffer 1102A; subsequent data page writing and encoding operations are deduced in the same way...; after that, when the data pages of the word lines WL120~WL122 are written, the error correction code encoding circuit 1101 Encoding is performed on the data pages of word lines WL120~WL122, and the generated check codes of the corresponding parts are output to the check code buffer 1102 and temporarily stored in the first buffer 1102A.

Then, when writing the last group of word lines (WL123~WL125) of the even group of word lines, the flash memory controller 110 not only executes the data writing (SLC program) and the corresponding error correction code, but also Read back the partial check codes of the data of all even-numbered word lines temporarily stored in the second buffer 1102B, and write all the check codes corresponding to the data of the even-numbered word lines into the last set of even-numbered words. The data page of the last character line WL125 of the character line, such as the last three data pages (marked 205), is used to store the Reed-Solomon check codes corresponding to the data of the even-numbered character lines.

In addition, when writing the last word line WL127 of the last group of odd-numbered word lines, the flash memory controller 110 will write the first word line WL127 in addition to executing the data writing (SLC program) and the corresponding error correction code. Read back the partial check codes of the data of all odd group word lines temporarily stored in the buffer 1102A, and write all the check codes corresponding to the data of the odd group of word lines to the last group of odd group word lines The data page of the last character line WL127, such as the last three data pages (marked 210), is used to store the Reed-Solomon check codes corresponding to the data of the odd-numbered character lines. In this way, the writing of the SLC data block is completed. Therefore, as far as the Reed-Solomon encoding operation is concerned, the check code corresponding to the data of the odd group of word lines is stored in the last plurality of data pages of the last word line WL127 of the last group of odd group of word lines. position, and the check code corresponding to the data of the even group of character lines is stored in the position of the last plurality of data pages of the last character line WL125 of the last group of even group of character lines.

In addition, the error correction code encoding circuit 1101 in the embodiment shown in Figure 2 performs a Reed-Solomon encoding operation, which can correct data page errors occurring in any three positions of the SLC data block, for example , the error correction code encoding circuit 1101 performs error correction encoding on the data of the three word lines WL0 ~ WL2 and generates the corresponding partial check code. If the three data pages of the same folding plane of the same chip of the same channel If an error occurs, for example, data pages P1, P9, and P17 have errors, the error correction code encoding circuit 1101 can use the generated corresponding partial check codes to correct the errors of the three data pages.

If a write failure (program fail) is detected when writing the SLC data block, for example, in terms of probability of occurrence, for example, a write failure of data page P9 is detected, the error correction code encoding circuit 1101 can Use the corresponding partial check code generated to correct the error on data page P9.

If a word line open is detected during the writing of the SLC data block, resulting in an error such as data page P9, the error correction code encoding circuit 1101 can use the corresponding part generated Check code to correct the error on data page P9.

If a two word line short is detected during the writing of the SLC data block, resulting in errors in data pages P9 and P17, for example, the error correction code encoding circuit 1101 can utilize the generated phase information. The corresponding part of the check code corrects the errors on data pages P9 and P17. If a short circuit occurs between two word lines, resulting in, for example, an error in the data page P17 of the word line WL2 and the data page P1 of the word line WL3, the error correction code encoding circuit 1101 can use a partial check code of a group of word lines WL0~WL2 and another set of partial check codes for word lines WL3~WL5 to correct errors in data page P17 of word line WL2 and data page P1 of word line WL3 respectively. If a short circuit occurs between two word lines, resulting in errors in the data pages P1 and P2 of the word line WL0, for example, the error correction code encoding circuit 1101 can use the partial check codes of a group of word lines WL0~WL2 to separate the word lines WL0 respectively. Corrected errors on data pages P1 and P2.

Therefore, whether it is a write failure when writing the SLC data block, a data page fault caused by an open circuit of one word line or a short circuit of two word lines, the error correction code encoding circuit 1101 can correct these errors accordingly. information page.

Please refer to Figure 3. Figure 3 is a schematic diagram of an SLC data block in the flash memory module 105 writing data to the TLC data block 1052 through internal copying. As shown in Figure 3, a set of three word line data of an SLC data block is written to a word line of the TLC data block 1052, correspondingly forming the least significant bit of a data page of the word line. The data of LSB, middle significant bit CSB and most significant bit MSB, for example, the word line data WL0~WL2 of the SLC data block are written to the TLC data block 1052 as the lowest value of the word line WL0 of the TLC data block 1052. The data of the significant bit LSB, the middle significant bit CSB and the most significant bit MSB; the word line data WL3~WL5 of the SLC data block are written to the TLC data block 1052 as the word line WL1 of the TLC data block 1052 The data of the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB; the word line data WL6~WL8 of the SLC data block are written to the TLC data block 1052 as the word line WL2 of the TLC data block 1052 The data of the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB; that is to say, the internal copy of the flash memory module 105 moves and writes the data of the SLC data block in the order of word lines. Fill in the character lines of the TLC data block.

Please refer to Figure 4. Figure 4 shows the flash memory controller 110 shown in Figure 1 writing three groups of data to multiple SLCs in the flash memory module 105 according to the first embodiment of the present invention. Data blocks 1051A~1051C are moved and written to the TLC data block through internal copying to form a schematic diagram of a super data block. Because the error correction code encoding circuit 1101 classifies the data into two groups of odd-numbered word lines and even-numbered word lines each time the SLC data block is written, and stores the corresponding generated check code in the odd The last 3 data pages of the last word line of the array word line and the last 3 data pages of the last word line of the even group word line. Therefore, when writing the TLC data block, as in As shown in Figure 4, the check codes corresponding to the odd-numbered word lines of the first group of data are stored in the last three data pages (marked 401A) of the middle significant bit CSB of the word line WL42 of the super block. ), and the corresponding check codes of the even-numbered word lines of the first group of data are stored in the last three data pages (marked 401B) of the most significant bit MSB of the word line WL41 of the super block; The check codes corresponding to the odd-numbered word lines of the second group of data are stored in the last three data pages (marked 402A) of the least significant bit LSB of the word line WL85 of the super block, and the second The check codes corresponding to the even-numbered word lines of the data of each group are stored in the last three data pages (marked as 402B) of the most significant bit MSB of the word line WL84 of the super block; the third group The check codes corresponding to the odd-numbered word lines of the data are stored in the last three data pages (marked 403A) of the most significant bit MSB of the word line WL127 of the super block, and the data of the third group The corresponding check codes of the even group of word lines are stored in the last three data pages (labeled 403B) of the least significant bits LSB of the word line WL127 of the super block.

If a short circuit between two word lines is detected, resulting in an error in the two data pages of the word lines WL0 and WL1 of the super block (as marked by the frame line 404), the flash memory module 105 can use the word line WL42. The check code 401A stored on the last three data pages of the middle significant bit CSB is used to correct the error of the data page of word line WL0, and the most significant bit MSB of word line WL41 is used to store the check code 401A on the last three data pages. Check code 401B is used to correct the error in the data page of word line WL1.

Similarly, if a short circuit of two word lines is detected, resulting in an error in the two data pages (marked by the frame line 405) of the word lines WL43 and WL44 of the super block, the flash memory module 105 can use the word The check code 402A stored in the least significant bit LSB of the last three data pages of element line WL85 is used to correct the errors of the least significant bit LSB, middle significant bit CSB and character of one data page of character line WL43 marked by 405. The error in the most significant bit MSB of the data page of line WL44 is used, and the check code 402B stored in the middle significant bit CSB of the last three data pages of word line WL84 is used to correct the word line WL43 marked by 405. Errors in the most significant bits MSB of the data page and errors in the least significant bits LSB and middle significant bits CSB of the word line WL44 data page.

Similarly, if a short circuit of two word lines is detected, causing an error in the two data pages (marked by the frame line 406) of the word lines WL125 and WL126 of the TLC data block, for example, the flash memory module 105 can Use the check code 403A stored on the most significant bits MSB of the last three data pages of word line WL127 to correct the errors in the middle significant bit CSB, most significant bit MSB and word of the data page of word line WL125 marked by 406 The error in the most significant bit MSB of the data page of word line WL126 is used, and the check code 403B stored in the least significant bit LSB of the last three data pages of word line WL127 is used to correct the word line WL125 marked by 406. Errors in the LSB of the data page and errors in the CSB and MSB of the word line WL126 marked by 406 in the data page.

If it is detected that a word line is broken or a writing failure causes an error in any data page of any word line in the super block (that is, any three consecutive sub-data pages have errors), the flash memory module 105 can use the corresponding stored check codes to correct errors in any three consecutive sub-data pages.

That is to say, when the flash memory controller 110 writes the data of three groups to the storage location management design of the check codes of the multiple SLC data blocks 1051A~1051C in the flash memory module 105, When the flash memory module 105 copies and writes the data from multiple SLC data blocks 1051A~1051C to the TLC data block through internal copying to form a super data block, if a word line break is detected, Errors such as a short circuit between two character lines or a writing failure can be corrected by the check codes stored in multiple SLC data blocks 1051A~1051C.

Furthermore, please refer to Figure 5. Figure 5 shows the flash memory controller 110 shown in Figure 1 executing a data writing (SLC program) to write data of a group to the flash memory according to the second embodiment of the present invention. A schematic diagram of the SLC data block in the memory module 105 completing an SLC data block writing operation. The error correction code encoding circuit 1101 of the flash memory controller 110 performs an encoding operation similar to a mutual exclusive OR operation of a fault-tolerant disk array on the data to generate a corresponding check code, and the check code buffer 1102 Used to temporarily store the corresponding check code generated. In addition, the mutual exclusive OR operation of the error correction code encoding circuit 1101 includes three different encoding engines to perform mutual exclusive OR operation on different word line data of the SLC data block; the detailed operation content is as follows.

The flash memory module 105 includes two channels and two flash memory chips. In order to achieve writing efficiency, the flash memory controller 110 writes data to the flash memory through the two channels. The two flash memory chips in the module 105 program the data pages of an SLC data block into different flash memory chips respectively. An SLC data block write operation by the flash memory controller 110 The data written includes 128 word lines (represented by WL0 to WL127 respectively), and each word line includes 8 data pages. For example, taking the word line WL0 as an example, the error correction code encoding circuit 1101 passes through the channel CH0 and PLN0 and PLN1 write data pages P1 and P2 to the flash memory chip CE0, and then write data pages P3 and P4 to another flash memory chip CE1 through the same channel CH0 and PLN0 and PLN1, and then Data pages P5 and P6 are written to the flash memory chip CE0 through another channel CH1 and PLN0 and PLN1, and then data pages P7 and P8 are written to the flash memory chip CE1 through channels CH1 and PLN0 and PLN1.

The error correction code encoding circuit 1101 sequentially sorts multiple word lines WL0 to WL127 of an SLC data block into a group. M is a positive integer greater than or equal to 2. For example, M is 3. For example, the character lines WL0~WL2 are the first group, the character lines WL3~WL5 are the second group, the character lines WL6~WL8 are the third group, the character lines WL9~WL11 are the fourth group..., character lines Lines WL120~WL122 are the third to last group, character lines WL123~WL125 are the second to last group, and the last group of character lines are WL126 and WL127, among which the first, third, fifth group...and so on are odd-numbered groups of word lines, and the second, fourth, sixth, etc., group of word lines are even-numbered groups of word lines. The flash memory controller 110 writes data of one group of word lines at a time ( Including the data of three character lines), the error correction code encoding circuit 1101 is used to perform an error correction encoding of a mutually exclusive OR operation on the data of the group of character lines, and the generated corresponding partial parity check code (partial parity code) is output to the check code buffer 1102 to temporarily store part of the check code.

Each time the error correction code encoding circuit 1101 writes data to a set of three different character lines, it uses three different encoding engines to perform mutually exclusive OR operations on the written data, and generates corresponding The partial check code is output to the check code buffer 1102 to temporarily store the partial check code, and the check code buffer 1102 stores the odd-numbered word line data corresponding to the partial check code. The partial check code is stored in a first buffer, and the partial check code corresponding to the even group of word line data is stored in a second buffer.

For example, the error correction code encoding circuit 1101 includes a first encoding engine, a second encoding engine and a third encoding engine. When writing the data pages P1~P24 of the word lines WL0~WL2, the first encoding engine is used in sequence. Perform a mutual exclusive OR operation on the data pages P1~P8 of the word line WL0 to generate a first partial check code, and use the second encoding engine to perform a mutual exclusive OR operation on the data pages P9~P16 of the word line WL1 to generate a first partial check code. The two-part check code and the third encoding engine are used to perform a mutual exclusive OR operation on the data pages P17~P24 of the word line WL2 to generate a third-part check code, and the generated partial check codes are output respectively. to the check code buffer 1102, and is temporarily stored in the first buffer; then the error correction code encoding circuit 1101 writes the data pages P1~P24 of the word lines WL3~WL5, and sequentially uses the first encoding engine to encode the data pages P1~P24 of the word lines WL3 The data pages P1~P8 of the word line WL4 perform a mutually exclusive OR operation to generate another first part of the check code, and the second encoding engine is used to perform a mutually exclusive OR operation on the data pages P9~P16 of the word line WL4 to generate another second part of the check code. Verify the code and use the third encoding engine to perform a mutually exclusive OR operation on the data pages P17~P24 of the word line WL5 to generate another third partial check code, and output the generated partial check codes to the check code respectively. The verification code buffer 1102 is temporarily stored in the second buffer area.

The subsequent data page writing and encoding operations are deduced in the same way...that is, for the data of the first character line, the data of the second character line, and the third character line of a group of odd-numbered character lines, The data of the character lines, as well as the data of the first character line, the second character line, and the third character line of a group of even-numbered character lines, all execute different times of mutual exclusion or operation to generate the corresponding check code. In order to write the corresponding check codes into the appropriate storage locations of the SLC data block, the error correction code encoding circuit 1101 writes the corresponding check codes to the data pages of the last six word lines WL122~WL127. The check code is written in the last data page of the last six character lines WL122~WL127 (as shown in the rectangular diagonal frame in Figure 5). For example, when writing the data page of character line WL122, the character The element line WL122 is the third character line of a group of odd-numbered character lines. The error correction code encoding circuit 1101 is written in the last data page of the character line WL122 to write all the third characters of all odd-numbered character lines. The check codes corresponding to the data of the word lines (that is, all the third part check codes generated by the third encoding engine in the odd-numbered word lines), when writing the data page of word line WL123 , the character line WL123 is the first character line of the last group of even-numbered character lines, and the error correction code encoding circuit 1101 is written in all the even-numbered character lines in the last data page of the character line WL123 All the check codes corresponding to the data of the first word line (that is, all the first part check codes generated by the first encoding engine in the even group of word lines), and the data written to word line WL124 page, the word line WL124 is the second word line of the last group of even group word lines, and the error correction code encoding circuit 1101 writes all the even group characters in the last data page of the word line WL124 The check codes corresponding to the data of all the second character lines in the line (that is, all the second part check codes generated by the second encoding engine in the even group of character lines), and when writing the character lines In the data page of WL125, the word line WL125 is the third word line of the last even group of word lines, and the error correction code encoding circuit 1101 writes all the even numbers in the last data page of the word line WL125. The check codes corresponding to the data of all the third character lines in the group of character lines (that is, all the third part check codes generated by the third encoding engine in the even group of character lines), and when writing When the data page of word line WL126 is written, word line WL126 is the first word line of the last odd-numbered group of word lines, and the error correction code encoding circuit 1101 is written in the last data page of word line WL126. Enter the check codes corresponding to the data of all the first character lines in all odd group character lines (that is, all the first part check codes generated by the first encoding engine in the odd group character lines), and in When writing the data page of word line WL127, word line WL127 is the second word line of the last odd group of word lines, and the error correction code encoding circuit 1101 is connected to the last data page of word line WL127 Write the check codes corresponding to the data of all the second character lines in all odd group character lines (that is, all the second part check codes generated by the second encoding engine in the odd group character lines) . In this way, the writing of the SLC data block is completed.

That is to say, when the flash memory controller 110 writes a group of data to an SLC data block, the flash memory controller 110 writes all the character lines of the SLC data block in sequence every M words. Classify a character line into a group of character lines to produce a plurality of odd groups of character lines and a plurality of even groups of character lines, and for each character line in an odd group and each character line in an even group A character line performs different encoding operations of mutually exclusive OR operations M times to generate M partial check codes for each character line of the odd number group and M partial check codes for each character line of the even number group. Partial check codes, write and store the M partial check codes of each character line of the odd array of the complex array in the last data page of the last M character lines of the odd array of complex array character lines. . Write and store the M partial check codes of each character line of the even group of complex numbers in the last data page of the last M character lines of the even group of character lines of the complex number group. In the above embodiment, M is 3, but this is not a limitation of this case.

The error correction code encoding circuit 1101 in the embodiment shown in Figure 5 performs a mutually exclusive OR encoding operation, which can correct a data page error that occurs at a position on a character line of the SLC data block. For example, If a writing failure is detected during the writing of the SLC data block, for example, a writing failure is detected on the data page P9 of the word line WL1, the error correction code encoding circuit 1101 can use the second encoding engine to The corresponding partial check code generated when processing the word line WL1 of the first group of word lines and other correct data pages P10~P16 of the same word line WL1, correct the data page P9 of the word line WL1 Mistake.

If an open circuit of a word line is detected during the writing of the SLC data block, resulting in, for example, an error in the data page P9 of the word line WL1, the error correction code encoding circuit 1101 can also use the second encoding engine to process the second encoding engine. Corresponding part of the check code generated by the word line WL1 of a group of word lines and other correct data pages P10~P16 of the same word line WL1, correct the error of the data page P9 of the word line WL1.

If a short circuit between two word lines is detected when writing the SLC data block, resulting in errors in data page P9 of word line WL1 and P17 of word line WL2, for example, the error correction code encoding circuit 1101 can be used The second encoding engine generates the corresponding partial check code when processing the word line WL1 of the first group of word lines and other correct data pages P10~P16 of the same word line WL1, and corrects the character line WL1 The error in data page P9, as well as the corresponding partial check code generated by the third encoding engine when processing the word line WL2 of the first group of word lines and other correct data pages P18~ of the same word line WL2 P24, correct the error in the data page P17 of word line WL2. If the data page P17 of the word line WL2 and the data page P1 of the word line WL3 are in error, the error correction code encoding circuit 1101 can use the third encoding engine to process the word line WL2 of the first group of word lines. Generate the corresponding partial check code and other correct data pages P18~P24 of the same word line WL2, correct the error of the data page P17 of the word line WL2, and use the first encoding engine to process the second group of characters Correct the error in the data page P1 of character line WL3 by using the corresponding partial check code generated when character line WL3 and other correct data pages P2~P8 of the same character line WL3. Therefore, whether it is a write failure when writing the SLC data block, a data page fault caused by an open circuit of one word line or a short circuit of two word lines, the error correction code encoding circuit 1101 can correct these errors accordingly. information page. The operation of the flash memory module 105 to write the data into the TLC data block through internal copying of the above-mentioned SLC data block is the same as the above-mentioned Figure 3, and will not be described again.

Next, please refer to Figure 6. Figure 6 shows the flash memory controller 110 shown in Figure 1 writing the data of three groups to multiple SLCs in the flash memory module 105 according to the second embodiment of the present invention. The data blocks 1051A~1051C move and write the data of the SLC data blocks 1051A~1051C to the TLC data block 1052 through internal copying to form a schematic diagram of a super block. Each time the error correction code encoding circuit 1101 performs writing of the SLC data block, it classifies the data into an odd number group of word lines and an even number group of word lines, and stores the corresponding generated check codes in all odd number group words. The last data pages of the last 3 character lines in the character line and the last data pages of the last 3 character lines of all even-numbered character lines, as shown in Figure 6, execute the TLC data block When writing, according to the order of data writing, the corresponding check code of the word line data in the first group, as indicated by 605A, is the last one written and stored in the word line WL40 of the TLC data block 1052. The most significant bits MSB of a data page, the last data page of word line WL41 and the least significant bits LSB and middle significant bits CSB of the last data page of word line WL42, among which the SLC data in the first group The check code of the odd group of word lines of the block is stored in the most significant bit MSB of the last data page of word line WL40 and the least significant bit LSB and middle significant bit CSB of the last data page of word line WL42 , and the check code of the even group of word lines of the SLC data block in the first group is stored in the last data page of word line WL41 (including the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB ).

The corresponding check code of the word line data in the second group, as indicated by 605B, is written and stored in the middle significant bit CSB and the most significant bit of the last data page of word line WL83 of TLC data block 1052. Significant bits MSB, LSB of the last data page of word line WL84, and LSB of the last data page of word line WL85, for odd-numbered word line data in the SLC data block in the second group , all the third part check codes generated by the third encoding engine are stored in the middle significant bit CSB of the last data page of the word line WL83 of the TLC data block 1052, and all the third part check codes generated by the first encoding engine The first part of the check code is stored in the most significant bit MSB of the last data page of word line WL84 of TLC data block 1052. All the second part of the check code generated by the second encoding engine is stored in the TLC data The least significant bit LSB of the last data page of word line WL85 of block 1052, and for the even group of word line data in the SLC data block of the second group, all the third data pages generated by the first encoding engine A part of the check code is stored in the most significant bit MSB of the last data page of word line WL83 of the TLC data block 1052. All the second part of the check code generated by the second encoding engine is stored in the TLC data area. The least significant bit LSB of the last data page of word line WL84 of block 1052. All third part check codes generated by the third encoding engine are stored in the last bit of word line WL84 of TLC data block 1052. The middle significant bit (CSB) of a data page.

The corresponding check code of the word line data of the third group, as indicated by 605C, is written and stored in the last data page (including the least significant bit LSB) of the word lines WL126 and 127 of the TLC data block 1052 , the middle significant bit (CSB) and the most significant bit (MSB)), where for the odd-numbered word line data in the SLC data block in the third group, all third part check codes generated by the third encoding engine are stored in The least significant bit LSB of the last data page of the word line WL126 of the TLC data block 1052, and all the first part check codes generated by the first encoding engine are stored in the word line WL127 of the TLC data block 1052. The middle significant bit (CSB) of the last data page and all the second part check codes generated by the second encoding engine are stored in the most significant bit (MSB) of the last data page on word line WL127 of TLC data block 1052. , and for the even group of word line data in the SLC data block in the third group, all the first part check codes generated by the first encoding engine are stored at the end of the word line WL126 of the TLC data block 1052 The middle significant bit (CSB) of a data page. All the second part check codes generated by the second encoding engine are stored in the most significant bit (MSB) of the last data page on word line WL126 of TLC data block 1052. All third part check codes generated by the third encoding engine are stored in the LSB of the last data page of word line WL127 of TLC data block 1052.

Therefore, when the flash memory module 105 moves the written data from the SLC data blocks 1051A to 1051C to the TLC data block 1052 through the internal copy operation, if a short circuit of two word lines is detected, resulting in, for example, a TLC data area An error occurs in the two data pages of word lines WL0 and WL1 in block 1052 (as marked by frame line 610). The flash memory module 105 can use the last data of word line WL42 stored in TLC data block 1052. The first part of the check code of the middle significant bit CSB of the page and the least significant bit LSB data of other data pages of word line WL0 are corrected by correcting the data of the least significant bit LSB of the data page of word line WL0 marked by 610, using The second part of the check code stored in the most significant bit MSB of the last data page of word line WL42 in TLC data block 1052 and the data of the middle significant bit CSB of other data pages of word line WL0 are used to correct 610 The data of the middle significant bit CSB of the data page of the marked word line WL0, and the third part of the check code using the most significant bit MSB of the last data page of word line WL40 stored in TLC data block 1052 and the most significant bit MSB data of other data pages of word line WL0 to correct the most significant bit MSB data of the data page of word line WL0 marked by 610. Similarly, the flash memory module 105 can utilize the first part of the check code of the least significant bit LSB of the last data page of the word line WL41 stored in the TLC data block 1052 and other data pages of the word line WL1 The data of the least significant bit LSB is used to correct the data of the least significant bit LSB of the data page of word line WL1 marked by 610, using the middle of the last data page of word line WL41 stored in TLC data block 1052 The second part of the check code of the valid bit CSB and the data of the middle significant bit CSB of other data pages of the word line WL1 are used to correct the data of the middle significant bit CSB of the data page of the word line WL1 marked by 610, and use The third part of the check code stored in the most significant bit MSB of the last data page of word line WL41 in TLC data block 1052 and the data of the most significant bit MSB of other data pages of word line WL1 are used to correct 610 The data of the most significant bit MSB of the data page of marked word line WL1.

Similarly, if the error caused by the short circuit of two word lines occurs in the consecutive data pages of any two consecutive word lines in the super block (for example, the error positions marked as 615 and 620), the flash memory module 105 can use the corresponding check code stored in the last data page of the last 6 character lines of an SLC data block in each group to correct the error. In addition, if it is detected that a word line is disconnected or a writing failure causes an error in any data page of any word line in the TLC data block 1052 (that is, all three valid bits of the same data page are incorrect or If two consecutive valid bits of two different data pages are wrong), the flash memory module 105 can use the corresponding stored check code to correct any three consecutive valid bit errors.

That is to say, the flash memory controller 110 writes the data of the three groups to the check code storage location management design of the multiple SLC data blocks 1051A ~ 1051C in the flash memory module 105. When the flash memory module 105 When the memory module 105 copies and moves the data from multiple SLC data blocks 1051A~1051C to the TLC data block through internal copying, if it detects that one character line is open, two character lines are short-circuited, or the writing Failure errors can be corrected by the check codes stored in multiple SLC data blocks 1051A~1051C.

Furthermore, the above-mentioned embodiments of this case are also applicable to structures such as MLC data blocks or QLC data blocks. When used in MLC data blocks, the above three groups of data are instead classified into two groups of data, and if If it is an encoding operation that performs a mutually exclusive OR operation, it will be implemented using two encoding engines. The other conditions are the same as when used in the TLC data block; therefore, if it is used in the QLC data block, the above three The group data is changed to data classified into four groups, and if the encoding operation is to perform a mutually exclusive OR operation, four encoding engines are used to implement it. Other conditions are the same as those used in the TLC data block; The structure of other data blocks can be deduced in the same way.

From the perspective of data storage cost (overhead), if two channels are used to write to two memory chips, and each memory chip has a folding plane design so that two blocks can be written at the same time, then one SLC data In terms of data writing in the block, there are 8*128 data pages for 128 character lines, and only 6 data pages need to be used to store the corresponding check codes, and the cost percentage is less than 1% (6/( 128*8)), that is, for writing of SLC data blocks and writing of TLC data blocks, only less than 1% of the data space is used to store the corresponding error correction check codes. The data space The usage efficiency is extremely high. And if 4 channels are used to write 4 memory chips, and each memory chip has a folding plane design so that 2 blocks can be written at the same time, then in terms of data writing in one SLC data block, 128 There are a total of 4*4*2*128 data pages for each character line, and only 6 data pages need to be used to store the corresponding check codes. The cost percentage will be lower, about 0.15% (6/(128 *4*4*2)), that is, for writing of SLC data blocks and writing of TLC data blocks, only about 0.15% of the data space is used to store the corresponding error correction check codes. , the data space is used more efficiently. The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

100:Flash memory device 105:Flash memory module 110:Flash memory controller 205,210,401A,401B,402A,402B,403A,403B,605A,605B,605C: Check code storage location 404,405,406,610,615,620: Data page of TLC data block 1051A, 1051B, 1051C: SLC data block 1052:TLC data block 1101: Error correction code encoding circuit 1102: Check code buffer 1102A, 1102B: Buffer

Figure 1 is a schematic diagram of a flash memory device according to an embodiment of the present invention. Figure 2 shows the first embodiment of the present invention. The flash memory controller shown in Figure 1 performs SLC data writing and writes data of a certain group to an SLC data block in the flash memory module for execution. Schematic diagram of an SLC data block write operation. Figure 3 is a schematic diagram of an SLC data block in a flash memory module writing data to a TLC data block through internal copying. Figure 4 shows the first embodiment of the present invention. The flash memory controller shown in Figure 1 writes the data of three groups to multiple SLC data blocks in the flash memory module and copies the data internally. Schematic diagram of moving and writing to TLC data block to form a super block. Figure 5 shows the second embodiment of the present invention. The flash memory controller shown in Figure 1 performs SLC data writing to write data of a group to the SLC data block in the flash memory module to complete once Schematic diagram of SLC data block write operation. Figure 6 shows the second embodiment of the present invention. The flash memory controller shown in Figure 1 writes the data of the three groups to multiple SLC data blocks in the flash memory module and copies the data through internal copying. A schematic diagram illustrating the data movement of some SLC data blocks and writing them into the TLC data blocks to form a super block.

100:Flash memory device 105:Flash memory module 110:Flash memory controller 1051A, 1051B, 1051C: SLC data block 1052:TLC data block 1101: Error correction code encoding circuit 1102: Check code buffer 1102A, 1102B: Buffer

Claims (13)

A flash memory device including: A flash memory module including N first data blocks and at least one second data block; and A flash memory controller has a plurality of channels respectively connected to the flash memory module. The flash memory controller is used to write a piece of data to the flash memory module. The flash memory module The memory controller respectively executes the single-layer unit data writing (SLC program) and performs an error correction coding operation applied to the data management mechanism of the fault-tolerant disk array to generate a check code corresponding to the data, and The data of the N groups in the data and the N check codes corresponding to the data of the N groups in the corresponding check codes are respectively written to the N first data blocks, so that the flash The memory module copies and moves the data of the N groups and the N check codes stored in the N first data blocks to the at least one second data block; wherein the one-digit number of the information stored in a unit in the N first data blocks is different from the one-digit number of the information stored in a unit in the at least one second data block; and, when writing When data is entered into the at least one second data block and a sudden shutdown occurs, the flash memory controller abandons the data stored in the at least one second data block and performs an internal copy from the Nth A data block moves written data to the at least one second data block. The flash memory device as described in item 1 of the patent application, wherein the unit in the N first data blocks stores 2-bit information, and one unit in the at least one second data block stores 2 ^N -bit information, N is greater than or equal to 2 and is an integer. For example, the flash memory device described in item 2 of the patent application, wherein N is equal to 3, the at least one second data block is a TLC data block, and the flash memory controller writes the The data is classified into three groups of data and written to three SLC data blocks respectively. For the flash memory device described in item 1 of the patent application, the N first data blocks are N SLC data blocks. When the flash memory controller writes data to a group of data to an SLC During the data block, the flash memory controller sorts all the word lines of the SLC data block into one group of word lines for every M word lines in order to generate a complex group of odd numbers. The word lines of the array and the word lines of the even number group of the complex number group, as well as the word lines of the odd number group of the complex number group and the word lines of the even number group of the complex number group, respectively perform different times of Reed-Solomon code encoding operations. , generate a first check code for the word line of the odd number group of the complex number group and a second check code for the word line of the even number group of the complex number group, write and store the first check code in the complex number group The last plurality of data pages of the last character line of the last group of character lines in the odd group of character lines, write and store the second check code in the last group of characters in the plural group of even group of character lines. The last plurality of data pages of the last character line of the line. The flash memory device as described in item 1 of the patent application, wherein when memory garbage collection is performed, the flash memory controller reads the N first data blocks from the outside The data is re-encoded and written, or the at least one second data block is read from the outside and re-encoded and written. The flash memory device described in item 1 of the patent application, wherein when writing data to the N first data blocks, the flash memory controller is based on the at least one second data block. A randomizer seed rule writes data to the N first data blocks. A flash memory storage management method is used for a flash memory module. The flash memory module includes N first data blocks and at least one second data block. The method includes: Respectively perform single-layer unit data writing and perform an error correction encoding operation of a data management mechanism applied to a fault-tolerant disk array to generate a corresponding check code for a piece of data; The data of the N groups in the data and the N check codes corresponding to the data of the N groups in the corresponding check codes are respectively written to the N first data blocks, so that the fast The flash memory module writes the data of the N groups and the N check codes respectively stored in the N first data blocks to the at least one second data block, wherein the N first data The number of bits of information stored in a unit in the block is different from the number of bits of information stored in a unit in the at least one second data block; and When data is written to the at least one second data block and a sudden shutdown occurs, the flash memory controller is caused to abandon the data stored in the at least one second data block and perform an internal copy from the N Move written data from a first data block to the at least one second data block. The flash memory storage management method described in item 7 of the patent application, wherein the unit in the N first data blocks stores 2-bit information, and one of the at least one second data blocks The unit stores 2 ^N bits of information, where N is greater than or equal to 2 and is an integer. The flash memory storage management method described in item 8 of the patent application, wherein N is equal to 3, the at least one second data block is a TLC data block, and the data is classified into three groups material. The flash memory storage management method described in item 7 of the patent application, wherein the N first data blocks are N SLC data blocks, and the flash memory storage management method further includes: When writing data to a group of data to an SLC data block, all the word lines of the SLC data block are sorted into a group of word lines every M character lines in order to generate a complex group of odd numbers. The character lines of complex number groups and the character lines of even number groups; For the word lines of the odd number group of the complex number group and the word lines of the even number group of the complex number group, respectively perform different times of Reed-Solomon code encoding operations to generate a first correction of the word line of the odd number group of the complex number group. The check code is a second check code of the word line of the even number group of the complex number group; and Write and store the first check code in the last plurality of data pages of the last character line of the last group of character lines in the odd group of plural word lines, write and store the second check code in The last plurality of data pages of the last character line of the last group of character lines in the plural group of even group of character lines. The flash memory storage management method described in item 7 of the patent application also includes: When memory garbage collection is performed, the data of the N first data blocks are read from the outside and re-encoded and written, or the at least one second data block is read from the outside and re-encoded and written. Write. The flash memory storage management method described in item 7 of the patent application also includes: When writing data to the N first data blocks, data is written to the N first data blocks according to a random seed number rule of the at least one second data block. A flash memory controller containing: A plurality of channels are respectively connected to a flash memory module. The flash memory module includes N first data blocks and at least one second data block; and an error correction code encoding circuit; The flash memory controller is used to write a piece of data to the flash memory module, perform single-layer unit data writing respectively, and use the error correction code encoding circuit to execute a program applied to a fault-tolerant disk array. The error correction coding operation of one of the data management mechanisms generates a corresponding check code of the data, and associates the data of the N groups in the data with the data of the N groups in the corresponding check code. The N check codes are respectively written into the N first data blocks, where one unit in the N first data blocks stores 2-bit data, allowing the flash memory module to store the N The data of the N groups and the N check codes respectively stored in the first data blocks are copied and moved to the at least one second data block, wherein a unit in the N first data blocks The number of bits of information stored is different from the number of bits of information stored in a unit in the at least one second data block; and, when data is written to the at least one second data block and a sudden occurrence When shutting down, the flash memory controller abandons the data stored in the at least one second data block and performs an internal copy to move the written data from the N first data blocks to the at least one second data block. Data block.