TWI643062B - Flash memory apparatus and storage management method for flash memory - Google Patents

Flash memory apparatus and storage management method for flash memory Download PDF

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Publication number
TWI643062B
TWI643062B TW106106328A TW106106328A TWI643062B TW I643062 B TWI643062 B TW I643062B TW 106106328 A TW106106328 A TW 106106328A TW 106106328 A TW106106328 A TW 106106328A TW I643062 B TWI643062 B TW I643062B
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Taiwan
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data
flash memory
data block
array
word line
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TW106106328A
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Chinese (zh)
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TW201812583A (en
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楊宗杰
許鴻榮
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慧榮科技股份有限公司
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Priority to US62/328,025 priority
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Priority claimed from CN201710271879.7A external-priority patent/CN107391026A/en
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Abstract

A flash memory storage management method includes: providing a flash memory module, the flash memory module comprising a plurality of single layer unit data blocks and at least one multi-level unit data block; The data is classified into a plurality of groups of data; respectively performing single-layer unit data writing and performing an error correction encoding operation of a similar fault-tolerant disk array to generate a corresponding check code to compare the plurality of groups of data and the corresponding check code Writing to the single-layer unit data blocks; when the writing of the single-layer unit data blocks is completed, performing internal copying, storing the complex group data stored in the single-layer unit data blocks, and the corresponding The check code is sequentially written to the at least one multi-level cell data block according to the storage order of the single-layer unit data blocks.

Description

Flash memory device and flash memory storage management method

The present invention relates to a flash memory device, and more particularly to a flash memory device and a memory management method for performing an error correction encoding operation similar to a fault tolerant disk array.

In general, for a flash memory controller to perform data writing to write a piece of data to a single layer unit data block or a multi-level unit data block, the conventional mechanism is used, for example, in a data block. The last page of the word line is placed with a check code corresponding to other data pages of the word line, so that when a write failure, a word line break, and a word line short circuit occur, the corresponding check code can be used. A certain degree of error correction, however, such data storage rate is too low, for example, if a word line includes 8 data pages, only 7 data pages are used to store data, and another data page is used to store the school. In this case, a ratio of 1/8 in a data block is used to store the check code, not to store the data, which is unacceptable from the user's point of view.

Therefore, one of the objectives of the present invention is to provide a flash memory device and a corresponding flash memory storage management method, which use an error correction coding operation similar to a fault tolerant disk array to reduce the incidence of errors and reduce the traditional mechanism. The number of check codes to be used, and the required check code is stored in the corresponding data page position appropriately, so that the required check can still be used when the write failure, the word line is broken, and the word line is shorted. The code solves the above problem by performing a certain degree of error correction.

In accordance with an embodiment of the invention, a flash memory device is disclosed. The flash memory device comprises a flash memory module and a flash memory controller, the flash memory module comprises a plurality of single layer unit data blocks and at least one multi-level unit data block, flash memory The controller has a plurality of channels respectively connected to the flash memory module, and the flash memory controller classifies a piece of data to be written into a plurality of groups of data, and the flash memory controller respectively performs single layer unit data writing. Invoking and executing a similar error-correcting disk array error correction encoding operation generates a corresponding check code to write the complex group data and the corresponding check code to a plurality of single-layer unit data blocks; when the complex number is completed When writing a single-layer unit data block, the flash memory module performs internal copying, and the data of the complex group and the corresponding check code stored in the plurality of single-layer unit data blocks are determined according to the data. In the order, the writing is sequentially performed to at least one multi-level unit data block.

According to an embodiment of the invention, a flash memory storage management method is further disclosed. The method includes: providing a flash memory module, the flash memory module comprising a plurality of single layer unit data blocks and at least one multi-level unit data block; classifying a piece of data to be written into a plurality Group data; respectively performing single-layer unit data writing and performing an error correction encoding operation similar to a fault-tolerant disk array to generate a corresponding check code to write the data of the complex group and the corresponding check code to The plurality of single-layer unit data blocks; when the writing of the plurality of single-layer unit data blocks is completed, performing an internal copy, storing the data of the plurality of groups stored in the plurality of single-layer unit data blocks and The corresponding check code is sequentially transferred to the at least one multi-level unit data block according to the order of the data.

Please refer to FIG. 1 , which is a schematic diagram of a device of a flash memory device 100 according to an embodiment of the invention. The flash memory device 100 includes a flash memory module 105 and a flash memory controller 110. The flash memory module 105 is a flash memory module having a two-dimensional planar architecture; limit. The flash memory module 105 includes a plurality of flash memory chips (not shown in FIG. 1), and each of the flash memory chips includes a plurality of single-level cell (SLC) blocks. Block) and a plurality of multi-lele-cell blocks, each unit of the single-layer unit data block can store 2 bits of data, and each unit of the multi-level unit data block can store 2 N The data of the bit, N is greater than or equal to 2 and is an integer. The multi-level cell data block, for example, includes a unit with a multi-level cell block, and can store 22 bits of data and a TLC block (triple-level). The unit of the cell block can store 23 yuan of data, the unit of the QLC block (quad-level cell block) can store 24 bits of data, and so on.

The flash memory controller 110 can be connected to the flash memory module 105 through a plurality of channels, so that data can be simultaneously written to different flash memory chips by using different channels, thereby increasing writing efficiency and flash memory. The controller 110 includes an error correction code encoding circuit 1101 and a parity check code buffer 1102. The error correction code encoding circuit 1101 is configured to perform an error correction code encoding operation on the data, for example, in the embodiment of the present invention. Encoding operations including Reed-solomon codes and/or encoding operations of exclusive-OR (XOR) operations to generate corresponding check codes, used by check code buffer 1102 The corresponding verification code generated by the temporary storage, and the flash memory controller 110 is used for a similar data management mechanism of a Redundant Array of Independent Disks (RAID) to write a piece of data into different The flash memory chip reduces the error rate, and simultaneously considers the check code of different encoding operations in the storage location of the single-layer unit data block when writing the data to the single-layer unit data block. And the storage location of the TLC data block, so that when the data is written to the single-layer unit data block, the data error can be corrected and the subsequent flash memory module 105 is operated by the internal copy operation from the single-layer unit area. When the block moves the data copy to the TLC data block, the data error can also be corrected.

In practice, in order to improve the efficiency of data writing and reduce the error rate, the flash memory module 105 includes a plurality of channels (in this embodiment, two channels, but not limited), when a channel executes a certain data page. When writing (page), another channel can be used to perform writing of another data page without waiting for the channel, and each channel has its own sequence transmitter in the flash memory controller 110 (sequencer) And each includes a plurality of flash memory chips (in this embodiment, two wafers, but not limited), so that one channel can simultaneously write different data pages to multiple flash memory chips without It is necessary to wait for one of the wafers. In addition, each flash memory chip can have a folded design and have two different planes, so that one flash memory chip can simultaneously utilize different data when writing. Two data blocks on two planes are used to perform writing of different data pages without waiting for one of the data blocks. Therefore, a super block of the flash memory module 105 is composed of a plurality of data pages of a plurality of flash memory chips of a plurality of channels. The above flash memory controller 110 writes the data in units of super data blocks, and first writes the data to the single layer unit data block in the flash memory module 105, and the single layer The unit data block buffer, and then copy and copy the data from the single layer unit data block to the TLC data block. In addition, it should be noted that in other embodiments, each flash memory chip may not have a folding design, that is, a flash memory chip uses a data block to execute a data page when data is written. Write, waiting for the writing of other data pages.

In the process of data writing, a piece of data is first written by the flash memory controller 110 to a plurality of single-layer unit data blocks 1051A to 1051C, and then moved from the single-layer unit data blocks 1051A to 1051C. To the multi-level cell data block 1052, for example, in the embodiment, a multi-layer data block with a TLC unit as an example is taken as an example, and the TLC unit can store 23- bit information, that is, three single-layer unit data. The blocks (hereinafter referred to as SLC data blocks) 1051A~1051C will be written to a TLC data block 1052. Based on this, it is considered that the writing of the SLC data blocks 1051A~1051C and the TLC data area are required. The writing of block 1052 is protected by error correction. The flash memory controller 110 classifies a piece of data into three groups of data. It should be noted that if the MLC unit is used as a multi-layer data block. for example, due to the MLC unit can store 22 bits of information, the flash memory controller 110 of the series will be classified as two groups of data, and if the department to QLC unit data block is a multi-layer architecture For example, because the QLC unit can be stored 2 4- bit information, so the flash memory controller 110 will classify the data into four groups of data; and so on. That is to say, when the unit of the multi-layer unit data block 1052 can store information with 2 N bits, N is greater than or equal to 2 and is an integer, and the number of single-layer unit data blocks is designed as N SLC data blocks. The flash memory controller 110 classifies the data to be written into N groups of data to be respectively written to the N SLC data blocks.

In this embodiment, after the flash memory controller 110 classifies the pen data into three groups of data, the first data writing (SLC program) is executed to write the first group of data into the above. The first SLC data block 1051A and the error correction code encoding circuit 1101 generate a corresponding check code and write it into the first SLC data block 1051A, thus completing the writing operation of the SLC data block, and then The flash memory controller 110 then performs a second data write (SLC program) to write the second group of data into the second SLC data block 1051B and generate a corresponding check using the error correction code encoding circuit 1101. The code is written into the second SLC data block 1051B, so that the second SLC data block write operation is completed, and the flash memory controller 110 then performs the third data write (SLC). The third group of data is written into the third SLC data block 1051C and the corresponding check code is generated by the error correction code encoding circuit 1101 and written into the third SLC data block 1051C, thus completing Third SLC Feed block write operation.

When the flash memory controller 110 performs a certain SLC program to write a certain group of data into a certain SLC data block, or after the data is written, the flash memory controller 110 will Check if there is an error, if the data is wrong, for example, a write failure of a certain SLC data block write, one word line open and/or a two word line short circuit (two word In the case of line short, the flash memory controller 110 corrects the above error by using the corresponding correction code generated by the error correction code encoding circuit 1101 at the time of writing the data.

When the data of the above three groups are written into the three SLC data blocks, the data is written in 1051A~1051C or one of the SLC data blocks is completed, the flash memory module 105 performs internal copying. In the SLC data blocks 1051A~1051C or one of the SLC data blocks, the data of the three groups or the data of a certain group are copied and moved, and the TLC program is executed in the order of the data of the three groups to a TLC data area. Block 1052 (that is, the aforementioned super data block), the TLC data block 1052 is composed of data pages of word lines of different flash memory chips of different channels, for example, a character of the TLC data block 1052. A data page of the line includes an upper page, a middle page, and a lower page. The internal copy of the flash memory module 105 is, for example, an SLC data area. A plurality of data pages on the Nth character line of the block are written to a plurality of upper data pages of one of the character lines of the TLC data block 1052, and the number of the N+1th character lines of the SLC data block is increased. Data pages are written to the same word line of TLC data block 1052 A plurality of intermediate data pages, and a plurality of data pages on the N+2th word line of the SLC data block are written to the plurality of lower data pages of the same word line of the TLC data block 1052. The data of all three groups is written to the TLC data block 1052, thus completing the writing operation of the super data block.

It should be noted that in order to make the internal copy easy to implement, meet the randomizer seed rule requirements of the TLC data block 1052, and simultaneously consider the error correction coding ability to reduce the error rate, the internal copy operation is based only on the data. The order moves the data to the positions of the upper, middle and lower data pages of the plurality of character lines of the TLC data block 1052, and the flash memory controller 110 writes the data of the different groups and the corresponding generated checksum. When the code is sent to the SLC data blocks 1051A to 1051C, the error correction code encoding circuit 1101 is incorrect according to the random number seed number rule requirement of the TLC data block and the write storage position of the check code of the error correction code. Correcting the encoding capability can correct the write failure of the SLC data block, the disconnection of a word line and/or the short of the two word lines when performing a write operation of the SLC data block, and can execute the super The write operation of the data block corrects the error caused by the write failure of the TLC data block 1052, the disconnection of a word line, and/or the short of the two word lines.

In addition, if the flash memory module 105 performs a garbage collection, the flash memory controller 110 reads the data from the SLC data blocks 1051A to 1051C and re-reads it by external reading. The error correction is performed to perform a data write (SLC program), and/or the data is read from the TLC data block 1052 and the error correction code is re-executed to perform a data write (SLC program). In addition, if the SLC program is written to an SLC data block and a shutdown occurs suddenly, the flash memory controller 110 reads back the data from the SLC data block and rewrites the error correction code and writes the data. (SLC program) to another new SLC data block. In addition, if the TLC program is written to the TLC data block 1052 and the power is suddenly turned off, the flash memory module 105 discards the data currently stored in the TLC data block 1052 and extracts the data from the SLC data. The blocks 1051A to 1051C re-send the corresponding material execution TLC data to the TLC data block 1052 by internal copying.

Referring to FIG. 2, FIG. 2 is a diagram showing a flash memory controller 110 shown in FIG. 1 of the first embodiment of the present invention, which performs SLC program writing to write data of a certain group to a flash memory. A schematic diagram of one of the SLC data blocks in the module 105 to perform a SLC data block write operation. The error correction code encoding circuit 1101 of the flash memory controller 110 performs a Reed Solomon (RS) encoding operation on a data-like array with a fault-tolerant disk array to generate a corresponding check code. The code check buffer 1102 is used to temporarily store the generated check code.

The flash memory module 105 includes two channels, and includes two flash memory chips and two sets of blocks of each chip having two different planes. For writing efficiency, the flash memory controller 110 is required. Two blocks of data are written to the two flash memory chips in the flash memory module 105 through two channels. As shown in the embodiment of FIG. 2, an SLC data block includes, for example, 128 word lines (represented by WL0 to WL127, respectively), and the SLC data block may be an SLC data block or a group. The SLC sub-data block is formed according to the definition of the SLC data block. For convenience of description, in the embodiment, 128 word lines are included as the size of one SLC data block, wherein each word line includes For example, there are 8 data pages. Taking the first character line WL0 of the SLC data block as an example, the flash memory controller 110 writes the data pages P1 and P2 to the channel CH0 and the folding planes PLN0 and PLN1. Flash memory chip CE0, then data pages P3, P4 are written to another flash memory chip CE1 by the same channel CH0 and folding planes PLN0, PLN1, and then by another channel CH1 and folding planes PLN0, PLN1 The data pages P5 and P6 are written to the flash memory chip CE0, and then the material pages P7 and P8 are written to the flash memory chip CE1 by the channel CH1 and the folding planes PLN0 and PLN1. Others are like this.

The flash memory controller 110 classifies each of the M word lines into a group by a plurality of word lines WL0 to WL127 of one SLC data block, and M is a positive integer greater than or equal to 2, for example, M 3, for example, the word lines WL0 WL WL2 are the first group, the word lines WL3 WL WL5 are the second group, the word lines WL6 WL WL8 are the third group, and the word lines WL9 WL WL11 are the fourth group... The meta-line WL120~WL122 is the third last group, the word line WL123~WL125 is the penultimate group, and the last group of character lines are WL126, WL127, among which the first, third, fifth group, etc. The line is an odd array word line, and the word lines of the second, fourth, sixth group, etc. are even array word lines, and the flash memory controller 110 writes a set of word lines each time. (including the data of three character lines), the error correction code encoding circuit 1101 performs error correction coding on the data of the group of character lines, and outputs the generated partial parity code to the corresponding portion. The check code buffer 1102 is used to temporarily store the check code of the portion.

The check code buffer 1102 stores the check code of the portion corresponding to the odd array word line data in a first buffer 1102A in the check code of the temporary storage portion, and corresponds to the even array word line data. The part of the check code is stored in a second buffer 1102B. For example, when the data pages P1 to P24 of the word lines WL0 WL WL2 are written, the error correction code encoding circuit 1101 performs an error on the data pages P1 to P24. Correcting the code, and outputting the generated check code of the corresponding part to the check code buffer 1102, temporarily storing it in the first buffer 1102A; then writing to the data pages P1~P24 of the word line WL3~WL5, The error correction code encoding circuit 1101 performs error correction coding on the data pages P1 to P24, and outputs the generated partial verification code to the check code buffer 1102, temporarily stored in the second buffer 1102B; When writing the data pages P25~P48 of the word line WL6~WL8, the error correction code encoding circuit 1101 performs error correction coding on the data pages P25~P48, and outputs the generated check code of the corresponding part to the checksum. The code buffer 1102 is temporarily stored in the first buffer 1102A; The data page writing and encoding operations are based on the following... After that, when writing the data pages of the word lines WL120 to WL122, the error correction code encoding circuit 1101 performs encoding on the data pages of the word lines WL120 to WL122, and The generated check code of the corresponding portion is output to the check code buffer 1102 and temporarily stored in the first buffer 1102A.

Then, when the flash memory controller 110 writes the last set of word lines (WL123~WL125) of the even array word line, in addition to performing the SLC program and the corresponding error correction code, The partial check code of the data of all the even array word lines temporarily stored in the second buffer 1102B is read back, and all the check codes corresponding to the data of the even array word line are written to the last set of even array words. The data page of the last word line WL125 of the line, such as the last three data pages (labeled 205), stores the Reed-Solomon check code corresponding to the data of the even array word line.

In addition, for writing the last word line WL127 of the last set of odd array word lines, the flash memory controller 110 will perform the first in addition to the SLC program and the corresponding error correction code. The partial check code of the data of all the odd array word lines temporarily stored in the buffer 1102A is read back, and all the check codes corresponding to the data of the odd array word line are written to the last set of odd array word lines. The data page of the last word line WL127, for example, the last three data pages (labeled 210), stores the Reed-Solomon check code corresponding to the data of the odd array word line. This completes the writing of the SLC data block. Therefore, in the case of the Reed-Solomon coding operation, the check code corresponding to the data of the odd array word line is stored in the last plurality of data pages of the last word line WL127 of the last set of odd array word lines. The position, and the parity code corresponding to the data of the even array word line is stored at the position of the last plurality of data pages of the last word line WL125 of the last set of even array word lines.

Further, the error correction code encoding circuit 1101 performs the Reed-Solomon encoding operation in the embodiment shown in Fig. 2, and can correct the error of the data page occurring at any three positions of the SLC data block, for example, The error correction code encoding circuit 1101 performs error correction coding on the data of the three word lines of the word lines WL0 WL WL2 and generates corresponding partial check codes, if three data pages of the same folding plane of the same wafer of the same channel If an error occurs, for example, the data pages P1, P9, and P17 are in error, the error correction code encoding circuit 1101 can correct the errors of the three data pages by using the corresponding partial check codes generated.

If a program fail occurs when the writing of the SLC data block is performed, for example, in the event of occurrence, for example, the data page P9 is detected to be failed, the error correction code encoding circuit 1101 may The error of the data page P9 is corrected by using the corresponding partial check code generated.

If it is detected that a word line open occurs during the writing of the SLC data block, causing, for example, a data page P9 error, the error correction code encoding circuit 1101 can utilize the corresponding portion generated. Check the code and correct the error of the data page P9.

If it is detected that a two word line short occurs when the writing of the SLC data block is performed, for example, the data pages P9 and P17 are both wrong, the error correction code encoding circuit 1101 can utilize the generated phase. The corresponding partial check code corrects the errors of the data pages P9 and P17. If a two-character line short circuit occurs, causing, for example, the data page P17 of the word line WL2 and the data page P1 of the word line WL3 to be erroneous, the error correction code encoding circuit 1101 can utilize a partial check code of a set of word lines WL0 WL WL2. And a partial check code of another set of word lines WL3 WL WL5 corrects the error of the data page P17 of the word line WL2 and the data page P1 of the word line WL3, respectively. If a two-character line short circuit occurs, causing, for example, the data pages P1, P2 of the word line WL0 to be erroneous, the error correction code encoding circuit 1101 can utilize the partial check codes of the set of word lines WL0 WL WL2 to respectively select the word line WL0. The error correction of the data pages P1 and P2.

Therefore, the error correction code encoding circuit 1101 can correct the errors correspondingly due to a data page error caused by a write failure, a word line break, or a two word line short circuit when the SLC data block write is performed. Information page.

Referring to FIG. 3, FIG. 3 is a schematic diagram of writing an SMC data block in the flash memory module 105 to the TLC data block 1052 by internal copying. As shown in FIG. 3, one set of three word line data of one SLC data block is written to one of the character lines of the TLC data block 1052, correspondingly forming the least significant bit of the data page of one of the word lines. The data of the LSB, the intermediate significant bit CSB and the most significant bit MSB, such as the word line data WL0~WL2 of the SLC data block, are written to the TLC data block 1052 as the lowest of the word line WL0 of the TLC data block 1052. The data of the valid bit LSB, the intermediate valid bit CSB and the most significant bit MSB; the word line data WL3~WL5 of the SLC data block are written to the TLC data block 1052 as the word line WL1 of the TLC data block 1052. The data of the least significant bit LSB, the intermediate significant bit CSB and the most significant bit MSB; the word line data WL6~WL8 of the SLC data block is written to the TLC data block 1052 as the word line WL2 of the TLC data block 1052 The data of the least significant bit LSB, the intermediate effective bit CSB and the most significant bit MSB; that is, the internal copy of the flash memory module 105 moves and writes the data of the SLC data block in the order of the word line. Fill in the word line of the TLC data block.

Referring to FIG. 4, FIG. 4 is a view showing a flash memory controller 110 shown in FIG. 1 of the first embodiment of the present invention writing data of three groups to a plurality of SLCs in the flash memory module 105. The data blocks 1051A~1051C are internally copied to the TLC data block to form a super data block. Since the error correction code encoding circuit 1101 performs the writing of the SLC data block each time, the data is classified into two groups of an odd array word line and an even array word line, and the corresponding generated check code is stored in the odd The last 3 data pages of the last character line of the last character line of the array word line and the last 3 data pages of the last character line of the even array word line. Therefore, when the writing of the TLC data block is performed, In the figure 4, the corresponding check code of the odd array word line of the data of the first group is stored in the last three data pages of the intermediate valid bit CSB of the character line WL42 of the super block (labeled as 401A). And the corresponding check code of the even array word line of the data of the first group is stored in the last three data pages of the most significant bit MSB of the character line WL41 of the super block (labeled as 401B); The corresponding check code of the odd array word line of the data of the second group is stored in the last three data pages (labeled 402A) of the least significant bit LSB of the character line WL85 of the super block, and the second The corresponding check code of the even array of character lines of the group data is stored in the super block. The last three data pages of the most significant bit MSB of the character line WL84 (labeled as 402B); the corresponding check code of the odd array word line of the third group of data is stored in the character of the super block The last three data pages of the most significant bit MSB of the line WL127 (labeled as 403A), and the corresponding check code of the even array word line of the data of the third group are stored in the character line WL127 of the super block. The last three data pages of the least significant bit LSB (labeled 403B).

If it is detected that the two word line short circuit causes an error such as two data pages of the character lines WL0, WL1 of the super block (as indicated by the frame line 404), the flash memory module 105 can utilize the word line WL42. The check code 401A stored on the last three data pages of the intermediate valid bit CSB corrects the error of the data page of the word line WL0, and is stored on the last three data pages of the most significant bit MSB of the word line WL41. The check code 401B corrects the error of the data page of the word line WL1.

Similarly, if a two-character line short circuit is detected, for example, two data pages of the character lines WL43, WL44 of the super block (as indicated by the frame line 405) are erroneous, the flash memory module 105 can utilize the word. The check code 402A stored on the least significant bit LSB of the last three data pages of the WL85 to correct the least significant bit LSB of the data page of one of the character lines WL43 indicated by 405, the error of the intermediate valid bit CSB, and the character Correcting the error of the most significant bit MSB of one of the data pages of the line WL44, and correcting the word line WL43 indicated by 405 by using the check code 402B stored on the intermediate effective bit CSB of the last three data pages of the word line WL84. The error of the most significant bit MSB of the data page and the error of the least significant bit LSB and the intermediate valid bit CSB of the data line WL44.

Similarly, if it is detected that the two word line short circuit causes an error such as two data pages of the character lines WL125 and WL126 of the TLC data block (as indicated by the frame line 406), the flash memory module 105 can Correcting the intermediate valid bit CSB of the data line WL125, the data page of the last valid data bit MSB of the last three data pages of the word line WL127, the error of the intermediate valid bit CSB of the data page, the error of the most significant bit MSB, and the word Correction of the most significant bit MSB of the data line of the WL 126, and the check code 403B stored on the least significant bit LSB of the last three data pages of the word line WL127, to correct the word line WL125 indicated by 406 The error of the least significant bit LSB of the data page and the error of the intermediate valid bit CSB and the most significant bit MSB of the data line WL126 indicated by 406.

If it is detected that a word line is broken or the writing fails, and any data page of any character line of the super block is wrong (that is, any three sub-pages are in error), the flash memory module 105 can use the corresponding stored check code to correct the error of any three consecutive sub-data pages.

That is, the storage location management design of the check codes of the plurality of SLC data blocks 1051A to 1051C written in the flash memory module 105 by the flash memory controller 110 is written. When the flash memory module 105 copies and copies the data from the plurality of SLC data blocks 1051A to 1051C to the TLC data block by internal copy to form a super data block, if a word line disconnection is detected, Errors in shorting or writing failure of two word lines can be corrected by the check codes stored in multiple SLC data blocks 1051A~1051C.

Furthermore, referring to FIG. 5, FIG. 5 is a diagram showing a flash memory controller 110 shown in FIG. 1 of the second embodiment of the present invention for performing a data write (SLC program) to write a group of data to a flash. The SLC data block in the memory module 105 is used to complete a SLC data block write operation. The error correction code encoding circuit 1101 of the flash memory controller 110 performs an encoding operation on the data with a mutual exclusion or operation of a similar fault-tolerant disk array to generate a corresponding check code, and the check code buffer 1102 Used to temporarily store the corresponding check code generated. In addition, the exclusive OR operation of the error correction code encoding circuit 1101 includes three different encoding engines to mutually exclusive or operate on different word line data of the SLC data block; the detailed operation contents are as follows.

The flash memory module 105 includes two channels and includes two flash memory chips. For writing efficiency, the flash memory controller 110 writes data to the flash memory through two channels. Two flash memory chips in the module 105 respectively program the data pages of one SLC data block into different flash memory chips, and one SLC data block write operation of the flash memory controller 110 The written data includes 128 word lines (represented by WL0 to WL127, respectively), and each word line includes 8 data pages. For example, the word line WL0 is taken as an example, and the error correction code encoding circuit 1101 is used for the channel. CH0 and PLN0, PLN1 write data pages P1 and P2 to the flash memory chip CE0, and then write the data pages P3 and P4 to another flash memory chip CE1 through the same channels CH0 and PLN0, PLN1, and then The data pages P5 and P6 are written to the flash memory chip CE0 by the other channels CH1 and PLN0, PLN1, and then the data pages P7 and P8 are written to the flash memory chip CE1 by the channels CH1 and PLN0, PLN1.

The error correction code encoding circuit 1101 classifies each of the M word lines into a group by a plurality of word lines WL0 to WL127 of one SLC data block, and M is a positive integer greater than or equal to 2, for example, 3. For example, the word lines WL0 WL WL2 are the first group, the word lines WL3 WL WL5 are the second group, the word lines WL6 WL WL8 are the third group, and the word lines WL9 WL WL11 are the fourth group. Lines WL120~WL122 are the third last group, word lines WL123~WL125 are the penultimate group, and the last group of word lines are WL126, WL127, among which the first, third, fifth group, etc. An odd array of word lines, and the word lines of the second, fourth, sixth group, etc. are even array word lines, and the flash memory controller 110 writes data of a set of word lines each time ( The data including the three character lines) is performed by using the error correction code encoding circuit 1101 to perform error correction coding of the exclusive or arithmetic operation on the data of the group of character lines, and the corresponding part of the generated check code (partial parity) The code is output to the check code buffer 1102 to temporarily store the check code of the portion.

When the error correction code encoding circuit 1101 writes data to a set of three different word lines, three different encoding engines are used to perform mutually exclusive or arithmetic coding on the written data, and the corresponding ones are generated. A part of the check code is output to the check code buffer 1102 to temporarily store the check code of the part, and the check code buffer 1102 corresponds to the character line data of the odd array when the check code of the temporary memory part 1102 is used. The check code of the part is stored in a first buffer, and the check code of the part corresponding to the character line data of the even array is stored in a second buffer.

For example, the error correction code encoding circuit 1101 includes a first encoding engine, a second encoding engine, and a third encoding engine. When the data pages P1 to P24 of the word lines WL0 WL WL2 are written, the first encoding engine is sequentially used. Performing a mutually exclusive OR operation on the data pages P1 P P8 of the word line WL0 to generate a first partial check code, and using the second encoding engine to mutually exclusive or operate on the data pages P9~P16 of the word line WL1 to generate a first The two-part check code and the data page P17~P24 of the word line WL2 are mutually exclusive ORed by the third encoding engine to generate a third partial check code, and the generated partial check codes are respectively output. The check code buffer 1102 is temporarily stored in the first buffer; then the error correction code encoding circuit 1101 writes the data pages P1 P P24 of the word lines WL3 WL WL5, and sequentially uses the first encoding engine for the word line WL3. The data pages P1~P8 perform a mutual exclusion operation to generate another first partial check code, and perform a mutual exclusion operation on the data pages P9~P16 of the word line WL4 by the second encoding engine to generate another second partial calibration. Code verification and use of the third encoding engine for word line WL5 The data pages P17~P24 perform a mutual exclusion operation to generate another third partial check code, and output the generated partial check codes to the check code buffer 1102, temporarily stored in the second buffer. .

Subsequent data page writing and encoding operations are based on the following, that is, the data of the first character line, the data of the second character line, and the third word for a set of odd array word lines. The data of the meta-line and the data of the first character line, the data of the second character line, and the data of the third character line of a set of even-array character lines are respectively executed for different times of mutual exclusion or The operation produces a corresponding check code. Then, in order to write the corresponding check code to the appropriate storage location of the SLC data block, the error correction code encoding circuit 1101 writes the corresponding data pages of the last six word lines WL122 to WL127. The check code is written in the last data page of the last six word lines WL122~WL127 (as shown by the rectangular slash box in FIG. 5), for example, when writing the data page of the word line WL122, the word The element line WL122 is a third word line of a set of odd array word lines, and the error correction code encoding circuit 1101 writes all the third lines in all the odd array word lines in the last data page of the word line WL122. The check code corresponding to the data of the word line (that is, all the third part check codes generated by the third encoding engine in the odd array word line), and when writing the data page of the word line WL123 The word line WL123 is the first word line of the last set of even array word lines, and the error correction code encoding circuit 1101 is written in all the even array word lines in the last data page of the word line WL123. The check code corresponding to the data of all the first character lines (that is, the even array of word lines) All first partial check codes generated by the first encoding engine, and when writing the data pages of the word line WL124, the word line WL124 is the second character line of the last set of even array word lines. The error correction code encoding circuit 1101 writes the check code corresponding to the data of all the second character lines in all the even array word lines in the last data page of the word line WL124 (that is, the even array character) All second partial check codes generated by the second encoding engine in the line, and when writing the data page of the word line WL125, the word line WL125 is the third word of the last set of even array word lines The error correction code encoding circuit 1101 writes the check code corresponding to the data of all the third character lines in all the even array word lines in the last data page of the word line WL125 (ie, even number) All third partial check codes generated by the third encoding engine in the group word line), and when writing the data page of the word line WL126, the word line WL126 is the last set of odd array word lines One word line, the error correction code encoding circuit 1101 is the last one of the word line WL126 The check code corresponding to the data of all the first character lines in all odd array word lines is written in the material page (that is, all the first part check codes generated by the first encoding engine in the odd array word lines) When the data page of the word line WL127 is written, the word line WL127 is the second word line of the last set of odd array word lines, and the error correction code encoding circuit 1101 is at the end of the word line WL127. A data page is written with the check code corresponding to the data of all the second character lines in all the odd array word lines (that is, all the second parts generated by the second encoding engine in the odd array word lines) Check code). This completes the writing of the SLC data block.

That is, when the flash memory controller 110 writes a group of data to an SLC data block, the flash memory controller 110 sequentially marks all the word lines of the SLC data block for each M word. The meta-line is grouped into a set of word lines to generate a character line of a complex array of odd-numbered arrays and a complex-array even-numbered array of word lines, and for each of a set of odd-arrayed character lines and a set of even-numbered arrays. a character line, respectively performing different M times of exclusive or exclusive encoding operations, generating M partial check codes of each character line of the set of odd arrays and M of each character line of the set of even arrays a partial check code, writing and storing M partial check codes of each character line of the odd array odd array in the last data page of the last M word lines in the complex array odd array word line And writing and storing the M partial check codes of each character line of the complex array even array in the last data page of the last M word lines in the complex array even array word line. In the above embodiment, M is 3, but this is not a limitation of the present case.

The error correction code encoding circuit 1101 performs a mutually exclusive or arithmetic coding operation in the embodiment shown in FIG. 5, and can correct a data page error occurring at a position on one of the word lines of the SLC data block, for example, If the occurrence of the write failure is detected when the writing of the SLC data block is performed, for example, the data page P9 of the word line WL1 is detected to be unsuccessfully written, the error correction code encoding circuit 1101 can utilize the second encoding engine. Corresponding partial check code generated when processing the word line WL1 of the first character line and other correct data pages P10~P16 of the same word line WL1, correcting the data page P9 of the word line WL1 error.

If it is detected that a word line break occurs when the writing of the SLC data block is performed and the data page P9 of the character line WL1 is incorrect, for example, the error correction code encoding circuit 1101 can also use the second encoding engine for processing. The corresponding partial check code generated when the word line WL1 of a set of word lines and the other correct data pages P10 to P16 of the same word line WL1 correct the error of the data page P9 of the word line WL1.

If it is detected that a two-character line short circuit occurs when the writing of the SLC data block is performed, causing, for example, the data page P9 of the word line WL1 and the P17 of the word line WL2 are both wrong, the error correction code encoding circuit 1101 can be utilized. The second encoding engine generates a corresponding partial check code generated by the word line WL1 of the first character line and other correct data pages P10~P16 of the same word line WL1, and corrects the word line WL1. The error of the data page P9, and the corresponding partial check code generated by the third coding engine when processing the word line WL2 of the first character line and the other correct data page P18 of the same word line WL2 P24, correcting the error of the data page P17 of the word line WL2. On the other hand, if the data page P17 of the word line WL2 and the data page P1 of the word line WL3 are in error, the error correction code encoding circuit 1101 can use the third encoding engine to process the word line WL2 of the first group of character lines. Corresponding partial check code and other correct data pages P18~P24 of the same word line WL2, correcting the error of the data page P17 of the word line WL2, and processing the second group of characters by using the first encoding engine The corresponding partial check code generated when the line word line WL3 is generated and the other correct data pages P2 to P8 of the same word line WL3 correct the error of the data page P1 of the word line WL3. Therefore, the error correction code encoding circuit 1101 can correct the errors correspondingly due to a data page error caused by a write failure, a word line break, or a two word line short circuit when the SLC data block write is performed. Information page. The operation of the flash memory module 105 to write the data to the TLC data block by the SLC data block by internal copy is the same as that of the foregoing FIG. 3 and will not be described again.

Referring to FIG. 6, FIG. 6 is a diagram showing the flash memory controller 110 shown in FIG. 1 of the second embodiment of the present invention writing data of three groups to a plurality of SLCs in the flash memory module 105. The data blocks 1051A to 1051C are internally copied to the data of the SLC data blocks 1051A to 1051C and are written into the TLC data block 1052 to form a super block. The error correction code encoding circuit 1101 classifies the data into odd array word lines and even array word lines each time the SLC data block is written, and stores the corresponding generated check codes in all odd array words. The last data page of the last three character lines in the line and the last data page of the last three word lines of all even array word lines, as shown in Figure 6, execute the TLC data block. When writing, according to the order in which the data is written, the corresponding check code of the word line data in the first group, as indicated by 605A, is written and stored in the last one of the word line WL40 of the TLC data block 1052. The most significant bit MSB of the data page, the last data page of the word line WL41, and the least significant bit LSB and the intermediate significant bit CSB of the last data page of the word line WL42, wherein the SLC data in the first group The check code of the odd array word line of the block is stored in the most significant bit MSB of the last data page of the word line WL40 and the least significant bit LSB and the intermediate effective bit CSB of the last data page of the word line WL42. And the even array of word lines of the SLC data block in the first group Check code stored in the word line WL41 of the last profile page (including the least significant bit LSB, CSB middle significant bit and the most significant bit MSB).

The corresponding check code of the word line data in the second group, as indicated by 605B, is written and stored in the middle valid bit CSB of the last data page of the word line WL83 of the TLC data block 1052 and the highest The valid bit MSB, the last data page of the word line WL84, and the least significant bit LSB of the last data page of the word line WL85, where for the second group, the odd array word line data in the SLC data block All third partial check codes generated by the third encoding engine are stored in the intermediate valid bit CSB of the last data page of the word line WL83 of the TLC data block 1052, all generated by the first encoding engine. The first part of the check code is stored in the most significant bit MSB of the last data page of the word line WL84 of the TLC data block 1052, and all the second part of the check code generated by the second coding engine is stored in the TLC data. The least significant bit LSB of the last data page of the word line WL85 of the block 1052, and all the pieces generated by the first encoding engine for the even array word line data of the SLC data block in the second group A part of the check code is stored in the TLC data area. The most significant bit MSB of the last data page of the character line WL83 of 1052, and all the second partial verification code generated by the second encoding engine are stored in the last of the word line WL84 of the TLC data block 1052. The least significant bit LSB of the data page, all third partial check codes generated by the third encoding engine are stored in the intermediate valid bit CSB of the last data page of the word line WL84 of the TLC data block 1052.

The corresponding check code of the third group of character line data, as indicated by 605C, is the last data page (including the least significant bit LSB) written and stored in the character line WL126, 127 of the TLC data block 1052. , the intermediate significant bit CSB and the most significant bit MSB), wherein for the odd array word line data in the SLC data block in the third group, all the third partial check code generated by the third encoding engine is stored in The least significant bit LSB of the last data page of the word line WL126 of the TLC data block 1052, all the first partial check code generated by the first encoding engine is stored in the word line WL127 of the TLC data block 1052. The intermediate valid bit CSB of the last data page, all the second partial check codes generated by the second encoding engine are stored in the most significant bit MSB of the last data page of the word line WL127 of the TLC data block 1052. And for the even array of word line data in the SLC data block in the third group, all the first part of the check code generated by the first encoding engine is stored at the end of the word line WL126 of the TLC data block 1052. Intermediate valid bit CSB of a data page All second partial check codes generated by the second encoding engine are stored in the most significant bit MSB of the last data page of the word line WL126 of the TLC data block 1052, and all generated by the third encoding engine The third partial check code is stored in the least significant bit LSB of the last data page of the word line WL127 of the TLC data block 1052.

Therefore, when the flash memory module 105 moves the write data from the SLC data blocks 1051A to 1051C to the TLC data block 1052 through the internal copy operation, if the two word line short circuit is detected, for example, the TLC data area is caused. An error occurs in the two data pages of the word lines WL0, WL1 of block 1052 (as indicated by the frame line 610), and the flash memory module 105 can utilize the last data of the word line WL42 stored in the TLC data block 1052. Correcting the first partial check code of the intermediate valid bit CSB of the page and the least significant bit LSB of the other data pages of the word line WL0, correcting the data of the least significant bit LSB of the data page of the 610 marked character line WL0, using The second partial check code of the most significant bit MSB of the last data page of the word line WL42 of the TLC data block 1052 and the intermediate valid bit CSB of the other data pages of the word line WL0 are corrected to be corrected 610. The data of the intermediate significant bit CSB of the data page of the marked word line WL0, and the third partial check code of the most significant bit MSB of the last data page of the word line WL40 stored in the TLC data block 1052 And other characters of the word line WL0 The data of the most significant bit MSB of the data page is used to correct the data of the most significant bit MSB of the data page of the 610 marked word line WL0. Similarly, the flash memory module 105 can utilize the first partial check code of the least significant bit LSB of the last data page of the word line WL41 stored in the TLC data block 1052 and other data pages of the word line WL1. The least significant bit LSB data is used to correct the data of the least significant bit LSB of the data page of the 610 marked word line WL1, using the middle of the last data page of the word line WL41 stored in the TLC data block 1052. The second partial check code of the valid bit CSB and the data of the intermediate valid bit CSB of the other data pages of the word line WL1 are used to correct the data of the intermediate effective bit CSB of the data page of the 610 marked word line WL1, and to utilize The third partial check code of the most significant bit MSB of the last data page of the word line WL41 of the TLC data block 1052 and the most significant bit MSB of the other data pages of the word line WL1 are stored to correct 610. The data of the most significant bit MSB of the data page of the marked word line WL1.

Similarly, if the error caused by the shorting of the two word lines is a continuous data page of any two consecutive word lines of the super block (for example, the wrong position indicated by 615, 620), the flash memory module 105 can correct the error by using the corresponding check code stored in the last data page of the last 6 word lines of an SLC data block in each group. In addition, if it is detected that a word line is broken or the write fails, any data page of any word line of the TLC data block 1052 is incorrect (that is, the three valid bits of the same data page are faulty or If the different valid bits of two consecutive data pages are in error, the flash memory module 105 can correct the error of any three consecutive valid bits by using the corresponding stored check code.

That is to say, the three groups of data are written by the flash memory controller 110 to the check code storage location management design of the plurality of SLC data blocks 1051A to 1051C in the flash memory module 105, when flashing When the memory module 105 copies and copies the data from the plurality of SLC data blocks 1051A to 1051C to the TLC data block by internal copying, if a word line disconnection, two word line short circuit or write is detected The failed error can be corrected by the check code stored in multiple SLC data blocks 1051A~1051C.

Furthermore, the above embodiments of the present invention are also applicable to an architecture such as an MLC data block or a QLC data block. When used in an MLC data block, the above three group data are classified into two groups of data, and if If the encoding operation is performed by mutual exclusion or operation, it is implemented by using two encoding engines. The other conditions are the same as those used in the TLC data block. Therefore, if it is used in the QLC data block, the above three The group data is changed into four groups of data, and if the encoding operation for performing the mutual exclusion or operation is implemented by using four encoding engines, the other conditions are the same as those used in the TLC data block. The architecture of other data blocks is the same.

In terms of the overhead of data storage, if two memory chips are written in two channels, and each memory chip has a folded plane design so that two blocks can be simultaneously written, one SLC data is used. For the data writing of the block, 128 word lines have 8*128 data pages, and only 6 data pages need to be used to store the corresponding check code, and the percentage of cost is less than 1% (6/( 128*8)), that is, for the writing of the SLC data block and the writing of the TLC data block, it is only necessary to use less than 1% of the data space for storing the corresponding error correction check code, the data space It is extremely efficient to use. If four memory chips are written in four channels, and each memory chip has a folded plane design so that two blocks can be simultaneously written, in the case of data writing of one SLC data block, 128 There are 4*4*2*128 data pages in the word line, and only 6 data pages need to be used to store the corresponding check code. The percentage of cost will be lower, about 0.15% (6/(128). *4*4*2)), that is, for the writing of the SLC data block and the writing of the TLC data block, it is only necessary to use about 0.15% of the data space for storing the corresponding error correction check code. The data space is more efficient to use. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Flash memory device

105‧‧‧Flash Memory Module

110‧‧‧Flash Memory Controller

205, 210, 401A, 401B, 402A, 402B, 403A, 403B, 605A, 605B, 605C‧‧‧ check code storage location

404, 405, 406, 610, 615, 620‧ ‧ TLC data block data page

1051A, 1051B, 1051C‧‧‧SLC data block

1052‧‧‧TLC data block

1101‧‧‧Error correction code encoding circuit

1102‧‧‧ checksum buffer

1102A, 1102B‧‧‧ buffer zone

FIG. 1 is a schematic diagram of an apparatus of a flash memory device according to an embodiment of the present invention. 2 is a first embodiment of the first embodiment of the present invention, the flash memory controller performs SLC data writing, and writes a certain group of data into one SLC data block in the flash memory module to execute Schematic diagram of a SLC data block write operation. Figure 3 is a schematic diagram of one of the SLC data blocks in the flash memory module writing data to the TLC data block by internal copying. Figure 4 is a diagram showing the flash memory controller shown in Fig. 1 of the first embodiment of the present invention writing data of three groups to a plurality of SLC data blocks in the flash memory module and copying the data by internal copying. A schematic diagram of moving a write to a TLC data block to form a super block. 5 is a second embodiment of the second embodiment of the present invention, the flash memory controller performs SLC data writing to write a group of data to the SLC data block in the flash memory module to complete the first time. Schematic diagram of SLC data block write operation. Figure 6 is a diagram showing the flash memory controller shown in Figure 1 of the second embodiment of the present invention writing data of three groups to a plurality of SLC data blocks in the flash memory module and The data of some SLC data blocks is transferred to the TLC data block to form a schematic diagram of a super block.

Claims (16)

  1. A flash memory device includes: a flash memory module including a plurality of single layer unit data blocks and at least one multi-level cell data block; and a flash memory controller having a plurality of channels Connected to the flash memory module, the flash memory controller first classifies a piece of data to be written into a plurality of groups of data, and the flash memory controller respectively performs single layer unit data writing ( SLC program) and performing one of the Reed-Solomon codes applied to the fault-tolerant disk array, the error correction encoding operation generates a corresponding check code to write the data of the complex group and the corresponding check code to the a plurality of single-layer unit data blocks; when the writing of the plurality of single-layer unit data blocks is completed, the flash memory module performs an internal copy, and the plurality of single-layer unit data is The data of the complex group stored in the block and the corresponding check code are sequentially transferred to the at least one multi-level unit data block according to the order of the data.
  2. The flash memory device of claim 1, wherein the unit of the at least one multi-level unit data block can store information having 2 N bits, N is greater than or equal to 2 and is an integer, the plurality of orders The layer unit data block is N SLC data blocks, and the flash memory controller classifies the data to be written into N groups of data to be respectively written to the N SLC data blocks.
  3. The flash memory device of claim 2, wherein N is equal to 3, the at least one multi-level cell data block is a TLC data block, and the flash memory controller writes the pen The incoming data is classified into three groups of data to be written to the three SLC data blocks.
  4. A flash memory device as described in claim 2, wherein the flash memory control When the controller writes data to a group of data to an SLC data block, the flash memory controller classifies all the word lines of the SLC data block in the order of each M word line. a set of word lines, to generate a character line of the complex array of odd-numbered arrays and a complex-array even-word array of character lines, and the character line of the complex array of odd-numbered arrays and the character-line of the complex-array even-array, respectively Performing a different Reed-Solomon code encoding operation to generate a first check code of the word line of the complex array and a second check code of the word line of the complex array even And storing the first check code in the last plurality of data pages of the last word line of the last set of word lines in the complex array of odd-numbered word lines, writing and storing the second check code in the complex number The last plurality of data pages of the last character line of the last set of character lines in the even-even array word line.
  5. The flash memory device of claim 1, wherein the flash memory controller reads the plurality of single layer unit data areas from the outside when performing a garbage collection. The block data is re-encoded and written, or the at least one multi-level cell data block is externally read and re-encoded and written.
  6. The flash memory device of claim 1, wherein the flash memory controller is from the single layer unit data area when writing data to a single layer unit data block and suddenly shutting down The block reads back the data and re-encodes and writes the data to another single-layer cell data block.
  7. The flash memory device of claim 1, wherein the flash memory controller discards the at least one more when writing data to the at least one multi-level cell data block and suddenly shutting down And storing the data stored in the layer data block, and performing the internal copy, and transferring the data from the plurality of single-layer unit data blocks to the at least one multi-level unit data block.
  8. The flash memory device of claim 1, wherein the flash memory controller is based on the at least one multi-level cell data block when writing data to the single-layer cell data blocks. A randomizer seed rule writes data to the plurality of single-layer unit data blocks.
  9. A flash memory storage management method includes: providing a flash memory module, the flash memory module comprising a plurality of single layer unit data blocks and at least one multi-level unit data block; The written data is classified into a plurality of groups of data; performing a single layer unit data writing (SLC program) and performing one of the Reed-Solomon codes applied to the fault-tolerant disk array to generate a corresponding correction Encoding, the data of the complex group and the corresponding check code are written to the plurality of single-layer unit data blocks; when the writing of the plurality of single-layer unit data blocks is completed, an internal copy is performed, And storing the data of the complex group and the corresponding check code stored in the plurality of single-layer unit data blocks in the order of the data, and sequentially moving the data into the at least one multi-level unit data block.
  10. The flash memory storage management method according to claim 9, wherein the unit of the at least one multi-level unit data block can store information having 2 N bits, N is greater than or equal to 2 and is an integer, the complex number The single-layer unit data block is N SLC data blocks, and the step of classifying the data to be written into the data of the complex group includes: classifying the data to be written into N groups of data To write to the N SLC data blocks separately.
  11. The flash memory storage management method according to claim 10, wherein N is equal to 3, the at least one multi-level unit data block is a TLC data block, and the data to be written is written. The steps of classifying data into N groups to be respectively written into the N SLC data blocks include: classifying the data to be written into three groups of data to be respectively written into three SLC data blocks. .
  12. The flash memory storage management method of claim 10, wherein the step of executing a single layer unit data write (SLC program) comprises: when writing data to a group of data to an SLC data block, All character lines of the SLC data block are sequentially grouped into a set of word lines per M word lines to generate a word line of the complex array odd number array and the character line of the complex array even array; The character line of the complex array odd-numbered array and the character line of the even-array even-array array respectively perform encoding operations of Reed-Solomon codes of different times, and generate a first check code of the character line of the odd-array array of the complex array a second check code of the word line of the complex array even array; and writing and storing the first check code of the last character of the last set of word lines in the complex array of the complex array word line The last plurality of data pages of the line, the second plurality of data pages of the last character line of the last set of character lines in the complex array even array word line are written and stored.
  13. The flash memory storage management method of claim 9, further comprising: when performing memory garbage collection, externally reading the data of the plurality of single-layer unit data blocks and performing re-removal Encoding and writing, or externally reading out the at least one multi-level cell data block and re-encoding and writing.
  14. The flash memory storage management method of claim 9, further comprising: reading data from the single-layer unit data block when writing data to a single-layer unit data block and suddenly shutting down the data block; Return the data and re-encode and write the data to another single-level unit data block.
  15. The flash memory storage management method of claim 9, further comprising: discarding the at least one multi-level unit when writing data to the at least one multi-level unit data block and suddenly shutting down Data stored in the data block, and performing the internal copy, and transferring data from the plurality of single-layer unit data blocks to the at least one multi-level unit data block.
  16. The flash memory storage management method of claim 9, further comprising: when writing data to the single-layer unit data blocks, according to one of the at least one multi-level unit data block Random number of seed rules, write data to the plurality of single-level unit data blocks.
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