TW201812583A - Flash memory apparatus and storage management method for flash memory - Google Patents

Flash memory apparatus and storage management method for flash memory Download PDF

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TW201812583A
TW201812583A TW106106328A TW106106328A TW201812583A TW 201812583 A TW201812583 A TW 201812583A TW 106106328 A TW106106328 A TW 106106328A TW 106106328 A TW106106328 A TW 106106328A TW 201812583 A TW201812583 A TW 201812583A
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flash memory
data block
array
slc
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TW106106328A
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TWI643062B (en
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楊宗杰
許鴻榮
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慧榮科技股份有限公司
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Priority to CN201710271879.7A priority Critical patent/CN107391026B/en
Priority to CN202010373248.8A priority patent/CN111679787B/en
Priority to US15/495,992 priority patent/US10236908B2/en
Publication of TW201812583A publication Critical patent/TW201812583A/en
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Publication of TWI643062B publication Critical patent/TWI643062B/en
Priority to US16/251,033 priority patent/US10771091B2/en
Priority to US16/896,210 priority patent/US11323133B2/en
Priority to US17/676,853 priority patent/US11916569B2/en
Priority to US18/413,007 priority patent/US20240154624A1/en

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    • G06F12/023—Free address space management
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    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
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    • G—PHYSICS
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    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
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Abstract

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Description

快閃記憶體裝置及快閃記憶體儲存管理方法Flash memory device and flash memory storage management method

本發明係關於一種快閃記憶體裝置，尤指一種執行一類似容錯式磁碟陣列的錯誤更正編碼操作之快閃記憶體裝置與儲存管理方法。The present invention relates to a flash memory device, and more particularly to a flash memory device and a memory management method for performing an error correction encoding operation similar to a fault tolerant disk array.

一般而言，對於一快閃記憶體控制器執行資料寫入以寫入一筆資料至單層單元資料區塊或是多層單元資料區塊，傳統的機制係採用於例如在一資料區塊的一字元線的最後一頁放置該字元線之其他資料頁所對應的校驗碼，使得當發生寫入失敗、字元線斷路及字元線短路時可利用該對應的校驗碼來進行一定程度的錯誤更正，然而，這樣的資料儲存率過低，例如一字元線如果包括8張資料頁，則僅有7張資料頁用來存資料，另一張資料頁是用來儲存校驗碼，如此一來，一個資料區塊中將會有1/8的比例是用來儲存校驗碼，而非用來儲存資料，就使用者的角度來說，無法被接受。In general, for a flash memory controller to perform data writing to write a piece of data to a single layer unit data block or a multi-level unit data block, the conventional mechanism is used, for example, in a data block. The last page of the word line is placed with a check code corresponding to other data pages of the word line, so that when a write failure, a word line break, and a word line short circuit occur, the corresponding check code can be used. A certain degree of error correction, however, such data storage rate is too low, for example, if a word line includes 8 data pages, only 7 data pages are used to store data, and another data page is used to store the school. In this case, a ratio of 1/8 in a data block is used to store the check code, not to store the data, which is unacceptable from the user's point of view.

因此，本發明的目的之一在於提供一種快閃記憶體裝置及對應的快閃記憶體儲存管理方法，採用一類似容錯式磁碟陣列的錯誤更正編碼操作，降低錯誤發生率，降低傳統機制所需要使用的校驗碼數目，同時適當地將所需的校驗碼儲存於對應的資料頁位置，令發生寫入失敗、字元線斷路及字元線短路時仍可利用所需的校驗碼來進行一定程度的錯誤更正，解決了上述的問題。Therefore, one of the objectives of the present invention is to provide a flash memory device and a corresponding flash memory storage management method, which use an error correction coding operation similar to a fault tolerant disk array to reduce the incidence of errors and reduce the traditional mechanism. The number of check codes to be used, and the required check code is stored in the corresponding data page position appropriately, so that the required check can still be used when the write failure, the word line is broken, and the word line is shorted. The code solves the above problem by performing a certain degree of error correction.

根據本發明一實施例，其揭露了一種快閃記憶體裝置。快閃記憶體裝置包含有一快閃記憶體模組與快閃記憶體控制器，快閃記憶體模組包括複數個單層單元資料區塊以及至少一多層單元資料區塊，快閃記憶體控制器具有複數條通道分別連接至快閃記憶體模組，快閃記憶體控制器係將一筆欲寫入之資料分類為複數群的資料，快閃記憶體控制器分別執行單層單元資料寫入以及執行一類似容錯式磁碟陣列的錯誤更正編碼操作產生一對應的校驗碼，以將複數群的資料以及對應的校驗碼寫入至複數個單層單元資料區塊；當完成複數個單層單元資料區塊的寫入時，快閃記憶體模組係執行內部複製，將複數個單層單元資料區塊所儲存之複數群的資料以及對應的校驗碼，依資料的先後順序，依序搬移寫入至至少一多層單元資料區塊。In accordance with an embodiment of the invention, a flash memory device is disclosed. The flash memory device comprises a flash memory module and a flash memory controller, the flash memory module comprises a plurality of single layer unit data blocks and at least one multi-level unit data block, flash memory The controller has a plurality of channels respectively connected to the flash memory module, and the flash memory controller classifies a piece of data to be written into a plurality of groups of data, and the flash memory controller respectively performs single layer unit data writing. Invoking and executing a similar error-correcting disk array error correction encoding operation generates a corresponding check code to write the complex group data and the corresponding check code to a plurality of single-layer unit data blocks; when the complex number is completed When writing a single-layer unit data block, the flash memory module performs internal copying, and the data of the complex group and the corresponding check code stored in the plurality of single-layer unit data blocks are determined according to the data. In the order, the writing is sequentially performed to at least one multi-level unit data block.

根據本發明一實施例，另揭露了一種快閃記憶體儲存管理方法。該方法包含有：提供一快閃記憶體模組，該快閃記憶體模組包括複數個單層單元資料區塊以及至少一多層單元資料區塊；將一筆欲寫入之資料分類為複數群的資料；分別執行單層單元資料寫入以及執行一類似容錯式磁碟陣列的錯誤更正編碼操作產生一對應的校驗碼，以將複數群的資料以及該對應的校驗碼寫入至該複數個單層單元資料區塊；當完成該複數個單層單元資料區塊的寫入時，執行一內部複製，將該複數個單層單元資料區塊所儲存之該複數群的資料以及該對應的校驗碼，依資料的先後順序，依序搬移寫入至該至少一多層單元資料區塊。According to an embodiment of the invention, a flash memory storage management method is further disclosed. The method includes: providing a flash memory module, the flash memory module comprising a plurality of single layer unit data blocks and at least one multi-level unit data block; classifying a piece of data to be written into a plurality Group data; respectively performing single-layer unit data writing and performing an error correction encoding operation similar to a fault-tolerant disk array to generate a corresponding check code to write the data of the complex group and the corresponding check code to The plurality of single-layer unit data blocks; when the writing of the plurality of single-layer unit data blocks is completed, performing an internal copy, storing the data of the plurality of groups stored in the plurality of single-layer unit data blocks and The corresponding check code is sequentially transferred to the at least one multi-level unit data block according to the order of the data.

請參照第1圖，其係為本發明一實施例之快閃記憶體裝置100的裝置示意圖。快閃記憶體裝置100包含快閃記憶體模組105及快閃記憶體控制器110，快閃記憶體模組105為一個具有二維平面架構的快閃記憶體模組；然此並非本案的限制。快閃記憶體模組105包含多個快閃記憶體晶片（並未繪示於第1圖），每一快閃記憶體晶片包括多個單層單元資料區塊（single-level cell (SLC) block）及多個多層單元資料區塊（multiple-lelve-cell block），單層單元資料區塊的每一單元可儲存2位元的資料，多層單元資料區塊的每一單元可儲存2N 位元的資料，N大於或等於2並為整數，多層單元資料區塊例如包括有MLC區塊（multi-level cell block）之單元可儲存22 位元的資料、TLC區塊（triple-level cell block）之單元可儲存23 元的資料、QLC區塊（quad-level cell block）之單元可儲存24 位元的資料，依此類推。Please refer to FIG. 1 , which is a schematic diagram of a device of a flash memory device 100 according to an embodiment of the invention. The flash memory device 100 includes a flash memory module 105 and a flash memory controller 110. The flash memory module 105 is a flash memory module having a two-dimensional planar architecture; limit. The flash memory module 105 includes a plurality of flash memory chips (not shown in FIG. 1), and each of the flash memory chips includes a plurality of single-level cell (SLC) blocks. Block) and a plurality of multi-lele-cell blocks, each unit of the single-layer unit data block can store 2 bits of data, and each unit of the multi-level unit data block can store 2 N The data of the bit, N is greater than or equal to 2 and is an integer. The multi-level cell data block, for example, includes a unit with a multi-level cell block, and can store 22 bits of data and a TLC block (triple-level). The unit of the cell block can store 23 yuan of data, the unit of the QLC block (quad-level cell block) can store 24 bits of data, and so on.

快閃記憶體控制器110可通過複數條通道連接至快閃記憶體模組105，使可利用不同條通道同時寫入資料至不同的快閃記憶體晶片，增加寫入效率，快閃記憶體控制器110包括一錯誤更正碼編碼電路1101及一校驗碼（parity check code）緩衝器1102，錯誤更正碼編碼電路1101用以對資料進行以一錯誤更正碼編碼操作，例如本案之實施例中包括里德-所羅門碼（Reed-solomon codes）的編碼操作及/或互斥或（exclusive-OR，XOR）運算的編碼操作，以產生相對應的校驗碼，校驗碼緩衝器1102用以暫存所產生之相對應的校驗碼，而快閃記憶體控制器110係用以一類似容錯式磁碟陣列（Redundant Array of Independent Disks, RAID）的資料管理機制，將一筆資料寫入不同的快閃記憶體晶片，降低出錯率，並在寫入資料至單層單元資料區塊時即同時考慮不同編碼操作的校驗碼於單層單元資料區塊的儲位位置以及於TLC資料區塊的儲存位置，令在寫入資料至單層單元資料區塊時可更正資料出錯以及後續快閃記憶體模組105通過內部複製（internal copy）操作由單層單元區塊將資料複製搬移至TLC資料區塊時亦可更正資料出錯。The flash memory controller 110 can be connected to the flash memory module 105 through a plurality of channels, so that data can be simultaneously written to different flash memory chips by using different channels, thereby increasing writing efficiency and flash memory. The controller 110 includes an error correction code encoding circuit 1101 and a parity check code buffer 1102. The error correction code encoding circuit 1101 is configured to perform an error correction code encoding operation on the data, for example, in the embodiment of the present invention. Encoding operations including Reed-solomon codes and/or encoding operations of exclusive-OR (XOR) operations to generate corresponding check codes, used by check code buffer 1102 The corresponding verification code generated by the temporary storage, and the flash memory controller 110 is used for a similar data management mechanism of a Redundant Array of Independent Disks (RAID) to write a piece of data into different The flash memory chip reduces the error rate, and simultaneously considers the check code of different encoding operations in the storage location of the single-layer unit data block when writing the data to the single-layer unit data block. And the storage location of the TLC data block, so that when the data is written to the single-layer unit data block, the data error can be corrected and the subsequent flash memory module 105 is operated by the internal copy operation from the single-layer unit area. When the block moves the data copy to the TLC data block, the data error can also be corrected.

實作上，為求資料寫入的效率及降低出錯率，快閃記憶體模組105包括多個通道（本案之實施例為2個通道，但非限定），當一通道執行某一資料頁（page）的寫入時，可採用另一通道來執行另一資料頁的寫入，而不需要等候該通道，每一通道在快閃記憶體控制器110中有各自的序列傳輸器（sequencer）且均包含了多個快閃記憶體晶片（本案之實施例為2個晶片，但非限定），使得一個通道可同時對多個快閃記憶體晶片執行不同資料頁的寫入，而不需要等候其中一個晶片，此外，每一快閃記憶體晶片可具有一折疊設計（folded）而具有不同的兩個平面（plane），令一個快閃記憶體晶片在資料寫入時可同時利用不同兩平面上的兩個資料區塊來執行不同資料頁的寫入，而不需要等候其中某一個資料區塊。因此，快閃記憶體模組105的一個超級資料區塊（super block）係由多個通道的多個快閃記憶體晶片的多個資料頁所組成。上述的快閃記憶體控制器110即係將資料以超級資料區塊為單位來進行寫入，先將資料寫入至快閃記憶體模組105內的單層單元資料區塊，由單層單元資料區塊緩衝，後續再從該些單層單元資料區塊將資料複製搬移至TLC資料區塊內。另外，應注意的是，其他實施例中，每一快閃記憶體晶片可不具有折疊設計，亦即，一個快閃記憶體晶片在資料寫入時係利用一資料區塊來執行一資料頁的寫入，其他資料頁的寫入需要等候時間。In practice, in order to improve the efficiency of data writing and reduce the error rate, the flash memory module 105 includes a plurality of channels (in this embodiment, two channels, but not limited), when a channel executes a certain data page. When writing (page), another channel can be used to perform writing of another data page without waiting for the channel, and each channel has its own sequence transmitter in the flash memory controller 110 (sequencer) And each includes a plurality of flash memory chips (in this embodiment, two wafers, but not limited), so that one channel can simultaneously write different data pages to multiple flash memory chips without It is necessary to wait for one of the wafers. In addition, each flash memory chip can have a folded design and have two different planes, so that one flash memory chip can simultaneously utilize different data when writing. Two data blocks on two planes are used to perform writing of different data pages without waiting for one of the data blocks. Therefore, a super block of the flash memory module 105 is composed of a plurality of data pages of a plurality of flash memory chips of a plurality of channels. The above flash memory controller 110 writes the data in units of super data blocks, and first writes the data to the single layer unit data block in the flash memory module 105, and the single layer The unit data block buffer, and then copy and copy the data from the single layer unit data block to the TLC data block. In addition, it should be noted that in other embodiments, each flash memory chip may not have a folding design, that is, a flash memory chip uses a data block to execute a data page when data is written. Write, waiting for the writing of other data pages.

就資料寫入的流程而言，一筆資料會先被快閃記憶體控制器110寫入至多個單層單元資料區塊1051A~1051C，之後再從該些單層單元資料區塊1051A~1051C搬移至多層單元資料區塊1052，例如，在本實施例，係以TLC單元為架構的多層資料區塊為例，TLC單元可儲存23 位元的資訊，也就是說，三個單層單元資料區塊（以下簡稱為SLC資料區塊）1051A~1051C的資料會被寫入至一個TLC資料區塊1052，據此，考量到需要共同對SLC資料區塊1051A~1051C的寫入以及TLC資料區塊1052的寫入進行錯誤更正的保護，快閃記憶體控制器110係將一筆資料分類為三個群（group）的資料，應注意的是，如果係以MLC單元為架構的多層資料區塊為例，由於MLC單元可儲存22 位元的資訊，所以快閃記憶體控制器110會將該筆資料分類為兩個群的資料，而如果係以QLC單元為架構的多層資料區塊為例，由於QLC單元可儲存24 位元的資訊，所以快閃記憶體控制器110會將該筆資料分類為四個群的資料；依此類推。也就是說，當上述多層單元資料區塊1052之單元可儲存具有2N 位元的資訊，N大於等於2並為整數，單層單元資料區塊的數目會設計為N個SLC資料區塊，快閃記憶體控制器110係將該筆欲寫入之資料分類為N個群的資料，以分別寫入至N個SLC資料區塊。In the process of data writing, a piece of data is first written by the flash memory controller 110 to a plurality of single-layer unit data blocks 1051A to 1051C, and then moved from the single-layer unit data blocks 1051A to 1051C. To the multi-level cell data block 1052, for example, in the embodiment, a multi-layer data block with a TLC unit as an example is taken as an example, and the TLC unit can store 23- bit information, that is, three single-layer unit data. The blocks (hereinafter referred to as SLC data blocks) 1051A~1051C will be written to a TLC data block 1052. Based on this, it is considered that the writing of the SLC data blocks 1051A~1051C and the TLC data area are required. The writing of block 1052 is protected by error correction. The flash memory controller 110 classifies a piece of data into three groups of data. It should be noted that if the MLC unit is used as a multi-layer data block. for example, due to the MLC unit can store 22 bits of information, the flash memory controller 110 of the series will be classified as two groups of data, and if the department to QLC unit data block is a multi-layer architecture For example, because the QLC unit can be stored 2 4- bit information, so the flash memory controller 110 will classify the data into four groups of data; and so on. That is to say, when the unit of the multi-layer unit data block 1052 can store information with 2 N bits, N is greater than or equal to 2 and is an integer, and the number of single-layer unit data blocks is designed as N SLC data blocks. The flash memory controller 110 classifies the data to be written into N groups of data to be respectively written to the N SLC data blocks.

在本實施例中，當快閃記憶體控制器110將該筆資料分類為三個群的資料後，會接著執行第一次的資料寫入（SLC program）將第一群的資料寫入上述第一個SLC資料區塊1051A以及利用錯誤更正碼編碼電路1101產生對應的校驗碼並寫入至第一個SLC資料區塊1051A中，如此便完成一次SLC資料區塊的寫入操作，之後快閃記憶體控制器110接著執行第二次的資料寫入（SLC program）將第二群的資料寫入上述第二個SLC資料區塊1051B以及利用錯誤更正碼編碼電路1101產生對應的校驗碼並寫入至第二個SLC資料區塊1051B中，如此便完成第二次的SLC資料區塊的寫入操作，以及快閃記憶體控制器110接著執行第三次的資料寫入（SLC program）將第三群的資料寫入上述第三個SLC資料區塊1051C以及利用錯誤更正碼編碼電路1101產生對應的校驗碼並寫入至第三個SLC資料區塊1051C中，如此便完成第三次的SLC資料區塊的寫入操作。In this embodiment, after the flash memory controller 110 classifies the pen data into three groups of data, the first data writing (SLC program) is executed to write the first group of data into the above. The first SLC data block 1051A and the error correction code encoding circuit 1101 generate a corresponding check code and write it into the first SLC data block 1051A, thus completing the writing operation of the SLC data block, and then The flash memory controller 110 then performs a second data write (SLC program) to write the second group of data into the second SLC data block 1051B and generate a corresponding check using the error correction code encoding circuit 1101. The code is written into the second SLC data block 1051B, so that the second SLC data block write operation is completed, and the flash memory controller 110 then performs the third data write (SLC). The third group of data is written into the third SLC data block 1051C and the corresponding check code is generated by the error correction code encoding circuit 1101 and written into the third SLC data block 1051C, thus completing Third SLC Feed block write operation.

當快閃記憶體控制器110執行某一次的資料寫入（SLC program）將某一群的資料寫入某一個SLC資料區塊時，或該次資料寫入之後，快閃記憶體控制器110會檢測是否出錯，如果資料有錯，例如發生某一SLC資料區塊寫入的寫入失敗（program fail）、一字元線斷路（one word line open）及/或兩字元線短路（two word line short）的情況，快閃記憶體控制器110會利用錯誤更正碼編碼電路1101於該次資料寫入時所產生之對應校驗碼來更正上述的錯誤。When the flash memory controller 110 performs a certain SLC program to write a certain group of data into a certain SLC data block, or after the data is written, the flash memory controller 110 will Check if there is an error, if the data is wrong, for example, a write failure of a certain SLC data block write, one word line open and/or a two word line short circuit (two word In the case of line short, the flash memory controller 110 corrects the above error by using the corresponding correction code generated by the error correction code encoding circuit 1101 at the time of writing the data.

當前述三個群的資料均寫入至三個SLC資料區塊時1051A~1051C或者某一個SLC資料區塊的資料寫入已完成時，快閃記憶體模組105係執行內部複製，從該些SLC資料區塊1051A~1051C或某一個SLC資料區塊中將三個群的資料或某一群的資料複製搬移並依三個群的資料順序執行資料寫入（TLC program）至一個TLC資料區塊1052（亦即前述的超級資料區塊），TLC資料區塊1052係由不同通道的不同快閃記憶體晶片的字元線的資料頁所組成，例如，TLC資料區塊1052的一字元線的一資料頁包括有上資料頁（upper page）、中間資料頁（middle page）以及下資料頁（lower page），快閃記憶體模組105的內部複製係依順序例如將一SLC資料區塊的第N條字元線上的多個資料頁寫入至TLC資料區塊1052之一字元線的多個上資料頁，將該SLC資料區塊的第N+1條字元線上的多個資料頁寫入至TLC資料區塊1052之同一字元線的多個中間資料頁，以及將該SLC資料區塊的第N+2條字元線上的多個資料頁寫入至TLC資料區塊1052之同一字元線的多個下資料頁。待所有三個群的資料均寫入至TLC資料區塊1052，如此便完成了該超級資料區塊的寫入操作。When the data of the above three groups are written into the three SLC data blocks, the data is written in 1051A~1051C or one of the SLC data blocks is completed, the flash memory module 105 performs internal copying. In the SLC data blocks 1051A~1051C or one of the SLC data blocks, the data of the three groups or the data of a certain group are copied and moved, and the TLC program is executed in the order of the data of the three groups to a TLC data area. Block 1052 (that is, the aforementioned super data block), the TLC data block 1052 is composed of data pages of word lines of different flash memory chips of different channels, for example, a character of the TLC data block 1052. A data page of the line includes an upper page, a middle page, and a lower page. The internal copy of the flash memory module 105 is, for example, an SLC data area. A plurality of data pages on the Nth character line of the block are written to a plurality of upper data pages of one of the character lines of the TLC data block 1052, and the number of the N+1th character lines of the SLC data block is increased. Data pages are written to the same word line of TLC data block 1052 A plurality of intermediate data pages, and a plurality of data pages on the N+2th word line of the SLC data block are written to the plurality of lower data pages of the same word line of the TLC data block 1052. The data of all three groups is written to the TLC data block 1052, thus completing the writing operation of the super data block.

應注意的是，為了令內部複製易於實現、符合TLC資料區塊1052的亂數種子數（randomizer seed）規則要求、以及同時考量錯誤更正編碼能力以降低出錯率，該內部複製操作係只是依資料的順序將資料搬移至TLC資料區塊1052的多條字元線的上、中、下資料頁的位置，而由快閃記憶體控制器110於寫入不同群的資料以及對應產生之校驗碼至該些SLC資料區塊1051A~1051C時，同時依據TLC資料區塊的亂數種子數規則要求以及考量錯誤更正編碼之校驗碼的寫入儲存位置，令錯誤更正碼編碼電路1101的錯誤更正編碼能力可於執行一次SLC資料區塊的寫入操作時更正SLC資料區塊的寫入失敗、一字元線斷路及/或兩字元線短路所造成的錯誤，以及可於執行該超級資料區塊的寫入操作時更正TLC資料區塊1052的寫入失敗、一字元線斷路及/或兩字元線短路所造成的錯誤。It should be noted that in order to make the internal copy easy to implement, meet the randomizer seed rule requirements of the TLC data block 1052, and simultaneously consider the error correction coding ability to reduce the error rate, the internal copy operation is based only on the data. The order moves the data to the positions of the upper, middle and lower data pages of the plurality of character lines of the TLC data block 1052, and the flash memory controller 110 writes the data of the different groups and the corresponding generated checksum. When the code is sent to the SLC data blocks 1051A to 1051C, the error correction code encoding circuit 1101 is incorrect according to the random number seed number rule requirement of the TLC data block and the write storage position of the check code of the error correction code. Correcting the encoding capability can correct the write failure of the SLC data block, the disconnection of a word line and/or the short of the two word lines when performing a write operation of the SLC data block, and can execute the super The write operation of the data block corrects the error caused by the write failure of the TLC data block 1052, the disconnection of a word line, and/or the short of the two word lines.

此外，如果快閃記憶體模組105進行記憶體垃圾回收（garbage collection），快閃記憶體控制器110係通過外部讀取，從該些SLC資料區塊1051A~1051C中讀取出資料並重新進行錯誤更正的編碼來執行資料寫入（SLC program），及/或從TLC資料區塊1052中讀取出資料並重新進行錯誤更正的編碼來執行資料寫入（SLC program）。此外，如果寫入資料（SLC program）至一SLC資料區塊且突然發生關機時，快閃記憶體控制器110係從該SLC資料區塊讀回資料並重新進行錯誤更正的編碼、寫入資料（SLC program）至另一新的SLC資料區塊。此外，如果寫入資料（TLC program）至TLC資料區塊1052且突然發生關機時，快閃記憶體模組105係放棄該TLC資料區塊1052中目前所儲存之資料，並從該些SLC資料區塊1051A~1051C，通過內部複製重新將對應的資料執行TLC資料寫入（TLC program）至該TLC資料區塊1052。In addition, if the flash memory module 105 performs a garbage collection, the flash memory controller 110 reads the data from the SLC data blocks 1051A to 1051C and re-reads it by external reading. The error correction is performed to perform a data write (SLC program), and/or the data is read from the TLC data block 1052 and the error correction code is re-executed to perform a data write (SLC program). In addition, if the SLC program is written to an SLC data block and a shutdown occurs suddenly, the flash memory controller 110 reads back the data from the SLC data block and rewrites the error correction code and writes the data. (SLC program) to another new SLC data block. In addition, if the TLC program is written to the TLC data block 1052 and the power is suddenly turned off, the flash memory module 105 discards the data currently stored in the TLC data block 1052 and extracts the data from the SLC data. The blocks 1051A to 1051C re-send the corresponding material execution TLC data to the TLC data block 1052 by internal copying.

請參照第2圖，第2圖為本發明第一實施例第1圖所示之快閃記憶體控制器110執行SLC資料寫入（SLC program）將某一群之資料寫入至快閃記憶體模組105內之一SLC資料區塊以執行一次SLC資料區塊寫入操作的示意圖。快閃記憶體控制器110之錯誤更正碼編碼電路1101係對資料執行以一類似容錯式磁碟陣列的里德-所羅門（Reed Solomon，RS）編碼操作，產生相對應的校驗碼，而校驗碼緩衝器1102用以暫存所產生之相對應的校驗碼。Referring to FIG. 2, FIG. 2 is a diagram showing a flash memory controller 110 shown in FIG. 1 of the first embodiment of the present invention, which performs SLC program writing to write data of a certain group to a flash memory. A schematic diagram of one of the SLC data blocks in the module 105 to perform a SLC data block write operation. The error correction code encoding circuit 1101 of the flash memory controller 110 performs a Reed Solomon (RS) encoding operation on a data-like array with a fault-tolerant disk array to generate a corresponding check code. The code check buffer 1102 is used to temporarily store the generated check code.

快閃記憶體模組105內包括有兩個通道，並包括兩個快閃記憶體晶片及每一晶片的兩組區塊有兩不同平面，為求寫入效率，快閃記憶體控制器110係通過兩個通道寫入資料至快閃記憶體模組105內的兩個快閃記憶體晶片的兩區塊。如第2圖之實施方式所示，一SLC資料區塊包括有例如128條字元線（分別由WL0至WL127表示之），該SLC資料區塊可以是由一個SLC資料區塊或是一組SLC子資料區塊所組成，視SLC資料區塊的定義而變，為方便描述，在實施例係將包括128條字元線視為一個SLC資料區塊的大小，其中每一條字元線包括有例如8個資料頁，以該SLC資料區塊的第一條字元線WL0為例，快閃記憶體控制器110藉由通道CH0及摺疊平面PLN0、PLN1將資料頁P1、P2寫入至快閃記憶體晶片CE0，接著藉由同一通道CH0及摺疊平面PLN0、PLN1將資料頁P3、P4寫入至另一快閃記憶體晶片CE1，接著由另一通道CH1及摺疊平面PLN0、PLN1將資料頁P5、P6寫入至快閃記憶體晶片CE0，接著藉由通道CH1及摺疊平面PLN0、PLN1將資料頁P7、P8寫入至快閃記憶體晶片CE1。其他則依此類推。The flash memory module 105 includes two channels, and includes two flash memory chips and two sets of blocks of each chip having two different planes. For writing efficiency, the flash memory controller 110 is required. Two blocks of data are written to the two flash memory chips in the flash memory module 105 through two channels. As shown in the embodiment of FIG. 2, an SLC data block includes, for example, 128 word lines (represented by WL0 to WL127, respectively), and the SLC data block may be an SLC data block or a group. The SLC sub-data block is formed according to the definition of the SLC data block. For convenience of description, in the embodiment, 128 word lines are included as the size of one SLC data block, wherein each word line includes For example, there are 8 data pages. Taking the first character line WL0 of the SLC data block as an example, the flash memory controller 110 writes the data pages P1 and P2 to the channel CH0 and the folding planes PLN0 and PLN1. Flash memory chip CE0, then data pages P3, P4 are written to another flash memory chip CE1 by the same channel CH0 and folding planes PLN0, PLN1, and then by another channel CH1 and folding planes PLN0, PLN1 The data pages P5 and P6 are written to the flash memory chip CE0, and then the material pages P7 and P8 are written to the flash memory chip CE1 by the channel CH1 and the folding planes PLN0 and PLN1. Others are like this.

快閃記憶體控制器110係將一個SLC資料區塊的多個字元線WL0至WL127依順序將每M條字元線編類為一組，M為大於或等於2的正整數，M例如為3，例如字元線WL0~WL2為第一組，字元線WL3~WL5為第二組，字元線WL6~WL8為第三組，字元線WL9~WL11為第四組…，字元線WL120~WL122為倒數第三組，字元線WL123~WL125為倒數第二組，最後一組字元線為WL126、WL127，其中第一、第三、第五組…等等的字元線為奇數組字元線，而第二、第四、第六組…等等的字元線為偶數組字元線，快閃記憶體控制器110每次寫入一組字元線之資料（包括三條字元線之資料），係利用錯誤更正碼編碼電路1101對於該組字元線之資料執行錯誤更正編碼，並將所產生之對應之部分的校驗碼（partial parity code）輸出至校驗碼緩衝器1102，以暫存部分的校驗碼。The flash memory controller 110 classifies each of the M word lines into a group by a plurality of word lines WL0 to WL127 of one SLC data block, and M is a positive integer greater than or equal to 2, for example, M 3, for example, the word lines WL0 WL WL2 are the first group, the word lines WL3 WL WL5 are the second group, the word lines WL6 WL WL8 are the third group, and the word lines WL9 WL WL11 are the fourth group... The meta-line WL120~WL122 is the third last group, the word line WL123~WL125 is the penultimate group, and the last group of character lines are WL126, WL127, among which the first, third, fifth group, etc. The line is an odd array word line, and the word lines of the second, fourth, sixth group, etc. are even array word lines, and the flash memory controller 110 writes a set of word lines each time. (including the data of three character lines), the error correction code encoding circuit 1101 performs error correction coding on the data of the group of character lines, and outputs the generated partial parity code to the corresponding portion. The check code buffer 1102 is used to temporarily store the check code of the portion.

校驗碼緩衝器1102於暫存部分的校驗碼時係將奇數組字元線資料所對應之部分的校驗碼儲存於一第一緩衝區1102A，將偶數組字元線資料所對應之部分的校驗碼儲存於一第二緩衝區1102B，舉例來說，當寫入字元線WL0~WL2之資料頁P1~P24時，錯誤更正碼編碼電路1101係對於資料頁P1~P24執行錯誤更正編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第一緩衝區1102A；接著當寫入字元線WL3~WL5之資料頁P1~P24， 錯誤更正碼編碼電路1101係對於資料頁P1~P24執行錯誤更正編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第二緩衝區1102B；接著錯誤當寫入字元線WL6~WL8之資料頁P25~P48，錯誤更正碼編碼電路1101係對於資料頁P25~P48執行錯誤更正編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第一緩衝區1102A；後續的資料頁寫入與編碼操作係依此類推…；之後，當寫入字元線WL120~WL122之資料頁，錯誤更正碼編碼電路1101係對於字元線WL120~WL122之資料頁執行編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第一緩衝區1102A。The check code buffer 1102 stores the check code of the portion corresponding to the odd array word line data in a first buffer 1102A in the check code of the temporary storage portion, and corresponds to the even array word line data. The part of the check code is stored in a second buffer 1102B. For example, when the data pages P1 to P24 of the word lines WL0 WL WL2 are written, the error correction code encoding circuit 1101 performs an error on the data pages P1 to P24. Correcting the code, and outputting the generated check code of the corresponding part to the check code buffer 1102, temporarily storing it in the first buffer 1102A; then writing to the data pages P1~P24 of the word line WL3~WL5, The error correction code encoding circuit 1101 performs error correction coding on the data pages P1 to P24, and outputs the generated partial verification code to the check code buffer 1102, temporarily stored in the second buffer 1102B; When writing the data pages P25~P48 of the word line WL6~WL8, the error correction code encoding circuit 1101 performs error correction coding on the data pages P25~P48, and outputs the generated check code of the corresponding part to the checksum. The code buffer 1102 is temporarily stored in the first buffer 1102A; The data page writing and encoding operations are based on the following... After that, when writing the data pages of the word lines WL120 to WL122, the error correction code encoding circuit 1101 performs encoding on the data pages of the word lines WL120 to WL122, and The generated check code of the corresponding portion is output to the check code buffer 1102 and temporarily stored in the first buffer 1102A.

接著，快閃記憶體控制器110於寫入偶數組字元線的最後一組字元線（WL123~WL125）時，除了執行資料寫入（SLC program）與對應的錯誤更正編碼外，亦將第二緩衝區1102B所暫存之所有偶數組字元線之資料的部分校驗碼讀回，並將偶數組字元線之資料所對應之所有校驗碼寫入至最後一組偶數組字元線之最後一條字元線WL125的資料頁，例如最後3個資料頁（標記為205），以儲存偶數組字元線之資料所對應的里德-所羅門校驗碼。Then, when the flash memory controller 110 writes the last set of word lines (WL123~WL125) of the even array word line, in addition to performing the SLC program and the corresponding error correction code, The partial check code of the data of all the even array word lines temporarily stored in the second buffer 1102B is read back, and all the check codes corresponding to the data of the even array word line are written to the last set of even array words. The data page of the last word line WL125 of the line, such as the last three data pages (labeled 205), stores the Reed-Solomon check code corresponding to the data of the even array word line.

另外，對於寫入最後一組奇數組字元線的最後一條字元線WL127時，快閃記憶體控制器110除了執行資料寫入（SLC program）與對應的錯誤更正編碼外，會將第一緩衝區1102A所暫存之所有奇數組字元線之資料的部分校驗碼讀回，並將奇數組字元線之資料所對應之所有校驗碼寫入至最後一組奇數組字元線之最後一條字元線WL127的資料頁，例如最後3個資料頁（標記為210），以儲存奇數組字元線之資料所對應的里德-所羅門校驗碼。如此便完成一次SLC資料區塊的寫入。因此，就里德-所羅門編碼操作而言，奇數組字元線之資料所對應的校驗碼係儲存於最後一組奇數組字元線之最後一條字元線WL127的最後複數張資料頁的位置，而偶數組字元線之資料所對應的校驗碼係儲存於最後一組偶數組字元線之最後一條字元線WL125的最後複數張資料頁的位置。In addition, for writing the last word line WL127 of the last set of odd array word lines, the flash memory controller 110 will perform the first in addition to the SLC program and the corresponding error correction code. The partial check code of the data of all the odd array word lines temporarily stored in the buffer 1102A is read back, and all the check codes corresponding to the data of the odd array word line are written to the last set of odd array word lines. The data page of the last word line WL127, for example, the last three data pages (labeled 210), stores the Reed-Solomon check code corresponding to the data of the odd array word line. This completes the writing of the SLC data block. Therefore, in the case of the Reed-Solomon coding operation, the check code corresponding to the data of the odd array word line is stored in the last plurality of data pages of the last word line WL127 of the last set of odd array word lines. The position, and the parity code corresponding to the data of the even array word line is stored at the position of the last plurality of data pages of the last word line WL125 of the last set of even array word lines.

此外，錯誤更正碼編碼電路1101在第2圖所示之實施例所執行的是里德-所羅門編碼操作，可更正發生在SLC資料區塊之任意三個位置之資料頁的出錯，舉例來說，錯誤更正碼編碼電路1101對於字元線WL0~WL2的三條字元線的資料執行錯誤更正編碼並產生相對應的部分校驗碼，如果同一通道的相同晶片的同一摺疊平面的三個資料頁出錯，例如資料頁P1、P9、P17出錯，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將該三個資料頁的錯誤更正。Further, the error correction code encoding circuit 1101 performs the Reed-Solomon encoding operation in the embodiment shown in Fig. 2, and can correct the error of the data page occurring at any three positions of the SLC data block, for example, The error correction code encoding circuit 1101 performs error correction coding on the data of the three word lines of the word lines WL0 WL WL2 and generates corresponding partial check codes, if three data pages of the same folding plane of the same wafer of the same channel If an error occurs, for example, the data pages P1, P9, and P17 are in error, the error correction code encoding circuit 1101 can correct the errors of the three data pages by using the corresponding partial check codes generated.

如果於執行該次SLC資料區塊的寫入時檢測到發生寫入失敗（program fail）的情況，例如以發生機率來說，例如檢測到資料頁P9寫入失敗，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將資料頁P9的錯誤更正。If a program fail occurs when the writing of the SLC data block is performed, for example, in the event of occurrence, for example, the data page P9 is detected to be failed, the error correction code encoding circuit 1101 may The error of the data page P9 is corrected by using the corresponding partial check code generated.

如果於執行該次SLC資料區塊的寫入時檢測到發生一字元線斷路（one word line open）而造成例如資料頁P9錯誤，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將資料頁P9的錯誤更正。If it is detected that a word line open occurs during the writing of the SLC data block, causing, for example, a data page P9 error, the error correction code encoding circuit 1101 can utilize the corresponding portion generated. Check the code and correct the error of the data page P9.

如果於執行該次SLC資料區塊的寫入時檢測到發生兩字元線短路（two word line short）而造成例如資料頁P9、P17均錯誤，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將資料頁P9、P17的錯誤更正。如果發生兩字元線短路而造成例如字元線WL2的資料頁P17與字元線WL3的資料頁P1出錯，錯誤更正碼編碼電路1101可利用一組字元線WL0~WL2的部分校驗碼以及另一組字元線WL3~WL5的部分校驗碼，分別將字元線WL2的資料頁P17與字元線WL3的資料頁P1的錯誤更正。如果發生兩字元線短路而造成例如字元線WL0的資料頁P1、P2錯誤，錯誤更正碼編碼電路1101可利用一組字元線WL0~WL2的部分校驗碼，分別將字元線WL0的資料頁P1、P2的錯誤更正。If it is detected that a two word line short occurs when the writing of the SLC data block is performed, for example, the data pages P9 and P17 are both wrong, the error correction code encoding circuit 1101 can utilize the generated phase. The corresponding partial check code corrects the errors of the data pages P9 and P17. If a two-character line short circuit occurs, causing, for example, the data page P17 of the word line WL2 and the data page P1 of the word line WL3 to be erroneous, the error correction code encoding circuit 1101 can utilize a partial check code of a set of word lines WL0 WL WL2. And a partial check code of another set of word lines WL3 WL WL5 corrects the error of the data page P17 of the word line WL2 and the data page P1 of the word line WL3, respectively. If a two-character line short circuit occurs, causing, for example, the data pages P1, P2 of the word line WL0 to be erroneous, the error correction code encoding circuit 1101 can utilize the partial check codes of the set of word lines WL0 WL WL2 to respectively select the word line WL0. The error correction of the data pages P1 and P2.

因此，無論是在執行SLC資料區塊寫入時發生寫入失敗、一字元線斷路或兩字元線短路所造成的資料頁錯誤，錯誤更正碼編碼電路1101均可對應地更正該些錯誤的資料頁。Therefore, the error correction code encoding circuit 1101 can correct the errors correspondingly due to a data page error caused by a write failure, a word line break, or a two word line short circuit when the SLC data block write is performed. Information page.

請參照第3圖，第3圖為快閃記憶體模組105內之一SLC資料區塊通過內部複製將資料寫入至TLC資料區塊1052的示意圖。如第3圖所示，一SLC資料區塊之一組三條字元線資料係寫入至TLC資料區塊1052之一字元線，對應地形成該字元線之一資料頁的最低有效位LSB、中間有效位CSB及最高有效位MSB的資料，例如SLC資料區塊之字元線資料WL0~WL2寫入至TLC資料區塊1052，作為該TLC資料區塊1052之字元線WL0之最低有效位LSB、中間有效位CSB及最高有效位MSB的資料；SLC資料區塊之字元線資料WL3~WL5寫入至TLC資料區塊1052，作為該TLC資料區塊1052之字元線WL1之最低有效位LSB、中間有效位CSB及最高有效位MSB的資料；SLC資料區塊之字元線資料WL6~WL8寫入至TLC資料區塊1052，作為該TLC資料區塊1052之字元線WL2之最低有效位LSB、中間有效位CSB及最高有效位MSB的資料；也就是說，快閃記憶體模組105的內部複製係將SLC資料區塊之資料依字元線的順序搬移並寫入填入至TLC資料區塊的字元線內。Referring to FIG. 3, FIG. 3 is a schematic diagram of writing an SMC data block in the flash memory module 105 to the TLC data block 1052 by internal copying. As shown in FIG. 3, one set of three word line data of one SLC data block is written to one of the character lines of the TLC data block 1052, correspondingly forming the least significant bit of the data page of one of the word lines. The data of the LSB, the intermediate significant bit CSB and the most significant bit MSB, such as the word line data WL0~WL2 of the SLC data block, are written to the TLC data block 1052 as the lowest of the word line WL0 of the TLC data block 1052. The data of the valid bit LSB, the intermediate valid bit CSB and the most significant bit MSB; the word line data WL3~WL5 of the SLC data block are written to the TLC data block 1052 as the word line WL1 of the TLC data block 1052. The data of the least significant bit LSB, the intermediate significant bit CSB and the most significant bit MSB; the word line data WL6~WL8 of the SLC data block is written to the TLC data block 1052 as the word line WL2 of the TLC data block 1052 The data of the least significant bit LSB, the intermediate effective bit CSB and the most significant bit MSB; that is, the internal copy of the flash memory module 105 moves and writes the data of the SLC data block in the order of the word line. Fill in the word line of the TLC data block.

請參照第4圖，第4圖為本發明第一實施例第1圖所示之快閃記憶體控制器110寫入三個群組之資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C並通過內部複製將資料搬移寫入至TLC資料區塊而形成一個超級資料區塊的示意圖。由於錯誤更正碼編碼電路1101於每次執行SLC資料區塊的寫入時，均把資料分類為奇數組字元線及偶數組字元線兩組，並將對應產生之校驗碼儲存於奇數組字元線之最後一字元線的最後3張資料頁及偶數組字元線之最後一字元線的最後3張資料頁，因此，當執行TLC資料區塊的寫入時，如第4圖所示，第一個群組之資料的奇數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL42的中間有效位CSB的最後三個資料頁（標記為401A），而第一個群組之資料的偶數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL41的最高有效位MSB的最後三個資料頁（標記為401B）；第二個群組之資料的奇數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL85的最低有效位LSB的最後三個資料頁（標記為402A），而第二個群組之資料的偶數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL84的最高有效位MSB的最後三個資料頁（標記為402B）；第三個群組之資料的奇數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL127的最高有效位MSB的最後三個資料頁（標記為403A），而第三個群組之資料的偶數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL127之最低有效位LSB的最後三個資料頁（標記為403B）。Referring to FIG. 4, FIG. 4 is a view showing a flash memory controller 110 shown in FIG. 1 of the first embodiment of the present invention writing data of three groups to a plurality of SLCs in the flash memory module 105. The data blocks 1051A~1051C are internally copied to the TLC data block to form a super data block. Since the error correction code encoding circuit 1101 performs the writing of the SLC data block each time, the data is classified into two groups of an odd array word line and an even array word line, and the corresponding generated check code is stored in the odd The last 3 data pages of the last character line of the last character line of the array word line and the last 3 data pages of the last character line of the even array word line. Therefore, when the writing of the TLC data block is performed, In the figure 4, the corresponding check code of the odd array word line of the data of the first group is stored in the last three data pages of the intermediate valid bit CSB of the character line WL42 of the super block (labeled as 401A). And the corresponding check code of the even array word line of the data of the first group is stored in the last three data pages of the most significant bit MSB of the character line WL41 of the super block (labeled as 401B); The corresponding check code of the odd array word line of the data of the second group is stored in the last three data pages (labeled 402A) of the least significant bit LSB of the character line WL85 of the super block, and the second The corresponding check code of the even array of character lines of the group data is stored in the super block. The last three data pages of the most significant bit MSB of the character line WL84 (labeled as 402B); the corresponding check code of the odd array word line of the third group of data is stored in the character of the super block The last three data pages of the most significant bit MSB of the line WL127 (labeled as 403A), and the corresponding check code of the even array word line of the data of the third group are stored in the character line WL127 of the super block. The last three data pages of the least significant bit LSB (labeled 403B).

如果檢測到兩字元線短路而造成例如該超級區塊之字元線WL0、WL1的兩資料頁（如框線404所標示）發生錯誤，快閃記憶體模組105可利用字元線WL42之中間有效位CSB的最後三張資料頁上儲存之校驗碼401A來更正字元線WL0之資料頁的錯誤，以及利用字元線WL41之最高有效位MSB之最後三張資料頁上儲存之校驗碼401B來更正字元線WL1之資料頁的錯誤。If it is detected that the two word line short circuit causes an error such as two data pages of the character lines WL0, WL1 of the super block (as indicated by the frame line 404), the flash memory module 105 can utilize the word line WL42. The check code 401A stored on the last three data pages of the intermediate valid bit CSB corrects the error of the data page of the word line WL0, and is stored on the last three data pages of the most significant bit MSB of the word line WL41. The check code 401B corrects the error of the data page of the word line WL1.

相同地，如果檢測到兩字元線短路而造成例如該超級區塊之字元線WL43、WL44的兩資料頁（如框線405所標示）發生錯誤，快閃記憶體模組105可利用字元線WL85之最後三張資料頁之最低有效位LSB上儲存之校驗碼402A來更正405所標示之字元線WL43之一資料頁之最低有效位LSB、中間有效位CSB的錯誤以及字元線WL44之一資料頁之最高有效位MSB的錯誤，以及利用字元線WL84之最後三張資料頁之中間有效位CSB上儲存之校驗碼402B，來更正405所標示之字元線WL43一資料頁之最高有效位MSB之錯誤以及字元線WL44一資料頁之最低有效位LSB、中間有效位CSB的錯誤。Similarly, if a two-character line short circuit is detected, for example, two data pages of the character lines WL43, WL44 of the super block (as indicated by the frame line 405) are erroneous, the flash memory module 105 can utilize the word. The check code 402A stored on the least significant bit LSB of the last three data pages of the WL85 to correct the least significant bit LSB of the data page of one of the character lines WL43 indicated by 405, the error of the intermediate valid bit CSB, and the character Correcting the error of the most significant bit MSB of one of the data pages of the line WL44, and correcting the word line WL43 indicated by 405 by using the check code 402B stored on the intermediate effective bit CSB of the last three data pages of the word line WL84. The error of the most significant bit MSB of the data page and the error of the least significant bit LSB and the intermediate valid bit CSB of the data line WL44.

相同地，如果是檢測到兩字元線短路而造成例如該TLC資料區塊之字元線WL125、WL126的兩資料頁（如框線406所標示）發生錯誤，快閃記憶體模組105可利用字元線WL127之最後三張資料頁之最高有效位MSB上儲存之校驗碼403A來更正406所標示之字元線WL125一資料頁之中間有效位CSB、最高有效位MSB的錯誤以及字元線WL126一資料頁之最高有效位MSB的錯誤，以及利用字元線WL127之最後三張資料頁之最低有效位LSB上儲存之校驗碼403B，來更正406所標示之字元線WL125一資料頁之最低有效位LSB之錯誤以及406所標示之字元線WL126一資料頁之中間有效位CSB、最高有效位MSB的錯誤。Similarly, if it is detected that the two word line short circuit causes an error such as two data pages of the character lines WL125 and WL126 of the TLC data block (as indicated by the frame line 406), the flash memory module 105 can Correcting the intermediate valid bit CSB of the data line WL125, the data page of the last valid data bit MSB of the last three data pages of the word line WL127, the error of the intermediate valid bit CSB of the data page, the error of the most significant bit MSB, and the word Correction of the most significant bit MSB of the data line of the WL 126, and the check code 403B stored on the least significant bit LSB of the last three data pages of the word line WL127, to correct the word line WL125 indicated by 406 The error of the least significant bit LSB of the data page and the error of the intermediate valid bit CSB and the most significant bit MSB of the data line WL126 indicated by 406.

如果是檢測到一字元線斷路或寫入失敗而造成超級區塊之任一字元線的任一資料頁發生錯誤（亦即連續任意三張子資料頁出錯），則快閃記憶體模組105均可利用對應儲存之校驗碼來更正連續任意三張子資料頁的錯誤。If it is detected that a word line is broken or the writing fails, and any data page of any character line of the super block is wrong (that is, any three sub-pages are in error), the flash memory module 105 can use the corresponding stored check code to correct the error of any three consecutive sub-data pages.

也就是說，通過快閃記憶體控制器110寫入三個群組之資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C的校驗碼之儲存位置管理設計，當快閃記憶體模組105通過內部複製將該些資料從多個SLC資料區塊1051A~1051C複製寫入至TLC資料區塊而形成一個超級資料區塊時，如果檢測到一字元線斷路、兩字元線短路或寫入失敗的錯誤，均可由多個SLC資料區塊1051A~1051C所儲存之校驗碼來進行更正。That is, the storage location management design of the check codes of the plurality of SLC data blocks 1051A to 1051C written in the flash memory module 105 by the flash memory controller 110 is written. When the flash memory module 105 copies and copies the data from the plurality of SLC data blocks 1051A to 1051C to the TLC data block by internal copy to form a super data block, if a word line disconnection is detected, Errors in shorting or writing failure of two word lines can be corrected by the check codes stored in multiple SLC data blocks 1051A~1051C.

再者，請參照第5圖，第5圖為本發明第二實施例第1圖所示之快閃記憶體控制器110執行資料寫入（SLC program）以寫入一個群之資料至快閃記憶體模組105內之SLC資料區塊以完成一次SLC資料區塊寫入操作的示意圖。快閃記憶體控制器110之錯誤更正碼編碼電路1101係對資料執行以一類似容錯式磁碟陣列的互斥或運算的編碼操作，產生相對應的校驗碼，而校驗碼緩衝器1102用以暫存所產生之相對應的校驗碼。此外，錯誤更正碼編碼電路1101的互斥或運算包括有三個不同的編碼引擎以對SLC資料區塊的不同字元線資料進行互斥或運算；詳細操作內容如下所述。Furthermore, referring to FIG. 5, FIG. 5 is a diagram showing a flash memory controller 110 shown in FIG. 1 of the second embodiment of the present invention for performing a data write (SLC program) to write a group of data to a flash. The SLC data block in the memory module 105 is used to complete a SLC data block write operation. The error correction code encoding circuit 1101 of the flash memory controller 110 performs an encoding operation on the data with a mutual exclusion or operation of a similar fault-tolerant disk array to generate a corresponding check code, and the check code buffer 1102 Used to temporarily store the corresponding check code generated. In addition, the exclusive OR operation of the error correction code encoding circuit 1101 includes three different encoding engines to mutually exclusive or operate on different word line data of the SLC data block; the detailed operation contents are as follows.

快閃記憶體模組105內包括有兩個通道，並包括兩個快閃記憶體晶片，為求寫入效率，快閃記憶體控制器110係通過兩個通道寫入資料至快閃記憶體模組105內的兩個快閃記憶體晶片，將一個SLC資料區塊之資料頁分別程式化至不同快閃記憶體晶片內，快閃記憶體控制器110的一次SLC資料區塊寫入操作所寫入的資料包括128條字元線（分別由WL0至WL127表示之），每一條字元線包括8個資料頁，例如以字元線WL0為例，錯誤更正碼編碼電路1101藉由通道CH0及PLN0、PLN1將資料頁P1、P2寫入至快閃記憶體晶片CE0，接著藉由同一通道CH0及PLN0、PLN1將資料頁P3、P4寫入至另一快閃記憶體晶片CE1，接著由另一通道CH1及PLN0、PLN1將資料頁P5、P6寫入至快閃記憶體晶片CE0，接著藉由通道CH1及PLN0、PLN1將資料頁P7、P8寫入至快閃記憶體晶片CE1。The flash memory module 105 includes two channels and includes two flash memory chips. For writing efficiency, the flash memory controller 110 writes data to the flash memory through two channels. Two flash memory chips in the module 105 respectively program the data pages of one SLC data block into different flash memory chips, and one SLC data block write operation of the flash memory controller 110 The written data includes 128 word lines (represented by WL0 to WL127, respectively), and each word line includes 8 data pages. For example, the word line WL0 is taken as an example, and the error correction code encoding circuit 1101 is used for the channel. CH0 and PLN0, PLN1 write data pages P1 and P2 to the flash memory chip CE0, and then write the data pages P3 and P4 to another flash memory chip CE1 through the same channels CH0 and PLN0, PLN1, and then The data pages P5 and P6 are written to the flash memory chip CE0 by the other channels CH1 and PLN0, PLN1, and then the data pages P7 and P8 are written to the flash memory chip CE1 by the channels CH1 and PLN0, PLN1.

錯誤更正碼編碼電路1101係將一個SLC資料區塊的多個字元線WL0至WL127依順序將每M條字元線編類為一組，M為大於或等於2的正整數，M例如為3，例如字元線WL0~WL2為第一組，字元線WL3~WL5為第二組，字元線WL6~WL8為第三組，字元線WL9~WL11為第四組…，字元線WL120~WL122為倒數第三組，字元線WL123~WL125為倒數第二組，最後一組字元線為WL126、WL127，其中第一、第三、第五組…等等的字元線為奇數組字元線，而第二、第四、第六組…等等的字元線為偶數組字元線，快閃記憶體控制器110每次寫入一組字元線之資料（包括三條字元線之資料），係利用錯誤更正碼編碼電路1101對於該組字元線之資料執行互斥或運算的錯誤更正編碼，並將所產生之對應之部分的校驗碼（partial parity code）輸出至校驗碼緩衝器1102，以暫存部分的校驗碼。The error correction code encoding circuit 1101 classifies each of the M word lines into a group by a plurality of word lines WL0 to WL127 of one SLC data block, and M is a positive integer greater than or equal to 2, for example, 3. For example, the word lines WL0 WL WL2 are the first group, the word lines WL3 WL WL5 are the second group, the word lines WL6 WL WL8 are the third group, and the word lines WL9 WL WL11 are the fourth group. Lines WL120~WL122 are the third last group, word lines WL123~WL125 are the penultimate group, and the last group of word lines are WL126, WL127, among which the first, third, fifth group, etc. An odd array of word lines, and the word lines of the second, fourth, sixth group, etc. are even array word lines, and the flash memory controller 110 writes data of a set of word lines each time ( The data including the three character lines) is performed by using the error correction code encoding circuit 1101 to perform error correction coding of the exclusive or arithmetic operation on the data of the group of character lines, and the corresponding part of the generated check code (partial parity) The code is output to the check code buffer 1102 to temporarily store the check code of the portion.

錯誤更正碼編碼電路1101每次寫入資料至一組三條不同字元線時，係採用三個不同的編碼引擎對於所寫入之資料執行互斥或運算的編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，以暫存部分的校驗碼，而校驗碼緩衝器1102於暫存部分的校驗碼時係將奇數組之字元線資料所對應之部分的校驗碼儲存於一第一緩衝區，將偶數組之字元線資料所對應之部分的校驗碼儲存於一第二緩衝區。When the error correction code encoding circuit 1101 writes data to a set of three different word lines, three different encoding engines are used to perform mutually exclusive or arithmetic coding on the written data, and the corresponding ones are generated. A part of the check code is output to the check code buffer 1102 to temporarily store the check code of the part, and the check code buffer 1102 corresponds to the character line data of the odd array when the check code of the temporary memory part 1102 is used. The check code of the part is stored in a first buffer, and the check code of the part corresponding to the character line data of the even array is stored in a second buffer.

舉例來說，錯誤更正碼編碼電路1101包括有第一編碼引擎、第二編碼引擎及第三編碼引擎，當寫入字元線WL0~WL2之資料頁P1~P24，依序利用第一編碼引擎對於字元線WL0的資料頁P1~P8執行互斥或運算以產生一第一部分校驗碼、利用第二編碼引擎對於字元線WL1的資料頁P9~P16進行互斥或運算以產生一第二部分校驗碼以及利用第三編碼引擎對於字元線WL2的資料頁P17~P24進行互斥或運算以產生一第三部分校驗碼，並將所產生之該些部分校驗碼分別輸出至校驗碼緩衝器1102，暫存於第一緩衝區；接著錯誤更正碼編碼電路1101寫入字元線WL3~WL5之資料頁P1~P24，依序利用第一編碼引擎對於字元線WL3的資料頁P1~P8執行互斥或運算以產生另一第一部分校驗碼、利用第二編碼引擎對於字元線WL4的資料頁P9~P16執行互斥或運算以產生另一第二部分校驗碼以及利用第三編碼引擎對於字元線WL5的資料頁P17~P24執行互斥或運算以產生另一第三部分校驗碼，並將所產生之該些部分校驗碼分別輸出至校驗碼緩衝器1102，暫存於第二緩衝區。For example, the error correction code encoding circuit 1101 includes a first encoding engine, a second encoding engine, and a third encoding engine. When the data pages P1 to P24 of the word lines WL0 WL WL2 are written, the first encoding engine is sequentially used. Performing a mutually exclusive OR operation on the data pages P1 P P8 of the word line WL0 to generate a first partial check code, and using the second encoding engine to mutually exclusive or operate on the data pages P9~P16 of the word line WL1 to generate a first The two-part check code and the data page P17~P24 of the word line WL2 are mutually exclusive ORed by the third encoding engine to generate a third partial check code, and the generated partial check codes are respectively output. The check code buffer 1102 is temporarily stored in the first buffer; then the error correction code encoding circuit 1101 writes the data pages P1 P P24 of the word lines WL3 WL WL5, and sequentially uses the first encoding engine for the word line WL3. The data pages P1~P8 perform a mutual exclusion operation to generate another first partial check code, and perform a mutual exclusion operation on the data pages P9~P16 of the word line WL4 by the second encoding engine to generate another second partial calibration. Code verification and use of the third encoding engine for word line WL5 The data pages P17~P24 perform a mutual exclusion operation to generate another third partial check code, and output the generated partial check codes to the check code buffer 1102, temporarily stored in the second buffer. .

後續的資料頁寫入與編碼操作係依此類推…，也就是說，對於一組奇數組字元線的第一條字元線的資料、第二條字元線的資料、第三條字元線的資料以及對於一組偶數組字元線的第一條字元線的資料、第二條字元線的資料、第三條字元線的資料，均分別執行不同次的互斥或運算，產生相對應的校驗碼。之後為了寫入該些對應的校驗碼於SLC資料區塊的適當儲存位置，錯誤更正碼編碼電路1101在寫入最後6條字元線WL122~WL127之資料頁時，係將該些相對應的校驗碼寫入於最後6條字元線WL122~WL127之最後一張資料頁（如第5圖之長方形斜線框所示），例如，在寫入字元線WL122之資料頁時，字元線WL122為一組奇數組字元線的第三條字元線，錯誤更正碼編碼電路1101係於字元線WL122的最後一張資料頁中寫入所有奇數組字元線中所有第三條字元線之資料所對應的校驗碼（亦即奇數組字元線中由第三編碼引擎所產生之所有第三部分校驗碼），而在寫入字元線WL123之資料頁時，字元線WL123為最後一組偶數組字元線的第一條字元線，錯誤更正碼編碼電路1101係於字元線WL123的最後一張資料頁中寫入所有偶數組字元線中所有第一條字元線之資料所對應的校驗碼（亦即偶數組字元線中由第一編碼引擎所產生之所有第一部分校驗碼），而在寫入字元線WL124之資料頁時，字元線WL124為最後一組偶數組字元線的第二條字元線，錯誤更正碼編碼電路1101係於字元線WL124的最後一張資料頁中寫入所有偶數組字元線中所有第二條字元線之資料所對應的校驗碼（亦即偶數組字元線中由第二編碼引擎所產生之所有第二部分校驗碼），而在寫入字元線WL125之資料頁時，字元線WL125為最後一組偶數組字元線的第三條字元線，錯誤更正碼編碼電路1101係於字元線WL125的最後一張資料頁中寫入所有偶數組字元線中所有第三條字元線之資料所對應的校驗碼（亦即偶數組字元線中由第三編碼引擎所產生之所有第三部分校驗碼），而在寫入字元線WL126之資料頁時，字元線WL126為最後一組奇數組字元線的第一條字元線，錯誤更正碼編碼電路1101係於字元線WL126的最後一張資料頁中寫入所有奇數組字元線中所有第一條字元線之資料所對應的校驗碼（亦即奇數組字元線中由第一編碼引擎所產生之所有第一部分校驗碼），而在寫入字元線WL127之資料頁時，字元線WL127為最後一組奇數組字元線的第二條字元線，錯誤更正碼編碼電路1101係於字元線WL127的最後一張資料頁中寫入所有奇數組字元線中所有第二條字元線之資料所對應的校驗碼（亦即奇數組字元線中由第二編碼引擎所產生之所有第二部分校驗碼）。如此便完成一次SLC資料區塊的寫入。Subsequent data page writing and encoding operations are based on the following, that is, the data of the first character line, the data of the second character line, and the third word for a set of odd array word lines. The data of the meta-line and the data of the first character line, the data of the second character line, and the data of the third character line of a set of even-array character lines are respectively executed for different times of mutual exclusion or The operation produces a corresponding check code. Then, in order to write the corresponding check code to the appropriate storage location of the SLC data block, the error correction code encoding circuit 1101 writes the corresponding data pages of the last six word lines WL122 to WL127. The check code is written in the last data page of the last six word lines WL122~WL127 (as shown by the rectangular slash box in FIG. 5), for example, when writing the data page of the word line WL122, the word The element line WL122 is a third word line of a set of odd array word lines, and the error correction code encoding circuit 1101 writes all the third lines in all the odd array word lines in the last data page of the word line WL122. The check code corresponding to the data of the word line (that is, all the third part check codes generated by the third encoding engine in the odd array word line), and when writing the data page of the word line WL123 The word line WL123 is the first word line of the last set of even array word lines, and the error correction code encoding circuit 1101 is written in all the even array word lines in the last data page of the word line WL123. The check code corresponding to the data of all the first character lines (that is, the even array of word lines) All first partial check codes generated by the first encoding engine, and when writing the data pages of the word line WL124, the word line WL124 is the second character line of the last set of even array word lines. The error correction code encoding circuit 1101 writes the check code corresponding to the data of all the second character lines in all the even array word lines in the last data page of the word line WL124 (that is, the even array character) All second partial check codes generated by the second encoding engine in the line, and when writing the data page of the word line WL125, the word line WL125 is the third word of the last set of even array word lines The error correction code encoding circuit 1101 writes the check code corresponding to the data of all the third character lines in all the even array word lines in the last data page of the word line WL125 (ie, even number) All third partial check codes generated by the third encoding engine in the group word line), and when writing the data page of the word line WL126, the word line WL126 is the last set of odd array word lines One word line, the error correction code encoding circuit 1101 is the last one of the word line WL126 The check code corresponding to the data of all the first character lines in all odd array word lines is written in the material page (that is, all the first part check codes generated by the first encoding engine in the odd array word lines) When the data page of the word line WL127 is written, the word line WL127 is the second word line of the last set of odd array word lines, and the error correction code encoding circuit 1101 is at the end of the word line WL127. A data page is written with the check code corresponding to the data of all the second character lines in all the odd array word lines (that is, all the second parts generated by the second encoding engine in the odd array word lines) Check code). This completes the writing of the SLC data block.

也就是說，當快閃記憶體控制器110寫入一群的資料至一SLC資料區塊時，快閃記憶體控制器110係將該SLC資料區塊的所有字元線依順序每M條字元線編類為一組字元線，以產生複數組奇數組的字元線及複數組偶數組的字元線，以及對一組奇數組的每一條字元線及一組偶數組的每一條字元線，分別執行不同M次的互斥或運算的編碼操作，產生該組奇數組的每一條字元線的M個部分校驗碼以及該組偶數組的每一條字元線的M個部分校驗碼，寫入並儲存該複數組奇數組的每一條字元線的M個部分校驗碼於該複數組奇數組字元線中最後M條字元線之最後一張資料頁、寫入並儲存該複數組偶數組的每一條字元線的M個部分校驗碼於該複數組偶數組字元線中最後M條字元線之最後一張資料頁。而以上述實施例，M為3，然此並非是本案的限制。That is, when the flash memory controller 110 writes a group of data to an SLC data block, the flash memory controller 110 sequentially marks all the word lines of the SLC data block for each M word. The meta-line is grouped into a set of word lines to generate a character line of a complex array of odd-numbered arrays and a complex-array even-numbered array of word lines, and for each of a set of odd-arrayed character lines and a set of even-numbered arrays. a character line, respectively performing different M times of exclusive or exclusive encoding operations, generating M partial check codes of each character line of the set of odd arrays and M of each character line of the set of even arrays a partial check code, writing and storing M partial check codes of each character line of the odd array odd array in the last data page of the last M word lines in the complex array odd array word line And writing and storing the M partial check codes of each character line of the complex array even array in the last data page of the last M word lines in the complex array even array word line. In the above embodiment, M is 3, but this is not a limitation of the present case.

錯誤更正碼編碼電路1101在第5圖所示之實施例所執行的是互斥或運算編碼操作，可更正發生在SLC資料區塊之一條字元線上一個位置的資料頁錯誤，舉例來說，如果於執行該次SLC資料區塊的寫入時檢測到發生寫入失敗的情況，例如檢測到字元線WL1的資料頁P9寫入失敗，錯誤更正碼編碼電路1101可利用第二編碼引擎於處理第一組字元線的字元線WL1時所產生之相對應的部分校驗碼及同一字元線WL1之的其他正確的資料頁P10~P16，更正字元線WL1的資料頁P9的錯誤。The error correction code encoding circuit 1101 performs a mutually exclusive or arithmetic coding operation in the embodiment shown in FIG. 5, and can correct a data page error occurring at a position on one of the word lines of the SLC data block, for example, If the occurrence of the write failure is detected when the writing of the SLC data block is performed, for example, the data page P9 of the word line WL1 is detected to be unsuccessfully written, the error correction code encoding circuit 1101 can utilize the second encoding engine. Corresponding partial check code generated when processing the word line WL1 of the first character line and other correct data pages P10~P16 of the same word line WL1, correcting the data page P9 of the word line WL1 error.

如果於執行該次SLC資料區塊的寫入時檢測到發生一字元線斷路而造成例如字元線WL1的資料頁P9錯誤，錯誤更正碼編碼電路1101亦可利用第二編碼引擎於處理第一組字元線的字元線WL1時所產生之相對應的部分校驗碼及同一字元線WL1之其他正確的資料頁P10~P16，更正字元線WL1的資料頁P9的錯誤。If it is detected that a word line break occurs when the writing of the SLC data block is performed and the data page P9 of the character line WL1 is incorrect, for example, the error correction code encoding circuit 1101 can also use the second encoding engine for processing. The corresponding partial check code generated when the word line WL1 of a set of word lines and the other correct data pages P10 to P16 of the same word line WL1 correct the error of the data page P9 of the word line WL1.

如果於執行該次SLC資料區塊的寫入時檢測到發生兩字元線短路而造成例如字元線WL1的資料頁P9與字元線WL2的P17均錯誤，錯誤更正碼編碼電路1101可利用第二編碼引擎於處理第一組字元線的字元線WL1時所產生之相對應的部分校驗碼及同一字元線WL1的其他正確的資料頁P10~P16，更正字元線WL1的資料頁P9的錯誤，以及利用第三編碼引擎於處理第一組字元線的字元線WL2時所產生之相對應的部分校驗碼及同一字元線WL2的其他正確的資料頁P18~P24，更正字元線WL2的資料頁P17的錯誤。而如果是字元線WL2的資料頁P17與字元線WL3的資料頁P1出錯，則錯誤更正碼編碼電路1101可利用第三編碼引擎於處理第一組字元線之字元線WL2時所產生之相對應的部分校驗碼及同一字元線WL2的其他正確的資料頁P18~P24，更正字元線WL2的資料頁P17的錯誤，以及利用第一編碼引擎於處理第二組字元線之字元線WL3時所產生之相對應的部分校驗碼及同一字元線WL3之其他正確的資料頁P2~P8，更正字元線WL3的資料頁P1的錯誤。因此，無論是在執行SLC資料區塊寫入時發生寫入失敗、一字元線斷路或兩字元線短路所造成的資料頁錯誤，錯誤更正碼編碼電路1101均可對應地更正該些錯誤的資料頁。快閃記憶體模組105通過內部複製將上述SLC資料區塊將資料寫入至TLC資料區塊的操作如同前述第3圖的內容，不再贅述。If it is detected that a two-character line short circuit occurs when the writing of the SLC data block is performed, causing, for example, the data page P9 of the word line WL1 and the P17 of the word line WL2 are both wrong, the error correction code encoding circuit 1101 can be utilized. The second encoding engine generates a corresponding partial check code generated by the word line WL1 of the first character line and other correct data pages P10~P16 of the same word line WL1, and corrects the word line WL1. The error of the data page P9, and the corresponding partial check code generated by the third coding engine when processing the word line WL2 of the first character line and the other correct data page P18 of the same word line WL2 P24, correcting the error of the data page P17 of the word line WL2. On the other hand, if the data page P17 of the word line WL2 and the data page P1 of the word line WL3 are in error, the error correction code encoding circuit 1101 can use the third encoding engine to process the word line WL2 of the first group of character lines. Corresponding partial check code and other correct data pages P18~P24 of the same word line WL2, correcting the error of the data page P17 of the word line WL2, and processing the second group of characters by using the first encoding engine The corresponding partial check code generated when the line word line WL3 is generated and the other correct data pages P2 to P8 of the same word line WL3 correct the error of the data page P1 of the word line WL3. Therefore, the error correction code encoding circuit 1101 can correct the errors correspondingly due to a data page error caused by a write failure, a word line break, or a two word line short circuit when the SLC data block write is performed. Information page. The operation of the flash memory module 105 to write the data to the TLC data block by the SLC data block by internal copy is the same as that of the foregoing FIG. 3 and will not be described again.

接著請參照第6圖，第6圖為本發明第二實施例第1圖所示之快閃記憶體控制器110寫入三個群之資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C並通過內部複製將該些SLC資料區塊1051A~1051C之資料搬移寫入至TLC資料區塊1052而形成一個超級區塊的示意圖。錯誤更正碼編碼電路1101於每次執行SLC資料區塊的寫入時，均把資料分類為奇數組字元線與偶數組字元線，並將對應產生之校驗碼儲存於所有奇數組字元線中最後3條字元線之最後每一張資料頁以及所有偶數組字元線之最後3條字元線之最後每一張資料頁，如第6圖所示，執行TLC資料區塊寫入時，依資料寫入的順序，第一群中的字元線資料的對應校驗碼，如605A所標示，係寫入並儲存於TLC資料區塊1052之字元線WL40之最後一張資料頁之最高有效位MSB、字元線WL41之最後一張資料頁以及字元線WL42之最後一張資料頁之最低有效位LSB與中間有效位CSB，其中第一個群中的SLC資料區塊的奇數組字元線的校驗碼儲存於字元線WL40之最後一張資料頁之最高有效位MSB以及字元線WL42之最後一張資料頁之最低有效位LSB與中間有效位CSB，而第一個群中的SLC資料區塊的偶數組字元線的校驗碼儲存於字元線WL41之最後一張資料頁（包括最低有效位LSB、中間有效位CSB與最高有效位MSB）。Referring to FIG. 6, FIG. 6 is a diagram showing the flash memory controller 110 shown in FIG. 1 of the second embodiment of the present invention writing data of three groups to a plurality of SLCs in the flash memory module 105. The data blocks 1051A to 1051C are internally copied to the data of the SLC data blocks 1051A to 1051C and are written into the TLC data block 1052 to form a super block. The error correction code encoding circuit 1101 classifies the data into odd array word lines and even array word lines each time the SLC data block is written, and stores the corresponding generated check codes in all odd array words. The last data page of the last three character lines in the line and the last data page of the last three word lines of all even array word lines, as shown in Figure 6, execute the TLC data block. When writing, according to the order in which the data is written, the corresponding check code of the word line data in the first group, as indicated by 605A, is written and stored in the last one of the word line WL40 of the TLC data block 1052. The most significant bit MSB of the data page, the last data page of the word line WL41, and the least significant bit LSB and the intermediate significant bit CSB of the last data page of the word line WL42, wherein the SLC data in the first group The check code of the odd array word line of the block is stored in the most significant bit MSB of the last data page of the word line WL40 and the least significant bit LSB and the intermediate effective bit CSB of the last data page of the word line WL42. And the even array of word lines of the SLC data block in the first group Check code stored in the word line WL41 of the last profile page (including the least significant bit LSB, CSB middle significant bit and the most significant bit MSB).

第二個群中的字元線資料的對應校驗碼，如605B所標示，係寫入並儲存於TLC資料區塊1052之字元線WL83之最後一張資料頁之中間有效位CSB與最高有效位MSB、字元線WL84之最後一張資料頁以及字元線WL85之最後一張資料頁之最低有效位LSB，其中對於第二個群中在SLC資料區塊的奇數組字元線資料，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL83之最後一張資料頁之中間有效位CSB，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL84之最後一張資料頁之最高有效位MSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL85之最後一張資料頁之最低有效位LSB，而對於第二個群中在SLC資料區塊的偶數組字元線資料，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL83之最後一張資料頁之最高有效位MSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL84之最後一張資料頁之最低有效位LSB，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL84之最後一張資料頁之中間有效位CSB。The corresponding check code of the word line data in the second group, as indicated by 605B, is written and stored in the middle valid bit CSB of the last data page of the word line WL83 of the TLC data block 1052 and the highest The valid bit MSB, the last data page of the word line WL84, and the least significant bit LSB of the last data page of the word line WL85, where for the second group, the odd array word line data in the SLC data block All third partial check codes generated by the third encoding engine are stored in the intermediate valid bit CSB of the last data page of the word line WL83 of the TLC data block 1052, all generated by the first encoding engine. The first part of the check code is stored in the most significant bit MSB of the last data page of the word line WL84 of the TLC data block 1052, and all the second part of the check code generated by the second coding engine is stored in the TLC data. The least significant bit LSB of the last data page of the word line WL85 of the block 1052, and all the pieces generated by the first encoding engine for the even array word line data of the SLC data block in the second group A part of the check code is stored in the TLC data area. The most significant bit MSB of the last data page of the character line WL83 of 1052, and all the second partial verification code generated by the second encoding engine are stored in the last of the word line WL84 of the TLC data block 1052. The least significant bit LSB of the data page, all third partial check codes generated by the third encoding engine are stored in the intermediate valid bit CSB of the last data page of the word line WL84 of the TLC data block 1052.

第三個群之字元線資料的對應校驗碼，如605C所標示，係寫入並儲存於TLC資料區塊1052之字元線WL126、127之最後一張資料頁（包括最低有效位LSB、中間有效位CSB與最高有效位MSB），其中對於第三個群中在SLC資料區塊的奇數組字元線資料，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL126之最後一張資料頁之最低有效位LSB，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL127之最後一張資料頁之中間有效位CSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL127之最後一張資料頁之最高有效位MSB，而對於第三個群中在SLC資料區塊的偶數組字元線資料，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL126之最後一張資料頁之中間有效位CSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL126之最後一張資料頁之最高有效位MSB，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL127之最後一張資料頁之最低有效位LSB。The corresponding check code of the third group of character line data, as indicated by 605C, is the last data page (including the least significant bit LSB) written and stored in the character line WL126, 127 of the TLC data block 1052. , the intermediate significant bit CSB and the most significant bit MSB), wherein for the odd array word line data in the SLC data block in the third group, all the third partial check code generated by the third encoding engine is stored in The least significant bit LSB of the last data page of the word line WL126 of the TLC data block 1052, all the first partial check code generated by the first encoding engine is stored in the word line WL127 of the TLC data block 1052. The intermediate valid bit CSB of the last data page, all the second partial check codes generated by the second encoding engine are stored in the most significant bit MSB of the last data page of the word line WL127 of the TLC data block 1052. And for the even array of word line data in the SLC data block in the third group, all the first part of the check code generated by the first encoding engine is stored at the end of the word line WL126 of the TLC data block 1052. Intermediate valid bit CSB of a data page All second partial check codes generated by the second encoding engine are stored in the most significant bit MSB of the last data page of the word line WL126 of the TLC data block 1052, and all generated by the third encoding engine The third partial check code is stored in the least significant bit LSB of the last data page of the word line WL127 of the TLC data block 1052.

因此，當快閃記憶體模組105透過內部複製操作從該些SLC資料區塊1051A~1051C搬移寫入資料至TLC資料區塊1052時，如果檢測到兩字元線短路而造成例如TLC資料區塊1052之字元線WL0、WL1的兩資料頁（如框線610所標示）發生錯誤，快閃記憶體模組105可利用儲存於TLC資料區塊1052之字元線WL42之最後一張資料頁之中間有效位CSB的第一部分校驗碼以及字元線WL0之其他資料頁的最低有效位LSB的資料，更正610所標記之字元線WL0之資料頁的最低有效位LSB的資料，利用儲存於TLC資料區塊1052之字元線WL42之最後一張資料頁之最高有效位MSB的第二部分校驗碼以及字元線WL0之其他資料頁的中間有效位CSB的資料，來更正610所標記之字元線WL0之資料頁的中間有效位CSB的資料，以及利用儲存於TLC資料區塊1052之字元線WL40之最後一張資料頁之最高有效位MSB的第三部分校驗碼以及字元線WL0之其他資料頁的最高有效位MSB的資料，來更正610所標記之字元線WL0之資料頁的最高有效位MSB的資料。相同地，快閃記憶體模組105可利用儲存於TLC資料區塊1052之字元線WL41之最後一張資料頁之最低有效位LSB的第一部分校驗碼以及字元線WL1之其他資料頁的最低有效位LSB的資料，來更正610所標記之字元線WL1之資料頁的最低有效位LSB的資料，利用儲存於TLC資料區塊1052之字元線WL41之最後一張資料頁之中間有效位CSB的第二部分校驗碼以及字元線WL1之其他資料頁的中間有效位CSB的資料，來更正610所標記之字元線WL1之資料頁的中間有效位CSB的資料，以及利用儲存於TLC資料區塊1052之字元線WL41之最後一張資料頁之最高有效位MSB的第三部分校驗碼以及字元線WL1之其他資料頁的最高有效位MSB的資料，來更正610所標記之字元線WL1之資料頁的最高有效位MSB的資料。Therefore, when the flash memory module 105 moves the write data from the SLC data blocks 1051A to 1051C to the TLC data block 1052 through the internal copy operation, if the two word line short circuit is detected, for example, the TLC data area is caused. An error occurs in the two data pages of the word lines WL0, WL1 of block 1052 (as indicated by the frame line 610), and the flash memory module 105 can utilize the last data of the word line WL42 stored in the TLC data block 1052. Correcting the first partial check code of the intermediate valid bit CSB of the page and the least significant bit LSB of the other data pages of the word line WL0, correcting the data of the least significant bit LSB of the data page of the 610 marked character line WL0, using The second partial check code of the most significant bit MSB of the last data page of the word line WL42 of the TLC data block 1052 and the intermediate valid bit CSB of the other data pages of the word line WL0 are corrected to be corrected 610. The data of the intermediate significant bit CSB of the data page of the marked word line WL0, and the third partial check code of the most significant bit MSB of the last data page of the word line WL40 stored in the TLC data block 1052 And other characters of the word line WL0 The data of the most significant bit MSB of the data page is used to correct the data of the most significant bit MSB of the data page of the 610 marked word line WL0. Similarly, the flash memory module 105 can utilize the first partial check code of the least significant bit LSB of the last data page of the word line WL41 stored in the TLC data block 1052 and other data pages of the word line WL1. The least significant bit LSB data is used to correct the data of the least significant bit LSB of the data page of the 610 marked word line WL1, using the middle of the last data page of the word line WL41 stored in the TLC data block 1052. The second partial check code of the valid bit CSB and the data of the intermediate valid bit CSB of the other data pages of the word line WL1 are used to correct the data of the intermediate effective bit CSB of the data page of the 610 marked word line WL1, and to utilize The third partial check code of the most significant bit MSB of the last data page of the word line WL41 of the TLC data block 1052 and the most significant bit MSB of the other data pages of the word line WL1 are stored to correct 610. The data of the most significant bit MSB of the data page of the marked word line WL1.

相似地，如果兩字元線短路而造成之錯誤是發生在超級區塊之任兩連續字元線的之連續資料頁（例如如615、620所標示的錯誤位置），快閃記憶體模組105均可利用每一群組中一SLC資料區塊之最後6條字元線之最後一資料頁所儲存之相對應的校驗碼來更正錯誤。此外，如果是檢測到一字元線斷路或寫入失敗而造成TLC資料區塊1052之任一字元線的任一資料頁發生錯誤（亦即同一資料頁的三個有效位均出錯或是連續兩不同資料頁的不同有效位出錯），則快閃記憶體模組105均可利用對應儲存之校驗碼來更正連續任意三個有效位的錯誤。Similarly, if the error caused by the shorting of the two word lines is a continuous data page of any two consecutive word lines of the super block (for example, the wrong position indicated by 615, 620), the flash memory module 105 can correct the error by using the corresponding check code stored in the last data page of the last 6 word lines of an SLC data block in each group. In addition, if it is detected that a word line is broken or the write fails, any data page of any word line of the TLC data block 1052 is incorrect (that is, the three valid bits of the same data page are faulty or If the different valid bits of two consecutive data pages are in error, the flash memory module 105 can correct the error of any three consecutive valid bits by using the corresponding stored check code.

也就是說，通過快閃記憶體控制器110寫入三個群的資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C的校驗碼儲存位置管理設計，當快閃記憶體模組105通過內部複製將該些資料從多個SLC資料區塊1051A~1051C複製搬移寫入至TLC資料區塊時，如果檢測到一字元線斷路、兩字元線短路或寫入失敗的錯誤，均可由多個SLC資料區塊1051A~1051C儲存之校驗碼來進行更正。That is to say, the three groups of data are written by the flash memory controller 110 to the check code storage location management design of the plurality of SLC data blocks 1051A to 1051C in the flash memory module 105, when flashing When the memory module 105 copies and copies the data from the plurality of SLC data blocks 1051A to 1051C to the TLC data block by internal copying, if a word line disconnection, two word line short circuit or write is detected The failed error can be corrected by the check code stored in multiple SLC data blocks 1051A~1051C.

再者，本案上述的實施例亦適用於MLC資料區塊或QLC資料區塊等架構，當使用於MLC資料區塊時，上述三個群資料改為分類為兩個群的資料，而對於如果是執行互斥或運算的編碼操作，則改用兩個編碼引擎來實現，其他的條件則與前述使用於TLC資料區塊時相同；因此，如果是使用於QLC資料區塊時，上述三個群資料改為分類為四個群的資料，而對於如果是執行互斥或運算的編碼操作，則改用四個編碼引擎來實現，其他的條件則與前述使用於TLC資料區塊時相同；其他資料區塊的架構則依此類推。Furthermore, the above embodiments of the present invention are also applicable to an architecture such as an MLC data block or a QLC data block. When used in an MLC data block, the above three group data are classified into two groups of data, and if If the encoding operation is performed by mutual exclusion or operation, it is implemented by using two encoding engines. The other conditions are the same as those used in the TLC data block. Therefore, if it is used in the QLC data block, the above three The group data is changed into four groups of data, and if the encoding operation for performing the mutual exclusion or operation is implemented by using four encoding engines, the other conditions are the same as those used in the TLC data block. The architecture of other data blocks is the same.

以資料儲存的成本（overhead）來看，如果是採用兩個通道寫入兩個記憶體晶片，且每一記憶體晶片具有折疊平面設計使可同時寫入兩個區塊，則以一個SLC資料區塊的資料寫入而言，128條字元線共有8*128個資料頁，而僅需要使用到6個資料頁來儲存對應的校驗碼，成本的百分比不到1%（6/(128*8)），亦即對於SLC資料區塊的寫入以及TLC資料區塊的寫入，只需使用低於1%的資料空間作為儲存相對應的錯誤更正校驗碼之用，資料空間的使用效率極高。而如果是採用4個通道寫入4個記憶體晶片，且每一記憶體晶片具有折疊平面設計使可同時寫入2個區塊，則以一個SLC資料區塊的資料寫入而言，128條字元線共有4*4*2*128個資料頁，而僅需要使用到6個資料頁來儲存對應的校驗碼，成本的百分比將可更低，約為0.15%（6/(128*4*4*2)），亦即對於SLC資料區塊的寫入以及TLC資料區塊的寫入，只需使用約為0.15%的資料空間作為儲存相對應的錯誤更正校驗碼之用，資料空間的使用效率更高。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。In terms of the overhead of data storage, if two memory chips are written in two channels, and each memory chip has a folded plane design so that two blocks can be simultaneously written, one SLC data is used. For the data writing of the block, 128 word lines have 8*128 data pages, and only 6 data pages need to be used to store the corresponding check code, and the percentage of cost is less than 1% (6/( 128*8)), that is, for the writing of the SLC data block and the writing of the TLC data block, it is only necessary to use less than 1% of the data space for storing the corresponding error correction check code, the data space It is extremely efficient to use. If four memory chips are written in four channels, and each memory chip has a folded plane design so that two blocks can be simultaneously written, in the case of data writing of one SLC data block, 128 There are 4*4*2*128 data pages in the word line, and only 6 data pages need to be used to store the corresponding check code. The percentage of cost will be lower, about 0.15% (6/(128). *4*4*2)), that is, for the writing of the SLC data block and the writing of the TLC data block, it is only necessary to use about 0.15% of the data space for storing the corresponding error correction check code. The data space is more efficient to use. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧快閃記憶體裝置
105‧‧‧快閃記憶體模組
110‧‧‧快閃記憶體控制器
205、210、401A、401B、402A、402B、403A、403B、605A、605B、605C‧‧‧校驗碼儲存位置
404、405、406、610、615、620‧‧‧TLC資料區塊的資料頁
1051A、1051B、1051C‧‧‧SLC資料區塊
1052‧‧‧TLC資料區塊
1101‧‧‧錯誤更正碼編碼電路
1102‧‧‧校驗碼緩衝器
1102A、1102B‧‧‧緩衝區 100‧‧‧Flash memory device
105‧‧‧Flash Memory Module
110‧‧‧Flash Memory Controller
205, 210, 401A, 401B, 402A, 402B, 403A, 403B, 605A, 605B, 605C‧‧‧ check code storage location
404, 405, 406, 610, 615, 620‧ ‧ TLC data block data page
1051A, 1051B, 1051C‧‧‧SLC data block
1052‧‧‧TLC data block
1101‧‧‧Error correction code encoding circuit
1102‧‧‧ checksum buffer
1102A, 1102B‧‧‧ buffer zone

第1圖為本發明一實施例之快閃記憶體裝置的裝置示意圖。 第2圖為本發明第一實施例第1圖所示之快閃記憶體控制器執行SLC資料寫入將某一群之資料寫入至快閃記憶體模組內之一SLC資料區塊以執行一次SLC資料區塊寫入操作的示意圖。 第3圖為快閃記憶體模組內之一SLC資料區塊通過內部複製將資料寫入至TLC資料區塊的示意圖。 第4圖為本發明第一實施例第1圖所示之快閃記憶體控制器寫入三個群的資料至快閃記憶體模組內的多個SLC資料區塊並通過內部複製將資料搬移寫入至TLC資料區塊而形成一個超級區塊的示意圖。 第5圖為本發明第二實施例第1圖所示之快閃記憶體控制器執行SLC資料寫入以寫入一個群之資料至快閃記憶體模組內之SLC資料區塊以完成一次SLC資料區塊寫入操作的示意圖。 第6圖為本發明第二實施例第1圖所示之快閃記憶體控制器寫入三個群之資料至快閃記憶體模組內的多個SLC資料區塊並通過內部複製將該些SLC資料區塊之資料搬移寫入至TLC資料區塊而形成一個超級區塊的示意圖。FIG. 1 is a schematic diagram of an apparatus of a flash memory device according to an embodiment of the present invention. 2 is a first embodiment of the first embodiment of the present invention, the flash memory controller performs SLC data writing, and writes a certain group of data into one SLC data block in the flash memory module to execute Schematic diagram of a SLC data block write operation. Figure 3 is a schematic diagram of one of the SLC data blocks in the flash memory module writing data to the TLC data block by internal copying. Figure 4 is a diagram showing the flash memory controller shown in Fig. 1 of the first embodiment of the present invention writing data of three groups to a plurality of SLC data blocks in the flash memory module and copying the data by internal copying. A schematic diagram of moving a write to a TLC data block to form a super block. 5 is a second embodiment of the second embodiment of the present invention, the flash memory controller performs SLC data writing to write a group of data to the SLC data block in the flash memory module to complete the first time. Schematic diagram of SLC data block write operation. Figure 6 is a diagram showing the flash memory controller shown in Figure 1 of the second embodiment of the present invention writing data of three groups to a plurality of SLC data blocks in the flash memory module and The data of some SLC data blocks is transferred to the TLC data block to form a schematic diagram of a super block.

Claims (16)

一種快閃記憶體裝置，包含有： 一快閃記憶體模組，包括複數個單層單元資料區塊以及至少一多層單元資料區塊；以及 一快閃記憶體控制器，具有複數條通道分別連接至該快閃記憶體模組，該快閃記憶體控制器係先將一筆欲寫入之資料分類為複數群的資料，該快閃記憶體控制器分別執行單層單元資料寫入（SLC program）以及執行一類似容錯式磁碟陣列的里德-所羅門碼之一錯誤更正編碼操作產生一對應的校驗碼，以將複數群的資料以及該對應的校驗碼寫入至該複數個單層單元資料區塊；當完成該複數個單層單元資料區塊的寫入時，該快閃記憶體模組係執行一內部複製（internal copy），將該複數個單層單元資料區塊所儲存之該複數群的資料以及該對應的校驗碼，依資料的先後順序，依序搬移寫入至該至少一多層單元資料區塊。A flash memory device includes: a flash memory module including a plurality of single layer unit data blocks and at least one multi-level cell data block; and a flash memory controller having a plurality of channels Connected to the flash memory module, the flash memory controller first classifies a piece of data to be written into a plurality of groups of data, and the flash memory controller respectively performs single layer unit data writing ( SLC program) and one of the Reed-Solomon codes performing a similar fault-tolerant disk array error correction encoding operation generates a corresponding check code to write the data of the complex group and the corresponding check code to the complex number a single layer unit data block; when the writing of the plurality of single layer unit data blocks is completed, the flash memory module performs an internal copy, and the plurality of single layer unit data areas The data of the complex group stored in the block and the corresponding check code are sequentially transferred to the at least one multi-level unit data block according to the order of the data. 如申請專利範圍第1項所述之快閃記憶體裝置，其中該至少一多層單元資料區塊之單元可儲存具有2N 位元的資訊，N大於等於2並為整數，該複數個單層單元資料區塊為N個SLC資料區塊，該快閃記憶體控制器係將該筆欲寫入之資料分類為N個群的資料，以分別寫入至該N個SLC資料區塊。The flash memory device of claim 1, wherein the unit of the at least one multi-level unit data block can store information having 2 N bits, N is greater than or equal to 2 and is an integer, the plurality of orders The layer unit data block is N SLC data blocks, and the flash memory controller classifies the data to be written into N groups of data to be respectively written to the N SLC data blocks. 如申請專利範圍第2項所述之快閃記憶體裝置，其中N等於3，該至少一多層單元資料區塊為一TLC資料區塊，該快閃記憶體控制器係將該筆欲寫入之資料分類為三個群的資料，以分別寫入至三個SLC資料區塊。The flash memory device of claim 2, wherein N is equal to 3, the at least one multi-level cell data block is a TLC data block, and the flash memory controller writes the pen The incoming data is classified into three groups of data to be written to the three SLC data blocks. 如申請專利範圍第2項所述之快閃記憶體裝置，其中當快閃記憶體控制器寫入資料至一群的資料至一SLC資料區塊時，該快閃記憶體控制器係將該SLC資料區塊的所有字元線（word line）依順序每M條字元線編類為一組字元線，以產生複數組奇數組的字元線及複數組偶數組的字元線，以及對該複數組奇數組的字元線及該複數組偶數組的字元線，分別執行不同次的里德-所羅門碼的編碼操作，產生該複數組奇數組的字元線的一第一校驗碼與該複數組偶數組的字元線的一第二校驗碼，寫入並儲存該第一校驗碼於該複數組奇數組字元線中最後一組字元線之最後一條字元線的最後複數張資料頁、寫入並儲存該第二校驗碼於該複數組偶數組字元線中最後一組字元線之最後一條字元線的最後複數張資料頁。The flash memory device of claim 2, wherein the flash memory controller is the SLC when the flash memory controller writes data to a group of data to an SLC data block. All word lines of the data block are grouped into a set of word lines per M word lines in order to generate a word line of the complex array odd number array and a complex array even array of word lines, and Performing a different Reed-Solomon code encoding operation on the character line of the odd array odd-numbered array and the character line of the complex array even array, respectively, generating a first school of the character line of the complex array odd array Querying and storing a second check code of the word line of the complex array even array, writing and storing the first check code in the last word of the last set of word lines in the complex array of the complex array word line The last plurality of data pages of the metaline, the second plurality of data pages of the last character line of the last set of character lines in the complex array even array word line are written and stored. 如申請專利範圍第1項所述之快閃記憶體裝置，其中當進行記憶體垃圾回收（garbage collection）時，該快閃記憶體控制器係從外部讀取出該複數個單層單元資料區塊之資料並進行重新編碼與寫入，或從外部讀取出該至少一多層單元資料區塊並進行重新編碼與寫入。The flash memory device of claim 1, wherein the flash memory controller reads the plurality of single layer unit data areas from the outside when performing a garbage collection. The block data is re-encoded and written, or the at least one multi-level cell data block is externally read and re-encoded and written. 如申請專利範圍第1項所述之快閃記憶體裝置，其中當寫入資料至一單層單元資料區塊且突然發生關機時，該快閃記憶體控制器係從該單層單元資料區塊讀回資料並重新進行編碼、寫入資料至另一單層單元資料區塊。The flash memory device of claim 1, wherein the flash memory controller is from the single layer unit data area when writing data to a single layer unit data block and suddenly shutting down The block reads back the data and re-encodes and writes the data to another single-layer cell data block. 如申請專利範圍第1項所述之快閃記憶體裝置，其中當寫入資料至該至少一多層單元資料區塊且突然發生關機時，該快閃記憶體控制器係放棄該至少一多層單元資料區塊所儲存之資料，並執行該內部複製，從該些複數單層單元資料區塊搬移寫入資料至該至少一多層單元資料區塊。The flash memory device of claim 1, wherein the flash memory controller discards the at least one more when writing data to the at least one multi-level cell data block and suddenly shutting down And storing the data stored in the layer data block, and performing the internal copy, and transferring the data from the plurality of single-layer unit data blocks to the at least one multi-level unit data block. 如申請專利範圍第1項所述之快閃記憶體裝置，其中當寫入資料至該些單層單元資料區塊時，該快閃記憶體控制器係依據該至少一多層單元資料區塊之一亂數種子數(randomizer seed)規則，寫入資料至該些複數單層單元資料區塊。The flash memory device of claim 1, wherein the flash memory controller is based on the at least one multi-level cell data block when writing data to the single-layer cell data blocks. A randomizer seed rule writes data to the plurality of single-layer unit data blocks. 一種快閃記憶體儲存管理方法，包含有： 提供一快閃記憶體模組，該快閃記憶體模組包括複數個單層單元資料區塊以及至少一多層單元資料區塊； 將一筆欲寫入之資料分類為複數群的資料； 分別執行單層單元資料寫入（SLC program）以及執行一類似容錯式磁碟陣列的里德-所羅門碼之一錯誤更正編碼操作產生一對應的校驗碼，以將複數群的資料以及該對應的校驗碼寫入至該複數個單層單元資料區塊； 當完成該複數個單層單元資料區塊的寫入時，執行一內部複製，將該複數個單層單元資料區塊所儲存之該複數群的資料以及該對應的校驗碼，依資料的先後順序，依序搬移寫入至該至少一多層單元資料區塊。A flash memory storage management method includes: providing a flash memory module, the flash memory module comprising a plurality of single layer unit data blocks and at least one multi-level unit data block; The written data is classified into a plurality of groups of data; a single layer unit data writing (SLC program) and a Reed-Solomon code performing a similar fault-tolerant disk array are respectively performed to generate a corresponding check. a code to write the data of the plurality of groups and the corresponding check code to the plurality of single-layer unit data blocks; when the writing of the plurality of single-layer unit data blocks is completed, performing an internal copy, The data of the complex group stored in the plurality of single-layer unit data blocks and the corresponding check code are sequentially transferred to the at least one multi-level unit data block according to the sequence of the data. 如申請專利範圍第9項所述之快閃記憶體儲存管理方法，其中該至少一多層單元資料區塊之單元可儲存具有2N 位元的資訊，N大於等於2並為整數，該複數個單層單元資料區塊為N個SLC資料區塊，以及將該筆欲寫入之資料分類為該複數群的資料之步驟包括：將該筆欲寫入之資料分類為N個群的資料，以分別寫入至該N個SLC資料區塊。The flash memory storage management method according to claim 9, wherein the unit of the at least one multi-level unit data block can store information having 2 N bits, N is greater than or equal to 2 and is an integer, the complex number The single-layer unit data block is N SLC data blocks, and the step of classifying the data to be written into the data of the complex group includes: classifying the data to be written into N groups of data To write to the N SLC data blocks separately. 如申請專利範圍第10項所述之快閃記憶體儲存管理方法，其中N等於3，該至少一多層單元資料區塊為一TLC資料區塊，以及將該筆欲寫入之資料分類為N個群的資料以分別寫入至該N個SLC資料區塊之步驟包括：將該筆欲寫入之資料分類為三個群的資料，以分別寫入至三個SLC資料區塊。The flash memory storage management method according to claim 10, wherein N is equal to 3, the at least one multi-level unit data block is a TLC data block, and the data to be written is classified as The step of writing the data of the N groups to the N SLC data blocks separately includes: classifying the data to be written into three groups of data to be respectively written into the three SLC data blocks. 如申請專利範圍第10項所述之快閃記憶體儲存管理方法，其中執行單層單元資料寫入（SLC program）之步驟包括： 當寫入資料至一群的資料至一SLC資料區塊時，將該SLC資料區塊的所有字元線依順序每M條字元線編類為一組字元線，以產生複數組奇數組的字元線及複數組偶數組的字元線； 對於該複數組奇數組的字元線及該複數組偶數組的字元線，分別執行不同次的里德-所羅門碼的編碼操作，產生該複數組奇數組的字元線的一第一校驗碼與該複數組偶數組的字元線的一第二校驗碼；以及 寫入並儲存該第一校驗碼於該複數組奇數組字元線中最後一組字元線之最後一條字元線的最後複數張資料頁、寫入並儲存該第二校驗碼於該複數組偶數組字元線中最後一組字元線之最後一條字元線的最後複數張資料頁。The flash memory storage management method of claim 10, wherein the step of executing a single layer unit data write (SLC program) comprises: when writing data to a group of data to an SLC data block, All the word lines of the SLC data block are sequentially grouped into a set of word lines per M word lines to generate a word line of the complex array odd number array and the character line of the complex array even array; The character line of the complex array odd-numbered array and the character line of the even-array even-array array respectively perform encoding operations of Reed-Solomon codes of different times, and generate a first check code of the character line of the odd-array array of the complex array a second check code of the word line of the complex array even array; and writing and storing the first check code of the last character of the last set of word lines in the complex array of the complex array word line The last plurality of data pages of the line, the second plurality of data pages of the last character line of the last set of character lines in the complex array even array word line are written and stored. 如申請專利範圍第9項所述之快閃記憶體儲存管理方法，其另包含有： 當進行記憶體垃圾回收時，從外部讀取出該複數個單層單元資料區塊之資料並進行重新編碼與寫入，或從外部讀取出該至少一多層單元資料區塊並進行重新編碼與寫入。The flash memory storage management method of claim 9, further comprising: when performing memory garbage collection, externally reading out data of the plurality of single layer unit data blocks and performing re Encoding and writing, or externally reading out the at least one multi-level cell data block and re-encoding and writing. 如申請專利範圍第9項所述之快閃記憶體儲存管理方法，其另包含有： 當寫入資料至一單層單元資料區塊且突然發生關機時，從該單層單元資料區塊讀回資料並重新進行編碼、寫入資料至另一單層單元資料區塊。The flash memory storage management method of claim 9, further comprising: reading from the single-layer unit data block when writing data to a single-layer unit data block and suddenly shutting down Return the data and re-encode and write the data to another single-level unit data block. 如申請專利範圍第9項所述之快閃記憶體儲存管理方法，其另包含有： 當寫入資料至該至少一多層單元資料區塊且突然發生關機時，放棄該至少一多層單元資料區塊所儲存之資料，並執行該內部複製，從該些複數單層單元資料區塊搬移寫入資料至該至少一多層單元資料區塊。The flash memory storage management method of claim 9, further comprising: discarding the at least one multi-level unit when writing data to the at least one multi-level unit data block and suddenly shutting down Data stored in the data block, and performing the internal copy, and transferring data from the plurality of single-layer unit data blocks to the at least one multi-level unit data block. 如申請專利範圍第9項所述之快閃記憶體儲存管理方法，其另包含有： 當寫入資料至該些單層單元資料區塊時，依據該至少一多層單元資料區塊之一亂數種子數規則，寫入資料至該些複數單層單元資料區塊。The flash memory storage management method of claim 9, further comprising: when writing data to the single-layer unit data blocks, according to one of the at least one multi-level unit data block Random number of seed rules, write data to the plurality of single-level unit data blocks.
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