TWI797996B - Flash memory apparatus, flash memory controller, and storage management method for flash memory - Google Patents

Flash memory apparatus, flash memory controller, and storage management method for flash memory Download PDF

Info

Publication number
TWI797996B
TWI797996B TW111106129A TW111106129A TWI797996B TW I797996 B TWI797996 B TW I797996B TW 111106129 A TW111106129 A TW 111106129A TW 111106129 A TW111106129 A TW 111106129A TW I797996 B TWI797996 B TW I797996B
Authority
TW
Taiwan
Prior art keywords
data
flash memory
word line
word lines
data block
Prior art date
Application number
TW111106129A
Other languages
Chinese (zh)
Other versions
TW202223651A (en
Inventor
楊宗杰
許鴻榮
Original Assignee
慧榮科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 慧榮科技股份有限公司 filed Critical 慧榮科技股份有限公司
Publication of TW202223651A publication Critical patent/TW202223651A/en
Application granted granted Critical
Publication of TWI797996B publication Critical patent/TWI797996B/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0608—Saving storage space on storage systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Description

快閃記憶體裝置、快閃記憶體控制器及快閃記憶體儲存管理 方法 Flash memory device, flash memory controller and flash memory storage management method

本發明係關於一種快閃記憶體裝置，尤指一種執行一類似容錯式磁碟陣列的錯誤更正編碼操作之快閃記憶體裝置與儲存管理方法。 The present invention relates to a flash memory device, in particular to a flash memory device and a storage management method for performing an error correction coding operation similar to a fault-tolerant disk array.

一般而言，對於一快閃記憶體控制器執行資料寫入以寫入一筆資料至單層單元資料區塊或是多層單元資料區塊，傳統的機制係採用於例如在一資料區塊的一字元線的最後一頁放置該字元線之其他資料頁所對應的校驗碼，使得當發生寫入失敗、字元線斷路及字元線短路時可利用該對應的校驗碼來進行一定程度的錯誤更正，然而，這樣的資料儲存率過低，例如一字元線如果包括8張資料頁，則僅有7張資料頁用來存資料，另一張資料頁是用來儲存校驗碼，如此一來，一個資料區塊中將會有1/8的比例是用來儲存校驗碼，而非用來儲存資料，就使用者的角度來說，無法被接受。 Generally speaking, for a flash memory controller to perform data writing to write a piece of data to a single-level cell data block or a multi-level cell data block, the traditional mechanism is used, for example, in a data block The last page of the word line places the check codes corresponding to the other data pages of the word line, so that when writing failures, word line breaks and word line short circuits occur, the corresponding check codes can be used to perform A certain degree of error correction, however, the data storage rate is too low, for example, if a character line includes 8 data pages, only 7 data pages are used to store data, and the other data page is used to store calibration Check code. In this way, 1/8 of a data block will be used to store check codes instead of data, which is unacceptable from the user's point of view.

因此，本發明的目的之一在於提供一種快閃記憶體裝置及對應的快閃記憶體儲存管理方法，採用一類似容錯式磁碟陣列的錯誤更正編碼操作，降低錯誤發生率，降低傳統機制所需要使用的校驗碼數目，同時適當地將所需的校驗碼儲存於對應的資料頁位置，令發生寫入失敗、字元線斷路及字元線短路時仍可利用所需的校驗碼來進行一定程度的錯誤更正，解決了上述的問題。 Therefore, one of the objectives of the present invention is to provide a flash memory device and a corresponding flash memory storage management method, which adopts an error correction coding operation similar to a fault-tolerant disk array, reduces the error rate, and reduces the error rate caused by traditional mechanisms. The number of check codes that need to be used, and at the same time properly store the required check codes in the corresponding data page positions, so that the required check codes can still be used when writing failures, word line breaks and word line short circuits occur Code to perform some degree of error correction, which solves the above problems.

根據本發明一實施例，其揭露了一種快閃記憶體裝置。快閃記憶體裝置包含有一快閃記憶體模組與快閃記憶體控制器，快閃記憶體模組包括複數個單層單元資料區塊以及至少一多層單元資料區塊，快閃記憶體控制器具有複數條通道分別連接至快閃記憶體模組，快閃記憶體控制器係將一筆欲寫入之資料分類為複數群的資料，快閃記憶體控制器分別執行單層單元資料寫入以及執行一類似容錯式磁碟陣列的錯誤更正編碼操作產生一對應的校驗碼，以將複數群的資料以及對應的校驗碼寫入至複數個單層單元資料區塊；當完成複數個單層單元資料區塊的寫入時，快閃記憶體模組係執行內部複製，將複數個單層單元資料區塊所儲存之複數群的資料以及對應的校驗碼，依資料的先後順序，依序搬移寫入至至少一多層單元資料區塊。 According to an embodiment of the present invention, a flash memory device is disclosed. The flash memory device includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of single-level unit data blocks and at least one multi-layer unit data block. The flash memory The controller has a plurality of channels respectively connected to the flash memory module. The flash memory controller classifies a piece of data to be written into multiple groups of data. The flash memory controller executes single-layer unit data writing Entering and performing an error correction encoding operation similar to a fault-tolerant disk array to generate a corresponding check code, so as to write the data of the complex group and the corresponding check code to a plurality of single-level unit data blocks; when the complex data is completed When a single-level unit data block is written, the flash memory module executes an internal copy, and the data of the multiple groups stored in the multiple single-level unit data blocks and the corresponding check codes are sequenced according to the order of the data Sequentially move and write to at least one MMU data block in sequence.

根據本發明一實施例，另揭露了一種快閃記憶體儲存管理方法。該方法包含有：提供一快閃記憶體模組，該快閃記憶體模組包括複數個單層單元資料區塊以及至少一多層單元資料區塊；將一筆欲寫入之資料分類為複數群的資料；分別執行單層單元資料寫入以及執行一類似容錯式磁碟陣列的錯誤更正編碼操作產生一對應的校驗碼，以將複數群的資料以及該對應的校驗碼寫入至該複數個單層單元資料區塊；當完成該複數個單層單元資料區塊的寫入時，執行一內部複製，將該複數個單層單元資料區塊所儲存之該複數群的資料以及該對應的校驗碼，依資料的先後順序，依序搬移寫入至該至少一多層單元資料區塊。 According to an embodiment of the present invention, a flash memory storage management method is also disclosed. The method includes: providing a flash memory module, the flash memory module includes a plurality of single-level unit data blocks and at least one multi-layer unit data block; classifying a piece of data to be written into plural group data; perform single-layer unit data writing and perform an error correction coding operation similar to a fault-tolerant disk array to generate a corresponding check code, so as to write the data of multiple groups and the corresponding check code into The plurality of single-level unit data blocks; when the writing of the plurality of single-level unit data blocks is completed, an internal copy is performed, and the data of the plurality of groups stored in the plurality of single-level unit data blocks and The corresponding check code is sequentially moved and written to the at least one MMU data block according to the sequence of the data.

100:快閃記憶體裝置 100: flash memory device

105:快閃記憶體模組 105:Flash memory module

110:快閃記憶體控制器 110: Flash memory controller

205,210,401A,401B,402A,402B,403A,403B,605A,605B,605C:校驗碼儲存位置 205, 210, 401A, 401B, 402A, 402B, 403A, 403B, 605A, 605B, 605C: check code storage location

404,405,406,610,615,620:TLC資料區塊的資料頁 404,405,406,610,615,620: Data pages for TLC data blocks

1051A,1051B,1051C:SLC資料區塊 1051A, 1051B, 1051C: SLC data blocks

1052:TLC資料區塊 1052: TLC data block

1101:錯誤更正碼編碼電路 1101: error correction code encoding circuit

1102:校驗碼緩衝器 1102: check code buffer

1102A,1102B:緩衝區 1102A, 1102B: buffer zone

第1圖為本發明一實施例之快閃記憶體裝置的裝置示意圖。 FIG. 1 is a device schematic diagram of a flash memory device according to an embodiment of the present invention.

第2圖為本發明第一實施例第1圖所示之快閃記憶體控制器執行SLC資料寫入 將某一群之資料寫入至快閃記憶體模組內之一SLC資料區塊以執行一次SLC資料區塊寫入操作的示意圖。 Figure 2 shows the flash memory controller shown in Figure 1 of the first embodiment of the present invention executing SLC data writing A schematic diagram of writing a certain group of data into an SLC data block in a flash memory module to perform a SLC data block write operation.

第3圖為快閃記憶體模組內之一SLC資料區塊通過內部複製將資料寫入至TLC資料區塊的示意圖。 FIG. 3 is a schematic diagram of one of the SLC data blocks in the flash memory module writing data into the TLC data block through internal replication.

第4圖為本發明第一實施例第1圖所示之快閃記憶體控制器寫入三個群的資料至快閃記憶體模組內的多個SLC資料區塊並通過內部複製將資料搬移寫入至TLC資料區塊而形成一個超級區塊的示意圖。 Figure 4 shows the flash memory controller shown in Figure 1 of the first embodiment of the present invention writes data of three groups to multiple SLC data blocks in the flash memory module and copies the data internally A schematic diagram of migrating and writing to a TLC data block to form a super block.

第5圖為本發明第二實施例第1圖所示之快閃記憶體控制器執行SLC資料寫入以寫入一個群之資料至快閃記憶體模組內之SLC資料區塊以完成一次SLC資料區塊寫入操作的示意圖。 Fig. 5 is the second embodiment of the present invention. The flash memory controller shown in Fig. 1 executes SLC data writing to write a group of data to the SLC data block in the flash memory module to complete one time. Schematic diagram of SLC data block write operation.

第6圖為本發明第二實施例第1圖所示之快閃記憶體控制器寫入三個群之資料至快閃記憶體模組內的多個SLC資料區塊並通過內部複製將該些SLC資料區塊之資料搬移寫入至TLC資料區塊而形成一個超級區塊的示意圖。 Figure 6 shows the second embodiment of the present invention. The flash memory controller shown in Figure 1 writes the data of three groups to multiple SLC data blocks in the flash memory module and copies them internally. A schematic diagram of moving and writing the data of some SLC data blocks to the TLC data blocks to form a super block.

請參照第1圖，其係為本發明一實施例之快閃記憶體裝置100的裝置示意圖。快閃記憶體裝置100包含快閃記憶體模組105及快閃記憶體控制器110，快閃記憶體模組105為一個具有二維平面架構的快閃記憶體模組；然此並非本案的限制。快閃記憶體模組105包含多個快閃記憶體晶片(並未繪示於第1圖)，每一快閃記憶體晶片包括多個單層單元資料區塊(single-level cell(SLC)block)及多個多層單元資料區塊(multiple-level-cell block)，單層單元資料區塊的每一單元可儲存2位元的資料，多層單元資料區塊的每一單元可儲存2N位元的資料，N大於或等於2並為整數，多層單元資料區塊例如包括有MLC區塊(multi-level cell block)之單元可儲存22位元的資料、TLC區塊(triple-level cell block)之單元可儲存23元的資料、QLC區塊(quad-level cell block)之單元可儲存24位元的資料，依 此類推。 Please refer to FIG. 1 , which is a device diagram of a flash memory device 100 according to an embodiment of the present invention. The flash memory device 100 includes a flash memory module 105 and a flash memory controller 110. The flash memory module 105 is a flash memory module with a two-dimensional planar structure; limit. The flash memory module 105 includes a plurality of flash memory chips (not shown in FIG. 1 ), and each flash memory chip includes a plurality of single-level cell (SLC) blocks. block) and multiple multi-level unit data blocks (multiple-level-cell block), each unit of a single-level unit data block can store 2 bits of data, and each unit of a multi-level unit data block can store 2 N For bit data, N is greater than or equal to 2 and is an integer. For example, a multi-level unit data block includes a unit of MLC block (multi-level cell block) that can store 22- bit data, TLC block (triple-level The unit of cell block) can store 2 3 -bit data, the unit of QLC block (quad-level cell block) can store 2 4 -bit data, and so on.

快閃記憶體控制器110可通過複數條通道連接至快閃記憶體模組105，使可利用不同條通道同時寫入資料至不同的快閃記憶體晶片，增加寫入效率，快閃記憶體控制器110包括一錯誤更正碼編碼電路1101及一校驗碼(parity check code)緩衝器1102，錯誤更正碼編碼電路1101用以對資料進行以一錯誤更正碼編碼操作，例如本案之實施例中包括里德-所羅門碼(Reed-solomon codes)的編碼操作及/或互斥或(exclusive-OR，XOR)運算的編碼操作，以產生相對應的校驗碼，校驗碼緩衝器1102用以暫存所產生之相對應的校驗碼，而快閃記憶體控制器110係用以一類似容錯式磁碟陣列(Redundant Array of Independent Disks,RAID)的資料管理機制，將一筆資料寫入不同的快閃記憶體晶片，降低出錯率，並在寫入資料至單層單元資料區塊時即同時考慮不同編碼操作的校驗碼於單層單元資料區塊的儲位位置以及於TLC資料區塊的儲存位置，令在寫入資料至單層單元資料區塊時可更正資料出錯以及後續快閃記憶體模組105通過內部複製(internal copy)操作由單層單元區塊將資料複製搬移至TLC資料區塊時亦可更正資料出錯。 The flash memory controller 110 can be connected to the flash memory module 105 through a plurality of channels, so that different channels can be used to write data to different flash memory chips at the same time, increasing the write efficiency, and the flash memory The controller 110 includes an error correction code encoding circuit 1101 and a parity check code buffer 1102. The error correction code encoding circuit 1101 is used to perform an error correction code encoding operation on data, such as in the embodiment of this case Including Reed-Solomon codes (Reed-solomon codes) encoding operation and/or exclusive-OR (exclusive-OR, XOR) operation encoding operation to generate the corresponding check code, the check code buffer 1102 is used for The generated corresponding check code is temporarily stored, and the flash memory controller 110 is used for a data management mechanism similar to a fault-tolerant disk array (Redundant Array of Independent Disks, RAID) to write a piece of data into different The flash memory chip reduces the error rate, and when writing data to the single-level unit data block, the check code of different encoding operations is considered at the same time in the storage position of the single-level unit data block and in the TLC data area The storage location of the block, so that data errors can be corrected when writing data to the single-layer unit data block, and the subsequent flash memory module 105 will copy and move the data from the single-layer unit block through an internal copy (internal copy) operation. Data errors can also be corrected when TLC data blocks.

實作上，為求資料寫入的效率及降低出錯率，快閃記憶體模組105包括多個通道(本案之實施例為2個通道，但非限定)，當一通道執行某一資料頁(page)的寫入時，可採用另一通道來執行另一資料頁的寫入，而不需要等候該通道，每一通道在快閃記憶體控制器110中有各自的序列傳輸器(sequencer)且均包含了多個快閃記憶體晶片(本案之實施例為2個晶片，但非限定)，使得一個通道可同時對多個快閃記憶體晶片執行不同資料頁的寫入，而不需要等候其中一個晶片，此外，每一快閃記憶體晶片可具有一折疊設計(folded)而具有不同的兩個平面(plane)，令一個快閃記憶體晶片在資料寫入時可同時利用不同兩平面上的兩個資料區塊來執行不同資料頁的寫入，而不需要等候其中某一個資 料區塊。因此，快閃記憶體模組105的一個超級資料區塊(super block)係由多個通道的多個快閃記憶體晶片的多個資料頁所組成。上述的快閃記憶體控制器110即係將資料以超級資料區塊為單位來進行寫入，先將資料寫入至快閃記憶體模組105內的單層單元資料區塊，由單層單元資料區塊緩衝，後續再從該些單層單元資料區塊將資料複製搬移至TLC資料區塊內。另外，應注意的是，其他實施例中，每一快閃記憶體晶片可不具有折疊設計，亦即，一個快閃記憶體晶片在資料寫入時係利用一資料區塊來執行一資料頁的寫入，其他資料頁的寫入需要等候時間。 In practice, in order to improve the efficiency of data writing and reduce the error rate, the flash memory module 105 includes multiple channels (the embodiment of this case is 2 channels, but not limited), when one channel executes a certain data page (page) writing, can adopt another channel to carry out the writing of another data page, and need not wait for this channel, and each channel has its own sequencer (sequencer) in the flash memory controller 110 ) and all include a plurality of flash memory chips (the embodiment of this case is 2 chips, but not limited), so that one channel can simultaneously write different data pages to multiple flash memory chips without It is necessary to wait for one of the chips. In addition, each flash memory chip can have a folded design (folded) and have two different planes (plane), so that a flash memory chip can use different planes at the same time when writing data. Two data blocks on two planes are used to write different data pages without waiting for one of them feed block. Therefore, a super block of the flash memory module 105 is composed of multiple data pages of multiple flash memory chips of multiple channels. The above-mentioned flash memory controller 110 promptly writes the data in units of super data blocks, and first writes the data to the single-layer unit data blocks in the flash memory module 105, and then the single-layer The unit data blocks are buffered, and then the data is copied and moved from these single-layer unit data blocks to the TLC data blocks. In addition, it should be noted that in other embodiments, each flash memory chip may not have a folded design, that is, a flash memory chip uses a data block to execute a data page when writing data. Writing, writing of other data pages requires a waiting time.

就資料寫入的流程而言，一筆資料會先被快閃記憶體控制器110寫入至多個單層單元資料區塊1051A~1051C，之後再從該些單層單元資料區塊1051A~1051C搬移至多層單元資料區塊1052，例如，在本實施例，係以TLC單元為架構的多層資料區塊為例，TLC單元可儲存23位元的資訊，也就是說，三個單層單元資料區塊(以下簡稱為SLC資料區塊)1051A~1051C的資料會被寫入至一個TLC資料區塊1052，據此，考量到需要共同對SLC資料區塊1051A~1051C的寫入以及TLC資料區塊1052的寫入進行錯誤更正的保護，快閃記憶體控制器110係將一筆資料分類為三個群(group)的資料，應注意的是，如果係以MLC單元為架構的多層資料區塊為例，由於MLC單元可儲存22位元的資訊，所以快閃記憶體控制器110會將該筆資料分類為兩個群的資料，而如果係以QLC單元為架構的多層資料區塊為例，由於QLC單元可儲存24位元的資訊，所以快閃記憶體控制器110會將該筆資料分類為四個群的資料；依此類推。也就是說，當上述多層單元資料區塊1052之單元可儲存具有2N位元的資訊，N大於等於2並為整數，單層單元資料區塊的數目會設計為N個SLC資料區塊，快閃記憶體控制器110係將該筆欲寫入之資料分類為N個群的資料，以分別寫入至N個SLC資料區塊。 As far as the data writing process is concerned, a piece of data is first written into multiple single-level unit data blocks 1051A-1051C by the flash memory controller 110, and then moved from these single-level unit data blocks 1051A-1051C To the multi-layer unit data block 1052, for example, in this embodiment, the multi-layer data block with the structure of the TLC unit is taken as an example, and the TLC unit can store 2-3 bits of information, that is to say, three single-level unit data The data of the blocks (hereinafter referred to as SLC data blocks) 1051A~1051C will be written into a TLC data block 1052. Accordingly, considering the need to jointly write the SLC data blocks 1051A~1051C and the TLC data area The writing of block 1052 is protected by error correction. The flash memory controller 110 classifies a piece of data into data of three groups. For example, since the MLC unit can store 22- bit information, the flash memory controller 110 will classify the data into two groups of data, and if the multi-layer data block based on the QLC unit is For example, since a QLC unit can store 24- bit information, the flash memory controller 110 will classify the data into four groups of data; and so on. That is to say, when the unit of the multi-level unit data block 1052 can store information with 2 N bits, N is greater than or equal to 2 and is an integer, the number of single-level unit data blocks will be designed as N SLC data blocks, The flash memory controller 110 classifies the data to be written into N groups of data for writing into N SLC data blocks respectively.

在本實施例中，當快閃記憶體控制器110將該筆資料分類為三個群的 資料後，會接著執行第一次的資料寫入(SLC program)將第一群的資料寫入上述第一個SLC資料區塊1051A以及利用錯誤更正碼編碼電路1101產生對應的校驗碼並寫入至第一個SLC資料區塊1051A中，如此便完成一次SLC資料區塊的寫入操作，之後快閃記憶體控制器110接著執行第二次的資料寫入(SLC program)將第二群的資料寫入上述第二個SLC資料區塊1051B以及利用錯誤更正碼編碼電路1101產生對應的校驗碼並寫入至第二個SLC資料區塊1051B中，如此便完成第二次的SLC資料區塊的寫入操作，以及快閃記憶體控制器110接著執行第三次的資料寫入(SLC program)將第三群的資料寫入上述第三個SLC資料區塊1051C以及利用錯誤更正碼編碼電路1101產生對應的校驗碼並寫入至第三個SLC資料區塊1051C中，如此便完成第三次的SLC資料區塊的寫入操作。 In this embodiment, when the flash memory controller 110 classifies the data into three groups After the data, the first data writing (SLC program) will be executed to write the data of the first group into the above-mentioned first SLC data block 1051A and use the error correction code encoding circuit 1101 to generate the corresponding check code and write Into the first SLC data block 1051A, thus completing a writing operation of the SLC data block, and then the flash memory controller 110 then executes the second data writing (SLC program) to write the second group Write the data into the second SLC data block 1051B and use the error correction code encoding circuit 1101 to generate the corresponding check code and write it into the second SLC data block 1051B, thus completing the second SLC data The writing operation of the block, and the flash memory controller 110 then executes the data writing (SLC program) for the third time to write the data of the third group into the above-mentioned third SLC data block 1051C and use the error correction code The encoding circuit 1101 generates a corresponding check code and writes it into the third SLC data block 1051C, thus completing the writing operation of the third SLC data block.

當快閃記憶體控制器110執行某一次的資料寫入(SLC program)將某一群的資料寫入某一個SLC資料區塊時，或該次資料寫入之後，快閃記憶體控制器110會檢測是否出錯，如果資料有錯，例如發生某一SLC資料區塊寫入的寫入失敗(program fail)、一字元線斷路(one word line open)及/或兩字元線短路(two word line short)的情況，快閃記憶體控制器110會利用錯誤更正碼編碼電路1101於該次資料寫入時所產生之對應校驗碼來更正上述的錯誤。 When the flash memory controller 110 executes a certain data write (SLC program) to write a certain group of data into a certain SLC data block, or after the data is written, the flash memory controller 110 will Check whether there is an error, if there is an error in the data, such as a write failure (program fail), a word line open (one word line open) and/or a two word line short circuit (two word line open) in a certain SLC data block. line short), the flash memory controller 110 will use the corresponding check code generated by the error correction code encoding circuit 1101 when the data is written in this time to correct the above error.

當前述三個群的資料均寫入至三個SLC資料區塊時1051A~1051C或者某一個SLC資料區塊的資料寫入已完成時，快閃記憶體模組105係執行內部複製，從該些SLC資料區塊1051A~1051C或某一個SLC資料區塊中將三個群的資料或某一群的資料複製搬移並依三個群的資料順序執行資料寫入(TLC program)至一個TLC資料區塊1052(亦即前述的超級資料區塊)，TLC資料區塊1052係由不同通道的不同快閃記憶體晶片的字元線的資料頁所組成，例如，TLC資料區塊1052的一字元線的一資料頁包括有上資料頁(upper page)、中間資料頁(middle page)以及下資料頁(lower page)，快閃記憶體模組105的內部複製係依順序例如 將一SLC資料區塊的第N條字元線上的多個資料頁寫入至TLC資料區塊1052之一字元線的多個上資料頁，將該SLC資料區塊的第N+1條字元線上的多個資料頁寫入至TLC資料區塊1052之同一字元線的多個中間資料頁，以及將該SLC資料區塊的第N+2條字元線上的多個資料頁寫入至TLC資料區塊1052之同一字元線的多個下資料頁。待所有三個群的資料均寫入至TLC資料區塊1052，如此便完成了該超級資料區塊的寫入操作。 When the data of the above-mentioned three groups are all written into the three SLC data blocks 1051A~1051C or when the data writing of a certain SLC data block has been completed, the flash memory module 105 executes the internal copy, from the In some SLC data blocks 1051A~1051C or in a certain SLC data block, the data of three groups or a certain group of data is copied and moved, and the data of the three groups is written in sequence (TLC program) to a TLC data area Block 1052 (i.e. the aforementioned super data block), TLC data block 1052 is composed of data pages of word lines of different flash memory chips of different channels, for example, a character of TLC data block 1052 A data page of a line includes an upper page, a middle page, and a lower page, and the internal replication of the flash memory module 105 is in sequence, for example Write multiple data pages on the Nth word line of an SLC data block to multiple upper data pages on a word line of the TLC data block 1052, and write the N+1th data page of the SLC data block Writing multiple data pages on the word line to multiple intermediate data pages on the same word line of the TLC data block 1052, and writing multiple data pages on the N+2th word line of the SLC data block Multiple lower data pages of the same word line entered into TLC data block 1052. After the data of all three groups are written into the TLC data block 1052, the writing operation of the super data block is completed.

應注意的是，為了令內部複製易於實現、符合TLC資料區塊1052的亂數種子數(randomizer seed)規則要求、以及同時考量錯誤更正編碼能力以降低出錯率，該內部複製操作係只是依資料的順序將資料搬移至TLC資料區塊1052的多條字元線的上、中、下資料頁的位置，而由快閃記憶體控制器110於寫入不同群的資料以及對應產生之校驗碼至該些SLC資料區塊1051A~1051C時，同時依據TLC資料區塊的亂數種子數規則要求以及考量錯誤更正編碼之校驗碼的寫入儲存位置，令錯誤更正碼編碼電路1101的錯誤更正編碼能力可於執行一次SLC資料區塊的寫入操作時更正SLC資料區塊的寫入失敗、一字元線斷路及/或兩字元線短路所造成的錯誤，以及可於執行該超級資料區塊的寫入操作時更正TLC資料區塊1052的寫入失敗、一字元線斷路及/或兩字元線短路所造成的錯誤。 It should be noted that, in order to make internal replication easy to implement, comply with the random number seed number (randomizer seed) rule requirement of TLC data block 1052, and consider the error correction coding ability to reduce the error rate at the same time, the internal replication operation system is only according to the data The data is moved to the position of the upper, middle and lower data pages of the multiple word lines of the TLC data block 1052 in sequence, and the flash memory controller 110 writes different groups of data and the corresponding parity When coding to these SLC data blocks 1051A~1051C, at the same time according to the random number seed number rule requirements of the TLC data block and considering the write storage location of the check code of the error correction code, the error of the error correction code encoding circuit 1101 is made The ability to correct encoding can correct errors caused by writing failures of SLC data blocks, open circuit of one word line and/or short circuit of two word lines when performing a write operation of SLC data block, and can be used when executing the super During the writing operation of the data block, the errors caused by the writing failure of the TLC data block 1052 , the open circuit of one word line and/or the short circuit of two word lines are corrected.

此外，如果快閃記憶體模組105進行記憶體垃圾回收(garbage collection)，快閃記憶體控制器110係通過外部讀取，從該些SLC資料區塊1051A~1051C中讀取出資料並重新進行錯誤更正的編碼來執行資料寫入(SLC program)，及/或從TLC資料區塊1052中讀取出資料並重新進行錯誤更正的編碼來執行資料寫入(SLC program)。此外，如果寫入資料(SLC program)至一SLC資料區塊且突然發生關機時，快閃記憶體控制器110係從該SLC資料區塊讀回資料並重新進行錯誤更正的編碼、寫入資料(SLC program)至另一新的SLC資料區塊。此外，如果寫入資料(TLC program)至TLC資料區塊1052且突然發生關機時，快 閃記憶體模組105係放棄該TLC資料區塊1052中目前所儲存之資料，並從該些SLC資料區塊1051A~1051C，通過內部複製重新將對應的資料執行TLC資料寫入(TLC program)至該TLC資料區塊1052。 In addition, if the flash memory module 105 performs memory garbage collection (garbage collection), the flash memory controller 110 reads data from the SLC data blocks 1051A-1051C through external reading and re- Perform error correction coding to execute data writing (SLC program), and/or read data from the TLC data block 1052 and perform error correction coding again to execute data writing (SLC program). In addition, if writing data (SLC program) to an SLC data block and suddenly shutting down, the flash memory controller 110 will read back the data from the SLC data block and re-encode the error correction and write the data (SLC program) to another new SLC data block. In addition, if the data (TLC program) is written to the TLC data block 1052 and a sudden shutdown occurs, the The flash memory module 105 discards the data currently stored in the TLC data block 1052, and re-writes the corresponding data from the SLC data blocks 1051A~1051C through internal copying (TLC program) to the TLC data block 1052.

請參照第2圖，第2圖為本發明第一實施例第1圖所示之快閃記憶體控制器110執行SLC資料寫入(SLC program)將某一群之資料寫入至快閃記憶體模組105內之一SLC資料區塊以執行一次SLC資料區塊寫入操作的示意圖。快閃記憶體控制器110之錯誤更正碼編碼電路1101係對資料執行以一類似容錯式磁碟陣列的里德-所羅門(Reed Solomon，RS)編碼操作，產生相對應的校驗碼，而校驗碼緩衝器1102用以暫存所產生之相對應的校驗碼。 Please refer to Fig. 2, Fig. 2 shows that the flash memory controller 110 shown in Fig. 1 of the first embodiment of the present invention executes the SLC data writing (SLC program) to write a certain group of data into the flash memory A schematic diagram of one SLC data block in the module 105 performing an SLC data block write operation. The error correction code encoding circuit 1101 of the flash memory controller 110 executes a Reed-Solomon (Reed Solomon, RS) encoding operation similar to a fault-tolerant disk array on the data to generate a corresponding check code, and the calibration The verification code buffer 1102 is used for temporarily storing the generated corresponding verification codes.

快閃記憶體模組105內包括有兩個通道，並包括兩個快閃記憶體晶片及每一晶片的兩組區塊有兩不同平面，為求寫入效率，快閃記憶體控制器110係通過兩個通道寫入資料至快閃記憶體模組105內的兩個快閃記憶體晶片的兩區塊。如第2圖之實施方式所示，一SLC資料區塊包括有例如128條字元線(分別由WL0至WL127表示之)，該SLC資料區塊可以是由一個SLC資料區塊或是一組SLC子資料區塊所組成，視SLC資料區塊的定義而變，為方便描述，在實施例係將包括128條字元線視為一個SLC資料區塊的大小，其中每一條字元線包括有例如8個資料頁，以該SLC資料區塊的第一條字元線WL0為例，快閃記憶體控制器110藉由通道CH0及摺疊平面PLN0、PLN1將資料頁P1、P2寫入至快閃記憶體晶片CE0，接著藉由同一通道CH0及摺疊平面PLN0、PLN1將資料頁P3、P4寫入至另一快閃記憶體晶片CE1，接著由另一通道CH1及摺疊平面PLN0、PLN1將資料頁P5、P6寫入至快閃記憶體晶片CE0，接著藉由通道CH1及摺疊平面PLN0、PLN1將資料頁P7、P8寫入至快閃記憶體晶片CE1。其他則依此類推。 In the flash memory module 105, two channels are included, and two flash memory chips and two groups of blocks of each chip have two different planes. For writing efficiency, the flash memory controller 110 Write data to two blocks of two flash memory chips in the flash memory module 105 through two channels. As shown in the embodiment of Fig. 2, an SLC data block includes, for example, 128 word lines (represented by WL0 to WL127 respectively), and the SLC data block can be composed of one SLC data block or a group of The composition of SLC sub-data blocks depends on the definition of SLC data blocks. For the convenience of description, in the embodiment, 128 word lines are considered as the size of an SLC data block, and each word line includes There are, for example, 8 data pages. Taking the first word line WL0 of the SLC data block as an example, the flash memory controller 110 writes the data pages P1 and P2 into the The flash memory chip CE0 then writes data pages P3 and P4 into another flash memory chip CE1 through the same channel CH0 and folding planes PLN0 and PLN1, and then writes data pages P3 and P4 into another flash memory chip CE1 through the same channel CH1 and folding planes PLN0 and PLN1. The data pages P5 and P6 are written into the flash memory chip CE0, and then the data pages P7 and P8 are written into the flash memory chip CE1 through the channel CH1 and the folding planes PLN0 and PLN1. Others and so on.

快閃記憶體控制器110係將一個SLC資料區塊的多個字元線WL0至WL127依順序將每M條字元線編類為一組，M為大於或等於2的正整數，M例如為 3，例如字元線WL0~WL2為第一組，字元線WL3~WL5為第二組，字元線WL6~WL8為第三組，字元線WL9~WL11為第四組…，字元線WL120~WL122為倒數第三組，字元線WL123~WL125為倒數第二組，最後一組字元線為WL126、WL127，其中第一、第三、第五組…等等的字元線為奇數組字元線，而第二、第四、第六組…等等的字元線為偶數組字元線，快閃記憶體控制器110每次寫入一組字元線之資料(包括三條字元線之資料)，係利用錯誤更正碼編碼電路1101對於該組字元線之資料執行錯誤更正編碼，並將所產生之對應之部分的校驗碼(partial parity code)輸出至校驗碼緩衝器1102，以暫存部分的校驗碼。 The flash memory controller 110 organizes a plurality of word lines WL0 to WL127 of an SLC data block into a group in sequence, and M is a positive integer greater than or equal to 2, and M is for example for 3. For example, word lines WL0~WL2 are the first group, word lines WL3~WL5 are the second group, word lines WL6~WL8 are the third group, word lines WL9~WL11 are the fourth group..., character Lines WL120~WL122 are the third group from the bottom, word lines WL123~WL125 are the second group from the bottom, and the last group of word lines are WL126 and WL127, among which the word lines of the first, third, fifth groups...etc. It is an odd group of word lines, and the second, fourth, sixth group... etc. are an even group of word lines, and the flash memory controller 110 writes the data of a group of word lines each time ( Including the data of three word lines), use the error correction code encoding circuit 1101 to perform error correction encoding on the data of the group of word lines, and output the generated corresponding part of the parity code (partial parity code) to the calibration The verification code buffer 1102 is used to temporarily store part of the verification codes.

校驗碼緩衝器1102於暫存部分的校驗碼時係將奇數組字元線資料所對應之部分的校驗碼儲存於一第一緩衝區1102A，將偶數組字元線資料所對應之部分的校驗碼儲存於一第二緩衝區1102B，舉例來說，當寫入字元線WL0~WL2之資料頁P1~P24時，錯誤更正碼編碼電路1101係對於資料頁P1~P24執行錯誤更正編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第一緩衝區1102A；接著當寫入字元線WL3~WL5之資料頁P1~P24，錯誤更正碼編碼電路1101係對於資料頁P1~P24執行錯誤更正編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第二緩衝區1102B；接著錯誤當寫入字元線WL6~WL8之資料頁P25~P48，錯誤更正碼編碼電路1101係對於資料頁P25~P48執行錯誤更正編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第一緩衝區1102A；後續的資料頁寫入與編碼操作係依此類推…；之後，當寫入字元線WL120~WL122之資料頁，錯誤更正碼編碼電路1101係對於字元線WL120~WL122之資料頁執行編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，暫存於第一緩衝區1102A。 The check code buffer 1102 stores the check code of the part corresponding to the word line data of the odd group in a first buffer 1102A when temporarily storing the part of the check code, and stores the part of the data corresponding to the word line data of the even group Part of the check code is stored in a second buffer 1102B. For example, when writing data pages P1-P24 of word lines WL0-WL2, the error correction code encoding circuit 1101 executes an error for data pages P1-P24 Correct the code, and output the check code of the corresponding part to the check code buffer 1102, and temporarily store it in the first buffer 1102A; then when writing into the data pages P1~P24 of the word lines WL3~WL5, The error correction code encoding circuit 1101 executes the error correction encoding for the data pages P1~P24, and outputs the check code of the corresponding part to the check code buffer 1102, which is temporarily stored in the second buffer 1102B; then the error When writing into the data pages P25~P48 of the word lines WL6~WL8, the error correction code encoding circuit 1101 performs error correction encoding on the data pages P25~P48, and outputs the check codes of the corresponding parts to the checker The code buffer 1102 is temporarily stored in the first buffer 1102A; subsequent data page writing and encoding operations are deduced by analogy...; after that, when writing the data page of the word line WL120~WL122, the error correction code encoding circuit 1101 Encoding is performed on the data pages of the word lines WL120~WL122, and the check code of the corresponding part is output to the check code buffer 1102 and temporarily stored in the first buffer 1102A.

接著，快閃記憶體控制器110於寫入偶數組字元線的最後一組字元線(WL123~WL125)時，除了執行資料寫入(SLC program)與對應的錯誤更正編 碼外，亦將第二緩衝區1102B所暫存之所有偶數組字元線之資料的部分校驗碼讀回，並將偶數組字元線之資料所對應之所有校驗碼寫入至最後一組偶數組字元線之最後一條字元線WL125的資料頁，例如最後3個資料頁(標記為205)，以儲存偶數組字元線之資料所對應的里德-所羅門校驗碼。 Next, when the flash memory controller 110 writes into the last group of word lines (WL123~WL125) of the even word lines, in addition to executing the data writing (SLC program) and the corresponding error correction code In addition to the code, part of the check codes of the data of all the even word lines temporarily stored in the second buffer 1102B are read back, and all the check codes corresponding to the data of the even word lines are written into the last The data pages of the last word line WL125 of a group of even word lines, for example, the last three data pages (marked as 205 ), are used to store the Reed-Solomon check code corresponding to the data of the even word lines.

另外，對於寫入最後一組奇數組字元線的最後一條字元線WL127時，快閃記憶體控制器110除了執行資料寫入(SLC program)與對應的錯誤更正編碼外，會將第一緩衝區1102A所暫存之所有奇數組字元線之資料的部分校驗碼讀回，並將奇數組字元線之資料所對應之所有校驗碼寫入至最後一組奇數組字元線之最後一條字元線WL127的資料頁，例如最後3個資料頁(標記為210)，以儲存奇數組字元線之資料所對應的里德-所羅門校驗碼。如此便完成一次SLC資料區塊的寫入。因此，就里德-所羅門編碼操作而言，奇數組字元線之資料所對應的校驗碼係儲存於最後一組奇數組字元線之最後一條字元線WL127的最後複數張資料頁的位置，而偶數組字元線之資料所對應的校驗碼係儲存於最後一組偶數組字元線之最後一條字元線WL125的最後複數張資料頁的位置。 In addition, when writing the last word line WL127 of the last group of odd word lines, the flash memory controller 110 will write the first Read back part of the check codes of the data of all the odd word lines temporarily stored in the buffer 1102A, and write all the check codes corresponding to the data of the odd word lines to the last group of odd word lines The data pages of the last word line WL127, for example, the last three data pages (marked as 210), are used to store the Reed-Solomon check codes corresponding to the data of the odd number of word lines. In this way, the writing of one SLC data block is completed. Therefore, as far as the Reed-Solomon encoding operation is concerned, the check codes corresponding to the data of the odd word lines are stored in the last multiple data pages of the last word line WL127 of the last group of odd word lines position, and the check code corresponding to the data of the even word line is stored in the position of the last plurality of data pages of the last word line WL125 of the last even group of word lines.

此外，錯誤更正碼編碼電路1101在第2圖所示之實施例所執行的是里德-所羅門編碼操作，可更正發生在SLC資料區塊之任意三個位置之資料頁的出錯，舉例來說，錯誤更正碼編碼電路1101對於字元線WL0~WL2的三條字元線的資料執行錯誤更正編碼並產生相對應的部分校驗碼，如果同一通道的相同晶片的同一摺疊平面的三個資料頁出錯，例如資料頁P1、P9、P17出錯，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將該三個資料頁的錯誤更正。 In addition, what the error correction code encoding circuit 1101 performs in the embodiment shown in FIG. 2 is a Reed-Solomon encoding operation, which can correct errors occurring in any three data pages of the SLC data block, for example , the error correction code encoding circuit 1101 performs error correction encoding on the data of the three word lines WL0~WL2 and generates a corresponding partial check code, if the three data pages of the same folding plane of the same chip of the same channel Errors, such as errors in the data pages P1, P9, and P17, the error correction code encoding circuit 1101 can use the generated corresponding partial check codes to correct the errors of the three data pages.

如果於執行該次SLC資料區塊的寫入時檢測到發生寫入失敗(program fail)的情況，例如以發生機率來說，例如檢測到資料頁P9寫入失敗，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將資料頁P9的錯 誤更正。 If a write failure (program fail) is detected when executing the writing of the SLC data block, for example, in terms of the probability of occurrence, for example, it is detected that the writing of the data page P9 fails, the error correction code encoding circuit 1101 can Use the corresponding part of the check code generated to correct the error on the data page P9 Error correction.

如果於執行該次SLC資料區塊的寫入時檢測到發生一字元線斷路(one word line open)而造成例如資料頁P9錯誤，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將資料頁P9的錯誤更正。 If it is detected that a word line open occurs when performing the writing of the SLC data block, which causes, for example, a data page P9 error, the error correction code encoding circuit 1101 can use the generated corresponding part Check code, correct the error on data page P9.

如果於執行該次SLC資料區塊的寫入時檢測到發生兩字元線短路(two word line short)而造成例如資料頁P9、P17均錯誤，錯誤更正碼編碼電路1101可利用所產生之相對應的部分校驗碼，將資料頁P9、P17的錯誤更正。如果發生兩字元線短路而造成例如字元線WL2的資料頁P17與字元線WL3的資料頁P1出錯，錯誤更正碼編碼電路1101可利用一組字元線WL0~WL2的部分校驗碼以及另一組字元線WL3~WL5的部分校驗碼，分別將字元線WL2的資料頁P17與字元線WL3的資料頁P1的錯誤更正。如果發生兩字元線短路而造成例如字元線WL0的資料頁P1、P2錯誤，錯誤更正碼編碼電路1101可利用一組字元線WL0~WL2的部分校驗碼，分別將字元線WL0的資料頁P1、P2的錯誤更正。 If it is detected that a two word line short occurs when executing the writing of the SLC data block, resulting in errors in data pages P9 and P17, for example, the error correction code encoding circuit 1101 can use the generated phase The corresponding part of the check code corrects the errors on the data pages P9 and P17. If two word lines are short-circuited to cause an error between the data page P17 of the word line WL2 and the data page P1 of the word line WL3, for example, the error correction code encoding circuit 1101 can use a set of partial check codes of the word lines WL0~WL2 and another set of partial check codes of the word lines WL3-WL5 to correct the errors of the data page P17 of the word line WL2 and the data page P1 of the word line WL3 respectively. If two word lines are short-circuited to cause errors on the data pages P1 and P2 of word line WL0, for example, the error correction code encoding circuit 1101 can use part of the check codes of a group of word lines WL0~WL2 to convert the word line WL0 respectively. Error corrections on data pages P1 and P2.

因此，無論是在執行SLC資料區塊寫入時發生寫入失敗、一字元線斷路或兩字元線短路所造成的資料頁錯誤，錯誤更正碼編碼電路1101均可對應地更正該些錯誤的資料頁。 Therefore, whether it is a data page error caused by a write failure, an open circuit of one word line or a short circuit of two word lines when writing the SLC data block, the error correction code encoding circuit 1101 can correct these errors correspondingly profile page.

請參照第3圖，第3圖為快閃記憶體模組105內之一SLC資料區塊通過內部複製將資料寫入至TLC資料區塊1052的示意圖。如第3圖所示，一SLC資料區塊之一組三條字元線資料係寫入至TLC資料區塊1052之一字元線，對應地形成該字元線之一資料頁的最低有效位LSB、中間有效位CSB及最高有效位MSB的資料，例如SLC資料區塊之字元線資料WL0~WL2寫入至TLC資料區塊1052，作為該TLC資料區塊1052之字元線WL0之最低有效位LSB、中間有效位CSB及最高有效位MSB的資料；SLC資料區塊之字元線資料WL3~WL5寫入至TLC資料區塊1052，作為該TLC資料區塊1052之字元線WL1之最低有效位LSB、中間有效位CSB及最 高有效位MSB的資料；SLC資料區塊之字元線資料WL6~WL8寫入至TLC資料區塊1052，作為該TLC資料區塊1052之字元線WL2之最低有效位LSB、中間有效位CSB及最高有效位MSB的資料；也就是說，快閃記憶體模組105的內部複製係將SLC資料區塊之資料依字元線的順序搬移並寫入填入至TLC資料區塊的字元線內。 Please refer to FIG. 3 . FIG. 3 is a schematic diagram of a SLC data block in the flash memory module 105 writing data into the TLC data block 1052 through internal replication. As shown in FIG. 3, a group of three word line data of an SLC data block is written to a word line of a TLC data block 1052, correspondingly forming the least significant bit of a data page of the word line The data of LSB, middle significant bit CSB and most significant bit MSB, for example, the word line data WL0~WL2 of the SLC data block are written to the TLC data block 1052 as the lowest value of the word line WL0 of the TLC data block 1052 The effective bit LSB, the middle effective bit CSB and the most significant bit MSB data; the word line data WL3~WL5 of the SLC data block are written to the TLC data block 1052 as the word line WL1 of the TLC data block 1052 Least significant bit LSB, middle significant bit CSB and most The data of the most significant bit MSB; the word line data WL6~WL8 of the SLC data block are written into the TLC data block 1052 as the least significant bit LSB and the middle significant bit CSB of the word line WL2 of the TLC data block 1052 and the data of the most significant bit MSB; that is to say, the internal replication of the flash memory module 105 is to move the data of the SLC data block in the order of the word line and write it into the characters filled in the TLC data block inside the line.

請參照第4圖，第4圖為本發明第一實施例第1圖所示之快閃記憶體控制器110寫入三個群組之資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C並通過內部複製將資料搬移寫入至TLC資料區塊而形成一個超級資料區塊的示意圖。由於錯誤更正碼編碼電路1101於每次執行SLC資料區塊的寫入時，均把資料分類為奇數組字元線及偶數組字元線兩組，並將對應產生之校驗碼儲存於奇數組字元線之最後一字元線的最後3張資料頁及偶數組字元線之最後一字元線的最後3張資料頁，因此，當執行TLC資料區塊的寫入時，如第4圖所示，第一個群組之資料的奇數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL42的中間有效位CSB的最後三個資料頁(標記為401A)，而第一個群組之資料的偶數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL41的最高有效位MSB的最後三個資料頁(標記為401B)；第二個群組之資料的奇數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL85的最低有效位LSB的最後三個資料頁(標記為402A)，而第二個群組之資料的偶數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL84的最高有效位MSB的最後三個資料頁(標記為402B)；第三個群組之資料的奇數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL127的最高有效位MSB的最後三個資料頁(標記為403A)，而第三個群組之資料的偶數組字元線的對應之校驗碼係儲存於超級區塊之字元線WL127之最低有效位LSB的最後三個資料頁(標記為403B)。 Please refer to FIG. 4. FIG. 4 shows the flash memory controller 110 shown in FIG. 1 of the first embodiment of the present invention writing three groups of data to multiple SLCs in the flash memory module 105. A schematic diagram of the data blocks 1051A-1051C and moving and writing data to the TLC data block through internal replication to form a super data block. Since the error correction code encoding circuit 1101 classifies the data into two groups of odd word lines and even word lines each time it executes the writing of the SLC data block, and stores the corresponding check code in the odd word line. The last 3 data pages of the last word line of the array word line and the last 3 data pages of the last word line of the even array word line, therefore, when executing the writing of the TLC data block, as in the first As shown in Figure 4, the check codes corresponding to the odd word lines of the data of the first group are stored in the last three data pages (marked as 401A) of the middle significant bit CSB of the word line WL42 of the super block ), and the corresponding check codes of the even word lines of the data of the first group are stored in the last three data pages (marked as 401B) of the most significant bit MSB of the word line WL41 of the super block; The corresponding check codes of the odd word lines of the data of the second group are stored in the last three data pages (marked 402A) of the least significant bit LSB of the word line WL85 of the superblock, and the second The check codes corresponding to the even word lines of the data of the groups are stored in the last three data pages (marked 402B) of the most significant bit MSB of the word line WL84 of the super block; the third group The corresponding check codes of the odd word lines of the data are stored in the last three data pages (marked 403A) of the most significant bit MSB of the word line WL127 of the super block, and the data of the third group The corresponding parity codes for the even wordlines are stored in the last three data pages (labeled 403B) of the least significant bit LSB of the wordline WL127 of the superblock.

如果檢測到兩字元線短路而造成例如該超級區塊之字元線WL0、WL1的兩資料頁(如框線404所標示)發生錯誤，快閃記憶體模組105可利用字元 線WL42之中間有效位CSB的最後三張資料頁上儲存之校驗碼401A來更正字元線WL0之資料頁的錯誤，以及利用字元線WL41之最高有效位MSB之最後三張資料頁上儲存之校驗碼401B來更正字元線WL1之資料頁的錯誤。 If it is detected that two word lines are short-circuited and cause for example two data pages (as indicated by the frame line 404) of the word lines WL0 and WL1 of the super block to be wrong, the flash memory module 105 can use the word The check code 401A stored on the last three data pages of the middle significant bit CSB of the line WL42 is used to correct the error of the data page of the word line WL0, and the last three data pages of the most significant bit MSB of the word line WL41 are used The stored check code 401B is used to correct the error of the data page of the word line WL1.

相同地，如果檢測到兩字元線短路而造成例如該超級區塊之字元線WL43、WL44的兩資料頁(如框線405所標示)發生錯誤，快閃記憶體模組105可利用字元線WL85之最後三張資料頁之最低有效位LSB上儲存之校驗碼402A來更正405所標示之字元線WL43之一資料頁之最低有效位LSB、中間有效位CSB的錯誤以及字元線WL44之一資料頁之最高有效位MSB的錯誤，以及利用字元線WL84之最後三張資料頁之中間有效位CSB上儲存之校驗碼402B，來更正405所標示之字元線WL43一資料頁之最高有效位MSB之錯誤以及字元線WL44一資料頁之最低有效位LSB、中間有效位CSB的錯誤。 Similarly, if a short circuit between two word lines is detected to cause an error in two data pages (as indicated by the frame line 405) of the word lines WL43 and WL44 of the super block, the flash memory module 105 can use the word The check code 402A stored on the least significant bit LSB of the last three data pages of the word line WL85 is used to correct the error of the least significant bit LSB, the middle significant bit CSB and the character of a data page of the word line WL43 indicated by 405 The error of the most significant bit MSB of a data page of the line WL44, and the check code 402B stored on the middle significant bit CSB of the last three data pages of the word line WL84 is used to correct the word line WL43 indicated by 405 The error of the most significant bit MSB of the data page and the error of the least significant bit LSB and the middle significant bit CSB of the word line WL44 of the data page.

相同地，如果是檢測到兩字元線短路而造成例如該TLC資料區塊之字元線WL125、WL126的兩資料頁(如框線406所標示)發生錯誤，快閃記憶體模組105可利用字元線WL127之最後三張資料頁之最高有效位MSB上儲存之校驗碼403A來更正406所標示之字元線WL125一資料頁之中間有效位CSB、最高有效位MSB的錯誤以及字元線WL126一資料頁之最高有效位MSB的錯誤，以及利用字元線WL127之最後三張資料頁之最低有效位LSB上儲存之校驗碼403B，來更正406所標示之字元線WL125一資料頁之最低有效位LSB之錯誤以及406所標示之字元線WL126一資料頁之中間有效位CSB、最高有效位MSB的錯誤。 Similarly, if two data pages (as indicated by frame line 406) of word lines WL125 and WL126 of the TLC data block are detected to be short-circuited, the flash memory module 105 can Use the check code 403A stored on the most significant bit MSB of the last three data pages of the word line WL127 to correct the errors of the middle significant bit CSB and the most significant bit MSB of the data page of the word line WL125 indicated by 406, and the word The error of the most significant bit MSB of the first data page of the word line WL126, and the check code 403B stored on the least significant bit LSB of the last three data pages of the word line WL127 is used to correct the word line WL125 marked by 406 The error of the least significant bit LSB of the data page and the error of the middle significant bit CSB and the most significant bit MSB of the data page on the word line WL126 indicated by 406 .

如果是檢測到一字元線斷路或寫入失敗而造成超級區塊之任一字元線的任一資料頁發生錯誤(亦即連續任意三張子資料頁出錯)，則快閃記憶體模組105均可利用對應儲存之校驗碼來更正連續任意三張子資料頁的錯誤。 If an error occurs in any data page of any word line of the superblock due to detection of a word line break or write failure (that is, errors in any three consecutive sub-data pages), the flash memory module 105 can use the corresponding stored check code to correct the errors of any three consecutive sub-data pages.

也就是說，通過快閃記憶體控制器110寫入三個群組之資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C的校驗碼之儲存位置管理設 計，當快閃記憶體模組105通過內部複製將該些資料從多個SLC資料區塊1051A~1051C複製寫入至TLC資料區塊而形成一個超級資料區塊時，如果檢測到一字元線斷路、兩字元線短路或寫入失敗的錯誤，均可由多個SLC資料區塊1051A~1051C所儲存之校驗碼來進行更正。 That is to say, the flash memory controller 110 writes three groups of data to the storage location management device of the check codes of the multiple SLC data blocks 1051A-1051C in the flash memory module 105. In other words, when the flash memory module 105 copies and writes these data from multiple SLC data blocks 1051A~1051C to the TLC data block to form a super data block through internal copying, if a character is detected Errors of open circuit, short circuit of two word lines or failure of writing can be corrected by the check codes stored in the plurality of SLC data blocks 1051A˜1051C.

再者，請參照第5圖，第5圖為本發明第二實施例第1圖所示之快閃記憶體控制器110執行資料寫入(SLC program)以寫入一個群之資料至快閃記憶體模組105內之SLC資料區塊以完成一次SLC資料區塊寫入操作的示意圖。快閃記憶體控制器110之錯誤更正碼編碼電路1101係對資料執行以一類似容錯式磁碟陣列的互斥或運算的編碼操作，產生相對應的校驗碼，而校驗碼緩衝器1102用以暫存所產生之相對應的校驗碼。此外，錯誤更正碼編碼電路1101的互斥或運算包括有三個不同的編碼引擎以對SLC資料區塊的不同字元線資料進行互斥或運算；詳細操作內容如下所述。 Furthermore, please refer to FIG. 5. FIG. 5 shows the flash memory controller 110 shown in FIG. 1 of the second embodiment of the present invention executing data writing (SLC program) to write a group of data to the flash memory A schematic diagram of the SLC data block in the memory module 105 to complete a writing operation of the SLC data block. The error correction code encoding circuit 1101 of the flash memory controller 110 executes an encoding operation similar to a fault-tolerant disk array's exclusive OR operation on the data to generate a corresponding check code, and the check code buffer 1102 It is used to temporarily store the generated corresponding verification code. In addition, the exclusive OR operation of the ECC encoding circuit 1101 includes three different encoding engines for exclusive OR operation on different word line data of the SLC data block; the detailed operation content is as follows.

快閃記憶體模組105內包括有兩個通道，並包括兩個快閃記憶體晶片，為求寫入效率，快閃記憶體控制器110係通過兩個通道寫入資料至快閃記憶體模組105內的兩個快閃記憶體晶片，將一個SLC資料區塊之資料頁分別程式化至不同快閃記憶體晶片內，快閃記憶體控制器110的一次SLC資料區塊寫入操作所寫入的資料包括128條字元線(分別由WL0至WL127表示之)，每一條字元線包括8個資料頁，例如以字元線WL0為例，錯誤更正碼編碼電路1101藉由通道CH0及PLN0、PLN1將資料頁P1、P2寫入至快閃記憶體晶片CE0，接著藉由同一通道CH0及PLN0、PLN1將資料頁P3、P4寫入至另一快閃記憶體晶片CE1，接著由另一通道CH1及PLN0、PLN1將資料頁P5、P6寫入至快閃記憶體晶片CE0，接著藉由通道CH1及PLN0、PLN1將資料頁P7、P8寫入至快閃記憶體晶片CE1。 The flash memory module 105 includes two channels and includes two flash memory chips. For writing efficiency, the flash memory controller 110 writes data to the flash memory through two channels. The two flash memory chips in the module 105 respectively program the data pages of one SLC data block into different flash memory chips, and one SLC data block write operation of the flash memory controller 110 The written data includes 128 word lines (respectively represented by WL0 to WL127), and each word line includes 8 data pages. For example, taking word line WL0 as an example, the error correction code encoding circuit 1101 passes through CH0, PLN0, PLN1 write data pages P1, P2 into flash memory chip CE0, then write data pages P3, P4 into another flash memory chip CE1 through the same channel CH0, PLN0, PLN1, and then The data pages P5 and P6 are written into the flash memory chip CE0 through another channel CH1 and PLN0 and PLN1, and then the data pages P7 and P8 are written into the flash memory chip CE1 through the channels CH1 and PLN0 and PLN1.

錯誤更正碼編碼電路1101係將一個SLC資料區塊的多個字元線WL0至WL127依順序將每M條字元線編類為一組，M為大於或等於2的正整數，M例如 為3，例如字元線WL0~WL2為第一組，字元線WL3~WL5為第二組，字元線WL6~WL8為第三組，字元線WL9~WL11為第四組…，字元線WL120~WL122為倒數第三組，字元線WL123~WL125為倒數第二組，最後一組字元線為WL126、WL127，其中第一、第三、第五組…等等的字元線為奇數組字元線，而第二、第四、第六組…等等的字元線為偶數組字元線，快閃記憶體控制器110每次寫入一組字元線之資料(包括三條字元線之資料)，係利用錯誤更正碼編碼電路1101對於該組字元線之資料執行互斥或運算的錯誤更正編碼，並將所產生之對應之部分的校驗碼(partial parity code)輸出至校驗碼緩衝器1102，以暫存部分的校驗碼。 The error correction code encoding circuit 1101 is to sequentially classify a plurality of word lines WL0 to WL127 of an SLC data block into a group of each M word lines, M is a positive integer greater than or equal to 2, and M is for example is 3, for example, word lines WL0~WL2 are the first group, word lines WL3~WL5 are the second group, word lines WL6~WL8 are the third group, word lines WL9~WL11 are the fourth group..., word Element lines WL120~WL122 are the third group from the bottom, word lines WL123~WL125 are the second group from the bottom, and the last group of word lines are WL126 and WL127, among which the characters in the first, third, fifth groups...etc. lines are odd word lines, and the second, fourth, sixth, etc. word lines are even word lines, and the flash memory controller 110 writes the data of a group of word lines each time (including the data of three word lines), use the error correction code coding circuit 1101 to perform the error correction code of exclusive OR operation on the data of the group of word lines, and generate the check code (partial check code) of the corresponding part parity code) is output to the check code buffer 1102 to temporarily store part of the check code.

錯誤更正碼編碼電路1101每次寫入資料至一組三條不同字元線時，係採用三個不同的編碼引擎對於所寫入之資料執行互斥或運算的編碼，並將所產生之對應之部分的校驗碼輸出至校驗碼緩衝器1102，以暫存部分的校驗碼，而校驗碼緩衝器1102於暫存部分的校驗碼時係將奇數組之字元線資料所對應之部分的校驗碼儲存於一第一緩衝區，將偶數組之字元線資料所對應之部分的校驗碼儲存於一第二緩衝區。 When the error correction code encoding circuit 1101 writes data into a group of three different word lines each time, it uses three different encoding engines to perform mutually exclusive OR operation encoding on the written data, and generates the corresponding Part of the check code is output to the check code buffer 1102 to temporarily store part of the check code, and when the check code buffer 1102 temporarily stores part of the check code, it will correspond to the word line data of the odd group Part of the check code is stored in a first buffer, and the part of the check code corresponding to the even word line data is stored in a second buffer.

舉例來說，錯誤更正碼編碼電路1101包括有第一編碼引擎、第二編碼引擎及第三編碼引擎，當寫入字元線WL0~WL2之資料頁P1~P24，依序利用第一編碼引擎對於字元線WL0的資料頁P1~P8執行互斥或運算以產生一第一部分校驗碼、利用第二編碼引擎對於字元線WL1的資料頁P9~P16進行互斥或運算以產生一第二部分校驗碼以及利用第三編碼引擎對於字元線WL2的資料頁P17~P24進行互斥或運算以產生一第三部分校驗碼，並將所產生之該些部分校驗碼分別輸出至校驗碼緩衝器1102，暫存於第一緩衝區；接著錯誤更正碼編碼電路1101寫入字元線WL3~WL5之資料頁P1~P24，依序利用第一編碼引擎對於字元線WL3的資料頁P1~P8執行互斥或運算以產生另一第一部分校驗碼、利用第二編碼引擎對於字元線WL4的資料頁P9~P16執行互斥或運算以產生另一第二部分校驗碼以及利 用第三編碼引擎對於字元線WL5的資料頁P17~P24執行互斥或運算以產生另一第三部分校驗碼，並將所產生之該些部分校驗碼分別輸出至校驗碼緩衝器1102，暫存於第二緩衝區。 For example, the error correction code encoding circuit 1101 includes a first encoding engine, a second encoding engine and a third encoding engine. When writing data pages P1~P24 of word lines WL0~WL2, the first encoding engine is used in sequence Execute exclusive OR operation on the data pages P1-P8 of the word line WL0 to generate a first partial check code, and use the second encoding engine to perform exclusive OR operation on the data pages P9-P16 of the word line WL1 to generate a first part of the check code. Two-part check codes and using the third encoding engine to perform exclusive OR operations on the data pages P17-P24 of the word line WL2 to generate a third part check code, and output the generated part check codes respectively To the check code buffer 1102, temporarily stored in the first buffer; then the error correction code encoding circuit 1101 writes the data pages P1~P24 of the word lines WL3~WL5, and sequentially uses the first encoding engine for the word line WL3 The data pages P1~P8 of the word line WL4 perform a mutually exclusive OR operation to generate another first part of the check code, and use the second encoding engine to perform a mutually exclusive OR operation on the data pages P9~P16 of the word line WL4 to generate another second part of the check code check code and benefit Use the third encoding engine to perform a mutually exclusive OR operation on the data pages P17-P24 of the word line WL5 to generate another third part of the check code, and output the generated part of the check code to the check code buffer The device 1102 is temporarily stored in the second buffer.

後續的資料頁寫入與編碼操作係依此類推…，也就是說，對於一組奇數組字元線的第一條字元線的資料、第二條字元線的資料、第三條字元線的資料以及對於一組偶數組字元線的第一條字元線的資料、第二條字元線的資料、第三條字元線的資料，均分別執行不同次的互斥或運算，產生相對應的校驗碼。之後為了寫入該些對應的校驗碼於SLC資料區塊的適當儲存位置，錯誤更正碼編碼電路1101在寫入最後6條字元線WL122~WL127之資料頁時，係將該些相對應的校驗碼寫入於最後6條字元線WL122~WL127之最後一張資料頁(如第5圖之長方形斜線框所示)，例如，在寫入字元線WL122之資料頁時，字元線WL122為一組奇數組字元線的第三條字元線，錯誤更正碼編碼電路1101係於字元線WL122的最後一張資料頁中寫入所有奇數組字元線中所有第三條字元線之資料所對應的校驗碼(亦即奇數組字元線中由第三編碼引擎所產生之所有第三部分校驗碼)，而在寫入字元線WL123之資料頁時，字元線WL123為最後一組偶數組字元線的第一條字元線，錯誤更正碼編碼電路1101係於字元線WL123的最後一張資料頁中寫入所有偶數組字元線中所有第一條字元線之資料所對應的校驗碼(亦即偶數組字元線中由第一編碼引擎所產生之所有第一部分校驗碼)，而在寫入字元線WL124之資料頁時，字元線WL124為最後一組偶數組字元線的第二條字元線，錯誤更正碼編碼電路1101係於字元線WL124的最後一張資料頁中寫入所有偶數組字元線中所有第二條字元線之資料所對應的校驗碼(亦即偶數組字元線中由第二編碼引擎所產生之所有第二部分校驗碼)，而在寫入字元線WL125之資料頁時，字元線WL125為最後一組偶數組字元線的第三條字元線，錯誤更正碼編碼電路1101係於字元線WL125的最後一張資料頁中寫入所有偶數組字元線中所 有第三條字元線之資料所對應的校驗碼(亦即偶數組字元線中由第三編碼引擎所產生之所有第三部分校驗碼)，而在寫入字元線WL126之資料頁時，字元線WL126為最後一組奇數組字元線的第一條字元線，錯誤更正碼編碼電路1101係於字元線WL126的最後一張資料頁中寫入所有奇數組字元線中所有第一條字元線之資料所對應的校驗碼(亦即奇數組字元線中由第一編碼引擎所產生之所有第一部分校驗碼)，而在寫入字元線WL127之資料頁時，字元線WL127為最後一組奇數組字元線的第二條字元線，錯誤更正碼編碼電路1101係於字元線WL127的最後一張資料頁中寫入所有奇數組字元線中所有第二條字元線之資料所對應的校驗碼(亦即奇數組字元線中由第二編碼引擎所產生之所有第二部分校驗碼)。如此便完成一次SLC資料區塊的寫入。 Subsequent data page writing and encoding operations are deduced by analogy...that is to say, for a group of odd groups of word lines, the data of the first word line, the data of the second word line, and the data of the third word line For the data of the word line and for the data of the first word line, the data of the second word line, and the data of the third word line of an even group of word lines, the mutual exclusion or operation to generate the corresponding check code. Afterwards, in order to write these corresponding check codes into appropriate storage locations of the SLC data block, the error correction code encoding circuit 1101 writes these corresponding The check code is written in the last data page of the last 6 word lines WL122~WL127 (as shown in the rectangular oblique box in Figure 5), for example, when writing the data page of the word line WL122, the word The word line WL122 is the third word line of a group of odd word lines, and the error correction code encoding circuit 1101 writes all the third word lines in all the odd word lines in the last data page of the word line WL122. The check code corresponding to the data of the word line (that is, all the third part of the check code generated by the third encoding engine in the odd word line), and when writing the data page of the word line WL123 , the word line WL123 is the first word line of the last even group of word lines, and the error correction code encoding circuit 1101 is written into all the even group word lines in the last data page of the word line WL123 The check codes corresponding to the data of all the first word lines (that is, all the first part of the check codes generated by the first encoding engine in the even word lines), and the data written in the word line WL124 When the word line WL124 is the second word line of the last even group of word lines, the error correction code encoding circuit 1101 writes all the even group characters in the last data page of the word line WL124 The check codes corresponding to the data of all the second word lines in the line (that is, all the second part of the check codes generated by the second encoding engine in the even number of word lines), and the write word line For the data page of WL125, the word line WL125 is the third word line of the last even group of word lines, and the error correction code encoding circuit 1101 writes all the even numbers in the last data page of the word line WL125 group character line There is a check code corresponding to the data of the third word line (that is, all the third part of the check code generated by the third encoding engine in the even word line), and before writing the word line WL126 During the data page, the word line WL126 is the first word line of the last group of odd group word lines, and the error correction code encoding circuit 1101 writes all the odd group words in the last data page of the word line WL126 The check codes corresponding to the data of all the first word lines in the word line (that is, all the first part of the check codes generated by the first encoding engine in the odd word line), and the write word line During the data page of WL127, the word line WL127 is the second word line of the last group of odd word lines, and the error correction code encoding circuit 1101 writes all the odd data pages in the last data page of the word line WL127. The check codes corresponding to the data of all the second word lines in the array word lines (that is, all the second partial check codes generated by the second encoding engine in the odd array word lines). In this way, the writing of one SLC data block is completed.

也就是說，當快閃記憶體控制器110寫入一群的資料至一SLC資料區塊時，快閃記憶體控制器110係將該SLC資料區塊的所有字元線依順序每M條字元線編類為一組字元線，以產生複數組奇數組的字元線及複數組偶數組的字元線，以及對一組奇數組的每一條字元線及一組偶數組的每一條字元線，分別執行不同M次的互斥或運算的編碼操作，產生該組奇數組的每一條字元線的M個部分校驗碼以及該組偶數組的每一條字元線的M個部分校驗碼，寫入並儲存該複數組奇數組的每一條字元線的M個部分校驗碼於該複數組奇數組字元線中最後M條字元線之最後一張資料頁、寫入並儲存該複數組偶數組的每一條字元線的M個部分校驗碼於該複數組偶數組字元線中最後M條字元線之最後一張資料頁。而以上述實施例，M為3，然此並非是本案的限制。 That is to say, when the flash memory controller 110 writes a group of data into an SLC data block, the flash memory controller 110 sequentially writes all the word lines of the SLC data block every M word lines The metalines are classified into a group of wordlines to generate wordlines of a complex odd group and wordlines of a complex even group, and for each wordline of a group of odd groups and each wordline of a group of even groups One word line, perform different M times of mutually exclusive OR operation encoding operations, generate M partial check codes for each word line of the group of odd groups and M of each word line of the group of even groups Partial check codes, write and store the M partial check codes of each word line of the odd array of complex arrays in the last data page of the last M word lines of the word lines of the odd array of complex arrays . Writing and storing M partial check codes of each word line of the complex even group in the last data page of the last M word lines in the complex even group of word lines. In the above embodiment, M is 3, but this is not a limitation of this case.

錯誤更正碼編碼電路1101在第5圖所示之實施例所執行的是互斥或運算編碼操作，可更正發生在SLC資料區塊之一條字元線上一個位置的資料頁錯誤，舉例來說，如果於執行該次SLC資料區塊的寫入時檢測到發生寫入失敗的情況，例如檢測到字元線WL1的資料頁P9寫入失敗，錯誤更正碼編碼電路1101可利 用第二編碼引擎於處理第一組字元線的字元線WL1時所產生之相對應的部分校驗碼及同一字元線WL1之的其他正確的資料頁P10~P16，更正字元線WL1的資料頁P9的錯誤。 What the error correction code encoding circuit 1101 performs in the embodiment shown in FIG. 5 is a mutually exclusive OR operation encoding operation, which can correct a data page error occurring at a position on a word line of an SLC data block. For example, If it is detected that a write failure occurs during the writing of the SLC data block, for example, it is detected that the data page P9 of the word line WL1 has failed to write, the error correction code encoding circuit 1101 can use Use the corresponding part of the check code generated by the second encoding engine when processing the word line WL1 of the first group of word lines and other correct data pages P10~P16 of the same word line WL1 to correct the word line WL1 data page P9 error.

如果於執行該次SLC資料區塊的寫入時檢測到發生一字元線斷路而造成例如字元線WL1的資料頁P9錯誤，錯誤更正碼編碼電路1101亦可利用第二編碼引擎於處理第一組字元線的字元線WL1時所產生之相對應的部分校驗碼及同一字元線WL1之其他正確的資料頁P10~P16，更正字元線WL1的資料頁P9的錯誤。 If it is detected that a word line disconnection occurs during the writing of the SLC data block, which causes an error on the data page P9 of the word line WL1, for example, the error correction code encoding circuit 1101 can also use the second encoding engine to process the second A set of corresponding part of the check code generated by the word line WL1 and other correct data pages P10-P16 of the same word line WL1 correct the error of the data page P9 of the word line WL1.

如果於執行該次SLC資料區塊的寫入時檢測到發生兩字元線短路而造成例如字元線WL1的資料頁P9與字元線WL2的P17均錯誤，錯誤更正碼編碼電路1101可利用第二編碼引擎於處理第一組字元線的字元線WL1時所產生之相對應的部分校驗碼及同一字元線WL1的其他正確的資料頁P10~P16，更正字元線WL1的資料頁P9的錯誤，以及利用第三編碼引擎於處理第一組字元線的字元線WL2時所產生之相對應的部分校驗碼及同一字元線WL2的其他正確的資料頁P18~P24，更正字元線WL2的資料頁P17的錯誤。而如果是字元線WL2的資料頁P17與字元線WL3的資料頁P1出錯，則錯誤更正碼編碼電路1101可利用第三編碼引擎於處理第一組字元線之字元線WL2時所產生之相對應的部分校驗碼及同一字元線WL2的其他正確的資料頁P18~P24，更正字元線WL2的資料頁P17的錯誤，以及利用第一編碼引擎於處理第二組字元線之字元線WL3時所產生之相對應的部分校驗碼及同一字元線WL3之其他正確的資料頁P2~P8，更正字元線WL3的資料頁P1的錯誤。因此，無論是在執行SLC資料區塊寫入時發生寫入失敗、一字元線斷路或兩字元線短路所造成的資料頁錯誤，錯誤更正碼編碼電路1101均可對應地更正該些錯誤的資料頁。快閃記憶體模組105通過內部複製將上述SLC資料區塊將資料寫入至TLC資料區塊的操作如同前述第3圖的內容，不再贅述。 If it is detected that two word lines are short-circuited when performing the writing of the SLC data block, for example, the data page P9 of the word line WL1 and the P17 of the word line WL2 are all wrong, the error correction code encoding circuit 1101 can use The corresponding part of the check code generated by the second encoding engine when processing the word line WL1 of the first group of word lines and other correct data pages P10~P16 of the same word line WL1, to correct the word line WL1 The error of the data page P9, and the corresponding part of the check code generated by the third encoding engine when processing the word line WL2 of the first group of word lines and other correct data pages P18~ of the same word line WL2 P24, Correct the error in the data page P17 of the word line WL2. And if the data page P17 of the word line WL2 and the data page P1 of the word line WL3 have an error, the error correction code encoding circuit 1101 can use the third encoding engine to process the word line WL2 of the first group of word lines. Generate the corresponding part of the check code and other correct data pages P18~P24 of the same word line WL2, correct the error of the data page P17 of the word line WL2, and use the first encoding engine to process the second group of characters Corresponding part of the check code and other correct data pages P2-P8 of the same word line WL3 generated during the word line WL3 correct the error of the data page P1 of the word line WL3. Therefore, whether it is a data page error caused by a write failure, an open circuit of one word line or a short circuit of two word lines when writing the SLC data block, the error correction code encoding circuit 1101 can correct these errors correspondingly profile page. The operation of the flash memory module 105 to write the data from the SLC data block to the TLC data block through internal copying is the same as that in FIG. 3 above, and will not be repeated here.

接著請參照第6圖，第6圖為本發明第二實施例第1圖所示之快閃記憶 體控制器110寫入三個群之資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C並通過內部複製將該些SLC資料區塊1051A~1051C之資料搬移寫入至TLC資料區塊1052而形成一個超級區塊的示意圖。錯誤更正碼編碼電路1101於每次執行SLC資料區塊的寫入時，均把資料分類為奇數組字元線與偶數組字元線，並將對應產生之校驗碼儲存於所有奇數組字元線中最後3條字元線之最後每一張資料頁以及所有偶數組字元線之最後3條字元線之最後每一張資料頁，如第6圖所示，執行TLC資料區塊寫入時，依資料寫入的順序，第一群中的字元線資料的對應校驗碼，如605A所標示，係寫入並儲存於TLC資料區塊1052之字元線WL40之最後一張資料頁之最高有效位MSB、字元線WL41之最後一張資料頁以及字元線WL42之最後一張資料頁之最低有效位LSB與中間有效位CSB，其中第一個群中的SLC資料區塊的奇數組字元線的校驗碼儲存於字元線WL40之最後一張資料頁之最高有效位MSB以及字元線WL42之最後一張資料頁之最低有效位LSB與中間有效位CSB，而第一個群中的SLC資料區塊的偶數組字元線的校驗碼儲存於字元線WL41之最後一張資料頁(包括最低有效位LSB、中間有效位CSB與最高有效位MSB)。 Then please refer to Fig. 6, Fig. 6 is the flash memory shown in Fig. 1 of the second embodiment of the present invention The memory controller 110 writes the data of the three groups to multiple SLC data blocks 1051A~1051C in the flash memory module 105, and transfers and writes the data of these SLC data blocks 1051A~1051C to the A schematic diagram of TLC data block 1052 to form a super block. The error correction code encoding circuit 1101 classifies the data into odd word lines and even word lines each time the SLC data block is written, and stores the corresponding check codes in all odd word lines Each last data page of the last 3 word lines in the metaline and each last data page of the last 3 word lines of all even word lines, as shown in Figure 6, execute the TLC data block When writing, according to the order in which the data is written, the corresponding check code of the word line data in the first group, as indicated by 605A, is written and stored in the last word line WL40 of the TLC data block 1052 The most significant bit MSB of the first data page, the least significant bit LSB and the middle significant bit CSB of the last data page of the word line WL41 and the last data page of the word line WL42, wherein the SLC data in the first group The check code of the odd word line of the block is stored in the most significant bit MSB of the last data page of word line WL40 and the least significant bit LSB and middle significant bit CSB of the last data page of word line WL42 , and the check code of the even word line of the SLC data block in the first group is stored in the last data page of the word line WL41 (including the least significant bit LSB, the middle significant bit CSB and the most significant bit MSB ).

第二個群中的字元線資料的對應校驗碼，如605B所標示，係寫入並儲存於TLC資料區塊1052之字元線WL83之最後一張資料頁之中間有效位CSB與最高有效位MSB、字元線WL84之最後一張資料頁以及字元線WL85之最後一張資料頁之最低有效位LSB，其中對於第二個群中在SLC資料區塊的奇數組字元線資料，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL83之最後一張資料頁之中間有效位CSB，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL84之最後一張資料頁之最高有效位MSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL85之最後一張資料頁之最低有效位LSB，而對於第二 個群中在SLC資料區塊的偶數組字元線資料，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL83之最後一張資料頁之最高有效位MSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL84之最後一張資料頁之最低有效位LSB，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL84之最後一張資料頁之中間有效位CSB。 The corresponding check code of the word line data in the second group, as indicated by 605B, is written and stored in the middle significant bit CSB and the most significant bit of the last data page of the word line WL83 of the TLC data block 1052 Significant bit MSB, the least significant bit LSB of the last data page of word line WL84 and the last data page of word line WL85, wherein for the odd-group word line data in the SLC data block in the second group , all the third part check codes generated by the third encoding engine are stored in the middle significant bit CSB of the last data page of the word line WL83 of the TLC data block 1052, and all the check codes generated by the first encoding engine The first part of the check code is stored in the most significant bit MSB of the last data page of the word line WL84 of the TLC data block 1052, and all the second part of the check code generated by the second encoding engine is stored in the TLC data The least significant bit LSB of the last data page of word line WL85 of block 1052, and for the second For the even word line data in the SLC data block in a group, all the first part check codes generated by the first encoding engine are stored in the last data page of the word line WL83 of the TLC data block 1052 The most significant bit MSB, all the second part of the check code generated by the second encoding engine is stored in the least significant bit LSB of the last data page of the word line WL84 of the TLC data block 1052, and is generated by the third encoding engine All generated third-part checksums are stored in the MSB CSB of the last data page of word line WL84 of TLC data block 1052 .

第三個群之字元線資料的對應校驗碼，如605C所標示，係寫入並儲存於TLC資料區塊1052之字元線WL126、127之最後一張資料頁(包括最低有效位LSB、中間有效位CSB與最高有效位MSB)，其中對於第三個群中在SLC資料區塊的奇數組字元線資料，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL126之最後一張資料頁之最低有效位LSB，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL127之最後一張資料頁之中間有效位CSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL127之最後一張資料頁之最高有效位MSB，而對於第三個群中在SLC資料區塊的偶數組字元線資料，由第一編碼引擎所產生之所有第一部分校驗碼係儲存於TLC資料區塊1052的字元線WL126之最後一張資料頁之中間有效位CSB，由第二編碼引擎所產生之所有第二部分校驗碼係儲存於TLC資料區塊1052的字元線WL126之最後一張資料頁之最高有效位MSB，由第三編碼引擎所產生之所有第三部分校驗碼係儲存於TLC資料區塊1052的字元線WL127之最後一張資料頁之最低有效位LSB。 The corresponding check code of the word line data of the third group, as indicated by 605C, is written and stored in the last data page (including the least significant bit LSB) of the word line WL126, 127 of the TLC data block 1052 , middle significant bit CSB and most significant bit MSB), wherein for the odd word line data in the SLC data block in the third group, all the third part check codes generated by the third encoding engine are stored in The least significant bit LSB of the last data page of the word line WL126 of the TLC data block 1052, all the first part check codes generated by the first encoding engine are stored on the word line WL127 of the TLC data block 1052 The CSB of the last data page, all the second part check codes generated by the second encoding engine are stored in the MSB of the last data page of the word line WL127 of the TLC data block 1052 , and for the even word line data in the SLC data block in the third group, all the first partial check codes generated by the first encoding engine are stored at the end of the word line WL126 of the TLC data block 1052 The middle significant bit CSB of a data page, all the second part check codes generated by the second encoding engine are stored in the most significant bit MSB of the last data page of the word line WL126 of the TLC data block 1052, All third-part checksums generated by the third encoding engine are stored in the LSB of the last data page of the word line WL127 of the TLC data block 1052 .

因此，當快閃記憶體模組105透過內部複製操作從該些SLC資料區塊1051A~1051C搬移寫入資料至TLC資料區塊1052時，如果檢測到兩字元線短路而造成例如TLC資料區塊1052之字元線WL0、WL1的兩資料頁(如框線610所標示)發生錯誤，快閃記憶體模組105可利用儲存於TLC資料區塊1052之字元線WL42之 最後一張資料頁之中間有效位CSB的第一部分校驗碼以及字元線WL0之其他資料頁的最低有效位LSB的資料，更正610所標記之字元線WL0之資料頁的最低有效位LSB的資料，利用儲存於TLC資料區塊1052之字元線WL42之最後一張資料頁之最高有效位MSB的第二部分校驗碼以及字元線WL0之其他資料頁的中間有效位CSB的資料，來更正610所標記之字元線WL0之資料頁的中間有效位CSB的資料，以及利用儲存於TLC資料區塊1052之字元線WL40之最後一張資料頁之最高有效位MSB的第三部分校驗碼以及字元線WL0之其他資料頁的最高有效位MSB的資料，來更正610所標記之字元線WL0之資料頁的最高有效位MSB的資料。相同地，快閃記憶體模組105可利用儲存於TLC資料區塊1052之字元線WL41之最後一張資料頁之最低有效位LSB的第一部分校驗碼以及字元線WL1之其他資料頁的最低有效位LSB的資料，來更正610所標記之字元線WL1之資料頁的最低有效位LSB的資料，利用儲存於TLC資料區塊1052之字元線WL41之最後一張資料頁之中間有效位CSB的第二部分校驗碼以及字元線WL1之其他資料頁的中間有效位CSB的資料，來更正610所標記之字元線WL1之資料頁的中間有效位CSB的資料，以及利用儲存於TLC資料區塊1052之字元線WL41之最後一張資料頁之最高有效位MSB的第三部分校驗碼以及字元線WL1之其他資料頁的最高有效位MSB的資料，來更正610所標記之字元線WL1之資料頁的最高有效位MSB的資料。 Therefore, when the flash memory module 105 transfers the written data from the SLC data blocks 1051A˜1051C to the TLC data block 1052 through the internal copy operation, if a two-word line short circuit is detected, such as the TLC data block The two data pages of the word lines WL0 and WL1 of the block 1052 (as indicated by the frame line 610) have errors, and the flash memory module 105 can use the word line WL42 stored in the TLC data block 1052 The first part of the check code of the middle significant bit CSB of the last data page and the data of the least significant bit LSB of other data pages of the word line WL0, correct the least significant bit LSB of the data page of the word line WL0 marked by 610 The data of the TLC data block 1052 is stored in the second part of the most significant bit MSB of the last data page of the word line WL42 of the TLC data block 1052 and the data of the middle significant bit CSB of the other data pages of the word line WL0 , to correct the data of the middle significant bit CSB of the data page of the word line WL0 marked by 610, and use the third most significant bit MSB of the last data page of the word line WL40 stored in the TLC data block 1052 Part of the parity code and the MSB data of other data pages of the word line WL0 are used to correct the MSB data of the data page of the word line WL0 marked by 610 . Similarly, the flash memory module 105 can use the first part of the check code stored in the least significant bit LSB of the last data page of the word line WL41 of the TLC data block 1052 and other data pages of the word line WL1 To correct the data of the least significant bit LSB of the data page of the word line WL1 marked by 610, use the data stored in the middle of the last data page of the word line WL41 of the TLC data block 1052 The second part of the check code of the valid bit CSB and the data of the middle valid bit CSB of other data pages of the word line WL1 are used to correct the data of the middle valid bit CSB of the data page of the word line WL1 marked by 610, and use Store the third part check code of the most significant bit MSB of the last data page of the word line WL41 of the TLC data block 1052 and the data of the most significant bit MSB of other data pages of the word line WL1 to correct 610 The data of the most significant bit MSB of the data page of word line WL1 is marked.

相似地，如果兩字元線短路而造成之錯誤是發生在超級區塊之任兩連續字元線的之連續資料頁(例如如615、620所標示的錯誤位置)，快閃記憶體模組105均可利用每一群組中一SLC資料區塊之最後6條字元線之最後一資料頁所儲存之相對應的校驗碼來更正錯誤。此外，如果是檢測到一字元線斷路或寫入失敗而造成TLC資料區塊1052之任一字元線的任一資料頁發生錯誤(亦即同一資料頁的三個有效位均出錯或是連續兩不同資料頁的不同有效位出錯)，則快閃記憶體模組105均可利用對應儲存之校驗碼來更正連續任意三個有效位的錯誤。 Similarly, if the error caused by the short circuit of two word lines occurs in the consecutive data pages of any two consecutive word lines of the super block (such as the error positions indicated by 615, 620), the flash memory module 105 can use the corresponding check code stored in the last data page of the last 6 word lines of an SLC data block in each group to correct errors. In addition, if an error occurs in any data page of any word line of the TLC data block 1052 due to detection of a word line disconnection or write failure (that is, all three valid bits of the same data page are wrong or If there are errors in different effective digits of two consecutive different data pages), the flash memory module 105 can use the correspondingly stored check codes to correct errors in any three consecutive effective digits.

也就是說，通過快閃記憶體控制器110寫入三個群的資料至快閃記憶體模組105內的多個SLC資料區塊1051A~1051C的校驗碼儲存位置管理設計，當快閃記憶體模組105通過內部複製將該些資料從多個SLC資料區塊1051A~1051C複製搬移寫入至TLC資料區塊時，如果檢測到一字元線斷路、兩字元線短路或寫入失敗的錯誤，均可由多個SLC資料區塊1051A~1051C儲存之校驗碼來進行更正。 That is to say, the flash memory controller 110 writes the data of three groups to the check code storage location management design of the plurality of SLC data blocks 1051A~1051C in the flash memory module 105, when the flash memory When the memory module 105 copies, moves and writes these data from multiple SLC data blocks 1051A~1051C to the TLC data block through internal copying, if it detects that one word line is disconnected, two word lines are short-circuited or written Failure errors can be corrected by the check codes stored in the multiple SLC data blocks 1051A˜1051C.

再者，本案上述的實施例亦適用於MLC資料區塊或QLC資料區塊等架構，當使用於MLC資料區塊時，上述三個群資料改為分類為兩個群的資料，而對於如果是執行互斥或運算的編碼操作，則改用兩個編碼引擎來實現，其他的條件則與前述使用於TLC資料區塊時相同；因此，如果是使用於QLC資料區塊時，上述三個群資料改為分類為四個群的資料，而對於如果是執行互斥或運算的編碼操作，則改用四個編碼引擎來實現，其他的條件則與前述使用於TLC資料區塊時相同；其他資料區塊的架構則依此類推。 Furthermore, the above-mentioned embodiment of this case is also applicable to structures such as MLC data blocks or QLC data blocks. When used in MLC data blocks, the above-mentioned three groups of data are classified into two groups of data, and if If it is an encoding operation that executes a mutually exclusive OR operation, use two encoding engines to implement it, and the other conditions are the same as when it is used in the TLC data block; therefore, if it is used in the QLC data block, the above three The group data is changed to be classified into four groups of data, and if it is an encoding operation that performs a mutually exclusive OR operation, four encoding engines are used to realize it, and other conditions are the same as those used in the TLC data block; The structure of other data blocks can be deduced by analogy.

以資料儲存的成本(overhead)來看，如果是採用兩個通道寫入兩個記憶體晶片，且每一記憶體晶片具有折疊平面設計使可同時寫入兩個區塊，則以一個SLC資料區塊的資料寫入而言，128條字元線共有8*128個資料頁，而僅需要使用到6個資料頁來儲存對應的校驗碼，成本的百分比不到1%(6/(128*8))，亦即對於SLC資料區塊的寫入以及TLC資料區塊的寫入，只需使用低於1%的資料空間作為儲存相對應的錯誤更正校驗碼之用，資料空間的使用效率極高。而如果是採用4個通道寫入4個記憶體晶片，且每一記憶體晶片具有折疊平面設計使可同時寫入2個區塊，則以一個SLC資料區塊的資料寫入而言，128條字元線共有4*4*2*128個資料頁，而僅需要使用到6個資料頁來儲存對應的校驗碼，成本的百分比將可更低，約為0.15%(6/(128*4*4*2))，亦即對於SLC資料區塊的寫入以及TLC資料區塊的寫入，只需使用約為0.15%的資料空間作為儲存相對應的錯誤更正校驗碼之用，資料空間的使用效率更高。 In terms of data storage overhead, if two channels are used to write two memory chips, and each memory chip has a folded planar design so that two blocks can be written at the same time, then one SLC data In terms of data writing in the block, there are 8*128 data pages in total for 128 word lines, and only 6 data pages are needed to store the corresponding check code, and the percentage of the cost is less than 1% (6/( 128*8)), that is, for the writing of the SLC data block and the writing of the TLC data block, it only needs to use less than 1% of the data space for storing the corresponding error correction check code. The data space The use efficiency is extremely high. And if 4 channels are used to write 4 memory chips, and each memory chip has a folded plane design so that 2 blocks can be written at the same time, then in terms of data writing of one SLC data block, 128 There are 4*4*2*128 data pages in total for a character line, and only 6 data pages are needed to store the corresponding check code, the percentage of cost will be lower, about 0.15% (6/(128 *4*4*2)), that is, for the writing of the SLC data block and the writing of the TLC data block, only about 0.15% of the data space is used for storing the corresponding error correction check code , more efficient use of data space.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:快閃記憶體裝置 100: flash memory device

105:快閃記憶體模組 105:Flash memory module

110:快閃記憶體控制器 110: Flash memory controller

1051A,1051B,1051C:SLC資料區塊 1051A, 1051B, 1051C: SLC data block

1052:TLC資料區塊 1052: TLC data block

1101:錯誤更正碼編碼電路 1101: error correction code encoding circuit

1102:校驗碼緩衝器 1102: check code buffer

1102A,1102B:緩衝區 1102A, 1102B: buffer zone

Claims (13)

一種快閃記憶體裝置，包含有：一快閃記憶體模組，包括N個第一資料區塊以及至少一第二資料區塊；以及一快閃記憶體控制器，具有複數條通道分別連接至該快閃記憶體模組，該快閃記憶體控制器係用來將一筆資料寫入至該快閃記憶體模組，該快閃記憶體控制器分別執行單層單元資料寫入(SLC program)並執行一應用於容錯式磁碟陣列的資料管理機制之一錯誤更正編碼操作產生該筆資料之一對應的校驗碼，以及依據該至少一第二資料區塊之一亂數種子數(randomizer seed)規則，將該筆資料中的N個群的資料以及該對應的校驗碼中的該N個群的資料所對應的N個校驗碼分別寫入至該N個第一資料區塊，令該快閃記憶體模組將該N個第一資料區塊所分別儲存之該N個群的資料以及該N個校驗碼，複製搬移至該至少一第二資料區塊，其中該N個第一資料區塊中的一單元所儲存之資訊的一位元數不同於該至少一第二資料區塊中的一單元所儲存之資訊的一位元數。 A flash memory device, comprising: a flash memory module, including N first data blocks and at least one second data block; and a flash memory controller, with a plurality of channels respectively connected To the flash memory module, the flash memory controller is used to write a piece of data into the flash memory module, and the flash memory controller executes single-level cell data writing (SLC program) and execute an error correction coding operation applied to a data management mechanism of a fault-tolerant disk array to generate a corresponding check code of the data, and a random number seed number based on the at least one second data block (randomizer seed) rule, write the N groups of data in the data and the N check codes corresponding to the N groups of data in the corresponding check codes to the N first data respectively blocks, so that the flash memory module copies and moves the data of the N groups and the N verification codes respectively stored in the N first data blocks to the at least one second data block, Wherein the number of one bit of information stored in a unit of the N first data blocks is different from the number of one bit of information stored in a unit of the at least one second data block. 如申請專利範圍第1項所述之快閃記憶體裝置，其中該N個第一資料區塊中的該單元儲存2位元的資訊，以及該至少一第二資料區塊中的一單元儲存2N位元的資訊，N大於等於2並為整數。 The flash memory device as described in item 1 of the scope of the patent application, wherein the unit in the N first data blocks stores 2-bit information, and a unit in the at least one second data block stores 2N-bit information, N is greater than or equal to 2 and is an integer. 如申請專利範圍第2項所述之快閃記憶體裝置，其中N等於3，該至少一第二資料區塊為一TLC資料區塊，該快閃記憶體控制器係將該筆資料分類為三個群的資料，以分別寫入至三個SLC資料區塊。 The flash memory device described in item 2 of the scope of the patent application, wherein N is equal to 3, the at least one second data block is a TLC data block, and the flash memory controller classifies the data as The data of the three groups can be respectively written into the three SLC data blocks. 如申請專利範圍第1項所述之快閃記憶體裝置，其中該N個第一資 料區塊為N個SLC資料區塊，當快閃記憶體控制器寫入資料至一群的資料至一SLC資料區塊時，該快閃記憶體控制器係將該SLC資料區塊的所有字元線(word line)依順序每M條字元線編類為一組字元線，以產生複數組奇數組的字元線及複數組偶數組的字元線，以及對該複數組奇數組的字元線及該複數組偶數組的字元線，分別執行不同次的里德-所羅門碼的編碼操作，產生該複數組奇數組的字元線的一第一校驗碼與該複數組偶數組的字元線的一第二校驗碼，寫入並儲存該第一校驗碼於該複數組奇數組字元線中最後一組字元線之最後一條字元線的最後複數張資料頁、寫入並儲存該第二校驗碼於該複數組偶數組字元線中最後一組字元線之最後一條字元線的最後複數張資料頁。 The flash memory device as described in item 1 of the scope of the patent application, wherein the N first capital The material block is N SLC data blocks. When the flash memory controller writes data to a group of data to an SLC data block, the flash memory controller will write all the words of the SLC data block The word line (word line) is sorted into a group of word lines every M word lines in sequence, so as to generate the word lines of the odd group of complex groups and the word lines of the even group of complex groups, and the word lines of the odd group of complex groups The word lines of the word lines of the complex array and the word lines of the even array of the complex array respectively perform different times of Reed-Solomon code encoding operations to generate a first check code of the word lines of the odd array of the complex array and the word line of the complex array A second check code of the word lines of the even group, write and store the first check code in the last multiple sheets of the last word line of the last word line of the last group of word lines in the odd group of word lines For the data page, write and store the second check code in the last multiple data pages of the last word line of the last group of word lines in the plurality of even word lines. 如申請專利範圍第1項所述之快閃記憶體裝置，其中當進行記憶體垃圾回收(garbage collection)時，該快閃記憶體控制器係從外部讀取出該N個第一資料區塊之資料並進行重新編碼與寫入，或從外部讀取出該至少一第二資料區塊並進行重新編碼與寫入。 The flash memory device as described in item 1 of the scope of the patent application, wherein when performing memory garbage collection (garbage collection), the flash memory controller reads out the N first data blocks from the outside and re-encode and write the data, or read the at least one second data block from the outside and re-encode and write. 如申請專利範圍第1項所述之快閃記憶體裝置，其中當寫入資料至該至少一第二資料區塊且突然發生關機時，該快閃記憶體控制器係放棄該至少一第二資料區塊所儲存之資料，並執行一內部複製，從該些複數第一資料區塊搬移寫入資料至該至少一第二資料區塊。 The flash memory device as described in item 1 of the scope of the patent application, wherein when writing data to the at least one second data block and suddenly shutting down, the flash memory controller abandons the at least one second data block The data stored in the data block is executed internally, and the written data is moved from the plurality of first data blocks to the at least one second data block. 一種快閃記憶體儲存管理方法，其係用於一快閃記憶體模組，該快閃記憶體模組包括N個第一資料區塊以及至少一第二資料區塊，該方法包含有：分別執行單層單元資料寫入以及執行一應用於容錯式磁碟陣列的資料管理 機制之一錯誤更正編碼操作產生一筆資料之一對應的校驗碼；以及依據該至少一第二資料區塊之一亂數種子數規則，將該筆資料中的N個群的資料以及該對應的校驗碼中的該N個群的資料所對應的N個校驗碼分別寫入至該N個第一資料區塊，令該快閃記憶體模組將該N個第一資料區塊所分別儲存之該N個群的資料以及該N個校驗碼寫入至該至少一第二資料區塊，其中該N個第一資料區塊中的一單元所儲存之資訊的一位元數不同於該至少一第二資料區塊中的一單元所儲存之資訊的一位元數。 A flash memory storage management method, which is used in a flash memory module, the flash memory module includes N first data blocks and at least one second data block, the method includes: Perform single-level cell data writes and perform data management for fault-tolerant disk arrays, respectively An error correction coding operation of the mechanism generates a check code corresponding to one of the data; and according to a random number seed number rule of the at least one second data block, the data of N groups in the data and the corresponding The N check codes corresponding to the data of the N groups in the check codes are respectively written into the N first data blocks, so that the flash memory module makes the N first data blocks The respectively stored data of the N groups and the N check codes are written into the at least one second data block, wherein one bit of information stored in a unit of the N first data blocks The number is different from a one-bit number of information stored in a cell in the at least one second data block. 如申請專利範圍第7項所述之快閃記憶體儲存管理方法，其中該N個第一資料區塊中的該單元儲存2位元的資訊，以及該至少一第二資料區塊中的一單元儲存2N位元的資訊，N大於等於2並為整數。 The flash memory storage management method described in item 7 of the scope of the patent application, wherein the unit in the N first data blocks stores 2-bit information, and one of the at least one second data blocks The unit stores information of 2 N bits, and N is greater than or equal to 2 and is an integer. 如申請專利範圍第8項所述之快閃記憶體儲存管理方法，其中N等於3，該至少一第二資料區塊為一TLC資料區塊，以及該筆資料係被分類為三個群的資料。 The flash memory storage management method described in item 8 of the scope of the patent application, wherein N is equal to 3, the at least one second data block is a TLC data block, and the data is classified into three groups material. 如申請專利範圍第7項所述之快閃記憶體儲存管理方法，其中該N個第一資料區塊為N個SLC資料區塊，以及該快閃記憶體儲存管理方法另包括：當寫入資料至一群的資料至一SLC資料區塊時，將該SLC資料區塊的所有字元線依順序每M條字元線編類為一組字元線，以產生複數組奇數組的字元線及複數組偶數組的字元線；對於該複數組奇數組的字元線及該複數組偶數組的字元線，分別執行不同次的里德-所羅門碼的編碼操作，產生該複數組奇數組的字元線的一第一校驗碼與該複數組偶數組的字元線的一第二校驗碼；以及 寫入並儲存該第一校驗碼於該複數組奇數組字元線中最後一組字元線之最後一條字元線的最後複數張資料頁、寫入並儲存該第二校驗碼於該複數組偶數組字元線中最後一組字元線之最後一條字元線的最後複數張資料頁。 As the flash memory storage management method described in item 7 of the scope of the patent application, wherein the N first data blocks are N SLC data blocks, and the flash memory storage management method further includes: when writing When the data is grouped into a SLC data block, all the word lines of the SLC data block are sorted into a group of word lines every M word lines in sequence, so as to generate a plurality of odd numbers of characters line and the word line of the complex even array; for the word line of the odd array of the complex array and the word line of the even array of the complex array, respectively perform different encoding operations of the Reed-Solomon code to generate the complex array a first check code of the word lines of the odd set and a second check code of the word lines of the complex even set; and Write and store the first check code in the last multiple data pages of the last word line in the last group of word lines in the odd array of word lines, write and store the second check code in The last plurality of data pages of the last word line of the last group of word lines in the plurality of even groups of word lines. 如申請專利範圍第7項所述之快閃記憶體儲存管理方法，其另包含有：當進行記憶體垃圾回收時，從外部讀取出該N個第一資料區塊之資料並進行重新編碼與寫入，或從外部讀取出該至少一第二資料區塊並進行重新編碼與寫入。 The flash memory storage management method described in item 7 of the scope of the patent application further includes: when performing memory garbage collection, reading the data of the N first data blocks from the outside and recoding and write, or read the at least one second data block from outside and re-encode and write. 如申請專利範圍第7項所述之快閃記憶體儲存管理方法，其另包含有：當寫入資料至該至少一第二資料區塊且突然發生關機時，放棄該至少一第二資料區塊所儲存之資料，並執行一內部複製，從該些複數第一資料區塊搬移寫入資料至該至少一第二資料區塊。 The flash memory storage management method described in item 7 of the scope of the patent application further includes: when writing data to the at least one second data block and suddenly shutting down, abandoning the at least one second data block block, and perform an internal copy to move and write data from the plurality of first data blocks to the at least one second data block. 一種快閃記憶體控制器，包含：複數條通道，分別連接至一快閃記憶體模組，該快閃記憶體模組包括N個第一資料區塊以及至少一第二資料區塊；以及一錯誤更正碼編碼電路；其中該快閃記憶體控制器用來將一筆資料寫入至該快閃記憶體模組，分別執行單層單元資料寫入並採用該錯誤更正碼編碼電路來執行一應用於容錯式磁碟陣列的資料管理機制之一錯誤更正編碼操作產生該筆資料之 一對應的校驗碼，以及依據該至少一第二資料區塊之一亂數種子數規則，將該筆資料中的N個群的資料以及該對應的校驗碼中的該N個群的資料所對應的N個校驗碼分別寫入至該N個第一資料區塊，其中該N個第一資料區塊中的一單元儲存2位元的資料，令該快閃記憶體模組將該N個第一資料區塊所分別儲存之該N個群的資料以及該N個校驗碼，複製搬移至該至少一第二資料區塊，其中該N個第一資料區塊中的一單元所儲存之資訊的一位元數不同於該至少一第二資料區塊中的一單元所儲存之資訊的一位元數。 A flash memory controller, comprising: a plurality of channels respectively connected to a flash memory module, the flash memory module includes N first data blocks and at least one second data block; and An error correction code encoding circuit; wherein the flash memory controller is used to write a piece of data into the flash memory module, respectively execute single-layer unit data writing and use the error correction code encoding circuit to execute an application One of the data management mechanisms of the fault-tolerant disk array, the error correction coding operation generates the data A corresponding check code, and according to a random number seed number rule of the at least one second data block, the data of the N groups in the data and the N groups in the corresponding check code The N check codes corresponding to the data are respectively written into the N first data blocks, wherein a unit in the N first data blocks stores 2-bit data, so that the flash memory module The data of the N groups and the N verification codes respectively stored in the N first data blocks are copied and moved to the at least one second data block, wherein in the N first data blocks A bit of information stored in a unit is different from a bit of information stored in a unit of the at least one second data block.
TW111106129A 2016-04-27 2017-02-24 Flash memory apparatus, flash memory controller, and storage management method for flash memory TWI797996B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662328025P 2016-04-27 2016-04-27
US62/328,025 2016-04-27

Publications (2)

Publication Number Publication Date
TW202223651A TW202223651A (en) 2022-06-16
TWI797996B true TWI797996B (en) 2023-04-01

Family

ID=61022891

Family Applications (13)

Application Number Title Priority Date Filing Date
TW108110612A TWI689930B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW110130076A TWI771151B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW107132887A TWI659423B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW109105951A TWI707345B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW106144650A TWI650755B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW106105508A TWI618070B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW109130011A TWI740629B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW111121269A TWI806649B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW112106392A TWI812576B (en) 2016-04-27 2017-02-24 Flash memory apparatus, flash memory controller, and storage management method for flash memory
TW111106129A TWI797996B (en) 2016-04-27 2017-02-24 Flash memory apparatus, flash memory controller, and storage management method for flash memory
TW106106328A TWI643062B (en) 2016-04-27 2017-02-24 Flash memory apparatus and storage management method for flash memory
TW109100013A TWI759673B (en) 2016-04-27 2017-02-24 Flash memory apparatus, flash memory controller, and storage management method for flash memory
TW107136718A TWI684857B (en) 2016-04-27 2017-02-24 Flash memory apparatus and storage management method for flash memory

Family Applications Before (9)

Application Number Title Priority Date Filing Date
TW108110612A TWI689930B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW110130076A TWI771151B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW107132887A TWI659423B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW109105951A TWI707345B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW106144650A TWI650755B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW106105508A TWI618070B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW109130011A TWI740629B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW111121269A TWI806649B (en) 2016-04-27 2017-02-20 Flash memory apparatus and storage management method for flash memory
TW112106392A TWI812576B (en) 2016-04-27 2017-02-24 Flash memory apparatus, flash memory controller, and storage management method for flash memory

Family Applications After (3)

Application Number Title Priority Date Filing Date
TW106106328A TWI643062B (en) 2016-04-27 2017-02-24 Flash memory apparatus and storage management method for flash memory
TW109100013A TWI759673B (en) 2016-04-27 2017-02-24 Flash memory apparatus, flash memory controller, and storage management method for flash memory
TW107136718A TWI684857B (en) 2016-04-27 2017-02-24 Flash memory apparatus and storage management method for flash memory

Country Status (2)

Country Link
CN (1) CN111710358B (en)
TW (13) TWI689930B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI656442B (en) * 2017-11-30 2019-04-11 慧榮科技股份有限公司 Method for access control in a memory device, and memory device and controller thereof
US10956049B2 (en) 2019-06-12 2021-03-23 International Business Machines Corporation Wear-aware block mode conversion in non-volatile memory
CN112130749B (en) * 2019-06-25 2023-12-22 慧荣科技股份有限公司 Data storage device and non-volatile memory control method
US11119855B2 (en) 2019-10-24 2021-09-14 International Business Machines Corporation Selectively storing parity data in different types of memory
US11573737B2 (en) * 2020-03-02 2023-02-07 Silicon Motion, Inc. Method and apparatus for performing disk management of all flash array server
US11809748B2 (en) * 2022-03-10 2023-11-07 Silicon Motion, Inc. Control method of flash memory controller and associated flash memory controller and electronic device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM369528U (en) * 2008-08-05 2009-11-21 Super Talent Electronics Inc Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices
US20120173920A1 (en) * 2010-12-30 2012-07-05 Seong Hun Park Memory system and method of operating the same
TW201535114A (en) * 2013-12-09 2015-09-16 Ibm Recording dwell time in a non-volatile memory system
TW201603047A (en) * 2013-08-23 2016-01-16 慧榮科技股份有限公司 Methods for accessing a storage unit of a flash memory and apparatuses using the same
TW201612908A (en) * 2014-07-03 2016-04-01 Sandisk Technologies Inc On-chip copying of data between NAND flash memory and ReRAM of a memory die

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906961B2 (en) * 2003-06-24 2005-06-14 Micron Technology, Inc. Erase block data splitting
JP2008257773A (en) * 2007-04-02 2008-10-23 Toshiba Corp Nonvolatile semiconductor memory device, method for controlling the same, nonvolatile semiconductor memory system, and memory card
US8843691B2 (en) * 2008-06-25 2014-09-23 Stec, Inc. Prioritized erasure of data blocks in a flash storage device
US8898374B2 (en) * 2010-07-21 2014-11-25 Silicon Motion, Inc. Flash memory device and method for managing flash memory device
US8892981B2 (en) * 2010-09-30 2014-11-18 Apple Inc. Data recovery using outer codewords stored in volatile memory
WO2012161659A1 (en) * 2011-05-24 2012-11-29 Agency For Science, Technology And Research A memory storage device, and a related zone-based block management and mapping method
US9141533B2 (en) * 2012-05-31 2015-09-22 Silicon Motion, Inc. Data storage device and flash memory control method for performing garbage collection
US9417958B2 (en) * 2012-06-06 2016-08-16 Silicon Motion Inc. Flash memory control method, controller and electronic apparatus
US9286985B2 (en) * 2013-02-12 2016-03-15 Kabushiki Kaisha Toshiba Semiconductor device with power mode transitioning operation
US8656255B1 (en) * 2013-03-15 2014-02-18 Avalanche Technology, Inc. Method for reducing effective raw bit error rate in multi-level cell NAND flash memory
WO2015013689A2 (en) * 2013-07-25 2015-01-29 Aplus Flash Technology, Inc. Nand array hiarchical bl structures for multiple-wl and all -bl simultaneous erase, erase-verify, program, program-verify, and read operations
CN107193684B (en) * 2013-08-23 2020-10-16 慧荣科技股份有限公司 Method for accessing storage unit in flash memory and device using the same
CN104424127A (en) * 2013-08-23 2015-03-18 慧荣科技股份有限公司 Method for accessing storage unit in flash memory and device using the same
CN108447516B (en) * 2013-08-23 2020-04-24 慧荣科技股份有限公司 Method for accessing memory cell in flash memory and device using the same
US9262268B2 (en) * 2013-12-20 2016-02-16 Seagate Technology Llc Method to distribute user data and error correction data over different page types by leveraging error rate variations
US9361182B2 (en) * 2014-05-20 2016-06-07 Transcend Information, Inc. Method for read disturbance management in non-volatile memory devices
JP6313245B2 (en) * 2014-09-09 2018-04-18 東芝メモリ株式会社 Semiconductor memory device
KR102233074B1 (en) * 2014-10-08 2021-03-30 삼성전자주식회사 Storage device and reliability verification method thereof
US9959059B2 (en) * 2014-10-20 2018-05-01 Sandisk Technologies Llc Storage error management
KR20160046391A (en) * 2014-10-20 2016-04-29 삼성전자주식회사 Hybrid DIMM structure and Driving Method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM369528U (en) * 2008-08-05 2009-11-21 Super Talent Electronics Inc Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices
US20120173920A1 (en) * 2010-12-30 2012-07-05 Seong Hun Park Memory system and method of operating the same
TW201603047A (en) * 2013-08-23 2016-01-16 慧榮科技股份有限公司 Methods for accessing a storage unit of a flash memory and apparatuses using the same
TW201535114A (en) * 2013-12-09 2015-09-16 Ibm Recording dwell time in a non-volatile memory system
TW201612908A (en) * 2014-07-03 2016-04-01 Sandisk Technologies Inc On-chip copying of data between NAND flash memory and ReRAM of a memory die

Also Published As

Publication number Publication date
TW201907300A (en) 2019-02-16
TW202223651A (en) 2022-06-16
TW201738892A (en) 2017-11-01
TW202341158A (en) 2023-10-16
TWI740629B (en) 2021-09-21
TWI812576B (en) 2023-08-11
TW201903777A (en) 2019-01-16
TW202014890A (en) 2020-04-16
TW202324097A (en) 2023-06-16
TWI684857B (en) 2020-02-11
CN111710358A (en) 2020-09-25
TWI771151B (en) 2022-07-11
TWI618070B (en) 2018-03-11
TWI659423B (en) 2019-05-11
TWI650755B (en) 2019-02-11
TWI759673B (en) 2022-04-01
TWI707345B (en) 2020-10-11
TWI643062B (en) 2018-12-01
TW202147326A (en) 2021-12-16
TW202115732A (en) 2021-04-16
TW201928977A (en) 2019-07-16
TWI689930B (en) 2020-04-01
TWI806649B (en) 2023-06-21
TW201812583A (en) 2018-04-01
TW201810280A (en) 2018-03-16
CN111710358B (en) 2022-06-03
TW202238601A (en) 2022-10-01
TW202025163A (en) 2020-07-01
TW202343265A (en) 2023-11-01

Similar Documents

Publication Publication Date Title
CN107391026B (en) Flash memory device and flash memory management method
CN107403646B (en) Flash memory device and flash memory management method
TWI797996B (en) Flash memory apparatus, flash memory controller, and storage management method for flash memory
US20240154624A1 (en) Flash memory apparatus and storage management method for flash memory
TWI845371B (en) Flash memory apparatus, flash memory controller, and storage management method for flash memory
TWI841391B (en) Flash memory apparatus and storage management method for flash memory