TWI812308B - Clock signal generating device and clock signal generating method thereof - Google Patents

Abstract

A clock signal generator and a clock signal generating method are provided. The clock signal generator is adapted for a test machine. The clock signal generating device includes a first oscillator, a second oscillator, a delay value generator and an output clock signal generator. The first oscillator and the second oscillator are activated alternatively. The first oscillator generates a first clock signal with a first frequency according to a delay value. The second oscillator generates a second clock signal with a second frequency according to the delay value, where phases of the first clock signal and the second clock signal are different. The delay value generator detects a pulse width of a reference pulse signal to generate the delay value. The output clock signal generator combines the first clock signal and the second clock signal to generate an output clock signal.

Description

Clock signal generating device and clock signal generating method

The present invention relates to a clock signal generating device and a clock signal generating method, and in particular, to a clock signal generating device and a clock signal generating method applied to a testing machine.

In the testing operation of integrated circuits, it is often necessary to use a testing machine to provide a test clock signal for execution. Among them, when a high-frequency test clock signal is required, a high-end test machine can be used to perform the test, but this approach will cause a significant increase in test costs. Therefore, in the conventional technology, a general test machine can be used, and the frequency of the test clock signal provided by the test machine can be multiplied to increase the frequency of the test clock signal.

In the conventional technology, a cutting signal can be provided from the outside to cut the signal waveform according to the test clock signal provided by the test machine to complete the frequency doubling action. The transition edge of the frequency multiplied test clock signal generated by this method often becomes unstable and reduces the stability and accuracy of the test action.

The present invention provides a clock signal generating device and a clock signal generating method, which can provide a testing machine with a relatively high-frequency output clock signal.

The clock signal generating device of the present invention includes a first oscillator, a second oscillator, a delay generator and an output clock signal generator. The first oscillator is periodically started according to the first control signal, and the first oscillator generates a first clock signal with a first frequency according to the delay value. The second oscillator is periodically started according to the second control signal, and the second oscillator generates a second clock signal with a second frequency according to the delay value, wherein the phase of the first clock signal and the second clock signal is Are not the same. The delay value generator is coupled to the first oscillator and the second oscillator. The delay value generator detects the pulse width of the reference pulse signal to generate a delay value. The output clock signal generator is coupled to the first oscillator and the second oscillator, and combines the first clock signal and the second clock signal to generate an output clock signal.

The clock signal generating method of the present invention includes: providing a first oscillator to be activated periodically according to a first control signal and generating a first clock signal with a first frequency according to a delay value; and providing a second oscillator. The device is periodically activated according to the second control signal and generates a second clock signal with a second frequency according to the delay value, wherein the phases of the first clock signal and the second clock signal are different; detecting refer to the pulse width of the pulse signal to generate a delay value; and combine the first clock signal and the second clock signal to generate an output clock signal.

Based on the above, the clock signal generation device and the clock signal generation method of the present invention can generate an output clock signal by selecting two clock signals in time-division interleaving. In this way, the clock signal generating device can generate an output clock signal with a relatively high frequency. In the test action of the integrated circuit, the test clock signal for executing the test action can be accelerated to increase the execution speed of the test action.

Referring to FIG. 1 , the clock signal generating device 100 is suitable for testing machines of integrated circuits. The clock signal generating device 100 includes oscillators 110 and 120, a delay value generator 130 and an output clock signal generator 140. In this embodiment, the oscillator 110 is periodically activated according to the control signal TCKT, and the oscillator 110 generates a first clock signal CK1 with a first frequency according to the delay value DLV. The oscillator 120 can be periodically activated according to the control signal TCKC, and the oscillator 120 generates a second clock signal CK2 with a second frequency according to the delay value DLV. The first frequency and the second frequency may be the same.

Please note here that the control signals TCKT and TCKC can be two clock signals with opposite phases, and the frequency of the control signals TCKT and TCKC can be equal to the clock signal for testing that can be supplied by the testing machine. In this embodiment, the oscillators 110 and 120 can be respectively activated or deactivated according to the voltage values of the control signals TCKT and TCKC. Among them, when the control signal TCKT is a logic value 1 (the control signal TCKC is a logic value 0), the oscillator 110 is started and the oscillator 120 is turned off; when the control signal TCKT is a logic value 0 (the control signal TCKC is a logic value 1 ), oscillator 120 is started and oscillator 110 is turned off. That is to say, the oscillators 110 and 120 can be started up and shut down alternately.

In this embodiment, the control signal TCKT may be a test clock signal provided by the test machine.

The delay value generator 130 is coupled to the oscillators 110,120. The delay value generator 130 receives the reference pulse signal RPS and generates the delay value DLV according to the detected pulse width of the reference pulse signal RPS. In this embodiment, the reference pulse signal RPS provides a reference pulse wave. The pulse width of the reference pulse wave may be equal to half a period of the control signal TCKT. That is, the delay value generator 130 may generate the delay value DLV according to a half cycle of the control signal TCKT.

In this embodiment, the delay values DLV provided by the delay value generator 130 to the oscillators 110 and 120 may be the same.

The output clock signal generator 140 is coupled to the oscillators 110 and 120 . The output clock signal generator 140 receives the first clock signal CK1 and the second clock signal CK2 generated by the oscillators 110 and 120 respectively, and receives the control signals TCKT and TCKC. The output clock signal generator 140 is used to combine the first clock signal CK1 and the second clock signal CK2 to generate the output clock signal OCK. In detail, the output clock signal generator 140 can select to output the first clock signal CK1 or the second clock signal CK2 according to the control signals TCKT and TCKC to generate the output clock signal OCK. Specifically, when the control signal TCKT is a logic value 1 (the control signal TCKC is a logic value 0), the output clock signal generator 140 selects to output the first clock signal CK1 to generate the output clock signal OCK; when the control signal TCKT When the logic value is 0 (the control signal TCKC is a logic value 1), the output clock signal generator 140 selects to output the second clock signal CK2 to generate the output clock signal OCK.

The output clock signal OCK is generated by combining the first clock signal CK1 and the second clock signal CK2. The frequency of the output clock signal OCK generated by the output clock signal generator 140 may be the frequency of the first clock signal CK1 and the second clock signal CK2. The second clock signal CK2 is twice the frequency. The frequency of the first clock signal CK1 and the second clock signal CK2 generated based on the control signals TCKT and TCKC can be equal to the frequency of the control signals TCKT and TCKC. That is to say, the clock signal generating device 100 of the present invention The frequency of the generated output clock signal OCK may be twice the frequency of the control signals TCKT and TCKC. The clock signal generating device 100 can provide an output clock signal OCK as a test clock signal for performing test actions, which can speed up the test actions.

It is worth mentioning that the delay value generator 130 generates the delay value DLV based on the half cycle of the control signal TCKT, and the oscillators 110 and 120 generate the first clock signal CK1 and the second clock signal CK1 based on the delay value DLV. Pulse signal CK2. Therefore, the first clock signal CK1 and the second clock signal CK2 may be two clock signals with a fixed phase difference, and this phase difference may be associated with a half cycle of the control signal TCKT. Therefore, the output clock signal OCK generated by the clock signal generating device 100 can be a clock signal with a stable transition edge, so that the test operation can be performed stably.

Referring to FIG. 2 , the clock signal generating device 200 includes oscillators 210 and 220 , a delay value generator 230 composed of sub-delay value generators 231 and 232 , and an output clock signal generator 240 . In this embodiment, the oscillator 210 is a ring oscillator, including a delay string 211 and a logic gate LG1. The logic gate LG1 is coupled between the paths of the delay string 211 receiving the control signal TCKT. The two input terminals of the logic gate LG1 receive the control signal TCKT and the first clock signal CK1 respectively. The output terminal of the logic gate LG1 is coupled to the delay string 211 . input terminal.

In this embodiment, the logic gate LG1 may be a NAND gate. When the control signal TCKT is a logic value 1, the logic gate LG1 transmits the inverted signal of the first clock signal CK1 to the delay string 211 and causes the delay string 211 to delay the received signal (the first signal) according to the delay value DLV. The inverse signal of the clock signal CK1). In this way, the oscillator 210 can generate the first clock signal CK1 with a period equal to twice the delay value DLV.

The oscillator 220 is also a ring oscillator and includes a delay string 221 and a logic gate LG2. The logic gate LG2 is coupled between the paths of the delay string 221 receiving the control signal TCKC. The two input terminals of the logic gate LG1 receive the control signal TCKC and the first clock signal CK2 respectively. The output terminal of the logic gate LG2 is coupled to the delay string 221 . input terminal. The details of the operation of the oscillator 220 are similar to the details of the operation of the oscillator 210 and will not be described again here.

In this embodiment, the output clock signal generator 240 can be a signal selector and can be constructed using the logic gate LG3. Logic gate LG3 is a combined logic gate composed of two AND gates and one OR gate. The logic gate LG3 can perform an AND logic operation on the control signal TCKT and the first clock signal CK1 to generate the first signal. The logic gate LG3 can also perform an AND logic operation on the control signal TCKC and the second clock signal CK2 to generate the second signal. The logic gate LG3 performs an OR logic operation on the first signal and the second signal to generate the output clock signal OCK.

Different from the previous embodiment, the delay value generator 230 of this embodiment is split into two sub-delay value generators 231 and 232. The sub-delay value generators 231 and 232 are coupled to the oscillators 210 and 220 respectively, and are used to provide delay values DLV to the delay strings 211 and 221. The sub-delay value generators 231 and 232 receive the reference pulse signal RPS and detect the pulse width of the reference pulse signal RPS to generate the delay value DLV. In this embodiment, the delay values DLV generated by the sub-delay value generators 231 and 232 may be the same. Furthermore, the sub-delay value generator 231 and the sub-delay value generator 232 may have the same circuit architecture.

Please refer to FIG. 3 below. The delay value generator 300 includes a plurality of unit delays 311~31N and a plurality of samplers 321~32N. A plurality of unit delays 311~31N are coupled to each other in series to form a delay string. The unit delayer 311 of the first stage receives the reference pulse signal RPS, and the unit delays 311~31N sequentially delay the reference pulse signal RPS and generate a plurality of delayed pulse signals DRP1~DRPN respectively. The samplers 321~32N are coupled to the unit delays 311~31N respectively. The samplers 321 to 32N jointly receive the sampling clock signal CKS and the reset signal RST. The samplers 321 ~ 32N respectively sample the delayed pulse signals DRP1 ~ DRPN according to the sampling clock signal CKS, and generate a plurality of bits DLV1 ~ DLVN of the sampled values respectively.

In this embodiment, the samplers 321 to 32N may be D-type flip-flops.

In this embodiment, the unit delays 311 to 31N can respectively provide the same unit delay. The time length of the unit delay is smaller than the pulse width of the reference pulse on the reference pulse signal RPS. The sampling clock signal CKS may be one of the control signals TCKT and TCKC in the embodiment of FIG. 2 . The samplers 321 ~ 32N can generate a plurality of bits DLV1 ~ DLVN that are sample values of logical values 1, 1, ..., 0, and 0 according to the sampling action performed by the clock signal CKS. Among them, the number of bits with a continuous logic value 1 in the bits DLV1~DLVN can represent the pulse width of the reference pulse on the reference pulse signal RPS.

Please refer to FIG. 2 and FIG. 4 synchronously below, in which the sub-delay value generators 231 and 232 provide the same delay value DLV (having multiple bits DLV<1:N>) to the delay strings 211 and 221 . The oscillator 210 generates the first clock signal CK1 according to the delay value DLV and the control signal TCKT, and the oscillator 220 generates the second clock signal CK2 according to the delay value DLV and the control signal TCKC. The output clock signal generator 240 synthesizes the first clock signal CK1 and the second clock signal CK2 and generates the output clock signal OCK. In FIG. 4 , the control signals TCKT and TCKC have opposite phases. When the control signal TCKT is a logic value 1, the first clock signal CK1 may transition to a logic value 1. When the control signal TCKT is a logic value 0, the first clock signal CK1 remains equal to the logic value 0. In addition, when the control signal TCKC is a logic value 1, the second clock signal CK2 may transition to a logic value 1, and when the control signal TCKC is a logic value 0, the first clock signal CK2 remains equal to the logic value 0. Therefore, the first clock signal CK1 and the second clock signal CK2 can be clock signals with a certain phase difference, and the frequencies of the first clock signal CK1, the second clock signal CK2, the control signals TCKT and TCKC can be Are the same.

In addition, the output clock signal OCK may be a combination of the first clock signal CK1 and the second clock signal CK2. The frequency of the output clock signal OCK may be twice that of the first clock signal CK1 and the second clock signal CK2. Since the first clock signal CK1 and the second clock signal CK2 have a fixed phase difference, and the transition edges are not close to or overlap with each other, the clock signal generating device 200 can provide a stable output clock signal OCK. .

Referring to FIG. 5 , in step S510 , a first oscillator is provided to be started periodically according to a first control signal and to generate a first clock signal with a first frequency according to a delay value. In step S520, a second oscillator is provided to be periodically started according to the second control signal and to generate a second clock signal with a second frequency according to the delay value, wherein the first clock signal is consistent with the second clock signal. The pulse signals have different phases, but the first frequency and the second frequency can be the same. In step S530, the pulse width of the reference pulse signal is detected to generate a delay value. In step S540, the first clock signal and the second clock signal are combined to generate an output clock signal.

The implementation details of the above steps have been described in detail in the foregoing embodiments and implementation modes, and will not be described again here.

To sum up, the clock signal generating device of the present invention can use the test clock signal provided by the test machine as the control signal, and generate an output clock signal with double frequency accordingly. The clock signal generating device of the present invention can effectively maintain the stability of the output clock signal by staggeredly starting different oscillators and combining the clock signals generated by the two oscillators to generate an output clock signal. In addition to improving the speed of test actions, it can also ensure the stability and accuracy of test actions.

100, 200: Clock signal generating device 110, 120, 210, 220: Oscillator 130, 230, 300: Delay value generator 140, 240: Output clock signal generator 211, 221: Delay string 231, 232: Sub-delay value generator 311~31N: Unit delayer 321~32N: Sampler CK1, CK2: clock signal DLV: delay value DLV1~DLVN, DLV<1:N>: multiple bits of the sampled value DRP1~DRPN: delayed pulse signal LG1~LG3: logic gate OCK: Output clock signal RPS: reference pulse signal S510~S530: Clock signal generation steps TCKT, TCKC: control signal

FIG. 1 is a schematic diagram of a clock signal generating device according to an embodiment of the present invention. FIG. 2 is a schematic circuit diagram of a clock signal generating device according to another embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a delay value generator in a clock signal generating device according to an embodiment of the present invention. FIG. 4 shows an operation waveform diagram of the clock signal generating device according to the embodiment of the present invention. FIG. 5 is a flowchart illustrating a method for generating a clock signal suitable for testing operations of an integrated circuit according to an embodiment of the present invention.

100: Clock signal generating device

110, 120: Oscillator

130: Delay value generator

140: Output clock signal generator

CK1, CK2: clock signal

DLV: delay value

OCK: Output clock signal

RPS: reference pulse signal

TCKT, TCKC: control signal

Claims (16)

A clock signal generating device includes: a first oscillator, which is periodically activated according to a first control signal; the first oscillator, along with the periodic transition action of the first control signal, according to a first control signal delay value to generate a first clock signal with a first frequency; a second oscillator that is periodically activated according to a second control signal, and the second oscillator follows the period of the second control signal a permanent transition action to generate a second clock signal with a second frequency according to the delay value, wherein the phases of the first clock signal and the second clock signal are different; a delay value generator, The first oscillator and the second oscillator are coupled to detect the pulse width of a reference pulse signal to generate the delay value; and an output clock signal generator is coupled to the first oscillator and the third oscillator. Two oscillators combine the first clock signal and the second clock signal to generate an output clock signal. The clock signal generating device according to claim 1, wherein the phases of the first control signal and the second control signal are complementary. The clock signal generating device according to claim 2, wherein the pulse width of the reference pulse signal is equal to half of the period of the first control signal. The clock signal generating device according to claim 1, wherein the delay value generator includes: A plurality of unit delays are coupled to each other in series to form a delay string. The delay string receives the reference pulse signal. The unit delays respectively generate a plurality of delayed pulse signals; and a plurality of samplers, Corresponding to the unit delays respectively, the delayed pulse signals are sampled according to a sampling clock signal to generate multiple bits of the sampled value. The clock signal generation device of claim 1, wherein the delay value generator includes: a first sub-delay value generator coupled to the first oscillator for providing the delay value to the first oscillator ; And a second sub-delay value generator, coupled to the second oscillator, for providing the delay value to the second oscillator. The clock signal generating device of claim 1, wherein the first oscillator and the second oscillator are both ring oscillators. The clock signal generating device of claim 1, wherein the first oscillator further includes: a first delay string; and a first logic gate coupled between the paths through which the delay string receives the first control signal. , the two input terminals of the first logic gate receive the first control signal and the first clock signal respectively, and the output terminal of the first logic gate is coupled to the input terminal of the first delay string; the second oscillator further comprising: a second delay string; and A second logic gate is coupled between the paths through which the second delay string receives the second control signal. Two input terminals of the second logic gate receive the second control signal and the second clock signal respectively. The second delay string receives the second control signal. The output terminals of the two logic gates are coupled to the input terminals of the second delay string. The clock signal generating device of claim 7, wherein the first logic gate is an NAND gate, and the second logic gate is an NAND gate. The clock signal generating device as claimed in claim 1, wherein the output clock signal generator is a signal selector for selecting the first clock signal when the first control signal is a first logic value. As the output clock signal, when the second control signal is the first logic value, the second clock signal is selected as the output clock signal. The clock signal generation device as claimed in claim 8, wherein the output clock signal generator performs a logical operation on the first control signal and the first clock signal to generate a first signal, for the second control signal An AND logic operation is performed on the signal and the second clock signal to generate a second signal, and an OR logic operation is performed on the first signal and the second signal to generate the output clock signal. The clock signal generating device of claim 1, wherein the frequency of the output clock signal is twice the first frequency. A method for generating a clock signal, including: providing a first oscillator to be periodically activated according to a first control signal, and following the periodic transition action of the first control signal, according to a delay value. generating a first clock signal having a first frequency; A second oscillator is provided to be periodically activated according to a second control signal, and with the periodic transition action of the second control signal, a second oscillator having a second frequency is generated according to the delay value. a clock signal, wherein the phases of the first clock signal and the second clock signal are different; detecting the pulse width of a reference pulse signal to generate the delay value; and combining the first clock signal and the The second clock signal is used to generate an output clock signal. The generation method according to claim 12, wherein the step of detecting the pulse width of the reference pulse signal to generate the delay value includes: providing a delay string composed of a plurality of unit delayers coupled to each other in series; The delay string receives the reference pulse signal, and sequentially delays the reference pulse signal to generate a plurality of delayed pulse signals; and samples the delayed pulse signals according to a sampling clock signal to generate the sample value Multiple bits. The generation method of claim 12, wherein the step of combining the first clock signal and the second clock signal to generate the output clock signal includes: selecting when the first control signal is a first logic value. The first clock signal is used as the output clock signal; and when the second control signal is the first logic value, the second clock signal is selected as the output clock signal. The method of claim 16, wherein the first clock signal is selected as the output clock signal when the first control signal is the first logic value. when the second control signal is the first logic value, the step of selecting the second clock signal as the output clock signal includes: performing an AND logic on the first control signal and the first clock signal operate to generate a first signal; perform an AND logical operation on the second control signal and the second clock signal to generate a second signal; and perform an OR logical operation on the first signal and the second signal to generate the Output clock signal. The generating method of claim 12, further comprising: performing a logical operation on the first control signal and the first clock signal to generate a first operation result, and transmitting the first operation result to the first an oscillator; and perform the logical operation on the second control signal and the second clock signal to generate a second operation result, and transmit the second operation result to the second oscillator.

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