TWI812308B - Clock signal generating device and clock signal generating method thereof - Google Patents
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本發明是有關於一種時脈信號產生裝置以及時脈信號的產生方法,且特別是有關於一種應用於測試機台的時脈信號產生裝置以及時脈信號的產生方法。The present invention relates to a clock signal generating device and a clock signal generating method, and in particular, to a clock signal generating device and a clock signal generating method applied to a testing machine.
在積體電路的測試動作中,常需要應用測試機以提供測試時脈信號來執行。其中,當需要高頻率的測試時脈信號時,可選用高階的測試機台來執行,但這樣的作法會造成測試成本大幅的增加。因此,在習知技術中,可應用一般的測試機台,並透過使測試機台所提供的測試時脈信號產生倍頻,以提升測試時脈信號的頻率。In the testing operation of integrated circuits, it is often necessary to use a testing machine to provide a test clock signal for execution. Among them, when a high-frequency test clock signal is required, a high-end test machine can be used to perform the test, but this approach will cause a significant increase in test costs. Therefore, in the conventional technology, a general test machine can be used, and the frequency of the test clock signal provided by the test machine can be multiplied to increase the frequency of the test clock signal.
在習知技術中,可由外部提供一個切割信號,來針對測試機台所提供的測試時脈信號進行信號波形切割,來完成倍頻的動作。這種作法所產生的倍頻後的測試時脈信號的轉態緣,常發生不穩定的現象,並降低測試動作的穩定性及準確度。In the conventional technology, a cutting signal can be provided from the outside to cut the signal waveform according to the test clock signal provided by the test machine to complete the frequency doubling action. The transition edge of the frequency multiplied test clock signal generated by this method often becomes unstable and reduces the stability and accuracy of the test action.
本發明提供一種時脈信號產生裝置以及時脈信號的產生方法,可提供測試機台依據有相對高頻率的輸出時脈信號。The present invention provides a clock signal generating device and a clock signal generating method, which can provide a testing machine with a relatively high-frequency output clock signal.
本發明的時脈信號產生裝置包括第一振盪器、第二振盪器、遲值產生器以及輸出時脈信號產生器。第一振盪器根據第一控制信號以被週期性的啟動,第一振盪器根據延遲值以產生具有第一頻率的第一時脈信號。第二振盪器根據第二控制信號以被週期性的啟動,第二振盪器根據延遲值以產生具有第二頻率的第二時脈信號,其中第一時脈信號與第二時脈信號的相位不相同。延遲值產生器耦接第一振盪器以及第二振盪器。延遲值產生器偵測參考脈波信號的脈波寬度以產生延遲值。輸出時脈信號產生器耦接第一振盪器以及第二振盪器,結合第一時脈信號與第二時脈信號以產生輸出時脈信號。The clock signal generating device of the present invention includes a first oscillator, a second oscillator, a delay generator and an output clock signal generator. The first oscillator is periodically started according to the first control signal, and the first oscillator generates a first clock signal with a first frequency according to the delay value. The second oscillator is periodically started according to the second control signal, and the second oscillator generates a second clock signal with a second frequency according to the delay value, wherein the phase of the first clock signal and the second clock signal is Are not the same. The delay value generator is coupled to the first oscillator and the second oscillator. The delay value generator detects the pulse width of the reference pulse signal to generate a delay value. The output clock signal generator is coupled to the first oscillator and the second oscillator, and combines the first clock signal and the second clock signal to generate an output clock signal.
本發明的時脈信號的產生方法包括:提供第一振盪器以根據第一控制信號以被週期性的啟動,並根據延遲值以產生具有第一頻率的第一時脈信號;提供第二振盪器以根據第二控制信號以被週期性的啟動,並根據延遲值以產生具有第二頻率的第二時脈信號,其中第一時脈信號與第二時脈信號的相位不相同;偵測參考脈波信號的脈波寬度以產生延遲值;以及,結合第一時脈信號與第二時脈信號以產生輸出時脈信號。The clock signal generating method of the present invention includes: providing a first oscillator to be activated periodically according to a first control signal and generating a first clock signal with a first frequency according to a delay value; and providing a second oscillator. The device is periodically activated according to the second control signal and generates a second clock signal with a second frequency according to the delay value, wherein the phases of the first clock signal and the second clock signal are different; detecting refer to the pulse width of the pulse signal to generate a delay value; and combine the first clock signal and the second clock signal to generate an output clock signal.
基於上述,本發明的時脈信號產生裝置及其時脈信號的產生方法可透過分時交錯的選擇兩個時脈信號以產生輸出時脈信號。如此一來,時脈信號產生裝置可產生具有相對高頻率的輸出時脈信號。在積體電路的測試動作中,可使執行測試動作的測試時脈信號被加速,提升測試動作的執行速率。Based on the above, the clock signal generation device and the clock signal generation method of the present invention can generate an output clock signal by selecting two clock signals in time-division interleaving. In this way, the clock signal generating device can generate an output clock signal with a relatively high frequency. In the test action of the integrated circuit, the test clock signal for executing the test action can be accelerated to increase the execution speed of the test action.
請參照圖1,時脈信號產生裝置100適用於積體電路的測試機台。時脈信號產生裝置100包括振盪器110、120、延遲值產生器130以及輸出時脈信號產生器140。在本實施例中,振盪器110根據控制信號TCKT以被週期性的啟動,振盪器110根據延遲值DLV以產生具有第一頻率的一第一時脈信號CK1。振盪器120則可根據控制信號TCKC以被週期性的啟動,振盪器120根據延遲值DLV以產生具有第二頻率的一第二時脈信號CK2。其中,第一頻率與第二頻率可以是相同的。Referring to FIG. 1 , the clock signal generating
在此請注意,控制信號TCKT以及TCKC可以是相位相反的二時脈信號,控制信號TCKT以及TCKC的頻率則可以與測試機台所可以供應的測試用的時脈信號相等。在本實施例中,振盪器110以及120可分別根據控制信號TCKT以及TCKC的電壓值來別被啟動或關閉。其中,當控制信號TCKT為邏輯值1時(控制信號TCKC為邏輯值0),振盪器110被啟動而振盪器120被關閉;當控制信號TCKT為邏輯值0時(控制信號TCKC為邏輯值1),振盪器120被啟動而振盪器110被關閉。也就是說,振盪器110、120可交錯被啟動及關閉。Please note here that the control signals TCKT and TCKC can be two clock signals with opposite phases, and the frequency of the control signals TCKT and TCKC can be equal to the clock signal for testing that can be supplied by the testing machine. In this embodiment, the
在本實施例中,控制信號TCKT可以為測試機台所可以提供的測試時脈信號。In this embodiment, the control signal TCKT may be a test clock signal provided by the test machine.
延遲值產生器130耦接至振盪器110、120。延遲值產生器130接收參考脈波信號RPS,並根據偵測參考脈波信號RPS的脈波寬度以產生延遲值DLV。在本實施例中,參考脈波信號RPS提供一參考脈波。參考脈波的脈波寬度可等於控制信號TCKT的半個週期。也就是說,延遲值產生器130可根據控制信號TCKT的半個週期來產生延遲值DLV。The
在本實施例中,延遲值產生器130提供至振盪器110、120的延遲值DLV可以是相同的。In this embodiment, the delay values DLV provided by the
輸出時脈信號產生器140耦接振盪器110以及120。輸出時脈信號產生器140接收振盪器110以及120分別產生的第一時脈信號CK1以及第二時脈信號CK2,並接收控制信號TCKT以及TCKC。輸出時脈信號產生器140用以結合第一時脈信號CK1與第二時脈信號CK2以產生輸出時脈信號OCK。在細節上,輸出時脈信號產生器140則可根據控制信號TCKT以及TCKC來選擇輸出第一時脈信號CK1或第二時脈信號CK2以產生輸出時脈信號OCK。具體來說,當控制信號TCKT為邏輯值1時(控制信號TCKC為邏輯值0),輸出時脈信號產生器140選擇輸出第一時脈信號CK1以產生輸出時脈信號OCK;當控制信號TCKT為邏輯值0時(控制信號TCKC為邏輯值1),輸出時脈信號產生器140選擇輸出第二時脈信號CK2以產生輸出時脈信號OCK。The output
透過結合第一時脈信號CK1以及第二時脈信號CK2來產生輸出時脈信號OCK,輸出時脈信號產生器140所產生的輸出時脈信號OCK的頻率可以為第一時脈信號CK1以及第二時脈信號CK2的頻率的兩倍。而基於控制信號TCKT、TCKC所產生的第一時脈信號CK1以及第二時脈信號CK2,其頻率可與控制信號TCKT、TCKC的頻率相等,也就是說,本發明的時脈信號產生裝置100所產生的輸出時脈信號OCK的頻率可以為控制信號TCKT、TCKC的頻率的兩倍。時脈信號產生裝置100則可提供輸出時脈信號OCK以作為進行測試動作的測試時脈信號,可加快測試動作的進行。The output clock signal OCK is generated by combining the first clock signal CK1 and the second clock signal CK2. The frequency of the output clock signal OCK generated by the output
值得一提的,由於延遲值產生器130是基於控制信號TCKT的半個週期來產生延遲值DLV,而振盪器110、120則是根據延遲值DLV來產生第一時脈信號CK1以及第二時脈信號CK2。因此,第一時脈信號CK1以及第二時脈信號CK2可以為具有固定相位差的二時脈信號,且這個相位差可與控制信號TCKT的半個週期相關聯。也因此,時脈信號產生裝置100所產生的輸出時脈信號OCK可以為具有穩定的轉態緣的時脈信號,可使測試動作穩定的被進行。It is worth mentioning that the
請參照圖2,時脈信號產生裝置200包括振盪器210、220、由子延遲值產生器231、232所構成的延遲值產生器230以及輸出時脈信號產生器240。在本實施例中,振盪器210為一環形振盪器(ring oscillator),包括延遲串211以及邏輯閘LG1。邏輯閘LG1耦接在延遲串211接收控制信號TCKT的路徑間,邏輯閘LG1的二輸入端分別接收控制信號TCKT以及第一時脈信號CK1,邏輯閘LG1的輸出端耦接至延遲串211的輸入端。Referring to FIG. 2 , the clock
在本實施例中,邏輯閘LG1可以為反及閘(NAND Gate)。邏輯閘LG1在當控制信號TCKT為邏輯值1時通過第一時脈信號CK1的反向信號以傳送至延遲串211中,並使延遲串211根據延遲值DLV以延遲所接收的信號(第一時脈信號CK1的反向信號)。如此一來,振盪器210可產生週期等於兩倍的延遲值DLV的第一時脈信號CK1。In this embodiment, the logic gate LG1 may be a NAND gate. When the control signal TCKT is a
振盪器220同樣為一環形振盪器,包括延遲串221以及邏輯閘LG2。邏輯閘LG2耦接在延遲串221接收控制信號TCKC的路徑間,邏輯閘LG1的二輸入端分別接收控制信號TCKC以及第一時脈信號CK2,邏輯閘LG2的輸出端耦接至延遲串221的輸入端。振盪器220的動作細節與振盪器210的動作細節相類似,在此恕不多贅述。The
在本實施例中,輸出時脈信號產生器240可以為信號選擇器,並可應用邏輯閘LG3來建構。邏輯閘LG3為二及閘與一或閘所組合成的組合式邏輯閘。邏輯閘LG3可針對控制信號TCKT以及第一時脈信號CK1進行及邏輯運算以產生第一信號。邏輯閘LG3並可針對控制信號TCKC以及第二時脈信號CK2進行及邏輯運算以產生第二信號。邏輯閘LG3並針對第一信號以及該第二信號進行或邏輯運算以產生輸出時脈信號OCK。In this embodiment, the output
與前述實施例不相同的,本實施例的延遲值產生器230拆分為兩個子延遲值產生器231、232。子延遲值產生器231、232分別耦接至振盪器210以及220,並用以提供延遲值DLV至延遲串211、221。子延遲值產生器231、232接收參考脈波信號RPS,並偵測參考脈波信號RPS的脈波寬度以產生延遲值DLV。在本實施例中,子延遲值產生器231、232所產生的延遲值DLV可以是相同的。並且,子延遲值產生器231與子延遲值產生器232可具有相同的電路架構。Different from the previous embodiment, the
以下請參照圖3,延遲值產生器300包括多個單位延遲器311~31N以及多個取樣器321~32N。多個單位延遲器311~31N相互串聯耦接成一延遲串。第一級的單位延遲器311接收參考脈波信號RPS,單位延遲器311~31N依序延遲參考脈波信號RPS並分別產生多個延遲後脈波信號DRP1~DRPN。取樣器321~32N分別耦接至單位延遲器311~31N。取樣器321~32N共同接收取樣時脈信號CKS以及重置信號RST。取樣器321~32N根據取樣時脈信號CKS分別取樣延遲後脈波信號DRP1~DRPN,並分別產生取樣值的多個位元DLV1~DLVN。Please refer to FIG. 3 below. The
本實施例中,取樣器321~32N可以為D型正反器。In this embodiment, the
在本實施例中,單位延遲器311~31N可分別提供相同的單位延遲。單位延遲的時間長度小於參考脈波信號RPS上的參考脈波的脈波寬度。取樣時脈信號CKS則可以為圖2實施例的控制信號TCKT以及TCKC的其中之一。取樣器321~32N根據時脈信號CKS所執行的取樣動作,可以產生分別為邏輯值1、1、…、0、0取樣值的多個位元DLV1~DLVN。其中,位元DLV1~DLVN中連續為邏輯值1的位元數量可以代表參考脈波信號RPS上的參考脈波的脈波寬度。In this embodiment, the unit delays 311 to 31N can respectively provide the same unit delay. The time length of the unit delay is smaller than the pulse width of the reference pulse on the reference pulse signal RPS. The sampling clock signal CKS may be one of the control signals TCKT and TCKC in the embodiment of FIG. 2 . The
以下請同步參照圖2以及圖4,其中,子延遲值產生器231、232提供相同的延遲值DLV(具有多個位元DLV<1:N>)至延遲串211以及221。振盪器210根據延遲值DLV以及控制信號TCKT以產生第一時脈信號CK1,振盪器220則根據延遲值DLV以及控制信號TCKC以產生第二時脈信號CK2。輸出時脈信號產生器240則合成第一時脈信號CK1以及第二時脈信號CK2並產生輸出時脈信號OCK。在圖4中,控制信號TCKT、TCKC的相位相反。而在控制信號TCKT為邏輯值1時,第一時脈信號CK1可轉態為邏輯值1,在控制信號TCKT為邏輯值0時,第一時脈信號CK1維持等於邏輯值0。另外,在控制信號TCKC為邏輯值1時,第二時脈信號CK2可轉態為邏輯值1,在控制信號TCKC為邏輯值0時,第一時脈信號CK2維持等於邏輯值0。也因此,第一時脈信號CK1與第二時脈信號CK2可為具有一定相位差的時脈信號,且第一時脈信號CK1、第二時脈信號CK2、控制信號TCKT以及TCKC的頻率可以是相同的。Please refer to FIG. 2 and FIG. 4 synchronously below, in which the
另外,輸出時脈信號OCK可以為第一時脈信號CK1與第二時脈信號CK2的組合。輸出時脈信號OCK的頻率則可以為第一時脈信號CK1與第二時脈信號CK2的兩倍。基於第一時脈信號CK1與第二時脈信號CK2具有一固定的相位差,且轉態緣皆不互相靠近或重疊,因此,時脈信號產生裝置200可提估穩定的輸出時脈信號OCK。In addition, the output clock signal OCK may be a combination of the first clock signal CK1 and the second clock signal CK2. The frequency of the output clock signal OCK may be twice that of the first clock signal CK1 and the second clock signal CK2. Since the first clock signal CK1 and the second clock signal CK2 have a fixed phase difference, and the transition edges are not close to or overlap with each other, the clock
請參照圖5,在步驟S510中,提供第一振盪器以根據第一控制信號以被週期性的啟動,並根據延遲值以產生具有第一頻率的第一時脈信號。在步驟S520中,提供第二振盪器以根據第二控制信號以被週期性的啟動,並根據延遲值以產生具有第二頻率的第二時脈信號,其中第一時脈信號與第二時脈信號的相位不相同,而第一頻率與第二頻率可以相同。在步驟S530中,偵測參考脈波信號的脈波寬度以產生延遲值。在步驟S540中,結合第一時脈信號與第二時脈信號以產生輸出時脈信號。Referring to FIG. 5 , in step S510 , a first oscillator is provided to be started periodically according to a first control signal and to generate a first clock signal with a first frequency according to a delay value. In step S520, a second oscillator is provided to be periodically started according to the second control signal and to generate a second clock signal with a second frequency according to the delay value, wherein the first clock signal is consistent with the second clock signal. The pulse signals have different phases, but the first frequency and the second frequency can be the same. In step S530, the pulse width of the reference pulse signal is detected to generate a delay value. In step S540, the first clock signal and the second clock signal are combined to generate an output clock signal.
關於上述步驟的實施細節,在前述的實施例以及實施方式中已有詳細的說明,在此恕不多贅述。The implementation details of the above steps have been described in detail in the foregoing embodiments and implementation modes, and will not be described again here.
綜上所述,本發明的時脈信號產生裝置可應用測試機台所提供的測試時脈信號來做為控制信號,並據以產生雙倍頻率的輸出時脈信號。本發明的時脈信號產生裝置透過交錯的啟動不同的振盪器,並透過結合二振盪器所產生的時脈信號來產生輸出時脈信號,可有效維持輸出時脈信號的穩定性。除提升測試動作的速率外,還可以確保測試動作的穩定度及正確性。To sum up, the clock signal generating device of the present invention can use the test clock signal provided by the test machine as the control signal, and generate an output clock signal with double frequency accordingly. The clock signal generating device of the present invention can effectively maintain the stability of the output clock signal by staggeredly starting different oscillators and combining the clock signals generated by the two oscillators to generate an output clock signal. In addition to improving the speed of test actions, it can also ensure the stability and accuracy of test actions.
100、200:時脈信號產生裝置
110、120、210、220:振盪器
130、230、300:延遲值產生器
140、240:輸出時脈信號產生器
211、221:延遲串
231、232:子延遲值產生器
311~31N:單位延遲器
321~32N:取樣器
CK1、CK2:時脈信號
DLV:延遲值
DLV1~DLVN、DLV<1:N>:取樣值的多個位元
DRP1~DRPN:遲後脈波信號
LG1~LG3:邏輯閘
OCK:輸出時脈信號
RPS:參考脈波信號
S510~S530:時脈信號的產生步驟
TCKT、TCKC:控制信號
100, 200: Clock
圖1繪示本發明一實施例的時脈信號產生裝置的示意圖。 圖2繪示本發明另一實施例的時脈信號產生裝置的電路示意圖。 圖3繪示本發明實施例的時脈信號產生裝置中的延遲值產生器的電路示意圖。 圖4繪示本發明實施例的時脈信號產生裝置的動作波形圖。 圖5繪示本發明一實施例的適用於積體電路的測試動作的時脈信號的產生方法的流程圖。 FIG. 1 is a schematic diagram of a clock signal generating device according to an embodiment of the present invention. FIG. 2 is a schematic circuit diagram of a clock signal generating device according to another embodiment of the present invention. FIG. 3 is a schematic circuit diagram of a delay value generator in a clock signal generating device according to an embodiment of the present invention. FIG. 4 shows an operation waveform diagram of the clock signal generating device according to the embodiment of the present invention. FIG. 5 is a flowchart illustrating a method for generating a clock signal suitable for testing operations of an integrated circuit according to an embodiment of the present invention.
100:時脈信號產生裝置 100: Clock signal generating device
110、120:振盪器 110, 120: Oscillator
130:延遲值產生器 130: Delay value generator
140:輸出時脈信號產生器 140: Output clock signal generator
CK1、CK2:時脈信號 CK1, CK2: clock signal
DLV:延遲值 DLV: delay value
OCK:輸出時脈信號 OCK: Output clock signal
RPS:參考脈波信號 RPS: reference pulse signal
TCKT、TCKC:控制信號 TCKT, TCKC: control signal
Claims (16)
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TW111124142A TWI812308B (en) | 2022-06-28 | 2022-06-28 | Clock signal generating device and clock signal generating method thereof |
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TW202401985A TW202401985A (en) | 2024-01-01 |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6204694B1 (en) * | 1999-05-21 | 2001-03-20 | Logicvision, Inc. | Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals |
US20190064747A1 (en) * | 2017-08-22 | 2019-02-28 | Seiko Epson Corporation | Time-to-digital converter, circuit device, physical quantity measurement apparatus, electronic apparatus, and vehicle |
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2022
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6204694B1 (en) * | 1999-05-21 | 2001-03-20 | Logicvision, Inc. | Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals |
US20190064747A1 (en) * | 2017-08-22 | 2019-02-28 | Seiko Epson Corporation | Time-to-digital converter, circuit device, physical quantity measurement apparatus, electronic apparatus, and vehicle |
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