CN117411470A - Clock signal generating device and clock signal generating method - Google Patents

Clock signal generating device and clock signal generating method Download PDF

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Publication number
CN117411470A
CN117411470A CN202210800636.9A CN202210800636A CN117411470A CN 117411470 A CN117411470 A CN 117411470A CN 202210800636 A CN202210800636 A CN 202210800636A CN 117411470 A CN117411470 A CN 117411470A
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CN
China
Prior art keywords
clock signal
signal
oscillator
generate
control signal
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Pending
Application number
CN202210800636.9A
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Chinese (zh)
Inventor
林哲民
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Winbond Electronics Corp
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Winbond Electronics Corp
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Filing date
Publication date
Application filed by Winbond Electronics Corp filed Critical Winbond Electronics Corp
Priority to CN202210800636.9A priority Critical patent/CN117411470A/en
Publication of CN117411470A publication Critical patent/CN117411470A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
    • H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators

Abstract

The invention provides a clock signal generating device and a clock signal generating method. The clock signal generating device comprises a first oscillator, a second oscillator, a delay value generator and an output clock signal generator. The first oscillator and the second oscillator are started in a staggered manner. The first oscillator generates a first clock signal having a first frequency according to the delay value. The second oscillator generates a second clock signal with a second frequency according to the delay value, wherein the phases of the first clock signal and the second clock signal are different. The delay value generator detects a pulse width of the reference pulse signal to generate a delay value. The output clock signal generator combines the first clock signal and the second clock signal to generate an output clock signal.

Description

Clock signal generating device and clock signal generating method
Technical Field
The present invention relates to a clock signal generating device and a clock signal generating method, and more particularly, to a clock signal generating device and a clock signal generating method for a test machine.
Background
In the testing of integrated circuits, it is often necessary to apply a tester to provide a test clock signal for execution. When a high-frequency test clock signal is required, a high-order test machine is selected for execution, but this approach can lead to a significant increase in test cost. Therefore, in the prior art, a general test machine can be applied, and the frequency of the test clock signal can be increased by multiplying the test clock signal provided by the test machine.
In the prior art, a cutting signal is provided from the outside to perform signal waveform cutting for the test clock signal provided by the test machine, so as to complete the frequency multiplication. The transition edge of the frequency-doubled test clock signal generated by this method is unstable, and the stability and accuracy of the test operation are reduced.
Disclosure of Invention
The invention is directed to a clock signal generating device and a clock signal generating method, which can provide a test machine for outputting a clock signal according to relatively high frequency.
According to an embodiment of the present invention, a clock signal generating apparatus includes a first oscillator, a second oscillator, a delay value generator, and an output clock signal generator. The first oscillator is periodically started according to a first control signal, and generates a first clock signal with a first frequency according to a delay value. The second oscillator is periodically started according to a second control signal, and generates a second clock signal with a second frequency according to the delay value, wherein the phases of the first clock signal and the second clock signal are different. The delay value generator is coupled to the first oscillator and the second oscillator. The delay value generator detects a pulse width of the reference pulse signal to generate a delay value. The output clock signal generator is coupled to the first oscillator and the second oscillator, and combines the first clock signal and the second clock signal to generate an output clock signal.
According to an embodiment of the present invention, a method of generating a clock signal includes: providing a first oscillator to be periodically started according to a first control signal and generating a first clock signal with a first frequency according to a delay value; providing a second oscillator to be periodically started according to a second control signal and generating a second clock signal with a second frequency according to a delay value, wherein the phases of the first clock signal and the second clock signal are different; detecting the pulse width of the reference pulse signal to generate a delay value; and combining the first clock signal and the second clock signal to generate an output clock signal.
Based on the above, the clock signal generating device and the clock signal generating method of the present invention can generate the output clock signal by selecting two clock signals through time-sharing interleaving. In this way, the clock signal generating device can generate an output clock signal with a relatively high frequency. In the test action of the integrated circuit, the test clock signal for executing the test action can be accelerated, and the execution rate of the test action is improved.
Drawings
FIG. 1 is a schematic diagram of a clock signal generating apparatus according to an embodiment of the invention;
FIG. 2 is a schematic circuit diagram of a clock signal generating apparatus according to another embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a delay value generator in a clock signal generating apparatus according to an embodiment of the invention;
FIG. 4 is a diagram showing an operation waveform of a clock signal generating apparatus according to an embodiment of the present invention;
FIG. 5 is a flowchart of a method for generating a clock signal suitable for testing operations of an integrated circuit according to an embodiment of the invention.
Description of the reference numerals
100. 200: clock signal generating means;
110. 120, 210, 220: an oscillator;
130. 230, 300: a delay value generator;
140. 240: an output clock signal generator;
211. 221: a delay string;
231. 232: a sub-delay value generator;
311 to 31N: a unit delayer;
321 to 32N: a sampler;
CK1, CK2: a clock signal;
DLV: a delay value;
DLV 1-DLVN, DLV <1: n >: sampling a plurality of bits of a value;
DRP1 to DRPN: a delayed pulse signal;
LG1 to LG3: a logic gate;
OCK: outputting a clock signal;
RPS: a reference pulse signal;
s510 to S530: generating a clock signal;
TCKT, TCKC: a control signal.
Detailed Description
Referring to fig. 1, a clock signal generating apparatus 100 is suitable for use in a test machine of an integrated circuit. The clock signal generating apparatus 100 includes oscillators 110, 120, a delay value generator 130, and an output clock signal generator 140. In the present embodiment, the oscillator 110 is periodically started according to the control signal TCKT, and the oscillator 110 generates the first clock signal CK1 having the first frequency according to the delay value DLV. The oscillator 120 is periodically started according to the control signal TCKC, and the oscillator 120 generates the second clock signal CK2 with the second frequency according to the delay value DLV. Wherein the first frequency and the second frequency may be the same.
Note that the control signals TCKT and TCKC may be two clock signals with opposite phases, and the frequencies of the control signals TCKT and TCKC may be equal to the test clock signals that may be supplied by the test machine. In the present embodiment, the oscillators 110 and 120 can be turned on or off according to the voltage values of the control signals TCKT and TCKC, respectively. When the control signal TCKT is a logic value 1 (the control signal TCKC is a logic value 0), the oscillator 110 is started and the oscillator 120 is turned off; when the control signal TCKT is logic value 0 (the control signal TCKC is logic value 1), the oscillator 120 is started and the oscillator 110 is turned off. That is, the oscillators 110, 120 may be alternately turned on and off.
In this embodiment, the control signal TCKT may be a test clock signal provided by the test machine.
The delay value generator 130 is coupled to the oscillators 110, 120. The delay value generator 130 receives the reference pulse signal RPS and generates the delay value DLV according to the pulse width of the detected reference pulse signal RPS. In this embodiment, the reference pulse signal RPS provides a reference pulse. The pulse width of the reference pulse may be equal to half the period of the control signal TCKT. That is, the delay value generator 130 may generate the delay value DLV according to a half period of the control signal TCKT.
In this embodiment, the delay value DLV provided by the delay value generator 130 to the oscillators 110, 120 may be the same.
The output clock signal generator 140 is coupled to the oscillators 110 and 120. The output clock signal generator 140 receives the first clock signal CK1 and the second clock signal CK2 generated by the oscillators 110 and 120, respectively, and receives the control signals TCKT and TCKC. The output clock signal generator 140 is used for combining the first clock signal CK1 and the second clock signal CK2 to generate an output clock signal OCK. In detail, the output clock signal generator 140 can select to output the first clock signal CK1 or the second clock signal CK2 according to the control signals TCKT and TCKC to generate the output clock signal OCK. Specifically, when the control signal TCKT is a logic value 1 (the control signal TCKC is a logic value 0), the output clock signal generator 140 selects the output first clock signal CK1 to generate the output clock signal OCK; when the control signal TCKT is a logic value 0 (the control signal TCKC is a logic value 1), the output clock signal generator 140 selects the output second clock signal CK2 to generate the output clock signal OCK.
By combining the first clock signal CK1 and the second clock signal CK2 to generate the output clock signal OCK, the frequency of the output clock signal OCK generated by the output clock signal generator 140 may be twice the frequency of the first clock signal CK1 and the second clock signal CK2. The frequency of the first clock signal CK1 and the second clock signal CK2 generated by the control signals TCKT and TCKC may be equal to the frequency of the control signals TCKT and TCKC, that is, the frequency of the output clock signal OCK generated by the clock signal generating device 100 of the present invention may be twice the frequency of the control signals TCKT and TCKC. The clock signal generating device 100 can provide the output clock signal OCK as the test clock signal for performing the test operation, so as to speed up the test operation.
It should be noted that, since the delay value generator 130 generates the delay value DLV based on the half period of the control signal TCKT, the oscillators 110 and 120 generate the first clock signal CK1 and the second clock signal CK2 according to the delay value DLV. Thus, the first clock signal CK1 and the second clock signal CK2 may be two clock signals with a fixed phase difference, and this phase difference may be associated with half a period of the control signal TCKT. Therefore, the output clock signal OCK generated by the clock signal generating device 100 can be a clock signal with stable transition edges, so that the test operation can be performed stably.
Referring to fig. 2, the clock signal generating apparatus 200 includes oscillators 210, 220, a delay value generator 230 composed of sub-delay value generators 231, 232, and an output clock signal generator 240. In the present embodiment, the oscillator 210 is a ring oscillator (ring oscillator), and includes a delay string 211 and a logic gate LG1. The logic gate LG1 is coupled between paths of the delay string 211 receiving the control signal TCKT, two input terminals of the logic gate LG1 respectively receive the control signal TCKT and the first clock signal CK1, and an output terminal of the logic gate LG1 is coupled to an input terminal of the delay string 211.
In the present embodiment, the logic Gate LG1 may be a NAND Gate (NAND Gate). The logic gate LG1 passes through the inverse of the first clock signal CK1 to be transmitted into the delay string 211 when the control signal TCKT is a logic value 1, and causes the delay string 211 to delay the received signal (the inverse of the first clock signal CK 1) according to the delay value DLV. In this way, the oscillator 210 can generate the first clock signal CK1 with a period equal to twice the delay DLV.
The oscillator 220 is also a ring oscillator, comprising a delay string 221 and a logic gate LG2. The logic gate LG2 is coupled between paths of the delay string 221 receiving the control signal TCKC, two input terminals of the logic gate LG1 respectively receive the control signal TCKC and the first clock signal CK2, and an output terminal of the logic gate LG2 is coupled to an input terminal of the delay string 221. The details of the operation of the oscillator 220 are similar to those of the oscillator 210, and will not be repeated here.
In the present embodiment, the output clock signal generator 240 may be a signal selector, and may be constructed using the logic gate LG 3. The logic gate LG3 is a combined logic gate formed by combining two AND gates and one OR gate. The logic gate LG3 performs an and logic operation on the control signal TCKT and the first clock signal CK1 to generate a first signal. The logic gate LG3 may perform an and logic operation with respect to the control signal TCKC and the second clock signal CK2 to generate a second signal. The logic gate LG3 performs an or logic operation on the first signal and the second signal to generate an output clock signal OCK.
Unlike the previous embodiment, the delay value generator 230 of the present embodiment is split into two sub-delay value generators 231, 232. The sub-delay value generators 231, 232 are coupled to the oscillators 210, 220, respectively, and are used for providing the delay values DLV to the delay strings 211, 221. The sub-delay value generators 231, 232 receive the reference pulse signal RPS and detect the pulse width of the reference pulse signal RPS to generate the delay value DLV. In this embodiment, the delay values DLV generated by the sub-delay value generators 231, 232 may be the same. Also, the sub-delay value generator 231 and the sub-delay value generator 232 may have the same circuit architecture.
Referring to fig. 3, the delay value generator 300 includes a plurality of unit delays 311 to 31N and a plurality of samplers 321 to 32N. The unit delays 311-31N are coupled in series to form a delay string. The unit delay device 311 of the first stage receives the reference pulse signal RPS, and the unit delay devices 311 to 31N sequentially delay the reference pulse signal RPS and generate a plurality of delayed pulse signals DRP1 to DRPN, respectively. The samplers 321 to 32N are coupled to the unit delays 311 to 31N, respectively. The samplers 321 to 32N commonly receive the sampling clock signal CKS and the reset signal RST. The samplers 321 to 32N sample the delayed pulse signals DRP1 to DRPN according to the sampling clock signal CKS, respectively, and generate a plurality of bits DLV1 to DLVN of the sampled value, respectively.
In this embodiment, the samplers 321 to 32N may be D-type flip-flops.
In the present embodiment, the unit delays 311 to 31N may respectively provide the same unit delay. The length of time of the unit delay is smaller than the pulse width of the reference pulse on the reference pulse signal RPS. The sampling clock signal CKS may be one of the control signals TCKT and TCKC in the embodiment of fig. 2. The samplers 321 to 32N can generate a plurality of bits DLV1 to DLVN having logical values 1, …, 0, and 0, respectively, according to the sampling operation performed by the clock signal CKS. The number of bits DLV 1-DLVN that are sequentially logic value 1 may represent the pulse width of the reference pulse on the reference pulse signal RPS.
Referring to fig. 2 and 4, the sub-delay value generators 231 and 232 provide the same delay value DLV (with a plurality of bits DLV <1:n >) to the delay strings 211 and 221. The oscillator 210 generates the first clock signal CK1 according to the delay value DLV and the control signal TCKT, and the oscillator 220 generates the second clock signal CK2 according to the delay value DLV and the control signal TCKC. The output clock signal generator 240 synthesizes the first clock signal CK1 and the second clock signal CK2 and generates the output clock signal OCK. In fig. 4, the phases of the control signals TCKT, TCKC are opposite. The first clock signal CK1 can be turned to logic 1 when the control signal TCKT is logic 1, and the first clock signal CK1 remains equal to logic 0 when the control signal TCKT is logic 0. In addition, the second clock signal CK2 may transition to logic 1 when the control signal TCKC is logic 1, and the first clock signal CK2 remains equal to logic 0 when the control signal TCKC is logic 0. Also, the first clock signal CK1 and the second clock signal CK2 may be clock signals having a certain phase difference, and the frequencies of the first clock signal CK1, the second clock signal CK2, the control signal TCKT, and TCKC may be the same.
In addition, the output clock signal OCK may be a combination of the first clock signal CK1 and the second clock signal CK2. The frequency of the output clock signal OCK may be twice that of the first clock signal CK1 and the second clock signal CK2. Based on the first clock signal CK1 and the second clock signal CK2 having a fixed phase difference, the transition edges are not close to each other or overlap, so that the clock signal generating device 200 can provide a stable output clock signal OCK.
Referring to fig. 5, in step S510, a first oscillator is provided to be periodically started according to a first control signal, and a first clock signal having a first frequency is generated according to a delay value. In step S520, a second oscillator is provided to be periodically started according to a second control signal, and a second clock signal having a second frequency is generated according to a delay value, wherein phases of the first clock signal and the second clock signal are different, and the first frequency and the second frequency may be the same. In step S530, the pulse width of the reference pulse signal is detected to generate a delay value. In step S540, the first clock signal and the second clock signal are combined to generate an output clock signal.
Details of the implementation of the above steps are described in the foregoing embodiments and implementations, and are not repeated herein.
In summary, the clock signal generating device of the present invention can apply the test clock signal provided by the test machine as the control signal, and generate the output clock signal with double frequency accordingly. The clock signal generating device of the invention can effectively maintain the stability of the output clock signal by starting different oscillators in an interlaced way and generating the output clock signal by combining the clock signals generated by the two oscillators. Besides improving the speed of the test action, the stability and the correctness of the test action can be ensured.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (16)

1. A clock signal generating apparatus, comprising:
a first oscillator periodically started according to a first control signal, the first oscillator generating a first clock signal having a first frequency according to a delay value;
a second oscillator periodically started according to a second control signal, wherein the second oscillator generates a second clock signal with a second frequency according to the delay value, and the phases of the first clock signal and the second clock signal are different;
a delay value generator coupled to the first oscillator and the second oscillator for detecting a pulse width of a reference pulse signal to generate the delay value; and
an output clock signal generator coupled to the first oscillator and the second oscillator, and combining the first clock signal and the second clock signal to generate an output clock signal.
2. The clock signal generation apparatus of claim 1, wherein the first control signal is complementary in phase to the second control signal.
3. The clock signal generating apparatus according to claim 2, wherein a pulse width of the reference pulse signal is equal to one half of a period of the first control signal.
4. The clock signal generating apparatus according to claim 1, wherein the delay value generator comprises:
the unit delays are mutually coupled in series to form a delay string, the delay string receives the reference pulse wave signal, and the unit delays respectively generate a plurality of delayed pulse wave signals; and
and a plurality of samplers, corresponding to the unit delays, for sampling the delayed pulse signals according to a sampling clock signal to generate a plurality of bits of the sampling value.
5. The clock signal generating apparatus according to claim 1, wherein the delay value generator comprises:
a first sub-delay value generator coupled to the first oscillator for providing the delay value to the first oscillator; and
and a second sub-delay value generator coupled to the second oscillator for providing the delay value to the second oscillator.
6. The clock signal generating apparatus of claim 1, wherein the first oscillator and the second oscillator are ring oscillators.
7. The clock signal generation apparatus of claim 1, wherein the first oscillator further comprises:
a first delay string; and
the first logic gate is coupled between paths of the delay string for receiving the first control signal, two input ends of the first logic gate respectively receive the first control signal and the first clock signal, and an output end of the first logic gate is coupled to an input end of the first delay string;
the second oscillator further includes:
a second delay string; and
the second logic gate is coupled between paths of the second delay string for receiving the second control signal, two input ends of the second logic gate respectively receive the second control signal and the second clock signal, and an output end of the second logic gate is coupled to an input end of the second delay string.
8. The clock signal generation apparatus of claim 7, wherein the first logic gate is a nand gate and the second logic gate is a nand gate.
9. The clock signal generation apparatus of claim 1, wherein the output clock signal generator is a signal selector to select the first clock signal as the output clock signal when the first control signal is a first logic value and to select the second clock signal as the output clock signal when the second control signal is the first logic value.
10. The clock signal generation apparatus of claim 8, wherein the output clock signal generator performs an and logic operation on the first control signal and the first clock signal to generate a first signal, performs an and logic operation on the second control signal and the second clock signal to generate a second signal, and performs an or logic operation on the first signal and the second signal to generate the output clock signal.
11. The clock signal generation apparatus of claim 1, wherein the output clock signal has a frequency that is twice the first frequency.
12. A method for generating a clock signal, comprising:
providing a first oscillator to be periodically started according to a first control signal and generating a first clock signal with a first frequency according to a delay value;
providing a second oscillator to be periodically started according to a second control signal and generating a second clock signal with a second frequency according to the delay value, wherein the phases of the first clock signal and the second clock signal are different;
detecting a pulse width of a reference pulse signal to generate the delay value; and
the first clock signal and the second clock signal are combined to generate an output clock signal.
13. The method of claim 12, wherein the step of detecting the pulse width of the reference pulse signal to generate the delay value comprises:
providing a delay string formed by coupling a plurality of unit delays in series with each other;
enabling the delay string to receive the reference pulse wave signal and sequentially delaying the reference pulse wave signal to generate a plurality of delayed pulse wave signals; and
a plurality of bits of the sampled value are generated by sampling the plurality of delayed pulse signals according to a sampling clock signal.
14. The method of claim 12, wherein the step of combining the first clock signal and the second clock signal to generate the output clock signal comprises:
selecting the first clock signal as the output clock signal when the first control signal is a first logic value; and
the second clock signal is selected as the output clock signal when the second control signal is the first logic value.
15. The method of generating a clock signal according to claim 14, wherein the step of selecting the first clock signal as the output clock signal when the first control signal is the first logic value, and selecting the second clock signal as the output clock signal when the second control signal is the first logic value comprises:
performing AND logic operation on the first control signal and the first clock signal to generate a first signal;
performing AND logic operation on the second control signal and the second clock signal to generate a second signal; and
an or logic operation is performed on the first signal and the second signal to generate the output clock signal.
16. The method of generating a clock signal according to claim 12, further comprising:
performing logic operation on the first control signal and the first clock signal to generate a first operation result, and transmitting the first operation result to the first oscillator; and
and carrying out logic operation on the second control signal and the second clock signal to generate a second operation result, and transmitting the second operation result to the second oscillator.
CN202210800636.9A 2022-07-08 2022-07-08 Clock signal generating device and clock signal generating method Pending CN117411470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210800636.9A CN117411470A (en) 2022-07-08 2022-07-08 Clock signal generating device and clock signal generating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210800636.9A CN117411470A (en) 2022-07-08 2022-07-08 Clock signal generating device and clock signal generating method

Publications (1)

Publication Number Publication Date
CN117411470A true CN117411470A (en) 2024-01-16

Family

ID=89487636

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210800636.9A Pending CN117411470A (en) 2022-07-08 2022-07-08 Clock signal generating device and clock signal generating method

Country Status (1)

Country Link
CN (1) CN117411470A (en)

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