TWI781017B - Test system and test circuit thereof - Google Patents

Abstract

The present invention provides a test system and test circuit thereof. The test circuit includes a command decoder, a trigger signal generator, a delay control signal generator, a delay circuit and a test data generator. The command decoder generates an adjustment signal by decoding a test command. The trigger signal generator generates a trigger signal according to a clock signal. The delay control signal generator generates a delay control signal according to the adjustment signal. The delay circuit generates a unit delay according to the delay control signal and delays the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples a preset data according to the sampling clock to obtain a test output signal. The test data generator has obtained a test output signal by sampling test data according to the sampling clocks.

Description

Test system and its test circuit

The present invention relates to a test system and its test circuit, and in particular to a memory test system and a memory test circuit.

The current mainstream I/O architecture of Dynamic Random Access Memory (DRAM) is Double Data Rate (DDR) architecture. Since the DDR architecture transmits data on the rising and falling edges of the bus clock, its data transmission frequency is twice the bus clock frequency. Taking the current fourth-generation double data rate (DDR4) specification as an example, under normal usage conditions, the bus clock frequency can be as high as about 1.6GHz, so the data transmission frequency of DDR4 can be as high as 3.2GHz.

However, in the application of product testing of memory chips, especially under wafer-level test conditions, it is difficult to provide memory with a frequency as high as that required in general use (for example: 1.6 GHz). A high-speed testing machine at the wafer level can usually provide a test frequency up to about 100MHz, which is far lower than the required frequency of DDR memory in general use. Furthermore, due to the high cost of high-speed testing machines, it is almost impossible to achieve a greater increase in testing frequency under current conditions. Therefore, the current wafer-level memory test will be limited by the test frequency of the testing machine, so that the clock frequency provided to the memory during the test is much lower than the required clock frequency of the memory under normal use. As a result, the test time is greatly lengthened, thereby raising the manufacturing cost of the memory chip.

The invention provides a test circuit, which can complete the test action inside the memory through the clock signal with a lower frequency.

The test circuit of the present invention includes a command decoding circuit, a trigger signal generator, a delay control signal generator, a delay circuit and a test data generator. The command decoding circuit generates an adjustment signal according to the decoded test command. The trigger signal generator generates a trigger signal according to the input clock signal. The delay control signal generator is coupled to the command decoding circuit and generates a delay control signal according to the adjustment signal. The delay circuit is coupled to the delay control signal generator and the trigger signal generator to generate a unit delay according to the delay control signal, and delay the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples test data according to a plurality of sampling clocks to obtain test output signals.

The testing system of the present invention includes a testing machine and a testing circuit. The testing machine is coupled to the testing circuit. The test circuit includes a command decoding circuit, a trigger signal generator, a delay control signal generator, a delay circuit and a test data generator. The command decoding circuit generates an adjustment signal according to the decoded test command. The trigger signal generator generates a trigger signal according to the input clock signal. The delay control signal generator is coupled to the command decoding circuit and generates a delay control signal according to the adjustment signal. The delay circuit is coupled to the delay control signal generator and the trigger signal generator to generate a unit delay according to the delay control signal, and delay the trigger signal based on the unit delay to generate a plurality of sampling clocks. The test data generator samples test data according to a plurality of sampling clocks to obtain test output signals. The test machine is used to provide test commands and input clock signals to the test circuit, receive the test output signals, and generate test results according to the test output signals.

Based on the above, the test circuit and test system of the present invention can use a lower frequency external clock signal to input the test circuit to obtain a test output signal with a higher clock signal frequency to complete the internal test operation of the memory. On the premise of not increasing the hardware cost of the tester, the test circuit can output an output signal with a higher frequency than the external input clock signal to shorten the test time. In addition, the technical solution of the present invention, in addition to not increasing the hardware cost of the testing machine, also does not need to use the technology of coupling the clock pulse input end of the testing circuit to the frequency multiplier, such as using a phase locked loop (Phase Locked Loop, PLL), etc. Therefore, the cost and complexity of the test system will not be increased.

Please refer to FIG. 1 , which is a schematic diagram of a test circuit according to an embodiment of the present invention. The test circuit 100 includes a command decoder 110 , a trigger signal generator 120 , a delay control signal generator 130 , a delay circuit 140 and a test data generator 150 . The delay control signal generator 130 is coupled to the command decoder 110 and the delay circuit 140 , and the delay circuit 140 is also coupled to the trigger signal generator 120 and the test data generator 150 .

The command decoder 110 receives and decodes a test command CMD from an external source such as a test machine. The trigger signal generator 120 receives a clock signal CLK from an external source such as a testing machine. The clock signal CLK may be a periodic clock signal. The trigger signal generator 120 generates a trigger signal TG according to the clock signal CLK. The trigger signal generator 120 can generate the trigger signal TG according to a transition edge of the clock signal CLK, wherein the transition edge can be a rising edge and/or a falling edge. The test data generator 150 is used to output the test output signal DOUT.

The command decoder 110 decodes the test command CMD and generates an adjustment signal TCODE. The command decoder 110 provides the adjustment signal TCODE to the delay control signal generator 130 . The delay control signal generator 130 generates the delay control signal Dctrl according to the adjustment signal TCODE. The delay circuit 140 can set a unit delay according to the delay control signal Dctrl, and delay the trigger signal TG one or more times based on the set unit delay, so as to sequentially generate a plurality of sampling clocks SCK1˜SCKn. It should be noted that the trigger signal TG is generated according to the triggering of the waveform of the clock signal CLK, and the delay circuit 140 delays the trigger signal TG multiple times according to the unit delay to generate the sampling clocks SCK1˜SCKn; that is, , each period of the clock signal CLK will generate sampling clocks SCK1˜SCKn. This means that the frequency of the sampling clocks SCK1-SCKn will be higher than the frequency of the clock signal CLK, and the frequency of the sampling clocks SCK1-SCKn can be determined by the time of the unit delay.

The test data generator 150 respectively samples a plurality of test data PD1 ˜ PDn according to the sampling clocks SCK1 ˜ SCKn to generate the test output signal DOUT. The test data PD1˜PDn can be the preset test data written into the temporary register (not shown in FIG. 1 ) of the test circuit 100 in advance, or the test data (such as memory Body readout data). The test data generator 150 can be a parallel to serial converter (parrel to serial converter), used to convert the test data PD1 ˜ PDn into serial data according to the sampling clocks SCK1 ˜ SCKn, and thereby generate the test output signal DOUT.

The test circuit 100 of this embodiment may be embedded in a memory chip to be tested. According to the above-mentioned implementation, the test circuit 100 of this embodiment can output the test output signal DOUT according to the input test command CMD and the clock signal CLK, so as to complete the internal test operation of the memory. And the test circuit 100 is characterized in that the frequency of the test output signal DOUT is higher than the frequency of the clock signal CLK.

Please refer to FIG. 2 , which is a schematic diagram of a test circuit according to another embodiment of the present invention. The test circuit 200 includes a command decoder 210 , a trigger signal generator 220 , a delay control signal generator 230 , a delay circuit 240 and a test data generator 250 . The delay control signal generator 230 is coupled to the command decoder 210 and the delay circuit 240 , and the delay circuit 240 is also coupled to the trigger signal generator 220 and the test data generator 250 . The command decoder 210 is used to receive the test command CMD, the trigger signal generator 220 is used to receive the clock signal CLK, and the test data generator 250 is used to generate the output test signal DOUT.

The difference between the test circuit 200 and the test circuit of the embodiment in FIG. 1 is that the delay circuit 240 includes a plurality of voltage-controlled delays VCD1 -VCDn connected in series. As shown in FIG. 2 , the input terminal of the voltage-controlled delay VCD1 is coupled to the trigger signal generator 220 , and the output terminal of the voltage-controlled delay VCD1 is sequentially connected to the voltage-controlled delays VCD2˜VCDn. The voltage-controlled delays VCD1 -VCDn are commonly coupled to the delay control signal generator 230 , and the output terminals of the voltage-controlled delays VCD1 -VCDn are respectively coupled to the test data generator 250 .

The delay control signal generator 230 generates the delay control signal Dctrl according to the adjustment signal TCODE generated by decoding the test command CMD from the command decoder 210 . The delay control signal Dctrl can have a voltage value, and each of the voltage-controlled delays VCD1˜VCDn can generate a unit delay according to the voltage value of the delay control signal Dctrl, and sequentially delay the trigger signal TG to generate a plurality of sampling clocks SCK1~SCKn. In this embodiment, the time length of the unit delay can be determined by the voltage value of the delay control signal Dctrl. Wherein, the time length of the unit delay may be positively or negatively correlated with the voltage value of the delay control signal Dctrl, and there is no certain limitation.

Please refer to FIG. 3 , which is a schematic diagram of a test circuit according to another embodiment of the present invention. The test circuit 300 includes a command decoder 310 , a trigger signal generator 320 , a delay control signal generator 330 , a delay circuit 340 and a test data generator 350 . The delay control signal generator 330 is coupled to the command decoder 310 and the delay circuit 340 , and the delay circuit 340 is also coupled to the trigger signal generator 320 and the test data generator 350 . The command decoder 310 is used to receive the test command CMD, the trigger signal generator 320 is used to receive the clock signal CLK, and the test data generator 350 is used to generate the output test signal DOUT.

The difference between the test circuit 300 and the test circuit in the embodiment shown in FIG. 1 is that the delay circuit 340 includes a delay line 341 and a selection circuit 342 , wherein the delay line 341 may include a plurality of delayers D1 -Dn connected in series. As shown in FIG. 3 , the input end of the delayer D1 is coupled to the trigger signal generator 320 , and the output end of the delayer D1 is sequentially connected to the delayers D2˜Dn. And the output terminals of the delays D1 ˜ Dn are respectively coupled to the selection circuit 342 . The selection circuit 342 is coupled to the delay control signal generator 330 and the test data generator 350 , and the selection circuit 342 selectively provides a plurality of output signals of the output terminals of the delayers D1 ˜Dn to the test data generator 350 .

Each of the delays D1 ˜Dn can generate a unit resolution delay, and sequentially delay the trigger signal TG and output it to the selection circuit 342 . The delay control signal generator 330 generates a delay control signal Dctrl according to the adjustment signal TCODE, and the selection circuit 342 can select some outputs of the delayers D1~Dn according to the delay control signal Dctrl to generate a plurality of sampling clocks SCK1 ~SCKn, where there is a unit delay in two sampling clocks with similar phases. For example, if the length of the set unit delay is 3 times of the unit analysis delay length, the delay control signal generator 330 will provide the delay control signal Dctrl to the selection circuit 342, and the selection circuit 342 will select the delay devices D3, D6, The delay signal generated by D9 . . . is provided to the test data generator 350 to generate a plurality of sampling clocks SCK1˜SCKn.

Please refer to FIGS. 4A˜4D , which illustrate multiple implementations of the delay line 341 of the embodiment shown in FIG. 3 . In FIG. 4A , the delay line 341 includes a plurality of buffers BUF1 -BUFn connected in series. In addition, in FIG. 4B, the delay line 341 further includes a plurality of resistor-capacitor networks, each of which can be respectively coupled to the input or output terminals of the corresponding buffers BUF1~BUFn, and used to improve the above-mentioned The length of the parsing delay in units. In FIG. 4B , taking the resistor-capacitor network RCN as an example, the resistor-capacitor network RCN is coupled to the output terminal of the buffer BUF1 . One end of the resistor R is coupled to the output end of the buffer BUF1 , the other end of the resistor R is coupled to one end of the capacitor C, and the other end of the capacitor C can be coupled to the reference ground.

In FIG. 4C , the delay line 341 includes a plurality of inverters INV1 - INVn connected in series. In FIG. 4D , the delay line 341 further includes a plurality of resistor-capacitor networks. The resistor-capacitor network can be coupled to the input terminal or the output terminal of each of the inverters INV1˜INVn, and used to increase the length of the above-mentioned unit resolution delay.

Please refer to FIG. 5 , which is a schematic diagram of a test system according to an embodiment of the present invention. The testing system 500 includes a testing circuit 510 and a testing machine 520 . The testing machine 520 is connected to the testing circuit 510 to perform testing. The test machine 520 is used to provide the test command CMD and the clock signal CLK to the test circuit 510 and receive the test output signal DOUT from the test circuit 510 . In this embodiment, the testing machine 520 can also provide a test selection signal SEL to the testing circuit 510 to enable the testing circuit 510 to perform testing.

Wherein, as shown in FIG. 5 , the test circuit 510 includes a command decoder 511 , a trigger signal generator 512 , a delay control signal generator 513 , a delay circuit 514 , a test data generator 515 , an output driver 516 , and a test receiver 517 . The command decoder 511 is coupled to the trigger signal generator 512 , the delay control signal generator 513 and the test receiver 517 . The trigger signal generator 512 is also coupled to a delay circuit 514 and an output driver 516 . The delay control signal generator 513 is also coupled to the delay circuit 514 . The delay circuit 514 is also coupled to the test data generator 515 . The test data generator 515 is also coupled to the output driver 516 . The command decoder 511 is coupled to the testing machine 520 to receive the testing command CMD. The trigger signal generator 512 is coupled to the testing machine 520 to receive the clock signal CLK. The test receiver 517 is coupled to the test machine 520 to receive the test selection signal SEL. The output driver 516 is coupled to the testing machine 520 and used for outputting the test output signal DOUT to complete the test.

The test circuit 510 in this embodiment is different from the test circuit in FIG. 1 in that the command decoder 511 can decode the test command CMD to provide the latent control signal LTctrl to the trigger signal generator 512 . The trigger signal generator 512 can also set a latency according to the latency control signal LTctrl. The trigger signal generator 512 can adjust the time point of generating the trigger signal TG according to the latency.

In addition, in the test circuit 510 in this embodiment, the test data generator 515 samples the test data PD1-PDn according to a plurality of sampling clocks SCK1-SCKn to generate the serial data SDA and provide it to the output driver 516, and the output driver 516 The trigger signal TG generated from the trigger signal generator 512 is also received. The output driver 516 generates the test output signal DOUT according to the trigger signal TG and the serial data SDA. Wherein, the test output signal DOUT may include a preamble signal part and a test data signal part. The pre-signal part can be correspondingly generated by the output driver 516 according to the trigger signal TG, and the test data signal part can be correspondingly generated by the output driver 516 according to the serial data SDA.

The testing circuit 510 in this embodiment also receives the testing selection signal SEL from the testing machine 520 through the testing receiver 517 . When the integrated circuit corresponding to the test circuit 510 is a device under test (DUT), the test circuit 510 can generate the enable signal EN according to the selection signal SEL, and provide the enable signal EN to the command decoder 511, So that the enable command decoder 511 can execute the decoding action of the test command CMD, and further execute subsequent test actions.

Please refer to FIG. 5 and FIG. 6 below. FIG. 6 illustrates waveform diagrams of the input clock signal and the test output signal in the embodiment of the test system as in FIG. 5 . Wherein, in FIG. 6 , the test output signal DOUT has a preamble signal part PB and the test data signal part, such as the test data signals d1~d9 . . . shown in FIG. 6 . The preamble signal part PB is generated according to the trigger signal TG provided by the trigger signal generator 512 , so relative to the rising edge trigger time point of the clock signal CLK, there is a delay of the latency LT_T. In this embodiment, one period of the clock signal CLK may correspond to eight test data signals (eg, test data signals d1 - d8 ).

It is worth mentioning that the trigger signal generator 512 can periodically generate the trigger signal TG according to multiple rising edges of the clock signal CLK.

Please refer to FIG. 5 and FIG. 7 synchronously below. FIG. 7 is a waveform diagram of a test operation in the latency adjustment mode of the test system according to an embodiment of the present invention. The test system of the embodiment of the present invention can perform the setting action of the latency time according to the test results of multiple times. In FIG. 7 , the command decoder 511 of the test system 500 can respectively execute test actions T1 - T4 by generating different latency control signals LTctrl. Wherein, the latency times of the test actions T1-T4 may be different first to fourth latency times respectively. Corresponding to different latency times, the output driver 516 can respectively generate test output signals DOUT with different occurrence times of the pre-signal parts during the test actions T1 - T4 . In this embodiment, the pre-signal portion of the test output signal DOUT may be logic 0. The testing machine 520 can sample the test output signal DOUT according to the set sampling point S0. Therefore, in the latency adjustment mode, the tester 520 can compare the above sampling result with logic 0, and then know whether the occurrence time of the preamble part of the test output signal DOUT is correct.

In FIG. 7 , in the test actions T1 and T4, the testing machine 520 can determine that the time at which the leading signal of the test output signal DOUT appears is incorrect, and in the testing actions T2 and T3, the testing machine 520 can determine that the test output signal DOUT is incorrect. The leading signal occurrence time of the output signal DOUT is correct. Accordingly, the testing machine 520 can further average the second latency and the third unit latency corresponding to the testing actions T2 and T3 to generate a set latency.

Please refer to FIG. 5 and FIG. 8 synchronously below. FIG. 8 is a waveform diagram of a test operation in the unit delay adjustment mode of the test system according to an embodiment of the present invention. The test system of the embodiment of the present invention can perform the setting action of the unit delay according to multiple test results. In FIG. 8, the delay control signal generator 513 in the test system 500 can respectively execute test actions T1'~T4' by generating different delay control signals Dctrl. Wherein, the unit delays of the test actions T1'~T4' may be different first to fourth unit delays respectively. Corresponding to different unit delays, the output driver 516 can respectively generate test output signals DOUT with different phases during the test operations T1'˜T4'. The testing machine 520 can sample the test output signal DOUT according to the set sampling points S1 - S8 . In the unit delay adjustment mode, the test output signal DOUT is generated according to the preset test data PD1˜PDn. Therefore, the testing machine 520 can compare the above sampling results with the test data PD1 ˜ PDn to know whether the test output signal DOUT is correct.

In FIG. 8, in the test actions T1' and T4', the tester 520 can determine that the test output signal DOUT is incorrect, and in the test actions T2' and T3', the tester 520 can determine that the test output signal DOUT is incorrect. DOUT is correct. Accordingly, the testing machine 520 can further average the second unit delay and the third unit delay corresponding to the test actions T2' and T3' to generate a set unit delay.

In the embodiment of the present invention, after the setting of the latency and the unit delay is completed, the test data generator 510 can be changed to receive data inside the integrated circuit, such as the read data of the memory. The testing machine 520 can sample and test the output signal DOUT according to the set sampling points to obtain the output data of the read data of the memory to complete the internal test of the memory.

In summary, the test system and its test circuit disclosed in the present invention can generate a relatively high-frequency sampling signal according to the clock signal input to the test circuit, and generate an output test signal through the sampling signal to complete the memory Part of the test action to shorten the test time. In this way, under the premise that no phase-locked loop (Phase Locked Loop, PLL) is required, the test system and its test circuit disclosed in the present invention can perform relatively high-frequency test actions without using a high-end test machine. Under certain conditions, the test rate can be effectively increased and the test cost can be reduced.

100, 200, 300, 510: test circuit 110, 210, 310, 511: command decoder 120, 220, 320, 512: trigger signal generator 130, 230, 330, 513: delay control signal generator 140, 240, 340, 514: delay circuit 150, 250, 350, 515: test data generator 341: delay line 342: Select circuit 500: test system 516: output driver 517:Test Receiver 520: Test machine BUF1~BUFn: buffer C: Capacitance CLK: clock signal CMD: test command d1~d9: test data signal D1~Dn: delayer Dctrl: delay control signal DOUT: Test output signal EN: enable signal INV1~INVn: Inverter LT_T: Latency time LTctrl: Latency control signal PB: front signal part PD1~PDn: test data R: resistance RCN: Resistor Capacitor Network S0, S1~S8: Sampling points SCK1~SCKn: sampling clock SDA: Serial Data SEL: test selection signal T1, T2, T3, T4, T1', T2', T3', T4': test action TCODE: adjust the signal TG: trigger signal VCD1~VCDn: voltage controlled delay

FIG. 1 is a schematic diagram of a test circuit according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a test circuit according to another embodiment of the present invention. FIG. 3 is a schematic diagram of a test circuit according to another embodiment of the present invention. FIG. 4A to FIG. 4D are schematic diagrams illustrating the implementation of the delay line in the embodiment of FIG. 3 of the present invention. FIG. 5 is a schematic diagram of an embodiment of the present invention. FIG. 6 is a waveform diagram of an input clock signal and a test output signal of the embodiment of the test system shown in FIG. 5 of the present invention. FIG. 7 is a waveform diagram of a test action in the latency adjustment mode of the test system of the present invention. FIG. 8 is a waveform diagram of a test operation in the unit delay adjustment mode of the test system of the present invention.

100: Test circuit

110: command decoder

120: Trigger signal generator

130: delay control signal generator

140: delay circuit

150: Test data generator

CMD: test command

CLK: clock signal

DOUT: Test output signal

TCODE: adjust the signal

Dctrl: delay control signal

TG: trigger signal

SCK1~SCKn: sampling clock

PD1~PDn: test data

Claims (18)

A test circuit receives a test command and an input clock signal to generate a test output signal, including: a command decoder for generating an adjustment signal according to decoding the test command; a trigger signal generator, which generates a trigger signal according to the input clock signal; a delay control signal generator, coupled to the command decoder, to generate a delay control signal according to the adjustment signal; a delay circuit, coupled to the delay control signal generator and the trigger signal generator, to generate a unit delay according to the delay control signal, and delay the trigger signal based on the unit delay to generate a plurality of sampling clocks; as well as A test data generator samples a plurality of test data according to the sampling clocks and converts them into a series of data. The test circuit as claimed in claim 1, wherein the delay circuit includes a plurality of voltage-controlled delayers, and the voltage-controlled delayers are connected in series, wherein each voltage-controlled delayer provides the unit delay according to the delay control signal , the voltage-controlled delays sequentially delay the trigger signal to respectively generate the sampling clocks. The test circuit as claimed in item 1, wherein the delay circuit comprises: a plurality of delayers, wherein the delayers are connected in series; and One selects the circuit, The delayers delay the trigger signal in sequence to generate a plurality of delayed signals, and the selection circuit selects part of the delayed signals according to the delay control signal to generate the sampling clocks. The test circuit as claimed in claim 3, wherein each of the delays is a buffer. The test circuit as claimed in claim 4, wherein each of the buffers further includes a resistor-capacitor network, and the resistor-capacitor network is coupled to the input terminal or the output terminal of the buffer. The test circuit as claimed in claim 3, wherein each of the delayers is an inverter. The test circuit as claimed in claim 6, wherein each of the inverters further includes a resistor-capacitor network, and the resistor-capacitor network is coupled to the input terminal or the output terminal of the inverter. The test circuit as described in claim 1, wherein the command decoder is further coupled to the trigger signal generator, the command decoder generates a latency control signal according to the test command, and the trigger signal generator generates a latency control signal according to the latency control signal , to delay the start time point of the trigger signal by a latency time. The test circuit as described in claim 8, further comprising: An output driver, coupled to the test data generator, outputs the test output signal according to the serial data. The test circuit as claimed in claim 9, wherein the output driver is further coupled to the trigger signal generator to output the test output signal according to the trigger signal and the serial data. The test circuit as claimed in claim 1, wherein the test data generator further generates the test output signal according to the serial data. A test system comprising: a testing machine; and The testing circuit as described in claim 1, the testing machine is coupled to the testing circuit, wherein the testing machine is used for: providing the test command and the input clock signal to the test circuit, and The test output signal is received, and a test result is generated according to the test output signal. The testing system according to claim 12, wherein the testing machine adjusts the unit delay through the test command, and generates a set unit delay according to the corresponding test result. The test system as described in claim 13, wherein the testing machine generates a first unit delay through a first test command, and generates a second unit delay through a second test command, when corresponding to the first test command and When a first test result and a second test result of the second test command are both passed, the tester calculates the average value of the first unit delay and the second unit delay to generate the set unit delay, wherein the first unit delay A unit of delay is different from the second unit of delay. The test system as described in claim 12, wherein the command decoder is further coupled to the trigger signal generator, the command decoder generates a latency control signal according to the test command, and the trigger signal generator generates a latency control signal according to the latency control signal , to delay the start time point of the trigger signal by a latency time. The test system as claimed in claim 15, wherein the testing machine adjusts the latency time through the test command, and generates a set latency time according to the corresponding test result. The test system as described in claim 16, wherein the testing machine generates a first latency through a first test command, and generates a second latency through a second test command, when corresponding to the first test command and When a first test result and a second test result of the second test command are both passed, the testing machine calculates the average value of the first latency and the second latency to generate the set latency, wherein the first latency A latency is different from the second latency. The test system as described in claim 12, wherein the test circuit further includes a test receiver coupled to the command decoder, the test receiver is configured to receive a test selection signal provided by the test machine, and according to the The test select signal enables the command decoder.

Images