TWI807542B - Memory system - Google Patents

Abstract

Provide a memory system in which semiconductor memory device can be accessed properly. A memory system includes: a memory controller and a semiconductor memory device. The memory controller transmits an operation and an address, and a first checking data to the semiconductor memory device. When the semiconductor memory device receives a first response information that indicating no error detected, it transmits or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the operation and the address, and the first checking data, it uses the first checking data to detect errors in the operation and the address, and transmits the first reply information when no error detected, and when no error detected in the operation or the address, transmits or receives read data or write data from the semiconductor memory device.

Description

memory system

The present invention relates to a memory system including a memory controller and a semiconductor memory device.

Known conventional memory systems include: semiconductor memory devices such as Dynamic Random Access Memory (DRAM), and memory controllers for controlling reading or writing of the semiconductor memory devices (for example, Patent Document 1: JP-A-2002-63791). The semiconductor memory device is configured to read or write data in a memory area (such as a memory cell) corresponding to the address according to the content of the command (such as a read command or a write command) when receiving a command packet including a command and an address from a memory controller.

However, in a conventional memory system, if an error occurs in a command or an address when the command packet is transmitted from the memory controller to the semiconductor memory device, the content of the command or the address may be changed. Therefore, it may become difficult to properly access the semiconductor memory device.

The memory system provided by the present invention includes: a memory controller; and a semiconductor memory device; the aforementioned memory controller is configured to: transmit instructions and addresses, and first inspection data for error detection of the aforementioned instructions and the aforementioned addresses to the aforementioned semiconductor memory device; When the command and the aforementioned address, and the aforementioned first check data, use the aforementioned first check data to perform error detection of the aforementioned command and the aforementioned address, when no error is detected in the aforementioned command and the aforementioned address, the aforementioned first response information is sent to the aforementioned memory controller;

According to the memory system of the present invention, it is possible to properly access the semiconductor memory device.

(first implementation type) As shown in FIG. 1 , the memory system includes a memory controller 10 and a semiconductor memory device 20 . In this embodiment, it is described that the semiconductor memory device 20 is a pseudo-Static Random Access Memory (pseudo-Static Random Access Memory, pSRAM) as an example. Here, pSRAM is a semiconductor memory device including an interface compatible with Static Random Access Memory (SRAM). In addition, pSRAM uses Dynamic Random Access Memory (DRAM) as memory cell memory data, and redesigns the access interface of DRAM to make it compatible with the access interface of SRAM. In this embodiment, a case where the semiconductor memory device 20 is a clock synchronous pSRAM that receives signals synchronously with a clock signal and is also an address data multiplex interface type pSRAM is shown as an example. The address-data multiplexer type pSRAM has address-data terminals configured to input each address signal and data signal. In addition, in the pSRAM of this embodiment, although the case of adopting double data rate (Double Data Rate, DDR) as the data transmission method is shown as an example, the pSRAM can also adopt single data rate (Single Data Rate, SDR).

The memory controller 10 is configured to: transmit an instruction (shown as Operation in the figure) and an address (shown as Address in the figure), and first check data (shown as CheckA in the figure) for error detection of the command and address to the semiconductor memory device 20; Or written data (shown as Data in the figure). On the other hand, the semiconductor memory device 20 is configured to perform: when receiving instructions and addresses from the memory controller 10, and the first check data, use the first check data to detect errors in the instructions and addresses, and when no errors are detected in the instructions and addresses, send the first response information (ReplyA (OK)) to the memory controller 10, and transmit or receive data read or written to the address according to the instructions between the memory controller 10.

In addition, the semiconductor memory device 20 is configured to: when any one of the command and the address detects an error, transmit the second response information (shown as ReplyA(NG) in the figure) to the memory controller 10 indicating that any one of the command and the address has detected an error. On the other hand, the memory controller 10 is configured to: when receiving the second response information (ReplyA(NG)) from the semiconductor memory device 20, retransmit the command and the address to the semiconductor memory device 20, so that the semiconductor memory device 20 can be re-accessed from the beginning.

Moreover, the memory controller 10 (one of the memory controller 10 and the semiconductor memory device 20) is configured to: transmit the written data and the second check data (shown as CheckD in the figure) for error detection of the data to the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20). On the other hand, the semiconductor memory device 20 is configured to: when receiving the data and the second check data (CheckD), use the second check data to perform data error detection, and when no error is detected in the data, send the third response information (shown as ReplyD (OK) in the figure) to the memory controller 10 indicating that no error has been detected in the data. In this case, since it is suppressed to maintain a state in which an error is included in the read or written data, the integrity of the data can be ensured.

Furthermore, the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20) is configured to perform: when an error is detected in the data, the fourth response information (shown as ReplyD (NG) shown in the figure) is transmitted to the memory controller 10 (one of the memory controller 10 and the semiconductor memory device 20 ) indicating that an error has been detected in the data; Therefore, compared with the case of re-accessing the writing of the data from the beginning (the case of re-transferring the command and address), the access efficiency can be improved. On the other hand, the memory controller 10 (one of the memory controller 10 and the semiconductor memory device 20) is configured to: when receiving the fourth response information (ReplyD(NG)), send the data and the second inspection data corresponding to the data to the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20). Therefore, when an error is detected in the data, the memory controller 10 retransmits the data, so that the data can be written again.

Furthermore, the semiconductor memory device 20 (the other one of the memory controller 10 and the semiconductor memory device 20) is configured to cancel waiting for retransmission of data when data is not retransmitted from the memory controller 10 (one of the memory controller 10 and the semiconductor memory device 20) until a specific time elapses. Therefore, in the case of no retransmission of data, the semiconductor memory device 20 can process other read or write accesses by canceling the retransmission of waiting data, and the processing efficiency of access can be improved.

The memory controller 10 is connected to an external host device (not shown in the figure), responds to commands from the host device, and accesses the semiconductor memory device 20 such as reading or writing. For example, when the memory controller 10 receives a write request for writing data into the semiconductor memory device 20 from the host device, or a read request for reading data from the semiconductor memory device 20, the chip select signal /CE is enabled (low level) and sent to the semiconductor memory device 20. In addition, the memory controller 10 transmits the clock signal received from the host device to the semiconductor memory device 20 as the external clock signal CLK.

The memory controller 10 includes a request control unit 11 and a sequence control unit 12 . The request control unit 11 and the sequence control unit 12 may also be constituted by dedicated hardware devices or logic circuits.

The memory controller 10 may also include: a central processing unit (Central Processing Unit, CPU) (omitted in the figure), memory devices such as random access memory (Random Access Memory, RAM) (omitted in the figure), a semiconductor memory device 20, and an interface (omitted in the figure) for transmitting and receiving signals between host devices. For example, the CPU of the memory controller 10 can also realize the functions of the request control unit 11 and the sequence control unit 12 by reading and executing the computer program stored in the memory device.

The request control unit 11 is configured to generate a conversion signal for converting the transmission mode of the address data signal ADQ transmitted or received between the memory controller 10 and the semiconductor memory device 20 when receiving a request for writing or reading from the semiconductor memory device 20 from the host device. Specifically, when the request control unit 11 receives a write request for writing data into the semiconductor memory device 20 from the host device, it outputs the conversion signal deson to the sequence control unit 12. The conversion signal deson is used to convert (de-serialize) the address data signal ADQ transmitted from the memory controller 10 to the semiconductor memory device 20 from the serial transmission method to the parallel transmission method of a specific number of bits (for example, 8 bits).

In addition, when the request control unit 11 receives a read request for reading data from the semiconductor memory device 20 from the host device, it outputs a conversion signal seron to the sequence control unit 12. The conversion signal seron is used to convert (serialize) the signal (such as reading data) transmitted from the semiconductor memory device 20 to the memory controller 10 from the parallel transmission method to the serial transmission method.

The sequence control unit 12 is configured to convert the transmission mode of the address data signal ADQ based on the conversion signal deson. In addition, the sequence control unit 12 includes a serializer/deserializer (SerDes) 12a and an error control unit 12b. The SerDes 12a converts the signals transmitted or received between the memory controller 10 and the semiconductor memory device 20 between the serial transmission method and the parallel transmission method. In addition, although in this embodiment, the case where the SerDes 12a deserializes the written data and serializes the read data is taken as an example for illustration, the SerDes 12a can also be configured to serialize the written data, such as from 64 bits to 8 bits, etc., and deserializes the read data. In addition, in this embodiment, the serial control unit 12 is an example of the "first serial control unit" of the present invention, and the SerDes 12a is an example of the "first serializer/deserializer" of the present invention.

For example, when the request control unit 11 receives a write request or a read request, when the converted signal deson is input from the request control unit 11, the SerDes 12a generates a read command or a write command (Operation) and an address (Address), and outputs them to the error control unit 12b. Next, SerDes 12a converts the command, address, and first check data into parallel transmission when the first check data (CheckA) for error detection of command and address (Address) is input from error control unit 12b. Next, the SerDes 12a transmits the command, address and first check data to the semiconductor memory device 20 as an address data signal ADQ.

In addition, the SerDes 12a receives from the semiconductor memory device 20 as the address data signal ADQ the first response information (ReplyA (OK)) indicating that there is no error detected in the write command and the address, and outputs the write data (Data) received from the host device to the error control unit 12b. Next, when the SerDes 12a receives the second inspection data for error detection of the written data from the error control unit 12b, the second inspection data and the written data are converted to a parallel transmission method. Then, the SerDes 12a sends the second check data and write data to the semiconductor memory device 20 as the address data signal ADQ.

Moreover, SerDes 12a receives from the semiconductor memory device 20 as the address data signal ADQ the second response information (ReplyA(NG)) indicating that any one of the write command and the address detects an error.

Furthermore, SerDes 12a receives from the semiconductor memory device 20 as the address data signal ADQ the second response information (ReplyA(NG)) indicating that any one of the read command and the address detects an error.

In addition, the SerDes 12a receives from the semiconductor memory device 20 as the address data signal ADQ the fourth response information (ReplyD(NG)) indicating that an error is detected in the write data, and then sends the write data and the second check data corresponding to the write data to the semiconductor memory device 20 as the address data signal ADQ.

For example, the second check data and the first check data can be configured as parity codes or cyclic redundancy check (Cyclic Redundancy Checking, CRC) codes and the like.

Next, the semiconductor memory device 20 includes: a sequence control unit 21; a command control unit 22; an address control unit 23; a word line control unit 24; a line control unit 25; a data control unit 26; a data bus control unit 27; The various parts 21-29 in the semiconductor memory device 20 may also be constituted by dedicated hardware devices or logic circuits.

The sequence control unit 21 is configured to convert the transmission mode of the address data signal ADQ transmitted and received between the memory controller 10 . In addition, the sequence control unit 21 includes a SerDes 21a and an error control unit 21b. Like the SerDes 12a of the memory controller 10, the SerDes 21a converts the signals transmitted or received between the memory controller 10 and the semiconductor memory device 20 between the serial transmission method and the parallel transmission method. In addition, the sequence control unit 21 is configured to transmit the data strobe signal RWDS to the sequence control unit 12 of the memory controller 10 . In addition, in this embodiment, the sequence control unit 21 is an example of the “second sequence control unit” of the present invention, the SerDes 21a is an example of the “second serializer/deserializer” of the present invention, and the error control unit 21b is an example of the “second error control unit” of the present invention.

When the SerDes 21a receives the command, address and first check data as the address data signal ADQ from the memory controller 10, it converts the command, address and first check data into a serial transmission mode and outputs it to the error control unit 21b. The error control unit 21b uses the first check data to detect errors of commands and addresses. When no error is detected from the command and address (Adress), the error control unit 21b outputs the first response information (ReplyA (OK)) indicating that no error is detected in the command and address (Adress) to the SerDes 21a.

SerDes 21a converts the first response information (ReplyA(OK)) into a parallel transmission method when the first response information (ReplyA(OK)) indicating that no error is detected in the command and address is input from the error control unit 21b, and transmits the first response information (ReplyA(OK)) to the memory controller 10 as the address data signal ADQ. In addition, in this case, the SerDes 21a outputs a signal ope indicating the content of the received command (read command or write command) to the command control unit 22 and a signal adr indicating the received address to the address control unit 23 .

On the other hand, when an error is detected in any one of the command and the address (Adress), the error control unit 21b outputs the second response information (ReplyA(NG)) indicating that any one of the command and the address (Adress) has detected an error to the SerDes 21a. SerDes 21a converts the second response information (ReplyA(NG)) into a parallel transmission method when the second response information (ReplyA(NG)) indicating an error detected in the command and address is input from the error control unit 21b, and transmits the second response information (ReplyA(NG)) to the memory controller 10 as the address data signal ADQ.

Furthermore, when the SerDes 21a receives the second check data and write data as the address data signal ADQ from the memory controller 10, it converts the second check data and write data into serial transmission and outputs them to the error control unit 21b. The error control unit 21b uses the second check data to detect errors in writing data. When no error is detected from the written data, the error control unit 21b outputs third response information (ReplyD(OK)) indicating that no error has been detected in the written data to the SerDes 21a.

SerDes 21a converts the third response information (ReplyD(OK)) into a parallel transmission method when the third response information (ReplyD(OK)) indicating that no error is detected in the written data is input from the error control unit 21b, and transmits the third response information (ReplyD(OK)) to the memory controller 10 as the address data signal ADQ. In addition, in this case, the SerDes 21a outputs a signal di indicating received data to the data control unit 26 .

On the other hand, when an error is detected from the written data, the error control unit 21b outputs fourth response information (ReplyD(NG)) indicating that an error has been detected in the written data to the SerDes 21a. SerDes 21a converts the fourth response information (ReplyD(NG)) into a parallel transmission method when the fourth response information (ReplyD(NG)) indicating that an error is detected in the written data is input from the error control unit 21b, and transmits the fourth response information (ReplyD(NG)) to the memory controller 10 as an address data signal ADQ.

Furthermore, the SerDes 21a outputs the read data to the error control unit 21b when the signal do indicating the read data is input from the data control unit 26 . Next, when the SerDes 21a inputs the second check data for error detection of the read data from the error control unit 21b, it converts the read data and the second check data into a parallel transmission method, and transmits the read data and the second check data to the memory controller 10 as an address data signal ADQ.

Furthermore, when the chip selection signal /CE changes from invalid (high level) to valid (low level), the error control unit 21b makes the signal busy (high level) indicating that the read or write access process is in progress and outputs it to the command control unit 22. The command control section 22 is configured to generate internal commands based on commands input from the memory controller 10 . Specifically, the command control unit 22 generates an internal command in response to the signal ope input from the sequence control unit 21 when a valid signal busy is input from the sequence control unit 21 . Here, the generated internal command includes, for example, a read signal, a write signal, and an update signal. The command control section 22 responds to the generated internal command, the signal wlon used to activate the word line is valid and output to the word line control section 24, the signal clon used to activate the bit line is valid and output to the row control section 25, and the signal saon used to activate the sense amplifier 28 is valid and output to the sense amplifier 28. In addition, the command control unit 22 uses the signal wloff for deactivating the word line to be valid and output to the word line control unit 24 .

The address control unit 23 is configured to control activation of word lines and bit lines corresponding to the address based on the address input from the memory controller 10 . Specifically, the address control unit 23 generates a column address signal ra indicating an activated word line and a row address signal ca indicating an activated bit line when the signal adr is input from the sequence control unit 21 . Next, the address control unit 23 outputs the generated column address signal ra to the word line control unit 24 , and outputs the generated row address signal ca to the row control unit 25 .

When the word line control unit 24 receives input from the command control unit 22 when the signal wlon is active, it outputs the signal wl for activating the word line indicated by the column address signal ra input from the address control unit 23 to the memory cell array 29 to activate (drive) the word line. In addition, when the signal wloff is input from the command control unit 22 while the signal wloff is active, the word line control unit 24 outputs the signal wl for deactivating the word line to the memory cell array 29 to deactivate the word line.

When the row control unit 25 receives input from the command control unit 22 when the signal clon is active, among the plurality of bit lines in the memory cell array 29, the signal cl for activating the bit lines indicated by the row address signal ca input from the address control unit 23 is output to the sense amplifier 28.

The data control unit 26 outputs a signal wdb indicating write data to the data bus control unit 27 when the signal di indicating write data is input from the sequence control unit 21 . In addition, the data control unit 26 outputs the signal do indicating the read data to the sequence control unit 21 when the signal rdb indicating the read data is input from the data bus control unit 27 .

The data bus control unit 27 outputs the signal cdb indicating the written data to the sense amplifier 28 when the signal wdb indicating the written data is input from the data control unit 26 . In addition, the data bus control unit 27 outputs the signal rdb indicating the read data to the data control unit 26 when the signal cdb indicating the read data is input from the sense amplifier 28 .

The sense amplifier 28 outputs the signal bl for activating the bit line shown by the signal cl input from the row control unit 25 to the memory cell array 29 when the signal saon is input from the command control unit 22 to activate (drive) the bit line. Next, the sense amplifier 28 reads and writes data to the memory cell through the activated bit line. For example, the sense amplifier 28 writes the signal cdb input from the data bus control part 27 indicating the write data into the memory cell through the activated bit line. In addition, the sense amplifier 28 outputs the data read from the memory cell to the data bus control unit 27 via the activated bit line.

The memory cell array 29 includes a plurality of memory cells (not shown) arranged in an array. In each memory cell, data input from the memory controller 10 is stored. Each memory cell can be a conventional 1T1C (1 transistor 1 capacitor) type memory cell. In addition, each memory cell is connected to a word line of any one of the plurality of word lines and a bit line of any one of the plurality of bit lines.

Referring to FIG. 2, a case where a write command is input from the memory controller 10 will be described as an example.

Firstly, when the semiconductor memory device 20 receives the command, the address and the first check data from the memory controller 10, it uses the first check data to detect the error of the command and the address. Then, when no error is detected, the semiconductor memory device 20 sends the first response information (ReplyA(OK)) indicating that no error is detected in the command and address to the memory controller 10 . In addition, the first response information (ReplyA(OK)) may be transmitted during the period from when a command and an address are input to when data is input or output.

In addition, the semiconductor memory device 20 makes the signal wlon active (high level) when no error is detected in the command and address. In this case, the signal wl is asserted (high level) used to activate the word line corresponding to the address.

On the other hand, when the memory controller 10 receives the first response information (ReplyA(OK)), it transmits the second checking data and writing data to the semiconductor memory device 20 . In addition, the second inspection data can also be transmitted during the delay.

When the semiconductor memory device 20 receives the second check data and the write data from the memory controller 10 , it uses the second check data to detect errors in the write data. In addition, the semiconductor memory device 20 makes the signal cl of the bit line corresponding to the address valid (high level). At this time, the sense amplifier 28 of the semiconductor memory device 20 can write the writing data into the memory cells in the memory cell array 29 by activating the bit line corresponding to the address.

Furthermore, when the semiconductor memory device 20 receives the write data and the chip selection signal/CE is invalid (high level), it will send the response information (the third response information (ReplyD(OK) or the fourth response information (ReplyD(NG))) indicating whether an error is detected in the write data to the memory controller 10.

In addition, the semiconductor memory device 20 makes the signal wloff active (high level) when the write data is correctly written into the memory cells in the memory cell array 29 . Therefore, the signal wl is deasserted (low level). In this way, when the memory controller 10 receives the first response information (ReplyA (OK)) from the semiconductor memory device 20 indicating that no error has been detected in the command and address, it can transmit data written to the address with the semiconductor memory device 20 .

Referring to FIG. 3 , a case where a write command is input from the memory controller 10 will be described as an example.

Firstly, when the semiconductor memory device 20 receives the command, the address and the first check data from the memory controller 10, it uses the first check data to detect the error of the command and the address. Then, when an error is detected, the semiconductor memory device 20 transmits the second response information (ReplyA(NG)) indicating that any one of the command and address has detected an error to the memory controller 10 . In addition, in this case, the semiconductor memory device 20 does not activate the word line and the bit line corresponding to the address.

On the other hand, when the memory controller 10 receives the second response information (ReplyA(NG)), it retransmits the command, the address and the first check data to the semiconductor memory device 20 .

When the semiconductor memory device 20 receives retransmitted commands, addresses and first check data from the memory controller 10, it uses the first check data to detect errors in the commands and addresses. Then, when no error is detected, the semiconductor memory device 20 sends the first response information (ReplyA(OK)) indicating that no error is detected in the command and address to the memory controller 10 . In addition, the operation of the semiconductor memory device 20 thereafter is the same as the example shown in FIG. 2 .

When an error is detected in the command and address, the memory controller 10 retransmits the command and address to the semiconductor memory device 20, so that the semiconductor memory device 20 can resume access from the beginning without starting an error operation.

Referring to FIG. 4, a case where a write command is input from the memory controller 10 will be described as an example.

Firstly, when the semiconductor memory device 20 receives the command, the address and the first check data from the memory controller 10, it uses the first check data to detect the error of the command and the address. In addition, the semiconductor memory device 20 makes the signal busy active (high level) when the chip select signal /CE changes from inactive (high level) to active (low level).

In addition, after the semiconductor memory device 20 transmits the first response information (ReplyA(OK)) to the memory controller 10, when receiving the second check data and write data, it uses the second check data to detect write data errors. In addition, as described above, the semiconductor memory device 20 performs writing of writing data.

Here, when an error is detected in the written data, the semiconductor memory device 20 transmits the fourth response information (ReplyD(NG)) indicating that an error has been detected in the written data to the memory controller 10 when the chip select signal /CE is invalid (high level). In addition, in this case, the semiconductor memory device 20 maintains the respective valid states of the signal wl and the signal busy.

On the other hand, when the memory controller 10 receives the fourth response information (ReplyD(NG)), it retransmits the second check data and write data to the semiconductor memory device 20 .

When the semiconductor memory device 20 receives the retransmitted second check data and write data from the memory controller 10 , it uses the second check data to detect errors in the write data. In addition, the semiconductor memory device 20 performs writing of writing data again. Next, if no error is detected in the written data, the semiconductor memory device 20 transmits the third response information (ReplyD(OK)) indicating that no error has been detected in the written data to the memory controller 10 . In addition, the semiconductor memory device 20 disables (low level) the signal wl and the signal busy respectively.

In this way, according to the memory system of this embodiment, it is possible to suppress the state in which errors are included in reading or writing data. In addition, according to the memory system related to the present embodiment, even in the case where an error is detected in the data, by waiting for the data to be transmitted, the semiconductor memory device 20 can continue access related to writing of the data. In addition, the semiconductor memory device 20 maintains the valid state of the signal wl while waiting for data to be retransmitted. For example, in the case of command and address retransmission, since the waiting time (delay) until the activation of the sense amplifier becomes unnecessary, the operation time can be shortened.

In addition, in this embodiment, the case where only the data is retransmitted when an error is detected in the data is described as an example, but the present invention is not limited to this case. For example, it is also possible to retransmit the command, and also retransmit the address corresponding to the row address signal ra and/or the row address signal ca, or retransmit the command and the address.

Furthermore, according to the memory system of this embodiment, when an error is detected in the data, the memory controller 10 retransmits the data, so that the data can be written again.

Referring to FIG. 5, a case where a write command is input from the memory controller 10 will be described as an example.

First, when an error is detected in the written data, the semiconductor memory device 20 deactivates the chip selection signal /CE (high level), and transmits the fourth response information (ReplyD(NG)) indicating that an error has been detected in the written data to the memory controller 10 . In addition, the operation of the semiconductor memory device 20 until an error is detected in writing data is the same as the example described with reference to FIG. 4 .

Here, the semiconductor memory device 20 may deactivate (low level) each of the signal wl and the signal busy when the second check data and write data are not received from the memory controller 10 during the period from the transmission of the fourth response information (ReplyD(NG)) to the memory controller 10 until a specific time elapses. Therefore, the standby state for retransmission of written data is released. In addition, the semiconductor memory device 20 may also measure elapsed time by using a built-in timer circuit (not shown in the figure) or the like.

In this way, according to the memory system of the present embodiment, the semiconductor memory device 20 can process another read or write access by canceling the wait for the retransmission of the data without retransmitting the data.

Next, with reference to FIG. 6, the semiconductor memory device 20 in the standby state (Standby) enables the chip selection signal /CE to be valid (low level), and when the command, address and first check data are input, the first check data is used to perform command and address error checks (step S100). Next, when the semiconductor memory device 20 detects an error (step S101: Yes), it outputs the second response information (ReplyA(NG)) to the memory controller 10, and shifts to the standby state. In addition, when no error is detected (step S101: No), the semiconductor memory device 20 outputs the first response information (ReplyA (OK)) to the memory controller 10, and transitions to the active state (Active).

When the semiconductor memory device 20 is transferred to the active state (Active), the memory cell 29 is activated (activation of the word line and the bit line) (step S102).

Next, the semiconductor memory device 20 performs read or write access according to the command and address (step S103 ). Here, in the case of write access, the semiconductor memory device 20 performs write access after receiving the second test data and write data.

In addition, the semiconductor memory device 20 uses the second check data to check the error of the written data (step S104 ).

Here, when an error is detected in the data (step S105: Yes), the semiconductor memory device 20 outputs the fourth response information (ReplyD(NG)) to the memory controller 10, and shifts to a state of waiting for retransmission of the data. Next, when the chip selection signal /CE is valid (low level), the semiconductor memory device 20 shifts to the processing of step S103. In addition, when the semiconductor memory device 20 waits for the retransmission of data for a certain period of time, it shifts to the processing of step S106 to be described later. When no error is detected in the data (step S105: No), the semiconductor memory device 20 outputs the third response information (ReplyD (OK)) to the memory controller 10, and performs inactivation of the memory cell array 29 (inactivation of the word line and the bit line) (step S106), and transfers to the standby state.

As mentioned above, according to the memory system of this embodiment, when the memory controller 10 receives the first response information (ReplyA (OK)) from the semiconductor memory device 20 indicating that no error has been detected in the command and address, it can transmit or receive data read or written to the address with the semiconductor memory device 20. Therefore, when a command packet is being transmitted, it becomes possible to suppress inappropriate access due to a change in the content of the command or an address, and access to the semiconductor memory device 20 can be appropriately performed. In addition, according to the memory system of this embodiment, the virtual static random access memory can be properly accessed.

(Second Implementation Type) The memory system of the second embodiment of the present invention will be described below. The semiconductor memory device 20 includes a plurality of memory banks for interleaved access.

Referring to FIG. 7 and FIG. 8 , the case where the semiconductor memory device 20 includes two memory banks (BNK0 and BNK1 ) will be described as an example. The time chart shown in Figure 7(a) and Figure 7(b) follows Figure 7(b) after Figure 7(a), showing a continuous time course, and the same is true for Figure 8(a) and (b).

As shown in FIG. 7, the semiconductor memory device can be configured such that the other memory bank (BNK1) can be accessed from the input of the command (Operation (BNK0)), the address (Address (BNK0)) and the first check data (CheckA (BNK0)) to one of the memory banks (BNK0) until the delay period until the data (Data (BNK0)) is input or output.

Same as the first embodiment, when no error is detected in the instruction (Operation (BNK0)) and address (Address (BNK0)) for one of the memory banks (BNK0), the semiconductor memory device 20 makes the word line wl (BNK0) of the corresponding address (Address (BNK0, row=Rm (Rm shows the column address, m is an integer))) effective (high level).

In addition, the semiconductor memory device 20 performs access to the other memory bank (BNK1) during the delay (delay (BNK0)) of the access to one of the memory banks (BNK0). Here, the semiconductor memory device 20 reads or writes data (Data (BNK1)) corresponding to an address (Address (BNK1, row=Ri (Ri indicates a column address, i is an integer))) received before the delay in accessing the other memory bank (BNK1) during access to the other memory bank (BNK1). Next, the semiconductor memory device 20, when no error is detected in the data (Data (BNK1)) (ReplyD (BNK1) is OK), receives the next access command (Operation (BNK1)) and address (Address (BNK1, row=Rj (Rj displays the column address, j is an integer))) to the other memory bank (BNK1). At this time, the semiconductor memory device 20 makes the word line wl (BNK1) corresponding to the address (Address (BNK1, row=Rj)) active (high level).

Next, the semiconductor memory device 20 accesses one of the memory banks (BNK0) during the delay (delay (BNK1)) of access to the other memory bank (BNK1). Here, the semiconductor memory device 20 reads or writes data (Data (BNK0)) corresponding to an address (Address (BNK0, row=Rm)) received before the delay of access to one of the memory banks (BNK0) during access to one of the memory banks (BNK0). Next, the semiconductor memory device 20, when no error is detected in the data (Data (BNK0)) (ReplyD (BNK0) is OK), receives the next access command (Operation (BNK0)) and address (Address (BNK0, row=Rn (Rn shows the column address, n is an integer))) to one of the memory banks (BNK0). At this time, the semiconductor memory device 20 makes the word line wl (BNK0) corresponding to the address (Address (BNK0, row=Rn)) active (high level).

As shown in FIG. 8, during access to one of the memory banks (BNK0), when an error is detected in the data (Data (BNK0)) (ReplyD (BNK0) is NG), after the semiconductor memory device 20 receives the data (Data (BNK0)) that has not detected an error, it can also receive the next access command (Operation (BNK0)) and address (Address (BNK0, row=Rn)). The delay of access to the other bank (BNK1) is extended (delay(BNK1)).

As described above, according to the memory system of the present embodiment, access to the semiconductor memory device 20 can be accelerated since a plurality of memory banks can be accessed in parallel at the same time.

(Third implementation type) A memory system according to a third embodiment of the present invention will be described below, in which the semiconductor memory device 20 is configured to internally generate refresh requests for performing memory cell refresh.

The semiconductor memory device 20 is configured to stop updating by retransmitting any one of the command, address, and data from the memory controller 10 until no error is detected when an error is detected in any one of the command, address, and data received from the memory controller 10 between generation of the refresh request signal and execution of the refresh.

Referring to FIG. 9, a case where a write command is input from the memory controller 10 will be described as an example.

First, when the chip selection signal /CE changes from valid (high level) to invalid (low level), the semiconductor memory device 20 makes the signal busy valid (high level), and the semiconductor memory device 20 internally generates (valid) the update request signal refreq during the period of receiving instructions, addresses and first inspection data, and uses the signal refwait to wait for the execution of the update to be valid (high level). For example, the refresh request signal refreq and the signal refwait can also be generated by the command control unit 22 of the semiconductor memory device 20 .

Next, when the semiconductor memory device 20 detects an error in the command and address, it sends the second response information (ReplyA(NG)) indicating the detected error to the memory controller 10 .

Then, when the semiconductor memory device 20 does not detect an error in the command and address retransmitted from the memory controller 10, it receives write data from the memory controller 10, and writes the received write data.

Next, when the semiconductor memory device 20 detects no error in the written data (when the third response information (ReplyD(OK)) is sent to the memory controller 10), the signal refwait is disabled (low level). In addition, the semiconductor memory device 20 executes refresh when the signal refwait is invalid (low level). Specifically, the semiconductor memory device 20 activates the signal wlon (high level) and the signal wl (high level) in order to activate the word line to be updated. In addition, the semiconductor memory device 20 uses the signal bl active (high level) for activating the bit line in order to execute refresh. Next, the semiconductor memory device 20 executes updating. In addition, when the refresh is completed, the semiconductor memory device 20 makes the signal wloff valid (high level) and at the same time makes the signal wl invalid (low level).

Although the description is omitted in the figure, when the semiconductor memory device 20 detects an error in the data, it can also wait for the execution of the update (the signal refwait is valid (high level)), until no error is detected in the data transmitted from the memory controller 10.

By stopping the execution of the update until no error is detected in any of the command, address, and data, it is possible to suppress the access delay caused by performing the update.

In addition, as a modified example of the third embodiment, the semiconductor memory device 20 may also transmit the fifth response information indicating the execution of the update to the memory controller 10 when an error is detected in any one of the command, address, and data received from the memory controller 10 during the period from generating the update request signal refreq to executing the update, and performing the update.

Referring to FIG. 10, a case where a write command is input from the memory controller 10 will be described as an example.

First, the semiconductor memory device 20 makes the signal busy active (high level) when the chip selection signal /CE changes from inactive (high level) to active (low level). Here, when the semiconductor memory device 20 internally generates (validates) the refresh request signal refreq during the period of receiving the command, the address and the first check data, the signal refwait used to wait for the execution of the refresh is valid.

Next, the semiconductor memory device 20 transmits the second response information (ReplyA(NG)) indicating the detected error to the memory controller 10 when an error is detected in the command and address. Here, the second response information (ReplyA(NG)) may also include fifth response information (shown as "Ref next" in the figure) indicating the update execution.

On the other hand, when the memory controller 10 receives the second response information (ReplyA(NG)) including the fifth response information ("Ref next"), it may also consider performing an update in the semiconductor memory device 20 until a certain time elapses, waiting for the transmission of the next accessing command (Operation), address and first check data.

Next, the semiconductor memory device 20 deactivates the signal busy (low level) once, and then enables it (high level). In addition, the semiconductor memory device 20 responds to the invalid (low level) signal busy to start updating, and makes the signal refwait invalid (low level). Next, the semiconductor memory device 20 performs the processing in the next access after finishing execution of the update.

By executing refresh when an error is detected in any of command, address, and data, for example, it is possible to suppress loss of memory information of semiconductor memory device 20 due to non-refreshing during a period in which retransmission of any of command, address, and data is repeatedly performed.

In the above-mentioned embodiments, although the case where the semiconductor memory device 20 is a pSRAM is taken as an example for description, the present invention is not limited to this case. For example, the semiconductor memory device 20 may also be a DRAM, a flash memory, or other semiconductor memory devices.

In addition, in the above-mentioned embodiment, although the case where the memory controller 10 transmits the write command (Operation (Write)) to the semiconductor memory device 20 is described as an example, even if the memory controller 10 transmits the read command (Operation (Read)) to the semiconductor memory device 20, the same effect as the above-mentioned embodiment can be obtained.

The semiconductor memory device 20 (one of the memory controller 10 and the semiconductor memory device 20) may also transmit the read data and the second check data for error detection of the read data to the memory controller 10 (the other of the memory controller 10 and the semiconductor memory device 20). In addition, when the memory controller 10 receives the read data and the second check data for error detection of the read data, it can also use the second check data to detect errors in the read data. When no error is detected in the read data, the third response information (ReplyD (OK)) indicating that no error has been detected in the read data is sent to the semiconductor memory device 20 to confirm that the read data has properly reached the memory controller 10.

In addition, when the memory controller 10 (the other of the memory controller 10 and the semiconductor memory device 20) detects an error in the data, it can also transmit the fourth response information (ReplyD(NG)) indicating that an error has been detected in the data to the semiconductor memory device 20 (one of the memory controller 10 and the semiconductor memory device 20), and wait until a specific time passes to transmit the data from the semiconductor memory device 20. Even when an error is detected in the data, the memory controller 10 can continue the access related to the read of the data by waiting for the data to be retransmitted. Therefore, the access efficiency can be improved compared with the case of re-accessing the reading of the data from the beginning (the case of re-sending the command and the address).

Furthermore, when the semiconductor memory device 20 (one of the memory controller 10 and the semiconductor memory device 20) receives the fourth response information (ReplyD(NG)), it can also send the data and the second check data corresponding to the data to the memory controller 10 (the other one of the memory controller 10 and the semiconductor memory device 20). Therefore, when an error is detected in the data, the data can be read again by retransmitting the data through the semiconductor memory device 20 .

In addition, the memory controller (the other one of the memory controller 10 and the semiconductor memory device 20) may cancel waiting for retransmission of data when no data is retransmitted from the semiconductor memory device 20 (one of the memory controller 10 and the semiconductor memory device 20) until a specific time elapses. In this case, the memory controller 10 can process other read or write accesses by canceling the waiting for the retransmission of the data without retransmitting the data, which can improve the processing efficiency of the access.

In the above-mentioned embodiment, although the case where the first inspection data is transmitted separately from the command and the address is described as an example, the present invention is not limited to this case. Fig. 11 shows an example of bit division of commands and addresses. In addition, it is assumed here that the semiconductor memory device 20 is a pSRAM.

In the example shown in FIG. 11 , each rising edge and falling edge of the external clock signal CLK inputs 8-bit address data signals ADQ[7]˜ADQ[0]. The command is configured in the address data signal ADQ[7]~ADQ[5] input on the rising edge of the first external clock signal CLK, and the address (Address[31]~Address[0]) is configured in the address data signal ADQ input from the first external clock signal CLK to the third external clock signal CLK. In addition, although the address data signals ADQ[7]~ADQ[0] input during the rising edge of the third external clock signal CLK and the address data signals ADQ[7]~ADQ[3] input during the falling edge of the third external clock signal CLK are reserved areas, they are unused areas. Here, at least a part of the reserved area may be used as the first inspection data. Therefore, the semiconductor memory device 20 becomes able to receive the first inspection data and the address at the same time. In addition, the first inspection data may also be arranged in the address data signal ADQ input on the rising edge or falling edge of the fourth and subsequent external clock signal CLK.

In addition, the data strobe signal RWDS can also be configured to represent the fifth response information for display execution update. For example, when the data strobe signal RWDS is at a high level (H), it may represent the fifth response message (“Ref next”) for displaying and updating. On the other hand, when the data strobe signal RWDS is at a low level (L), it can also represent a signal (“Immediate”) that can directly transmit and receive the address data signal ADQ.

As shown in FIG. 12, the data strobe signal RWDS can also be configured to represent the first response message (ReplyA(OK)) or the second response message (ReplyA(NG)). For example, when the logic level (high level or low level) of the data strobe signal RWDS is maintained (“kept”) during the rising edge of the fourth external clock signal CLK, the data strobe signal RWDS can also represent the first response message (ReplyA(OK)). On the other hand, when the logic level (high level or low level) of the data strobe signal RWDS is inverted (“inverted”) on the rising edge of the fourth external clock signal CLK, the data strobe signal RWDS can also represent the second response information (ReplyA(NG)). In addition, for example, it is also possible to respond to the state of the data strobe signal RWDS on the rising edge or falling edge of the fifth external clock signal CLK, representing the first response information (ReplyA(OK)) or the second response information (ReplyA(NG)).

10: Memory Controller 11: Request Control Department 12: Sequence Control Department 12a: Serializer/deserializer (Serializer/deserializer) (SerDes) 12b: Error control section 20: Semiconductor memory device 21: Sequence Control Department 21a: Serializer/Deserializer (SerDes) 21b: Error Control Section 22: Command Control Department 23: Address Control Section 24: Character Line Control Section 25: Row Control Department 26: Data Control Department 27: Data bus control section 28: Sense amplifier 29: Memory cell array Address: address ADQ: Address data signal BANK, BNK0, BNK1: memory banks /CE: chip select signal CheckA: first check data CheckD: The second check data CLK: external clock signal Data: data Deson, Seron: Change the signal Operation: instruction ReplyA: Response information ReplyD: Response information Retryrd, Retrywr: Signal RWDS: data strobe signal S100~S108: Flow chart steps adr, bl, busy: signal ca: row address signal cdb, rdb, wdb: signal cl: bit line clon: signal to activate the bit line di, do: signal ope: signal ra: row address signal refreq: Refresh request signal refwait: signal saon: signal wl: character line wloff: signal wlon: signal

[FIG. 1] is a block diagram showing a configuration example of a memory system related to the first embodiment of the present invention. [Fig. 2] is a time chart showing the timing of signals in the semiconductor memory device when no errors are included in commands and addresses. [FIG. 3] is a time chart showing the timing of signals in the semiconductor memory device when an error is included in any of the command and the address. [Fig. 4] is a time chart showing the timing of signals in a semiconductor memory device when data contains errors. [FIG. 5] is a time chart showing the time course of signals in a semiconductor memory device when a specific time elapses while waiting for data to be retransmitted. [FIG. 6] is a flow chart showing an example of the operation of a semiconductor memory device. [Fig. 7] (a) and (b) are time charts showing the timing of signals in the semiconductor memory device in the memory system related to the second embodiment of the present invention. [Fig. 8] (a) and (b) are time charts showing the timing of signals in the semiconductor memory device. [FIG. 9] It is a time chart showing the timing of signals in the semiconductor memory device in the memory system related to the third embodiment of the present invention. [Fig. 10] It is a time chart showing the timing of signals in the semiconductor memory device. [FIG. 11] is a schematic diagram showing an example of bit allocation of commands and addresses. [FIG. 12] is a timing diagram showing the timing of the data strobe signal.

10: Memory Controller 11: Request Control Department 12: Sequence Control Department 12a: Serializer/deserializer (Serializer/deserializer) (SerDes) 12b: Error control section 20: Semiconductor memory device 21: Sequence Control Department 21a: Serializer/Deserializer (SerDes) 21b: Error Control Section 22: Command Control Department 23: Address Control Section 24: Character Line Control Section 25: Row Control Department 26: Data Control Department 27: Data bus control section 28: Sense amplifier 29: Memory cell array Address: address ADQ: Address data signal /CE: chip select signal CheckA: first check data CheckD: The second check data CLK: external clock signal Data: data Deson, Seron: Change the signal Operation: instruction ReplyA: Response information ReplyD: Response information Retryrd, Retrywr: Signal RWDS: data strobe signal adr, bl, busy: signal ca: row address signal cdb, rdb, wdb: signal cl: bit line clon: signal to activate the bit line di, do: signal ope: signal ra: row address signal saon: signal wl: word line wloff: signal wlon: signal

Claims (15)

A memory system comprising: memory controller; and Semiconductor memory devices; The aforementioned memory controller, configured to: transmitting the command and address, and the first check data for error detection of the aforementioned command and the aforementioned address to the aforementioned semiconductor memory device; and When receiving the first response information from the aforementioned semiconductor memory device indicating that no error has been detected in the aforementioned command and the aforementioned address, transmit or receive data read or written to the aforementioned address according to the aforementioned command with the aforementioned semiconductor memory device; The aforementioned semiconductor memory device configured to: When receiving the aforementioned command, the aforementioned address, and the aforementioned first check data from the aforementioned memory controller, use the aforementioned first check data to perform error detection on the aforementioned command and the aforementioned address, and when no error is detected in the aforementioned command and the aforementioned address, send the aforementioned first response information to the aforementioned memory controller; and When no error is detected in the aforementioned command and the aforementioned address, the data read or written to the aforementioned address is transmitted or received according to the aforementioned command with the aforementioned memory controller. The memory system according to claim 1, wherein the aforementioned semiconductor memory device is configured as: When any one of the aforementioned command and the aforementioned address detects an error, sending the second response information indicating that any of the aforementioned command and the aforementioned address detects an error to the aforementioned memory controller; The foregoing memory controller is configured as: When receiving the second response information from the semiconductor memory device, retransmit the command and the address to the semiconductor memory device. Such as the memory system of claim 1, wherein One of the aforementioned memory controller and the aforementioned semiconductor memory device is configured to: Sending the aforementioned read or written data, and the second check data for error detection of the aforementioned data to the other of the aforementioned memory controller and the aforementioned semiconductor memory device; The other of the aforementioned memory controller and the aforementioned semiconductor memory device is configured to: When receiving the aforementioned data and the aforementioned second check data, use the aforementioned second check data to perform error detection on the aforementioned data, and when no error is detected in the aforementioned data, send the third response information indicating that no error has been detected in the aforementioned data to one of the aforementioned memory controller and the aforementioned semiconductor memory device. Such as the memory system of claim 3, wherein The other of the aforementioned memory controller and the aforementioned semiconductor memory device is configured to perform: When an error is detected in the aforementioned data, a fourth response message indicating that an error is detected in the aforementioned data is sent to one of the aforementioned memory controller and the aforementioned semiconductor memory device; and Waiting for the data to be retransmitted from one of the memory controller and the semiconductor memory device until a specific time elapses. Such as the memory system of claim 4, wherein One of the aforementioned memory controller and the aforementioned semiconductor memory device is configured to: When receiving the aforementioned fourth response information, the aforementioned data and the aforementioned second inspection data corresponding to the aforementioned data are sent to the other of the aforementioned memory controller and the aforementioned semiconductor memory device. Such as the memory system of claim 4, wherein The other of the aforementioned memory controller and the aforementioned semiconductor memory device is configured to: When the data is not retransmitted from one of the memory controller and the semiconductor memory device until the specified time elapses, the waiting for retransmission of the data is cancelled. The memory system according to claim 1, wherein the aforementioned semiconductor memory device further includes: a plurality of memory banks (banks) accessed in an interleaved manner. The memory system according to claim 1, wherein, when the semiconductor memory device is configured to internally generate an update request signal for performing the update, when an error is detected in any of the command, the address, and the data received from the memory controller between the generation of the refresh request signal and the execution of the update, execution of the update is stopped by retransmitting any of the command, address, and data from the memory controller until the error becomes undetected. The memory system according to claim 1, wherein, when the semiconductor memory device is configured to internally generate an update request signal for performing the update, it is configured to transmit fifth response information indicating that the update is executed to the memory controller when an error is detected in any of the command, the address, and the data received from the memory controller between the generation of the update request signal and the execution of the update. The memory system according to claim 1, wherein the aforementioned semiconductor memory device is a virtual static random access memory. The memory system according to claim 1, wherein the aforementioned memory controller includes: The request control unit, when receiving a request from the host device to write or read the semiconductor memory device, generates a conversion signal, the conversion signal is used to convert the transmission method of the address data signal transmitted or received between the memory controller and the semiconductor memory device; and The first sequence control unit converts the transmission method of the address data signal based on the conversion signal; in The aforementioned first sequence control unit includes: a first serializer/deserializer serializing or deserializing the address signal based on the conversion signal; and The first error control unit uses the aforementioned instruction and the aforementioned address to generate the aforementioned first inspection data; Wherein, the aforementioned first serializer/deserializer is configured to: When the request control unit receives write, when the conversion signal is input from the request control unit, a write command and an address are generated and output to the first error control unit; When the first check data corresponding to the generated write command and address is input from the first error control unit, the generated write command and address and the first check data are sent to the semiconductor memory device as the address data signal; and When receiving the generated write command from the semiconductor memory device and the first response information indicating that no error has been detected in the address as the address data signal, the write data received from the host device is output to the first error control unit. The memory system according to claim 11, wherein the first error control unit is configured to use the written data to generate second check data for error detection of the written data; The serializer/deserializer is configured to transmit the second check data and the write data as the address data signal to the semiconductor memory device when the second check data is input from the first error control unit. The memory system according to claim 11, wherein the first error control unit is configured to generate a signal for retransmitting the write command and address and the first check data when receiving second response information indicating that an error has been detected from any of the write command and address from the semiconductor memory device as the address data signal; The first serializer/deserializer is configured to, when receiving the second response information from the semiconductor memory device as the address data signal, retransmit the write command, the address and the first check data as the address data signal to the semiconductor memory device when a signal for retransmitting the write command, the address, and the first check data is input from the first error control section. The memory system according to claim 11, wherein the aforementioned semiconductor memory device further includes a second serial control unit for converting the transmission method of the aforementioned address data signal transmitted or received between the aforementioned memory controller; The aforementioned second sequence control unit includes: a second serializer/deserializer for serializing or deserializing the aforementioned address data signal; and The second error control unit uses the first inspection data received from the memory controller to detect errors of the command and the address; The aforementioned second serializer/deserializer is configured to: In the case of receiving the aforementioned command, the aforementioned address, and the aforementioned first check data from the aforementioned memory controller as the aforementioned address data signal, converting the aforementioned command, the aforementioned address, and the aforementioned first check data into a serial transmission method and outputting it to the aforementioned second error control unit; When the aforementioned first response information is input from the aforementioned second error control unit, the aforementioned first response information is converted into a parallel transmission method, the aforementioned first response information is output to the memory controller as the aforementioned address data signal, the signal displaying the content of the aforementioned command is output to the command control unit that generates an internal command based on the aforementioned command, and the signal displaying the aforementioned address is output to the address control unit that controls activation of the word line and bit line corresponding to the aforementioned address; and When the aforementioned second response information is input from the aforementioned second error control unit, the aforementioned second response information is transformed into a parallel transmission method, and the aforementioned second response information is sent to the aforementioned memory controller as the aforementioned address data signal. Such as the memory system of claim 14, wherein The aforementioned second error control unit is configured to use the second check data for error detection of the aforementioned written data to perform error detection of the aforementioned written data; The aforementioned second serializer/deserializer is configured to: When receiving the write data and second check data for error detection of the write data from the memory controller as address data signals, output the write data and the second check data to the second error control unit; When the fourth response information indicating that an error is detected in the write data is input from the second error control unit, the fourth response information is sent to the memory controller as the address data signal.