KR102645215B1 - Memory system - Google Patents

Abstract

[Project] Provide a memory system that can properly access semiconductor memory devices.
[Solution] The memory system includes a memory controller 10 and a semiconductor memory device 20. The memory controller 10 transmits a command, an address, and first inspection data to the semiconductor memory device 20, and when receiving first response information indicating that an error has not been detected from the semiconductor memory device 20, , data to be read or written is transmitted or received to and from the semiconductor memory device 20. When receiving a command, an address, and first inspection data, the semiconductor memory device 20 detects errors in the command and address using the first inspection data, and when no error is detected, first response information. is transmitted, and when no error is detected in the command or address, the data to be read or written is transmitted or received to and from the memory controller 10.

Description

Memory system{MEMORY SYSTEM}

The present invention relates to a memory system including a memory controller and a semiconductor memory device.

Conventionally, a memory system including a semiconductor memory device such as DRAM (Dynamic Random Access Memory) and a memory controller that performs control such as reading or writing to the semiconductor memory device is known (for example, patent document 1).

In such a memory system, when the semiconductor memory device receives a command packet containing a command and an address from the memory controller, the semiconductor memory device creates a storage area corresponding to the address based on the contents of the command (e.g., read command, write command). It is configured to read or write data (for example, a memory cell).

J.P. 2002-63791 A

However, in a conventional memory system, if an error (bit error) occurs in a command or address during transmission of a command packet from a memory controller to a semiconductor memory device, the contents of the command or the address may change. As a result, there was a risk that it would become difficult to properly access the semiconductor memory device.

The present invention was made in view of the above problems, and its purpose is to provide a memory system capable of appropriately accessing a semiconductor memory device.

In order to solve the above problem, the present invention includes a memory controller and a semiconductor memory device, wherein the memory controller stores a command and an address and first test data for detecting errors in the command and the address into the semiconductor memory. When first response information indicating that an error is not detected in the command and the address is received from the semiconductor memory device, the data to be read or written to the address based on the command is transmitted to the device. It is configured to perform transmission or reception to and from a semiconductor memory device, wherein the semiconductor memory device performs the first test when receiving the command, the address, and the first test data from the memory controller. Performing error detection of the command and the address using data, and transmitting the first response information to the memory controller when an error is not detected in the command and the address; and detecting an error in the command and the address. Provided is a memory system configured to transmit or receive data to be read or written to the address based on the command when not detected, to and from the memory controller (invention 1).

According to this invention (invention 1), when the memory controller receives first response information indicating that no error has been detected in the command and address from the semiconductor memory device, the memory controller stores data to be read or written for the address in the semiconductor memory device. It becomes possible to transmit or receive data to and from the device. This makes it possible to suppress inappropriate access due to changes in the content or address of the command during transmission of the command packet, making it possible to access the semiconductor memory device appropriately.

In the above invention (invention 1), when an error is detected in either the command or the address, the semiconductor memory device sends second response information indicating that an error has been detected in either the command or the address. is configured to transmit to the memory controller, and the memory controller may be configured to retransmit the command and the address to the semiconductor memory device when the second response information is received from the semiconductor memory device (invention 2).

According to this invention (invention 2), when an error is detected in either the command or the address, the memory controller retransmits the command and address to the semiconductor memory device, so that the semiconductor memory device does not initiate an incorrect operation and allows access. You can restart from the beginning.

In the above inventions (inventions 1 to 2), one of the memory controller and the semiconductor memory device sends the data to be read or written and second inspection data for detecting errors in the data to the memory controller and the semiconductor memory device. configured to transmit to the other of the devices, wherein the other of the memory controller and the semiconductor memory device, when receiving the data and the second test data, uses the second test data to detect errors in the data. When detection is performed and an error is not detected in the data, third response information indicating that an error is not detected in the data may be transmitted to one of the memory controller and the semiconductor memory device (Invention 3) .

According to this invention (invention 3), it is possible to prevent a state containing errors in data being read or written from being maintained, and thus the integrity of the data can be ensured.

In the above invention (invention 3), when an error is detected in the data, the other of the memory controller and the semiconductor memory device sends fourth response information indicating that an error has been detected in the data to the memory controller and the semiconductor memory device. It may be configured to transmit to one of the semiconductor memory devices and wait until a predetermined time elapses for the data to be retransmitted from one of the memory controller and the semiconductor memory device (invention 4).

According to this invention (invention 4), even if an error is detected in data, the other of the memory controller and the semiconductor memory device continues access to read or write the data by waiting for the data to be retransmitted. It becomes possible to do it. This makes it possible to increase access efficiency compared to, for example, the case where access to read or write this data is restarted from the beginning (when the command and address are retransmitted).

In the above invention (invention 4), when one of the memory controller and the semiconductor memory device receives the fourth response information, the data and the second test data corresponding to the data are sent to the memory controller. and may be configured to retransmit to the other of the semiconductor memory devices (invention 5).

According to this invention (invention 5), when an error is detected in data, one of the memory controller and the semiconductor memory device retransmits the data, so that the data can be read or written again.

In the above inventions (inventions 4 to 5), when the other of the memory controller and the semiconductor memory device does not retransmit the data from one of the memory controller and the semiconductor memory device until the predetermined time elapses. Alternatively, it may be configured to cancel waiting for retransmission of the data (invention 6).

According to this invention (invention 6), the other of the memory controller and the semiconductor memory device releases the waiting for retransmission of the data when the data is not retransmitted, thereby making it possible to process another read or write access. do. This allows access processing efficiency to be improved.

In the above inventions (inventions 1 to 6), the semiconductor memory device may have a plurality of banks accessed in an interleave manner (invention 7).

According to this invention (invention 7), it becomes possible to access a plurality of banks simultaneously and in parallel, thereby speeding up access to the semiconductor memory device.

In the above inventions (inventions 1 to 7), the semiconductor memory device is configured to internally generate a refresh request signal for executing refresh, and after the refresh request signal is generated until the refresh is executed. If an error is detected in any of the command, address, and data received from the memory controller in the meantime, any of the command, address, and data is retransmitted from the memory controller to resolve the error. The refresh may be configured to stop execution until no longer detected (invention 8).

According to this invention (invention 8), the execution of the refresh is stopped until an error is no longer detected in any of the command, address, and data, thereby making it possible to suppress the delay in access resulting from the execution of the refresh. I do it.

In the above inventions (inventions 1 to 7), the semiconductor memory device is configured to internally generate a refresh request signal for executing refresh, and after the refresh request signal is generated until the refresh is executed. If an error is detected in any of the command, address, and data received from the memory controller in the meantime, fifth response information indicating that the refresh is executed is transmitted to the memory controller, and the refresh is performed. It may be configured to execute (invention 9).

According to this invention (invention 9), when an error is detected in any of the command, address, and data, refresh is performed, so that, for example, retransmission of any of the command, address, and data is repeatedly performed. It becomes possible to suppress loss of memory information in the semiconductor memory device due to the fact that refresh is not performed during this period.

In the above inventions (inventions 1 to 9), the semiconductor memory device may be a pseudo-static random access memory (invention 10).

According to this invention (invention 10), the pseudo-static random access memory can be accessed appropriately.

In the above inventions (1 to 10), when the memory controller receives a write or read request for the semiconductor memory device from the host device, a transmission method of an address data signal transmitted and received between the memory controller and the semiconductor memory device is provided. A request control unit for generating a conversion signal for conversion, and a first sequence control unit for converting a transmission method of the address data signal based on the conversion signal, wherein the first sequence control unit is configured to convert the address data signal into a transmission method based on the conversion signal. A first serializer/serial-to-parallel converter (SerDes) for serializing or serial-parallelizing an address data signal, and a first error control unit for generating the first test data using the command and the address, 1 SerDes generates and outputs a write command and address to the first error control unit when the request control unit receives a write request and the conversion signal is input from the request control unit, and the generated write command and when the first inspection data corresponding to the address is input from the first error control unit, transmitting the generated write command and address and the first inspection data as the address data signal to the semiconductor memory device, and generating the write command and the address. Outputting write data received from the host device to the first error control unit when first response information indicating that no error is detected in the command and address is received from the semiconductor memory device as the address data signal. It may be configured to do so (invention 11).

According to this invention (invention 11), when the memory controller receives first response information indicating that no error is detected in the write command and address from the semiconductor memory device, the memory controller converts the write data received from the host device into the first error. It becomes possible to output to the detection unit.

In the invention (invention 11), the first error control unit is configured to generate second inspection data for error detection of the write data using the write data, and the SerDes is configured to generate the second inspection data for error detection of the write data. When data is input from the first error control unit, the second inspection data and the write data may be transmitted to the semiconductor memory device as the address data signal (invention 12).

According to this invention (invention 12), the memory controller becomes possible to transmit write data and second inspection data to the semiconductor memory device.

In the above inventions (inventions 11 to 12), the first error control unit receives second response information indicating that an error has been detected in one of the write command and the address as the address data signal from the semiconductor memory device. In this case, the first SerDes is configured to generate a signal for retransmitting the write command and address and the first test data, and the first SerDes receives the second response information as the address data signal from the semiconductor memory device. In this case, when a signal for retransmitting the write command, the address, and the first inspection data is input from the first error control unit, the write command, the address, and the first inspection data are transmitted to the semiconductor as the address data signal. It may be configured to retransmit to a storage device (invention 13).

According to this invention (invention 13), when an error is detected in either the command or the address, the memory controller retransmits the command and the address to the semiconductor memory device, so that the semiconductor memory device does not initiate an erroneous operation and allows access. You can restart from the beginning.

In the above inventions (inventions 11 to 13), the semiconductor memory device includes a second sequence control unit that converts a transmission method of the address data signal transmitted and received between the memory controller, and the second sequence control unit , a second serializer/deserializer (SerDes) for serializing or serial-parallelizing the address data signal, and performing error detection of the command and the address using the first inspection data received from the memory controller. It has a second error control unit, wherein the second SerDes, when receiving the command, the address, and the first test data as the address data signal from the memory controller, performs the command, the address, and the first test data. Converting data into a serial transmission method and outputting it to the second error control unit, converting the first response information into a parallel transmission method when the first response information is input from the second error control unit, and 1 Response information is output to the memory controller as the address data signal, a signal representing the contents of the command is output to a command control section that generates an internal command based on the command, and a signal representing the address is output to the address. Outputting to an address control unit that controls to activate the corresponding word line and bit line, converting the second response information into a parallel transmission method when the second response information is input from the second error control unit, and It may be configured to transmit second response information as the address data signal to the memory controller (invention 14).

According to this invention (invention 14), the semiconductor memory device can change the transmission method of the address data signal transmitted and received between the memory controller and at the same time, execute the command using the first inspection data received from the memory controller. and address error detection. In addition, the semiconductor memory device can process the command when no error is detected in the command or address (when first response information is generated), and at the same time detects an error in either the command or the address. When is detected (when the second response information is generated), it becomes possible to transmit the second response information to the memory controller.

In the above invention (invention 14), the second error control unit is configured to perform error detection of the write data using second inspection data for error detection of the write data, and the second SerDes is configured to: When receiving the write data and second inspection data for error detection of the write data as an address data signal from the memory controller, outputting the write data and the second inspection data to the second error control unit; When fourth response information indicating that an error has been detected in the write data is input from the second error control unit, the fourth response information may be transmitted as the address data signal to the memory controller ( Invention 15).

According to this invention (invention 15), the semiconductor memory device can transmit fourth response information to the memory controller when an error is detected in the write data.

According to the memory system of the present invention, it is possible to properly access a semiconductor memory device.

1 is a block diagram showing a configuration example of a memory system according to a first embodiment of the present invention.
Figure 2 is a time chart showing the time transition of signals in a semiconductor memory device when commands and addresses do not contain errors.
Figure 3 is a time chart showing the time transition of signals in a semiconductor memory device when an error is included in either a command or an address.
Figure 4 is a time chart showing the time transition of signals in a semiconductor memory device when data contains an error.
Figure 5 is a time chart showing the time transition of signals in a semiconductor memory device when a predetermined time has elapsed while waiting for data retransmission.
Figure 6 is a flow chart showing an example of the operation of a semiconductor memory device.
7(a) and 7(b) are time charts showing the time transition of signals in the semiconductor memory device in the memory system according to the second embodiment of the present invention.
Figures 8(a) and (b) are time charts showing the time transition of signals in a semiconductor memory device.
Fig. 9 is a time chart showing the time transition of signals in the semiconductor memory device in the memory system according to the third embodiment of the present invention.
Figure 10 is a time chart showing the time transition of signals in a semiconductor memory device.
Fig. 11 is a diagram showing an example of bit allocation of commands and addresses.
Figure 12 is a time chart showing the time trend of the data strobe signal.

Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, this embodiment is an example, and the present invention is not limited to this.

In addition, in this specification, etc., notations such as "first", "second", and "third" are used to distinguish a certain component from other components, and are used to distinguish the number, order, or priority of the corresponding component. It is not intended to limit degrees, etc. For example, when the descriptions “first element” and “second element” are present, it does not mean that only two elements, “first element” and “second element”, are employed, and “first element” It does not mean that "must precede the "second element."

(First Embodiment)

1 is a block diagram showing a configuration example of a memory system according to a first embodiment of the present invention. As shown in FIG. 1, the memory system according to this embodiment includes a memory controller 10 and a semiconductor memory device 20.

In this embodiment, the case where the semiconductor memory device 20 is a pseudo-static random access memory (pSRAM: pseudo-static random access memory) will be explained as an example. Here, pSRAM is a semiconductor memory device equipped with an interface compatible with SRAM (Static Random Access Memory). In addition, pSRAM stores data using DRAM (Dynamic Random Access Memory) as a memory cell array, redesigned the access interface of DRAM, and made it compatible with the access interface of SRAM.

In addition, in this embodiment, the semiconductor memory device 20 is a clock synchronous pSRAM that receives signals in synchronization with a clock signal, and the case of an address data multiplex interface type pSRAM is shown as an example. The address data multiplex interface type pSRAM has an address data terminal configured to input each of an address signal and a data signal. In addition, in the pSRAM of this embodiment, the case where the DDR (Double Data Rate) method is adopted as the data transmission method is shown as an example, but the pSRAM may adopt the SDR (Single Data Rate) method.

In this embodiment, the memory controller 10 includes a command (indicated as Operation in the drawing), an address (indicated as Address in the drawing), and first inspection data for detecting errors in the command and address (in the drawing, , transmitting the first response information (indicated as CheckA in the drawing) to the semiconductor memory device 20 and indicating that no error was detected in the command and address (indicated as ReplyA (OK) in the drawing) to the semiconductor memory device 20. When received from 20, it is configured to transmit or receive data (indicated as Data in the drawing) to be read or written to the address based on the command to and from the semiconductor memory device 20. .

On the other hand, when the semiconductor memory device 20 receives the command, address, and first inspection data from the memory controller 10, the semiconductor memory device 20 performs error detection of the command and address using the first inspection data, and detects errors in the command and address. If an error is not detected, first response information (ReplyA(OK)) is transmitted to the memory controller 10, and if an error is not detected in the command or address, the address is read or It is configured to transmit or receive data to be written to and from the memory controller 10.

Additionally, in this embodiment, when an error is detected in either the command or the address, the semiconductor memory device 20 sends second response information (in the figure) indicating that an error was detected in either the command or the address. It is configured to transmit (indicated as ReplyA(NG)) to the memory controller 10. On the other hand, the memory controller 10 is configured to retransmit the command and address to the semiconductor memory device 20 when the second response information (ReplyA(NG)) is received from the semiconductor memory device 20. In this case, when an error is detected in either the command or the address, the memory controller 10 retransmits the command and address to the semiconductor memory device 20, thereby resuming access to the semiconductor memory device 20 from the beginning. You can.

In addition, in this embodiment, the memory controller 10 (one of the memory controller 10 and the semiconductor memory device 20) stores data to be written and second inspection data for detecting errors in the data (as shown in the figure). It is configured to transmit (indicated as CheckD) to the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20). On the other hand, when the semiconductor memory device 20 receives the data and the second inspection data (CheckD), error detection of the data is performed using the second inspection data (CheckD), and if no error is detected in the data, the semiconductor memory device 20 performs error detection in the data. In this case, it is configured to transmit third response information (indicated as ReplyD(OK) in the drawing) to the memory controller 10 indicating that no error has been detected in the data. In this case, it is possible to prevent a state containing errors in data being read or written from being maintained, so data integrity can be ensured.

Additionally, in this embodiment, the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20) displays an error message indicating that an error has been detected in the data when an error is detected in the data. transmitting the fourth response information (indicated as ReplyD(NG) in the drawing) to the memory controller 10 (either the memory controller 10 or the semiconductor memory device 20), and receiving data from the memory controller 10. It is configured to wait until a predetermined time elapses for the message to be retransmitted. In this case, even if an error is detected in the data, the semiconductor memory device 20 waits for the data to be retransmitted, making it possible to continue accessing the writing of the data. This makes it possible to increase access efficiency compared to, for example, the case where access to write this data is restarted from the beginning (when the command and address are retransmitted).

Additionally, in this embodiment, when the memory controller 10 (one of the memory controller 10 and the semiconductor memory device 20) receives the fourth response information (ReplyD(NG)), the corresponding data and , and is configured to retransmit the second inspection data (CheckD) corresponding to the data to the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20). As a result, when an error is detected in the data, the memory controller 10 retransmits the data, allowing the data to be written again.

Additionally, in this embodiment, the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20) continues to operate the memory controller 10 (memory controller 10) until a predetermined time elapses. ) and the semiconductor memory device 20 ), and is configured to cancel waiting for retransmission of data when data is not retransmitted. This makes it possible for the semiconductor memory device 20 to process another read or write access by releasing the waiting for retransmission of the data when the data is not retransmitted. Therefore, access processing efficiency can be improved.

With reference to FIG. 1, the configuration of the memory controller 10 in this embodiment will be described. The memory controller 10 is connected to an external host device (not shown) and performs access, such as reading or writing, to the semiconductor memory device 20 in accordance with instructions from the host device. For example, the memory controller 10 sends a write request for writing data to the semiconductor memory device 20 or a read request for reading data from the semiconductor memory device 20 from the host device. Upon reception, the chip select signal/CE is asserted (low level) and transmitted to the semiconductor memory device 20. Additionally, the memory controller 10 transmits the clock signal received from the host device as an external clock signal CLK to the semiconductor memory device 20.

In this embodiment, the memory controller 10 includes a request control unit 11 and a sequence control unit 12. The request control unit 11 and the sequence control unit 12 may be configured by dedicated hardware devices or logic circuits.

In addition, the memory controller 10 includes a CPU (Central Processing Unit) (not shown), a storage device (not shown) such as RAM (Random Access Memory), a semiconductor memory device 20, and a host device. An interface (not shown) may be provided for transmitting and receiving signals between each other. Here, the CPU of the memory controller 10 may realize the functions of the request control unit 11 and the sequence control unit 12 by, for example, reading and executing the program stored in the storage device.

When the request control unit 11 receives a write or read request for the semiconductor memory device 20 from the host device, the request control unit 11 transmits an address data signal (ADQ) transmitted and received between the memory controller 10 and the semiconductor memory device 20. It is configured to generate a conversion signal for converting the method. Specifically, when the request control unit 11 receives a write request for writing data to the semiconductor memory device 20 from the host device, the request control unit 11 transmits the write request from the memory controller 10 to the semiconductor memory device 20. A conversion signal (deson) for converting (serial-to-parallel conversion) the address data signal (ADQ) from a serial transmission method to a parallel transmission method of a predetermined number of bits (e.g., 8 bits) is output to the sequence control unit 12. do.

Additionally, when the request control section 11 receives a read request for reading data from the semiconductor memory device 20 from the host device, it outputs a conversion signal (deson) to the sequence control section 12 and A conversion signal (seron) for converting (serializing) the signal (e.g., read data, etc.) transmitted from (20) to the memory controller 10 from the parallel transmission method to the serial transmission method is sent to the sequence control unit 12. Print out.

The sequence control unit 12 is configured to convert the transmission method of the address data signal ADQ based on the conversion signal deson. Additionally, the sequence control unit 12 includes a serial converter/deserializer (SerDes) 12a and an error control unit 12b. The SerDes 12a converts signals transmitted or received between the memory controller 10 and the semiconductor memory device 20 between a serial transmission method and a parallel transmission method. In addition, in this embodiment, the case where the SerDes 12a serially converts the write data to parallel and serially converts the read data is explained as an example, but the SerDes 12a converts the write data into, for example, 8 bits from 64 bits. It may be configured to perform serial conversion into bits or the like and serial-to-parallel conversion of the read data. Additionally, in this embodiment, the sequence control unit 12 is an example of the “first sequence control unit” of the present invention, and SerDes (12a) is an example of the “first serializer/deserializer (SerDes)” of the present invention. This is an example, and the error control unit 12b is an example of the “first error control unit” of the present invention.

For example, when the request control section 11 receives a write request or a read request and a conversion signal (deson) is input from the request control section 11, the SerDes 12a sends a read command or a write command ( Operation and address are generated and output to the error control unit 12b. Next, when the first inspection data (CheckA) for error detection of the command (Operation) and the address (Address) is input from the error control unit 12b, the SerDes (12a) generates the command (Operation), the address (Address), and The first test data (CheckA) is converted to parallel transmission. Then, SerDes 12a transmits a command (Operation), an address (Address), and first inspection data (CheckA) as an address data signal (ADQ) to the semiconductor memory device 20.

In addition, the SerDes 12a sends first response information (ReplyA (OK)) indicating that an error was not detected in the write command (Operation) and the address (Address) as the address data signal ADQ to the semiconductor memory device 20. When received from, the write data (Data) received from the host device is output to the error control unit 12b. Next, when the second check data (CheckD) for detecting errors in the write data (Data) is input from the error control unit 12b, the SerDes (12a) detects the second check data (CheckD) and the write data (Data). Convert to parallel transmission method. Then, the SerDes 12a transmits the second inspection data (CheckD) and the write data (Data) as an address data signal (ADQ) to the semiconductor memory device 20.

In addition, the SerDes 12a sends second response information (ReplyA(NG)) indicating that an error has been detected in either the write command (Operation) or the address (Address) as the address data signal (ADQ) to the semiconductor memory device ( 20), when the write command (Operation), the address (Address), and the signal (retrywr) for retransmitting the first inspection data (CheckA) are input from the error control unit 12b, the write command (Operation) ), the address (Address), and the first inspection data (CheckA) are retransmitted to the semiconductor memory device 20 as the address data signal (ADQ).

In addition, the SerDes 12a sends second response information (ReplyA(NG)) indicating that an error has been detected in either the read command (Operation) or the address (Address) as the address data signal (ADQ) to the semiconductor memory device ( 20), when the read command (Operation), the address (Address), and the signal (retryrd) for retransmitting the first inspection data (CheckA) are input from the error control unit 12b, the read command (Operation) ), the address (Address), and the first inspection data (CheckA) are retransmitted to the semiconductor memory device 20 as the address data signal (ADQ).

Additionally, when the SerDes 12a receives fourth response information (ReplyD(NG)) indicating that an error has been detected in the write data (Data) as the address data signal (ADQ) from the semiconductor memory device 20, The write data (Data) and the second inspection data (CheckD) corresponding to the write data (Data) are retransmitted to the semiconductor memory device 20 as an address data signal (ADQ).

When a command (Operation) and an address (Address) are input from the SerDes 12a, the error control unit 12b generates first inspection data (CheckA) for detecting errors in the command (Operation) and the address (Address), The generated first inspection data (CheckA) is output to SerDes (12a). Here, the first check data (CheckA) may be composed of, for example, a parity code or a CRC (Cyclic Redundancy Checking) code.

Additionally, when write data Data is input from SerDes 12a, the error control unit 12b generates second test data CheckD for detecting errors in the write data Data, and generates second test data CheckD. (CheckD) is output to SerDes (12a). Here, the second test data (CheckD), like the first test data (CheckA), may be composed of, for example, a parity code or a CRC (Cyclic Redundancy Checking) code.

Additionally, the error control unit 12b is configured to respond when second response information (ReplyA(NG)) indicating that an error has been detected in either the write command (Operation) or the address (Address) is transmitted from the semiconductor memory device 20. A signal (retrywr) for retransmitting the write command (Operation), address (Address), and first test data (CheckA) is output to SerDes (12a).

Additionally, the error control unit 12b operates when second response information (ReplyA(NG)) indicating that an error has been detected in either the read command (Operation) or the address (Address) is transmitted from the semiconductor memory device 20. A signal (retryrd) for retransmitting the read command (Operation), address (Address), and first test data (CheckA) is output to SerDes (12a).

Next, the configuration of the semiconductor memory device 20 in this embodiment will be described. The semiconductor memory device 20 includes a sequence control unit 21, a command control unit 22, an address control unit 23, a word line control unit 24, a column control unit 25, a data control unit 26, and , a data bus control unit 27, a sense amplifier 28, and a memory cell array 29. Each section 21 to 29 in the semiconductor memory device 20 may be configured by a dedicated hardware device or logic circuit. Additionally, in this embodiment, in order to simplify the explanation, other well-known structures, such as power supply circuits, chip select terminals, clock terminals, and address data input/output terminals, are not shown.

The sequence control unit 21 is configured to convert the transmission method of the address data signal (ADQ) transmitted and received to and from the memory controller 10. Additionally, the sequence control unit 21 includes a SerDes 21a and an error control unit 21b. Like the SerDes 12a of the memory controller 10, the SerDes 21a transfers signals transmitted or received between the memory controller 10 and the semiconductor memory device 20 between the serial transmission method and the parallel transmission method. Convert. Additionally, in this embodiment, the sequence control unit 21 is configured to transmit a data strobe signal (RWDS) to the sequence control unit 12 of the memory controller 10. Additionally, in this embodiment, the sequence control unit 21 is an example of the “second sequence control unit” of the present invention, and SerDes 21a is an example of the “second serial converter/deserializer (SerDes)” of the present invention. , and the error control unit 21b is an example of the “second error control unit” of the present invention.

When the SerDes (21a) receives a command (Operation), an address (Address), and first check data (CheckA) as an address data signal (ADQ) from the memory controller 10, the command (Operation), an address (Address) ) and the first inspection data (CheckA) are converted to serial transmission and output to the error control unit 21b.

Additionally, the SerDes 21a sends the first response when first response information (ReplyA(OK)) indicating that an error has not been detected in the command (Operation) and the address (Address) is input from the error control unit 21b. The information (ReplyA(OK)) is converted into a parallel transmission method, and the first response information (ReplyA(OK)) is transmitted to the memory controller 10 as an address data signal (ADQ). Additionally, in this case, the SerDes 21a outputs a signal ope indicating the contents of the received command (Operation) (read command or write command) to the command control unit 22, and outputs the received address (Address). The indicated signal (adr) is output to the address control unit 23.

Additionally, the SerDes 21a responds when second response information (ReplyA(NG)) indicating that an error has been detected in either the command (Operation) or the address (Address) is input from the error control unit 21b. 2 The response information (ReplyA(NG)) is converted into a parallel transmission method, and the second response information (ReplyA(NG)) is transmitted to the memory controller 10 as an address data signal (ADQ).

In addition, when the SerDes 21a receives the second check data (CheckD) and the write data (Data) from the memory controller 10 as the address data signal (ADQ), the SerDes (21a) receives the second check data (CheckD) and the write data (Data). (Data) is converted to serial transmission and output to the error control unit 21b.

Additionally, when third response information (ReplyD(OK)) indicating that an error was not detected in the write data Data is input from the error control unit 21b, SerDes 21a sends third response information (ReplyD(OK)). OK)) is converted into a parallel transmission method, and the third response information (ReplyD(OK)) is transmitted to the memory controller 10 as an address data signal (ADQ). Also, in this case, the SerDes 21a outputs a signal di indicating the received write data Data to the data control unit 26.

Additionally, when fourth response information (ReplyD(NG)) indicating that an error has been detected in the write data (Data) is input from the error control unit 21b, the SerDes (21a) provides fourth response information (ReplyD(NG)). )) is converted into a parallel transmission method, and the fourth response information (ReplyD(NG)) is transmitted to the memory controller 10 as an address data signal (ADQ).

Additionally, when the signal do indicating read data is input from the data control unit 26, the SerDes 21a outputs the read data Data to the error control unit 21b. And, when the second inspection data (CheckD) for error detection of the read data (Data) is input from the error control unit 21b, the SerDes (21a) detects the read data (Data) and the second inspection data (CheckD). is converted to a parallel transmission method, and the read data (Data) and the second check data (CheckD) are transmitted to the memory controller 10 as an address data signal (ADQ).

When the command (Operation), address (Address), and first inspection data (CheckA) are input from the SerDes (21a), the error control unit 21b uses the first inspection data (CheckA) to determine the command (Operation) and address ( Address) error detection. And, when no error is detected in the command (Operation) or address (Address), the error control unit 21b sends first response information (ReplyA) indicating that no error was detected in the command (Operation) or address (Address). (OK)) is output to SerDes (21a). On the other hand, when an error is detected in either the command (Operation) or the address (Address), the error control unit 21b is configured to display a second signal indicating that an error has been detected in either the command (Operation) or the address (Address). Response information (ReplyA(NG)) is output to SerDes (21a).

Additionally, when the second inspection data (CheckD) and the write data (Data) are input from the SerDes 21a, the error control unit 21b detects an error in the write data (Data) using the second inspection data (CheckD). do it Then, when an error is not detected in the write data Data, the error control unit 21b sends third response information (ReplyD(OK)) indicating that an error is not detected in the write data Data to SerDes (21a). ) is output. On the other hand, when an error is detected in the write data Data, the error control unit 21b sends fourth response information (ReplyD(NG)) indicating that an error was detected in the write data Data to the SerDes 21a. Print out.

Additionally, when the read data Data is input from the SerDes 21a, the error control unit 21b generates second inspection data CheckD for detecting errors in the read data Data, and generates the generated second inspection data CheckD. (CheckD) is output to SerDes (21a). Here, the second check data (CheckD) may be composed of a parity code, a CRC (Cyclic Redundancy Checking) code, etc., as described above.

Additionally, the error control unit 21b sends a signal (busy) indicating that a read or write access is being processed when the chip select signal/CE changes from negate (high level) to assert (low level). It is asserted (high level) and output to the command control unit 22.

The command control unit 22 is configured to generate internal commands based on commands input from the memory controller 10. Specifically, when an asserted (high level) signal (busy) is input from the sequence control unit 21, the command control unit 22 operates according to the signal (ope) input from the sequence control unit 21. Creates an internal command. Here, the generated internal commands include, for example, a read signal, a write signal, a refresh signal, etc. According to the generated internal command, the command control unit 22 asserts a signal (wlon) for activating the word line and outputs it to the word line control unit 24, and asserts a signal (clon) for activating the bit line. is asserted and output to the thermal control unit 25, and a signal (saon) for activating the sense amplifier 28 is asserted and output to the sense amplifier 28. Additionally, the command control unit 22 asserts a signal (wloff) for deactivating the word line and outputs it to the word line control unit 24.

The address control unit 23 controls, based on the address input from the memory controller 10, to activate the word line and bit line corresponding to the address. Specifically, when the signal adr is input from the sequence control unit 21, the address control unit 23 generates a row address signal ra indicating the word line to be activated, and a column address signal (ra) indicating the bit line to be activated. produces ca). Then, the address control unit 23 outputs the generated row address signal ra to the word line control unit 24 and outputs the generated column address signal ca to the column control unit 25.

The word line control unit 24 controls the word line indicated by the row address signal ra input from the address control unit 23 when the signal wlon is asserted and is input from the command control unit 22. An activation signal (wl) is output to the memory cell array 29 to activate (drive) the corresponding word line. Additionally, when the signal wloff is input from the command control unit 22 in an asserted state, the word line control unit 24 sends a signal wl for deactivating the activated word line to the memory cell array 29. ) to deactivate the corresponding word line.

When the signal (clon) is input from the command control section 22 in an asserted state, the column control section 25 selects the input from the address control section 23 among the plurality of bit lines in the memory cell array 29. A signal (cl) for activating the bit line indicated by the column address signal (ca) is output to the sense amplifier 28.

When the signal di indicating write data is input from the sequence control unit 21, the data control unit 26 outputs a signal wdb indicating write data to the data bus control unit 27. Additionally, when the signal rdb representing read data is input from the data bus control section 27, the data control section 26 outputs a signal do indicating read data to the sequence control section 21.

When the signal wdb representing write data is input from the data control section 26, the data bus control unit 27 outputs a signal cdb indicating write data to the sense amplifier 28. Additionally, when the signal cdb representing read data is input from the sense amplifier 28, the data bus control section 27 outputs a signal rdb representing the read data to the data control section 26.

The sense amplifier 28 is configured to activate the bit line indicated by the signal cl input from the column control unit 25 when the signal saon is input from the command control unit 22 in an asserted state. A signal bl is output to the memory cell array 29 to activate (drive) the corresponding bit line. Then, the sense amplifier 28 reads and writes data to the memory cell via the activated bit line. For example, the sense amplifier 28 writes a signal cdb representing write data input from the data bus control unit 27 to the memory cell through the activated bit line. Additionally, the sense amplifier 28 outputs data read from the memory cell to the data bus control unit 27 via the activated bit line.

The memory cell array 29 includes a plurality of memory cells (not shown) arranged in a matrix (array) form. Data input from the memory controller 10 is stored in each memory cell. Each memory cell may be a well-known 1T1C (1 transistor 1 capacitor) type memory cell. Additionally, each memory cell is connected to one word line out of a plurality of word lines and to one bit line out of a plurality of bit lines.

In addition, since the details of the read/write control of data for each memory cell in the memory cell array 29 are the same as known techniques, a more detailed description is omitted in this embodiment.

Next, with reference to FIG. 2, an example of the operation of the semiconductor memory device 20 in this embodiment will be described. FIG. 2 is a time chart showing the time transition of signals in the semiconductor memory device 20 when commands and addresses do not contain errors. In addition, here, the case where a write command (Operation) is input from the memory controller 10 is explained as an example.

First, when the semiconductor memory device 20 receives a command (Operation), an address (Address), and first inspection data (CheckA) from the memory controller 10, the semiconductor memory device 20 executes a command (Operation) using the first inspection data (CheckA). ) and address error detection. And, when an error is not detected, the semiconductor memory device 20 sends first response information (ReplyA (OK)) indicating that an error was not detected in the command (Operation) and address (Address) to the memory controller (10). ) is sent to Additionally, the first response information (ReplyA(OK)) may be transmitted during the latency from when the command and address are input until data is input or output.

Additionally, the semiconductor memory device 20 asserts (high level) the signal wlon when no error is detected in the command (Operation) or address (Address). In this case, the signal wl for activating the word line corresponding to the address is asserted (high level).

Meanwhile, when the memory controller 10 receives the first response information (ReplyA(OK)), it transmits the second inspection data (CheckD) and the write data (Data) to the semiconductor memory device 20. Additionally, the second inspection data (CheckD) may be transmitted during latency.

When the semiconductor memory device 20 receives the second inspection data (CheckD) and the write data (Data) from the memory controller 10, the semiconductor memory device 20 detects an error in the write data (Data) using the second inspection data (CheckD). do it Additionally, the semiconductor memory device 20 asserts (high level) the signal cl for activating the bit line corresponding to the address. At this time, the sense amplifier 28 of the semiconductor memory device 20 activates the bit line corresponding to the address, so that write data Data is written to the memory cells in the memory cell array 29.

Additionally, the semiconductor memory device 20, when the chip select signal/CE is negated (high level) after receiving the write data (Data), provides response information (second) indicating whether an error has been detected in the write data. 3 Response information (ReplyD(OK)) or fourth response information (ReplyD(NG)) is transmitted to the memory controller 10.

Additionally, the semiconductor memory device 20 asserts (high level) the signal wloff when the write data Data is correctly written to the memory cells in the memory cell array 29. This causes the signal wl to be negate (low level).

In this way, when the memory controller 10 receives the first response information (ReplyA(OK)) indicating that no error was detected in the command (Operation) and the address (Address) from the semiconductor memory device 20, , it becomes possible to transmit data written for the address (Address) to and from the semiconductor memory device 20.

With reference to FIG. 3, another example of the operation of the semiconductor memory device 20 in this embodiment will be described. FIG. 3 is a time chart showing the time transition of signals in the semiconductor memory device 20 when an error is included in either the command or the address. Meanwhile, here, as in FIG. 2, the case where a write command (Operation) is input from the memory controller 10 will be described as an example.

First, when the semiconductor memory device 20 receives a command (Operation), an address (Address), and first inspection data (CheckA) from the memory controller 10, the semiconductor memory device 20 executes a command (Operation) using the first inspection data (CheckA). ) and address error detection. And, when an error is detected, the semiconductor memory device 20 sends second response information (ReplyA(NG)) indicating that an error was detected in either the command (Operation) or the address (Address) to the memory controller ( Send to 10). Also, in this case, the semiconductor memory device 20 does not activate the word line and bit line corresponding to the address.

Meanwhile, upon receiving the second response information (ReplyA(NG)), the memory controller 10 retransmits the command (Operation), address (Address), and first inspection data (CheckA) to the semiconductor memory device 20. .

When the semiconductor memory device 20 receives the command (Operation), address (Address), and first inspection data (CheckA) retransmitted from the memory controller 10, it executes the command (Operation) using the first inspection data (CheckA). ) and address error detection. And, when an error is not detected, the semiconductor memory device 20 sends first response information (ReplyA (OK)) indicating that an error was not detected in the command (Operation) and address (Address) to the memory controller (10). ) is sent to Additionally, the operation of the semiconductor memory device 20 after this is the same as the example shown in FIG. 2.

In this way, when an error is detected in the command (Operation) and address (Address), the memory controller 10 retransmits the command (Operation) and address (Address) to the semiconductor memory device 20, thereby ) makes it possible to resume access from the beginning without initiating an erroneous operation.

With reference to FIG. 4, another example of the operation of the semiconductor memory device 20 in this embodiment will be described. Figure 4 is a time chart showing the time transition of signals in a semiconductor memory device when data contains an error. In addition, here, as in FIGS. 2 and 3, the case where a write command (Operation) is input from the memory controller 10 is explained as an example.

First, when the semiconductor memory device 20 receives a command (Operation), an address (Address), and first inspection data (CheckA) from the memory controller 10, the semiconductor memory device 20 executes a command (Operation) using the first inspection data (CheckA). ) and address error detection. Additionally, the semiconductor memory device 20 asserts (high level) the signal (busy) when the chip select signal/CE changes from negate (high level) to assert (low level).

In addition, when the semiconductor memory device 20 receives the second test data (CheckD) and the write data (Data) after transmitting the first response information (ReplyA(OK)) to the memory controller 10, the semiconductor memory device 20 performs the second test Error detection of write data Data is performed using data CheckD. Additionally, the semiconductor memory device 20 writes write data Data, as described above.

Here, when an error is detected in the write data Data, the semiconductor memory device 20 sends fourth response information indicating that an error was detected in the write data when the chip select signal/CE is negated (high level). ReplyD(NG)) is transmitted to the memory controller 10. Also, in this case, the semiconductor memory device 20 maintains each of the signal wl and the signal busy in the asserted state.

Meanwhile, upon receiving the fourth response information (ReplyD(NG)), the memory controller 10 retransmits the second inspection data (CheckD) and write data (Data) to the semiconductor memory device 20.

When the semiconductor memory device 20 receives the second inspection data (CheckD) and the write data (Data) retransmitted from the memory controller 10, the semiconductor memory device 20 uses the second inspection data (CheckD) to detect errors in the write data (Data). Perform detection. Additionally, the semiconductor memory device 20 writes the write data Data again. Then, when an error is not detected in the write data Data, the semiconductor memory device 20 sends third response information ReplyD(OK) indicating that an error was not detected in the write data Data to the memory controller 10. ) is sent to Additionally, the semiconductor memory device 20 negates (low levels) each of the signal wl and the signal busy.

In this way, according to the memory system according to the present embodiment, it is possible to prevent a state containing an error in data being read or written from being maintained.

In addition, according to the memory system according to the present embodiment, even when an error is detected in the data (Data), the semiconductor memory device 20 waits for the data (Data) to be retransmitted, thereby It becomes possible to continue accessing the writing. Additionally, the semiconductor memory device 20 maintains the signal wl in an asserted state while waiting for retransmission of data, thereby activating the sense amplifier when, for example, a command and an address are retransmitted. Since waiting time (latency) is unnecessary, operation time can be shortened.

In addition, in this embodiment, the case where only the data (Data) is retransmitted when an error is detected in the data (Data) has been described as an example, but the present invention is not limited to this case. For example, the command (Operation) may be retransmitted, the address (Address) corresponding to the row address signal (ra) and/or the column address signal (ca) may be retransmitted, and the command (Operation) and address (Address) may be retransmitted. It may be retransmitted.

Additionally, according to the memory system according to the present embodiment, when an error is detected in the data (Data), the memory controller 10 retransmits the data (Data), so that writing of the data (Data) can be performed again. .

With reference to FIG. 5, another example of the operation of the semiconductor memory device 20 in this embodiment will be described. Figure 5 is a time chart showing the time transition of signals in a semiconductor memory device when a predetermined time has elapsed while waiting for data retransmission. In addition, here, as in FIGS. 2 to 4, the case where a write command (Operation) is input from the memory controller 10 is explained as an example.

First, when an error is detected in the write data Data, the semiconductor memory device 20 sends fourth response information indicating that an error has been detected in the write data when the chip select signal/CE is negated (high level). (ReplyD(NG)) is transmitted to the memory controller 10. Additionally, the operation of the semiconductor memory device 20 until an error is detected in the write data Data is the same as the example explained with reference to FIG. 4.

Here, the semiconductor memory device 20 transmits the fourth response information (ReplyD(NG)) to the memory controller 10 and writes the second inspection data (CheckD) and When data (Data) is not received from the memory controller 10, each of the signal wl and the signal busy may be negate (low level). This cancels the waiting state for retransmission of the write data (Data). Additionally, the semiconductor memory device 20 may measure elapsed time using a built-in timer circuit (not shown) or the like.

In this way, according to the memory system according to the present embodiment, when the data (Data) is not retransmitted, the semiconductor memory device 20 releases the waiting for retransmission of the data (Data), thereby performing another read or It becomes possible to handle write access.

Next, with reference to FIG. 6, an example of the operation flow of the semiconductor memory device 20 will be described. The semiconductor memory device 20 is in a standby state, when the chip select signal/CE is asserted (low level) and the command (Operation), address (Address), and first inspection data (CheckA) are input. , error checking of the command (Operation) and address (Address) is performed using the first inspection data (CheckA) (step S100). Then, when an error is detected (step S101: Yes), the semiconductor memory device 20 outputs the second response information (ReplyA(NG)) to the memory controller 10 and transitions to the standby state. In addition, when an error is not detected (step S101: No), the semiconductor memory device 20 outputs first response information (ReplyA (OK)) to the memory controller 10 and enters the active state (active). Fulfill.

When the semiconductor memory device 20 transitions to the active state (active), it activates the memory cell array 29 (activates the word line and bit line) (step S102).

Next, the semiconductor memory device 20 performs read or write access based on the command (Operation) and the address (Address) (step S103). Here, in the case of write access, the semiconductor memory device 20 performs write access after receiving the second inspection data (CheckD) and write data (Data).

Additionally, the semiconductor memory device 20 performs an error check of the data Data using the second inspection data CheckD (step S104).

Here, when an error is detected in the data (Data) (step S105: Yes), the semiconductor memory device 20 outputs fourth response information (ReplyD(NG)) to the memory controller 10 and returns the data (Data ) transitions to a waiting state for retransmission. Then, when the chip select signal/CE is asserted (low level), the semiconductor memory device 20 proceeds to the processing in step S103. In addition, when the semiconductor memory device 20 waits for retransmission of data (Data) and a predetermined time has elapsed, the semiconductor memory device 20 moves to the process of step S106, which will be described later.

When no error is detected in the data (Step S105: No), the semiconductor memory device 20 outputs third response information (ReplyD (OK)) to the memory controller 10, and the memory cell array ( 29) is deactivated (deactivated word line and bit line) (step S106), and the process moves to the standby state.

As described above, according to the memory system of this embodiment, the memory controller 10 sends the first response information (ReplyA(OK)) indicating that no error was detected in the command (Operation) and the address (Address) to the semiconductor. When received from the memory device 20, it becomes possible to transmit or receive data to be read or written for the address (Address) to and from the semiconductor memory device 20. This makes it possible to suppress inappropriate access due to changes in the content of the command (Operation) or the address (Address) during transmission of the command packet, thereby ensuring appropriate access to the semiconductor memory device 20. You can.

Additionally, according to the memory system of this embodiment, the pseudo-static random access memory can be accessed appropriately.

(Second Embodiment)

Hereinafter, a second embodiment of the present invention will be described. The memory system of this embodiment differs from the first embodiment in that the semiconductor memory device 20 includes a plurality of banks accessed in an interleaved manner. Hereinafter, a configuration different from that of the first embodiment will be described.

7 and 8, an example of the operation of the semiconductor memory device 20 in this embodiment will be described. 7 and 8 are time charts showing the time transition of signals within the semiconductor memory device 20. In addition, the time charts shown in Fig. 7(a) and Fig. 7(b) show a continuous time trend following Fig. 7(a) and Fig. 7(b), and Fig. 8(a) and Fig. 8(b) ) The same applies to In addition, in the example shown in the drawing, the case where the semiconductor memory device 20 is provided with two banks (BNK0 and BNK1) will be described as an example.

As shown in FIG. 7, in the semiconductor memory device 20 of this embodiment, a command (Operation(BNK0)), an address (Address(BNK0)), and first test data (CheckA) for one bank (BNK0) It is configured so that during the latency from when (BNK0)) is input until data (Data(BNK0)) is input or output, access to the other bank (BNK1) is performed.

Similar to the above-described first embodiment, when an error is not detected in the command (Operation (BNK0)) and the address (Address (BNK0)) for one bank (BNK0), the semiconductor memory device 20 stores the address (Address). Assert (high level) the word line (wl) (BNK0) corresponding to (BNK 0, row = Rm (Rm represents the row address, and m is an integer)).

Additionally, the semiconductor memory device 20 performs access to the other bank (BNK1) while the latency (latency (BNK0)) of access to one bank (BNK0) is present. Here, when accessing the other bank (BNK1), the semiconductor memory device 20 uses the address (Address(BNK 1, row=Ri) received before the latency of access to the other bank (BNK1) (Ri is the row It indicates an address, and i is an integer))), and the corresponding data (Data(BNK1)) is read or written. Then, when an error is not detected in the data (Data(BNK1)) (ReplyD(BNK1) is “OK”), the semiconductor memory device 20 issues a command for the next access to the other bank (BNK1). (Operation(BNK1)) and address (Address(BNK 1, row=Rj (Rj represents the row address, j is an integer))). At this time, the semiconductor memory device 20 asserts (high level) the word line (wl) (BNK1) corresponding to the address (Address (BNK1, row = Rj)).

Next, the semiconductor memory device 20 accesses one bank (BNK0) while the latency (latency (BNK1)) of access to the other bank (BNK1). Here, when accessing one bank (BNK0), the semiconductor memory device 20 stores data ( Data (BNK0)) is read or written. Then, the semiconductor memory device 20, when no error is detected in the data (Data(BNK0)) (when ReplyD(BNK0) is “OK”), sends a command for the next access to one bank (BNK0) ( Operation(BNK0)) and address (Address(BNK 0,row=Rn (Rn represents the row address, n is an integer))). At this time, the semiconductor memory device 20 asserts (high level) the word line (wl) (BNK0) corresponding to the address (Address (BNK0, row = Rn)).

Additionally, as shown in FIG. 8, when an error is detected in the data (Data(BNK0)) when accessing one bank (BNK0) (when ReplyD(BANK0) is "NG"), the semiconductor memory device ( 20) After receiving data (Data(BNK0)) for which no error was detected, other access commands (Operation(BNK0)) and address (Address(BNK0,row=Rn)) are received. The latency (latency (BNK1)) of access to the side bank (BNK1) may be extended.

As described above, according to the memory system of this embodiment, access to a plurality of banks can be performed simultaneously and in parallel, so access to the semiconductor memory device 20 can be accelerated.

(Third Embodiment)

Hereinafter, a third embodiment of the present invention will be described. The memory system of this embodiment differs from each of the above embodiments in that the semiconductor memory device 20 is configured to internally generate a refresh request for refreshing memory cells. Hereinafter, configurations different from each of the above embodiments will be described.

In this embodiment, the semiconductor memory device 20 receives the command (Operation), address (Address), and data (Data) from the memory controller 10 between the generation of the refresh request signal and the execution of the refresh. ), when an error is detected in any of the commands (Operation), addresses (Address), and data (Data), the refresh is continued until the error is no longer detected by being retransmitted from the memory controller 10. It is configured to stop execution.

With reference to FIG. 9, an example of the operation of the semiconductor memory device 20 in this embodiment will be described. FIG. 9 is a time chart showing the time transition of signals in the semiconductor memory device 20. In addition, here, the case where a write command (Operation) is input from the memory controller 10 is explained as an example.

First, the semiconductor memory device 20 asserts (high level) the signal (busy) when the chip select signal/CE changes from negate (high level) to assert (low level). Here, the semiconductor memory device 20 generates (asserts) a refresh request signal (refreq) internally while receiving the command (Operation), address (Address), and first inspection data (CheckA). , assert (high level) a signal (refwait) to wait for refresh execution. Additionally, the refresh request signal (refreq) and signal (refwait) may be generated by, for example, the command control unit 22 of the semiconductor memory device 20.

And, when an error is detected in the command (Operation) and the address (Address), the semiconductor memory device 20 sends second response information (ReplyA(NG)) indicating that the error was detected to the memory controller 10. Send.

Next, the semiconductor memory device 20 receives write data (Data) from the memory controller 10 when no error is detected in the command (Operation) and address (Address) retransmitted from the memory controller 10. Then, the received write data Data is written.

And, the semiconductor memory device 20 sends a signal (refwait) when an error is not detected in the write data (Data) (when the third response information (ReplyD(OK)) is transmitted to the memory controller 10). Negate (low level). Additionally, the semiconductor memory device 20 performs refresh when the signal refwait is negated (low level). Specifically, the semiconductor memory device 20 asserts (high level) the signal wlon and simultaneously asserts (high level) the signal wl in order to activate the word line to be refreshed. . Additionally, the semiconductor memory device 20 asserts (high level) the signal bl for activating the bit line to perform refresh. Then, the semiconductor memory device 20 performs refresh. Additionally, when the refresh is completed, the semiconductor memory device 20 asserts (high level) the signal wloff and negates (low level) the signal wl.

In addition, although the description is omitted in the drawing, when an error is detected in the data (Data), the semiconductor memory device 20 continues until the error is no longer detected in the data transmitted from the memory controller 10. You may wait for refresh execution (assert a signal (refwait) (high level)).

In this way, according to the present embodiment, the execution of the refresh is stopped until an error is no longer detected in any of the command (Operation), address (Address), and data (Data), resulting in the refresh being executed. It becomes possible to suppress delays in access.

In addition, as a modification of the third embodiment, the semiconductor memory device 20 includes a command (Operation) received from the memory controller 10 between the generation of the refresh request signal (refreq) and the time the refresh is executed, When an error is detected in either the address or data, the fifth response information indicating that refresh is to be performed may be transmitted to the memory controller 10 and refresh may be performed.

With reference to Fig. 10, an example of the operation of the semiconductor memory device 20 in the modified example will be described. FIG. 10 is a time chart showing the time transition of signals within the semiconductor memory device 20. In addition, here, the case where a write command (Operation) is input from the memory controller 10 is explained as an example.

First, the semiconductor memory device 20 asserts (high level) the signal (busy) when the chip select signal/CE changes from negate (high level) to assert (low level). Here, when the semiconductor memory device 20 internally generates (asserts) a refresh request signal (refreq) while receiving a command (Operation), an address (Address), and first inspection data (CheckA), Asserts (high level) a signal (refwait) to wait for refresh execution.

And, when an error is detected in the command (Operation) and the address (Address), the semiconductor memory device 20 sends second response information (ReplyA(NG)) indicating that the error was detected to the memory controller 10. Send. Here, the second response information (ReplyA(NG)) may include fifth response information (indicated as “Ref next” in the drawing) indicating that refresh is performed.

Meanwhile, when the memory controller 10 receives the second response information (ReplyA(NG)) including the fifth response information (“Ref next”), refresh is performed in the semiconductor memory device 20. Considering this, transmission of the command (Operation), address (Address), and first inspection data (CheckA) in the next access may be waited until a predetermined time has elapsed.

Next, the semiconductor memory device 20 negates (low level) the signal (busy) once and then asserts (high level) it. Additionally, the semiconductor memory device 20 starts refresh execution in accordance with the signal busy being negated (low level) and negates the signal refwait (low level).

Then, the semiconductor memory device 20 performs processing for the next access after execution of refresh is completed.

In this way, according to this modification, when an error is detected in any of the command (Operation), address (Address), and data (Data), refresh is performed, for example, the command (Operation), address (Address), and data (Data). It is possible to suppress loss of storage information in the semiconductor memory device 20 due to no refresh being performed while either (Address) or data (Data) is repeatedly retransmitted.

Each embodiment described above is described to facilitate understanding of the present invention, and is not described to limit the present invention. Therefore, each element disclosed in each of the above embodiments is intended to include all design changes and equivalents that fall within the technical scope of the present invention.

For example, in the above-described embodiment, the case where the semiconductor memory device 20 is pSRAM was described as an example, but the present invention is not limited to this case. For example, the semiconductor memory device 20 may be DRAM, flash memory, or another semiconductor memory device.

In addition, in the above-described embodiment, the case where the memory controller 10 transmits a write command (Operation (Write)) to the semiconductor memory device 20 was described as an example, but the memory controller 10 transmits a read command (Operation) Even when transmitting to the semiconductor memory device 20, the same effects as in the above-described embodiment are obtained.

For example, the semiconductor memory device 20 (one of the memory controller 10 and the semiconductor memory device 20) sends read data and second inspection data (CheckD) for detecting errors in the read data to the memory controller ( 10) may be transmitted to (the other of the memory controller 10 and the semiconductor memory device 20). Additionally, when receiving the read data and the second inspection data (CheckD), the memory controller 10 performs error detection of the read data using the second inspection data (CheckD), and detects an error in the read data. If not, third response information (ReplyD(OK)) indicating that no error was detected in the read data may be transmitted to the semiconductor memory device 20. In this case, the semiconductor memory device 20 can confirm that the data to be written is properly reaching the memory controller 10 by receiving the third response information (ReplyD(OK)).

Additionally, in the above case, the memory controller 10 (the other of the memory controller 10 and the semiconductor memory device 20), when an error is detected in the data, displays a second message indicating that an error has been detected in the data. 4 Response information (ReplyD(NG)) is transmitted to the semiconductor memory device 20 (either the memory controller 10 or the semiconductor memory device 20), and data is retransmitted from the semiconductor memory device 20 for a predetermined period of time. You may wait until this has elapsed. In this case, even if an error is detected in the data, the memory controller 10 waits for the data to be retransmitted, making it possible to continue accessing the data. This makes it possible to increase access efficiency compared to, for example, the case where access for reading this data is restarted from the beginning (when the command and address are retransmitted).

Additionally, in the above case, when the semiconductor memory device 20 (one of the memory controller 10 and the semiconductor memory device 20) receives the fourth response information (ReplyD(NG)), the data and , the second inspection data (CheckD) corresponding to the data may be retransmitted to the memory controller 10 (the other of the memory controller 10 and the semiconductor memory device 20). Accordingly, when an error is detected in the data, the semiconductor memory device 20 retransmits the data, allowing the data to be read again.

Additionally, in the above case, the memory controller 10 (the other of the memory controller 10 and the semiconductor memory device 20) continues to operate the semiconductor memory device 20 (memory controller 10) until a predetermined time elapses. ) and the semiconductor memory device 20), if data is not retransmitted, waiting for retransmission of data may be released. In this case, the memory controller 10 releases waiting for retransmission of data when the data has not been retransmitted, thereby making it possible to process other read or write accesses. This allows access processing efficiency to be improved.

In addition, in the above embodiment, the case where the first inspection data (CheckA) is transmitted divided into a command (Operation) and an address (Address) has been described as an example, but the present invention is not limited to this case. Figure 11 shows an example of bit allocation for commands (Operation) and addresses (Address). In addition, here, it is assumed that the semiconductor memory device 20 is pSRAM.

In the example shown in FIG. 11, 8-bit address data signals (ADQ[7] to ADQ[0]) are input for each rising edge and falling edge of the external clock signal (CLK). Here, a command (Operation) is configured in the address data signals (ADQ[7] to ADQ[5]) input at the rising edge of the first external clock signal (CLK), and the first external clock signal (CLK) ), addresses (Address[31] to Address[0]) are configured in the address data signal (ADQ) input from the third external clock signal (CLK). In addition, the address data signals (ADQ[7] to ADQ[0]) input at the rising edge of the third external clock signal (CLK), and the address data signals (ADQ[7] to ADQ[0]) input at the falling edge of the third external clock signal (CLK). The address data signals (ADQ[7]) to ADQ[3] are reserved areas, but are unused areas. Therefore, the first inspection data (CheckA) may be constructed using at least a part of this reserved area. This makes it possible for the semiconductor memory device 20 to receive the first inspection data (CheckA) simultaneously with the address (Address). Additionally, the first inspection data (CheckA) may be comprised of the address data signal (ADQ) input on the rising edge or falling edge of the fourth and subsequent external clock signals (CLK).

Additionally, in the example shown in FIG. 11, the data strobe signal RWDS may be configured to display fifth response information indicating that refresh is being performed. For example, when the data strobe signal (RWDS) is at a high level (H), fifth response information (“Ref next”) indicating that refresh is performed may be displayed. Meanwhile, when the data strobe signal (RWDS) is at a low level (L), a signal (“Immediate”) indicating that the address data signal (ADQ) can be transmitted and received immediately may be displayed.

Additionally, as shown in FIG. 12, the data strobe signal RWDS may be configured to display first response information (ReplyA(OK)) or second response information (ReplyA(NG)). For example, if the logic level (high level or low level) of the data strobe signal (RWDS) is maintained (“kept”) on the rising edge of the fourth external clock signal (CLK), the data strobe signal (RWDS) ) may indicate first response information (ReplyA(OK)). Meanwhile, when the logic level (high level or low level) of the data strobe signal (RWDS) is inverted (“inverted”) at the rising edge of the fourth external clock signal (CLK), the data strobe signal (RWDS) is: Second response information (ReplyA(NG)) may be displayed. Also, for example, depending on the state of the data strobe signal (RWDS) at the rising edge or falling edge of the fifth or subsequent external clock signal (CLK), the first response information (ReplyA (OK)) or the second response Information (ReplyA(NG)) may be displayed.

In addition, the configuration of the memory controller 10 and the semiconductor memory device 20 shown in FIG. 1 is an example, and may be changed as appropriate, and various other configurations may be adopted.

10: memory controller 11: request control unit
12: Sequence control unit
12a: Serializer·Serial-to-parallel converter (SerDes)
12b: error control unit 20: semiconductor memory device
21: Sequence control unit
21a: Serial converter/serial-parallel converter (SerDes)
2lb: error control unit 22: command control unit
23: Address control unit 24: Word line control unit
25: heat control unit 26: data control unit
27: data bus control unit 28: sense amplifier
29: Memory cell array

Claims (15)

As a memory system,
memory controller; and
semiconductor memory device
Including, the memory controller,
transmitting a command and an address and first inspection data for detecting errors in the command and the address to the semiconductor memory device;
When first response information indicating that no error has been detected in the command and the address is received from the semiconductor memory device, data to be read or written for the address based on the command is stored between the semiconductor memory device and the semiconductor memory device. sending or receiving from
It is configured to do,
The semiconductor memory device,
When the command, the address, and the first inspection data are received from the memory controller, error detection of the command and the address is performed using the first inspection data, and an error is detected in the command and the address. If not, transmitting the first response information to the memory controller,
When no error is detected in the command or the address, transmitting or receiving data to be read or written for the address based on the command to and from the memory controller.
It is configured to do,
When the semiconductor memory device is configured to internally generate a refresh request signal for executing a refresh, the command received from the memory controller between the generation of the refresh request signal and the execution of the refresh , when an error is detected in any of the address or the data, executing the refresh until the error is no longer detected by retransmitting any of the command, the address, and the data from the memory controller. A memory system configured to stop. As a memory system,
memory controller; and
semiconductor memory device
Including, the memory controller,
transmitting a command and an address and first inspection data for detecting errors in the command and the address to the semiconductor memory device;
When first response information indicating that no error has been detected in the command and the address is received from the semiconductor memory device, data to be read or written for the address based on the command is stored between the semiconductor memory device and the semiconductor memory device. sending or receiving from
It is configured to do,
The semiconductor memory device,
When the command, the address, and the first inspection data are received from the memory controller, error detection of the command and the address is performed using the first inspection data, and an error is detected in the command and the address. If not, transmitting the first response information to the memory controller,
When no error is detected in the command or the address, transmitting or receiving data to be read or written for the address based on the command to and from the memory controller.
It is configured to do,
When the semiconductor memory device is configured to internally generate a refresh request signal for executing a refresh, the command received from the memory controller between the generation of the refresh request signal and the execution of the refresh , when an error is detected in either the address or the data, transmitting fifth response information indicating that the refresh is to be performed to the memory controller, and executing the refresh. According to paragraph 1,
The semiconductor memory device,
configured to transmit, to the memory controller, second response information indicating that an error has been detected in either the command or the address when an error is detected in either the command or the address;
The memory controller is,
A memory system, configured to retransmit the command and the address to the semiconductor memory device when the second response information is received from the semiconductor memory device. According to paragraph 1,
One of the memory controller and the semiconductor memory device,
configured to transmit the data to be read or written and second inspection data for detecting errors in the data to the other of the memory controller and the semiconductor memory device,
The other of the memory controller and the semiconductor memory device,
When the data and the second inspection data are received, error detection of the data is performed using the second inspection data, and when no error is detected in the data, no error is detected in the data. A memory system configured to transmit third response information indicating information to one of the memory controller and the semiconductor memory device. According to paragraph 4,
The other of the memory controller and the semiconductor memory device,
When an error is detected in the data, transmitting fourth response information indicating that an error has been detected in the data to one of the memory controller and the semiconductor memory device;
Waiting until a predetermined time elapses for the data to be retransmitted from one of the memory controller and the semiconductor memory device.
A memory system configured to perform. According to clause 5,
One of the memory controller and the semiconductor memory device,
and, when receiving the fourth response information, retransmit the data and the second test data corresponding to the data to the other of the memory controller and the semiconductor memory device. According to clause 5,
The other of the memory controller and the semiconductor memory device,
and cancel waiting for retransmission of the data when the data is not retransmitted from one of the memory controller and the semiconductor memory device until the predetermined time elapses. According to any one of claims 1 to 7,
A memory system, wherein the semiconductor memory device has a plurality of banks accessed in an interleaved manner. 8. The memory system according to any one of claims 1 to 7, wherein the semiconductor memory is a pseudo-static random access memory. According to any one of claims 1 to 7,
The memory controller is,
a request control unit that, when receiving a write or read request for the semiconductor memory device from a host device, generates a conversion signal for converting a transmission method of an address data signal transmitted and received between the memory controller and the semiconductor memory device;
A first sequence control unit that converts the transmission method of the address data signal based on the conversion signal
Provided with, the first sequence control unit,
a first serializer/serial-to-parallel converter (SerDes) that serializes or serial-parallels the address data signal based on the conversion signal;
A first error control unit that generates the first inspection data using the command and the address.
Provided with, and the first SerDes is,
When the request control unit receives a write request and the conversion signal is input from the request control unit, generating a write command and an address and outputting them to the first error control unit;
When the first inspection data corresponding to the generated write command and address is input from the first error control unit, transmitting the generated write command and address and the first inspection data as the address data signal to the semiconductor memory device. ,
When first response information indicating that an error is not detected in the generated write command and address is received from the semiconductor memory device as the address data signal, output the write data received from the host device to the first error control unit. doing
A memory system configured to perform. According to clause 10,
The first error control unit is configured to use the write data to generate second inspection data for detecting errors in the write data,
The SerDes is configured to transmit the second inspection data and the write data as the address data signal to the semiconductor memory device when the second inspection data is input from the first error control unit. According to clause 10,
When receiving second response information indicating that an error has been detected in any of the write command and address from the semiconductor memory device as the address data signal, the first error control unit controls the write command and address and the first error control unit. 1 configured to generate a signal for retransmitting test data,
When the first SerDes receives the second response information as the address data signal from the semiconductor memory device, a signal for retransmitting the write command and address and the first inspection data is received from the first error control unit. A memory system, configured to retransmit the write command and address and the first inspection data as the address data signal to the semiconductor memory device when input. According to clause 10,
The semiconductor memory device includes a second sequence control unit that converts a transmission method of the address data signal transmitted and received between the memory controller,
The second sequence control unit,
a second serial converter/serial-to-parallel converter (SerDes) that serializes or serial-parallels the address data signal;
A second error control unit that detects errors in the command and the address using the first test data received from the memory controller.
Provided, and the second SerDes is,
When the command, the address, and the first test data are received from the memory controller as the address data signal, the command, the address, and the first test data are converted into serial transmission and transmitted to the second error control unit. printing,
When the first response information is input from the second error control unit, the first response information is converted into a parallel transmission method, the first response information is output as the address data signal to the memory controller, and the command Outputting a signal representing the content to a command control section that generates an internal command based on the command, and outputting a signal representing the address to an address control section controlling activating a word line and a bit line corresponding to the address. ,
When the second response information is input from the second error control unit, converting the second response information into a parallel transmission method and transmitting the second response information as the address data signal to the memory controller.
A memory system configured to perform. According to clause 13,
the second error control unit is configured to perform error detection of the write data using second inspection data for error detection of the write data,
The second SerDes is,
When receiving the write data and second inspection data for error detection of the write data as an address data signal from the memory controller, outputting the write data and the second inspection data to the second error control unit;
When fourth response information indicating that an error has been detected in the write data is input from the second error control unit, transmitting the fourth response information as the address data signal to the memory controller.
A memory system configured to perform. delete